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MICROCHIP PIC18F1220/1320 Data Sheet

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1. 54 2004 Microchip Technology Inc DS39605C page 283 PIC18F1220 1320 FIGURE 23 31 AIPD LVD vs VoD SLEEP MODE LVDL3 LVDLO 0001 2V 50 45 Typical statistical mean 25 C Maximum mean 86 40 C to 125 C 40 Minimum mean 3o 40 C to 125 C Max 4125 C 35 Max 85 C 30 T Typ 25 C 25 yp a amp Low Voltage Detection Range Normal Operating Range Vpp V FIGURE 23 32 AlPD BOR vs VDD 40 C TO 125 C SLEEP MODE BORV1 BORVO z 11 2V Typical statistical mean 25 C Maximum mean 36 40 C to 125 C x Minimum mean 36 40 C to 125 C Max 125 C Device may be in Reset Device is Operating L VDD V DS39605C page 284 2004 Microchip Technology Inc PIC18F1220 1320 FIGURE 23 33 AlPD A D 40 C TO 125 C SLEEP MODE A D ENABLED NOT CONVERTING 10 T Max 85 C 3 0 1 2 0 01 Typical statistical mean 25 C Maximum mean 36 40 C to 125 C T 25 C Minimum mean 3o 40 C to 125 C yp 0 001 VDD V FIGURE 23 34 AVERAGE Fosc vs VDD FOR VARIOUS R s EXTERNAL RC MODE C 2
2. BRA Unconditional Branch BSF Bit Set f Syntax abel BRA n Syntax abel BSF fjb a Operands 1024 lt n x 1023 Operands 0 lt f lt 255 Operation PC 2 2n PC lt Li 0 Status Affected None Encodi Operation 1 gt f lt b gt ncoaing 1101 0 Bole eee aoe Status Affected None Description Add the 2 s complement number On to the PC Since the PC will Encoding 1000 bbba ffff ffff have incremented to fetch the next Description Bit b in register f is set If a is 0 instruction the new address will be the Access Bank will be selected PC 2 2n This instruction is a overriding the BSR value If a 1 two cycle instruction then the bank will be selected as Words 1 per the BSR value Cycles 2 Words 1 Q Cycle Activity Cycles 1 Q1 Q2 Q3 Q4 Q Cycle Activity Decode Read literal Process Write to PC Q1 Q2 Q3 Q4 n Data Decode Read Process Write No No No No register f Data register f operation operation operation operation Example BSF FLAG REG 7 Example HERE BRA Jump Before Instruction F FLAG REG 0x0A Before Instruction PC address HERE After Instruction FLAG REG 0x8A After Instruction PC address Jump 2004 Microchip Technology Inc DS39605C page 203 PIC18F1220 1320 BTFSC Syntax Operands Operation Status Affected Encodi
3. FIGURE 14 2 TIMER3 BLOCK DIAGRAM CONFIGURED IN 16 BIT READ WRITE MODE Data Bus lt 7 0 gt zx 8 TMR3H eu BN Write TMR3L Read TMR3L Vi d L CCP Special Event Trigger Set TMR3IF Flag bt 814 V TMR3 V ESS Synchronized on Overflow Timer3 CLR Clock Input High Byte TMR3L To Timer1 Clock Input TMR3ON e d OnOf T3SYNG T10SO D gt T13CKI i 3C Prescaler Synchronize ENE T1OSCEN Fosc 4 1 2 4 8 f det Enable a Internal o T1OSI x Oscillator Clock A 2 Peripheral DEEE ER T3CKPS1 T3CKPSO Clocks Note 1 When the T1OSCEN bit is cleared the inverter and feedback resistor are turned off This eliminates power drain TMR3CS DS39605C page 112 2004 Microchip Technology Inc PIC18F1220 1320 14 2 Timer1 Oscillator The Timer1 oscillator may be used as the clock source for Timer3 The Timer1 oscillator is enabled by setting the TIOSCEN T1CON lt 3 gt bit The oscillator is a low power oscillator rated for 32 kHz crystals See Section 12 2 Timer1 Oscillator for further details 14 3 Timer3 Interrupt The TMRS register pair TMR3H TMR3L increments from 0000h to FFFFh and rolls over to 0000h The TMR3 interrupt if enabled is generated on overflow which is latched in interrupt flag bit TMR3IF PIR2 12 This interrupt can be enabled disabled by setting clearing TMR3 Interru
4. FIGURE 3 3 TRANSITION TIMING TO PRI IDLE MODE ar ce a a a obec See te OS Bch ee eS ee os aaa nummum ee TN ASE EE TS EE PC Foe FIGURE 3 4 TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE Qt a Q3 Qm ose E a PU Sar up Day E Peripheral mA Ly ora ES ur Wake Event 2004 Microchip Technology Inc DS39605C page 23 PIC18F1220 1320 3 3 2 SEC IDLE MODE When a wake event occurs the peripherals continue to In SEC IDLE mode the CPU is disabled but the be clocked from the Timer1 oscillator After a 10 us SET NU as delay following the wake event the CPU begins exe peripherals continue to be clocked from the Timer1 2 oscillator This mode is entered by setting the Idle bit cuting code being cl cked by the Timert oscillator ne modifying bits SCS1 SCS0 01 and executing n microcontroller operates in SEC RUN mode until the SLEEP instruction When the clock source is switched primary clock becomes ready nenge pimay Os see Figure 3 5 to the Timert oscillator the primary becomes ready a clock switchback to the primary clock den occurs see Figure 3 6 When the clock switch is com eu reo es plete the T1RUN bitis cleared the OSTS bit is set and the primary clock is providing the system clock The IDLEN and SCS bits are not affected by the wake up The Timer1 oscill
5. a m s enu 2004 Microchip Technology Inc DS39605C page 97 PIC18F1220 1320 TABLE 10 3 PORTB FUNCTIONS Name Bit Buffer Function RBO AN4 INTO bit 0 TTLO STA Input output port pin analog input or external interrupt input 0 RB1 AN5 TX CK INT1 biti TTL ST2 Input output port pin analog input Enhanced USART Asynchronous Transmit Addressable USART Synchronous Clock or external interrupt input 1 RB2 P1B INT2 bit2 TTL ST input output port pin or external interrupt input 2 Internal software programmable weak pull up RB3 CCP1 P1A bit3 TTL ST Input output port pin or Capturet input Compare1 output PWM output Internal software programmable weak pull up RB4 AN6 RX DT KBIO bit4 TTL ST input output port pin with interrupt on change analog input Enhanced USART Asynchronous Receive or Addressable USART Synchronous Data RB5 PGM KBI1 bit5 TTL ST Input output port pin with interrupt on change Internal software programmable weak pull up Low Voltage ICSP enable pin RB6 PGC T10SO T13CKI bite TTL ST S9 input output port pin with interrupt on change Timer1 P1C KBI2 Timer3 clock input or Timertoscillator output Internal software programmable weak pull up Serial programming clock RB7 PGD T10SI P1D KBI3 bit7 TTL ST Input output port pin with interrupt on change or Tim
6. P1A Modulated 5 a Delay Delay 1o Half Bridge P1B Modulated f P1A Active Full Bridge P1B Inactive LS 01 Forward P1C Inactive i P1D Modulated P1A Inactive i i i iw P1B Modulated iy Full Bridge f 1 Reverse em f P1C Active P1D Inactive Relationships Period 4 Tosc PR2 1 TMR2 Prescale Value Duty Cycle Tosc CCPR1L lt 7 0 gt CCP1CON lt 5 4 gt TMR2 Prescale Value Delay 4 Tosc PWM1CON lt 6 0 gt Note 1 Dead band delay is programmed using the PWM1CON register Section 15 5 6 Programmable Dead Band Delay 2004 Microchip Technology Inc DS39605C page 121 PIC18F1220 1320 15 5 4 HALF BRIDGE MODE In the Half Bridge Output mode two pins are used as outputs to drive push pull loads The PWM output signal is output on the RB3 CCP1 P1A pin while the complementary PWM output signal is output on the RB2 P1B INT2 pin Figure 15 6 This mode can be used for half bridge applications as shown in Figure 15 7 or for full bridge applications where four power switches are being modulated with two PWM signals In Half Bridge Output mode the programmable dead band delay can be used to prevent shoot through current in half bridge power devices The value of bits PDC6 PDCO PWM1CON lt 6 0 gt sets the number of instruction cycles before the output is dri
7. IORLW Inclusive OR literal with W Syntax label IORLW k Operands 0 lt k lt 255 Operation W OR k gt W Status Affected N Z Encoding 0000 1001 kkkk kkkk Description The contents of W are OR ed with the eight bit literal K The result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to W literal k Data Example IORLW 0x35 Before Instruction W Ox9A After Instruction W OxBF IORWF Inclusive OR W with f Syntax label IORWF f d a Operands 0 lt f lt 255 de 0 1 ae 0 1 Operation W OR f 2 dest Status Affected N Z Encoding 0001 ooda ffff ffff Description Inclusive OR W with register f If d is 0 the result is placed in W If d is 1 the result is placed back in register f default If a is o the Access Bank will be selected over riding the BSR value If a 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example IORWF RESULT W Before Instruction RESULT W 0x13 0x91 After Instruction RESULT W 0x13 0x93 DS39605C page 214 2004 Microchip Technology Inc PIC18F1220 1320 LFSR Load FSR Syntax l
8. 2004 Microchip Technology Inc DS39605C page 137 PIC18F1220 1320 TABLE 16 3 BAUD RATES FOR ASYNCHRONOUS MODES CONTINUED SYNC 0 BRGH 1 BRG16 1 or SYNC 1 BRG16 1 DE Fosc 40 000 MHz Fosc 20 000 MHz Fosc 10 000 MHz Fosc 8 000 MHz K Actual SPBRG Actual 96 SPBRG Actual 96 SPBRG Actual SPBRG Rate Error value Rate Error value Rate Error value Rate Error value K decimal K decimal K decimal K decimal 0 3 0 300 0 00 33332 0 300 0 00 16665 0 300 0 00 8332 300 0 01 6665 1 2 1 200 0 00 8332 1 200 0 02 4165 1 200 0 02 2082 1200 0 04 1665 2 4 2 400 0 02 4165 2 400 0 02 2082 2 402 0 06 1040 2400 0 04 832 9 6 9 606 0 06 1040 9 596 0 03 520 9 615 0 16 259 9615 0 16 207 19 2 19 193 0 03 520 19 231 0 16 259 19 231 0 16 129 19230 0 16 103 57 6 57 803 0 35 172 57 471 0 22 86 58 140 0 94 42 57142 0 79 34 115 2 114 943 0 22 86 116 279 0 94 42 113 636 1 36 21 117647 2 12 16 SYNC 0 BRGH 1 BRG16 1 or SYNC 1 BRG16 1 NE Fosc 4 000 MHz Fosc 2 000 MHz Fosc 1 000 MHz K Actual SPBRG Actual 96 SPBRG Actual 96 SPBRG Rate Error value Rate Error value Rate Error value K decimal K decimal K decimal 0 3 0 300 0 01 3332 300 0 04 1665 300 0 04 832 1 2 1 200 0 04 832 1201 0 16 415 1201 0 16 207 2 4 2 404 0 16 415 2403 0 16 207 2403 0 16 103 9 6 9 615 0 16 103 9615 0 16 51 9615 0 16 25 19 2 19 231
9. BZ Branch if Zero CALL Subroutine Call Syntax abel BZ n Syntax abel CALL k s Operands 128 lt n lt 127 Operands O lt k lt 1048575 Operation if Zero bit is 1 se 0 1 PC 2 2n 5 PC Operation PC 4 gt TOS Status Affected None p Ed nd gt if s Encoding 1110 0000 nnnn nnnn W gt WS Description If the Zero bit is 1 then the Status STATUSS program will branch BSR gt BSRS The 2 s complement number 2n is Status Affected None added to the PC Since the PC will have incremented to fetch the next Encoding instruction the new address will be Tst word k lt 7 0 gt TTO a RARE kkkko PC 2 2n This instruction is then 2nd word k lt 19 8 gt 1111 ikiskkk i kkkk kkkkg a two cycle instruction Description Subroutine call of entire 2 Mbyte Words 1 memory range First return address PC 4 is pushed onto Cycles 1 2 the return stack If s 1 the W Q Cycle Activity Status and BSR registers are also If Jump pushed into their respective Q1 Q2 Q3 Q4 shadow registers WS STATUSS Decode Read literal Process Write to PC and BSRS If s 0 no update n Data occurs default Then the 20 bit No No No No value k is loaded into PC 20 1 gt operation operation operation operation CALL is a two cycle instruction If No Jump Words 2 Q1 Q2 Q3 Q4 Cycles 2 Decode Read literal Process No Q Cycle Activity n Data operation
10. d J P J BE 3L DS39605C page 142 2004 Microchip Technology Inc 16 3 2 EUSART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 16 5 The data is received on the RB4 AN6 RX DT KBIO pin and drives the data recovery block The data recovery block is actually a high speed shifter operating at x16 times the baud rate whereas the main receive serial shifter operates at the bit rate or at Fosc This mode would typically be used in RS 232 systems To set up an Asynchronous Reception 1 ook w 10 FIGURE 16 5 Initialize the SPBRGH SPBRG registers for the appropriate baud rate Set or clear the BRGH and BRG16 bits as required to achieve the desired baud rate Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN If interrupts are desired set enable bit RCIE If 9 bit reception is desired set bit RX9 Enable the reception by setting bit CREN Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set Read the RCSTA register to get the 9th bit if enabled and determine if any error occurred during reception Read the 8 bit received data by reading the RCREG register If any error occurred clear the error by clearing enable bit CREN If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are set 16 3 3
11. CE n 1 c i PN Voy H p F S A1 Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 20 20 Pitch p 026 0 65 Overall Height A 079 2 00 Molded Package Thickness A2 065 069 073 1 65 1 75 1 85 Standoff A1 002 0 05 Overall Width E 291 307 323 7 40 7 80 8 20 Molded Package Width E1 197 209 220 5 00 5 30 5 60 Overall Length D 272 283 289 295 7 20 7 50 Foot Length L 022 030 037 0 55 0 75 0 95 Lead Thickness c 004 010 0 09 0 25 Foot Angle f 0 4 8 0 4 8 Lead Width B 009 015 0 22 0 38 Controlling Parameter Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MO 150 Drawing No C04 072 Revised 11 03 03 V AU K c M QE C QME 3L DS39605C page 290 2004 Microchip Technology Inc PIC18F1220 1320 28 Lead Plastic Quad Flat No Lead Package ML 6x6 mm Body Punch
12. Compares the contents of data memory location f to the contents of W by performing an unsigned subtraction If the contents of f are greater than the contents of WREG then the fetched instruction is discarded and a NOP is executed instead making this a two cycle instruction If a is 0 the Access Bank will be selected overriding the BSR value If a 1 then the bank will be selected as per the BSR value default 1 1 2 Note 3 cycles if skip and followed by a 2 word instruction CPFSLT Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Compare f with W skip if f W label CPFSLT f a 0 lt f lt 255 ae 0 1 f W skip if f W unsigned comparison None 0110 000a EEEE ffff Compares the contents of data memory location f to the contents of W by performing an unsigned subtraction If the contents of f are less than the contents of W then the fetched instruction is discarded and a NOP is executed instead making this a two cycle instruction If a is o the Access Bank will be selected If a is 1 the BSR will not be overridden default 1 1 2 Note 3 cycles if skip and followed by a 2 word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process
13. RAO ANO 1 1 26 RAO 1 0 ST Digital I O ANO Analog Analog input 0 RA1 AN1 LVDIN 2 2 27 RA1 1 0 ST Digital I O AN1 l Analog Analog input 1 LVDIN l Analog Low Voltage Detect input RA2 AN2 VREF 6 7 7 RA2 1 0 ST Digital 1 0 AN2 Analog Analog input 2 VREF Analog A D reference voltage low input RA3 AN3 VREF 7 8 8 RAS3 1 0 ST Digital I O AN3 Analog Analog input 3 VREF Analog A D reference voltage high input RA4 TOCKI 3 3 28 RA4 O ST OD Digital I O Open drain when configured as output TOCKI ST TimerO external clock input RA5 See the MCLR VPP RAS pin RA6 See the OSC2 CLKO RA6 pin RA7 See the OSC1 CLKI RA7 pin Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power OD Open drain no P diode to VDD DS39605C page 8 2004 Microchip Technology Inc PIC18F1220 1320 TABLE 1 2 PIC18F1220 1320 PINOUT 1 0 DESCRIPTIONS CONTINUED Pin Number Pin Buffer dr Pin Name Description PDIP Type Type SOIC SSOP QFN PORTB is a bidirectional I O port PORTB can be software programmed for internal weak pull ups on all inputs RBO AN4 INTO 8 9 9 RBO 1 0 TTL Digital I O AN4 Analog Analog input 4 INTO ST External interrupt O RB1 ANS TX CK INT1 9 10 10 RB1 1 0 TTL Digital I O AN5 Analog Analog input 5 TX O EUSART asynchronous tra
14. matically repeat the A D acquisition period with minimal counter TABLE 17 2 SUMMARY OF A D REGISTERS g 5 7 z A Value on val e on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR all other Resets INTCON GIE PEIE TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 0000 0000 0000 GIEH GIEL PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMRAIF 000 000 000 000 PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE 000 000 000 000 IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMRAIP 111 111 111 111 PIR2 OSCFIF EEIF LVDIF TMR3IF 0 0 00 0 O 00 PIE2 OSCFIE EEIE LVDIE TMRSIE 0 0 00 0 O 00 IPR2 OSCFIP EEIP LVDIP TMR3IP 1 1 11 1 1 11 ADRESH A D Result Register High Byte XXXX XXXX uuuu uuuu ADRESL A D Result Register Low Byte XXXX XXXX uuuu uuuu ADCONO VCFG1 VCFGO CHS2 CHS1 CHSO GO DONE ADON 00 0 0000 00 0 0000 ADCON 1 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFGO 000 0000 000 0000 ADCON2 ADFM ACQT2 ACQT1 ACQTO ADCS2 ADCS1 ADCSO 0 00 0000 0 00 0000 PORTA RA7 RAG RAs RA4 RA3 RA2 RA1 RAO qqox 0000 uuou 0000 TRISA TRISA79 TRISA6 PORTA Data Direction Register qq 1 1111 11 1 1111 PORTB Read PORTB pins Write LATB Latch XXXX XXXX UUUU uuuu TRISB PORTB Data Direction Register 1111 1111 1111 1111 LATB PORTB Output Data Latch XXXX XXXX uuuu uuuu Legend x
15. CCPIIE TMR2IE TMR1IE bit 7 Unimplemented Read as 0 ADIE A D Converter Interrupt Enable bit 1 Enables the A D interrupt 0 Disables the A D interrupt RCIE EUSART Receive Interrupt Enable bit 1 Enables the EUSART receive interrupt 0 Disables the EUSART receive interrupt TXIE EUSART Transmit Interrupt Enable bit 1 Enables the EUSART transmit interrupt 0 Disables the EUSART transmit interrupt Unimplemented Read as 0 CCP1IE CCP1 Interrupt Enable bit 1 Enables the CCP1 interrupt 0 Disables the CCP1 interrupt TMR2IE TMR2 to PR2 Match Interrupt Enable bit 1 Enables the TMR2 to PR2 match interrupt 0 Disables the TMR2 to PR2 match interrupt TMR1IE TMR1 Overflow Interrupt Enable bit 1 Enables the TMR1 overflow interrupt 0 Disables the TMR1 overflow interrupt bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown DS39605C page 80 2004 Microchip Technology Inc PIC18F1220 1320 REGISTER 9 7 PIE2 PERIPHERAL INTERRUPT ENABLE REGISTER 2 R W 0 U 0 U 0 R W 0 U 0 R W 0 R W 0 U 0 OSCFIE EEIE LVDIE TMRSIE bit 7 bit 0 bit 7 OSCFIE Oscillator Fail Interrupt Enable bit 1 Enabled 0 Disabled bit 6 5 Unimplemented Read as 0 bit 4 EEIE Data EEPROM Flash Write Operation Interrupt Enable bit
16. 65 RAGING ocior tree ere te e END Re 61 Table Late sr dan Rr 60 Table Pointer nce ooo dann dete des 60 Boundaries Based on Operation 60 Table Pointer Boundaries Table Reads and Table Writes 57 Write Sequence 000 00 0 eeen 63 Writing to Unexpected Termination ssssse 65 Write Verify i ere nete 65 G GOTO sn edat e dee eed 212 H Hardware Multiplier seen 71 Introduction ssessssssseeeeneeeeeenenenn nene 71 Operation Performance Comparison 71 l VO Pons 25 345 stir fU ODER RUE rre 87 ID Eocations onasi h dee dee 171 188 In Circuit Debugger ss In Circuit Serial Programming ICSP e Indirect Addressing eene INDF and FSR Registers sieneen Operation Indirect Addressing Operation esses Indirect File Operand ss INESNZ itti oret aerea Initialization Conditions for All Registers Instruction Cycle esses Instruction Flow Pipelining eee CLRWDT GOME P CPFSEQ CPFSGT CPFSLT DAME ee Sh leo PPP DCFSNZ DECF rM DECFSZ General Format GOTO E NL me Aa Game cee hr misent is INCFSZ INFSNZ 2004 Microchip Technology Inc DS39605C page 299 PIC18F1220 1320 Migration from Mid Range
17. 2004 Microchip Technology Inc DS39605C page 281 PIC18F1220 1320 FIGURE 23 27 VoL vs lo OVER TEMPERATURE 40 C TO 125 C VDD 5 0V 1 0 0 9 0 8 0 7 0 6 Max 85 C a 0 5 o gt 0 4 0 3 0 2 ay aA 0 0 0 5 10 15 20 25 lot mA FIGURE 23 28 AIPD TIMER1 OSCILLATOR 10 C TO 70 C SLEEP MODE TMR1 COUNTER DISABLED Max 10 C to 70 C Typical statistical mean 25 C Maximum mean 30 40 C to 125 C Minimum mean 3o 40 C to 125 C VDD V DS39605C page 282 2004 Microchip Technology Inc PIC18F1220 1320 FIGURE 23 29 AIPD FSCM vs VoD OVER TEMPERATURE PRI IDLE MODE EC OSCILLATOR AT 32 kHz 40 C TO 125 C 4 5 4 0 Max 40 C 3 5 3 0 D a Typ 25 C AIPD pA D e Typical statistical mean 25 C 1 0 Maximum mean 36 40 C to 125 C Minimum mean 3o 40 C to 125 C 0 5 0 0 voo V FIGURE 23 30 AlPD WDT 40 C TO 125 C SLEEP MODE ALL PERIPHERALS DISABLED Typical statistical mean 25 C Maximum mean 3o 40 C to 125 C Minimum mean 3o 40 C to 125 C Max 125 C AIPD uA Max 85 C VDD V EGET EDO M ES MEE 2 A e occ c
18. RD PORTB Schmitt Trigger Input Buffer INT1 CK Input o Analog Input Mode To A D Converter E Note 1 O pins have diode protection to VDD and Vss 2 To enable weak pull ups set the appropriate TRIS bit s and clear the RBPU bit INTCON2 7 2004 Microchip Technology Inc DS39605C page 91 PIC18F1220 1320 FIGURE 10 9 BLOCK DIAGRAM OF RB2 P1B INT2 PIN VDD RBPUO RBPU y p Weak Pull up P1B Enable P1B Data P1B D Tri State 1 Auto Shutdown Data Bus Data Latch js a es WR LATB or RB2 pin PORTB CK E TRIS Latch Wasim e D Q b TTL WR TRISB Input CKN Buffer t 5 RD TRISB RD LATB lt q Q D RD PORTB EN Schmitt INT2 Input Trigger RD PORTB Note 1 O pins have diode protection to VDD and Vss 2 To enable weak pull ups set the appropriate TRIS bit s and clear the RBPU bit INTCON2 lt 7 gt DS39605C page 92 2004 Microchip Technology Inc PIC18F1220 1320 FIGURE 10 10 BLOCK DIAGRAM OF RB3 CCP1 P1A PIN ECCP1 pin Output Enable T ECCP1 4 pin Input Enable VDD eR RR 2 ES MED RBPU d irp Weak LE Pull up P1A C Tri State Auto Shutdown ECCP1 P1A Data Out
19. TBLPTRU TBLPTRH TBLPTRL y Program Memory TBLPTR Table Latch 8 bit TABLAT REL Note 1 Table Pointer points to a byte in program memory 2004 Microchip Technology Inc DS39605C page 57 PIC18F1220 1320 FIGURE 6 2 TABLE WRITE OPERATION Instruction TBLWT Program Memory Holding Registers Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory TBLPTR Table Latch 8 bit TABLAT Note 1 Table Pointer actually points to one of eight holding registers the address of which is determined by TBLPTRL lt 2 0 gt The process for physically writing data to the program memory array is discussed in Section 6 5 Writing to Flash Program Memory 6 2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions These include the e EECON register EECON register TABLAT register TBLPTR registers 6 2 1 EECON1 AND EECON2 REGISTERS EECON is the control register for memory accesses EECON2 is not a physical register Reading EECON2 will read all o s The EECON2 register is used exclusively in the memory write and erase sequences Control bit EEPGD determines if the access will be to program or data EEPROM memory When clear operations will access the data EEPROM memory When set program memory is accessed Control bit CF
20. 2004 Microchip Technology Inc DS39605C page 307 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480 792 7277 Technical Support 480 792 7627 Web Address www microchip com Atlanta 3780 Mansell Road Suite 130 Alpharetta GA 30022 Tel 770 640 0034 Fax 770 640 0307 Boston 2 Lan Drive Suite 120 Westford MA 01886 Tel 978 692 3848 Fax 978 692 3821 Chicago 333 Pierce Road Suite 180 Itasca IL 60143 Tel 630 285 0071 Fax 630 285 0075 Dallas 16200 Addison Road Suite 255 Addison Plaza Addison TX 75001 Tel 972 818 7423 Fax 972 818 2924 Detroit Tri Atria Office Building 32255 Northwestern Highway Suite 190 Farmington Hills MI 48334 Tel 248 538 2250 Fax 248 538 2260 Kokomo 2767 S Albright Road Kokomo IN 46902 Tel 765 864 8360 Fax 765 864 8387 Los Angeles 25950 Acero St Suite 200 Mission Viejo CA 92691 Tel 949 462 9523 Fax 949 462 9608 San Jose 1300 Terra Bella Avenue Mountain View CA 94043 Tel 650 215 1444 Fax 650 961 0286 Toronto 6285 Northam Drive Suite 108 Mississauga Ontario L4V 1X5 Canada Tel 905 673 0699 Fax 905 673 6509 ASIA PACIFIC Australia Microchip Technology Australia Pty Ltd Unit 32 41 Rawson Street Epping 2121 NSW Sydney Australia Tel 61 2 9868 6733 Fax 61 2 9868 6755 China Beijing Unit 706B Wan Tai
21. TABLE 16 7 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION s a Value on value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR all other Resets INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000x 0000 000u PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMRAIF 000 000 000 000 PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE 000 000 000 000 IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMRAIP 111 111 111 111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 00x 0000 00x TXREG EUSART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCTL RCIDL SCKP BRG16 WUE ABDEN 1 1 0 00 1 1 0 00 SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend x unknown unimplemented read as 0 Shaded cells are not used for synchronous master transmission PIGET M RUE AER NN SS J ec Y ul 2004 Microchip Technology Inc DS39605C page 149 PIC18F1220 1320 16 4 2 EUSART SYNCHRONOUS MASTER 3 Ensure bits CREN and SREN are clear RECEPTION 4 If interrupts are desired set enable bit RCIE Once Synchronous mode is selected reception
22. Stack Level 1 Stack Level 31 Reset Vector 0000h 4 High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On Chip Program Memory 1FFFh 2000h S Q a 2 o E 0 2 o 2 D Read 0 1FFFFFh 200000h 2004 Microchip Technology Inc DS39605C page 41 PIC18F1220 1320 5 2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur The PC Program Counter is pushed onto the stack when a CALL Or RCALL instruction is executed or an interrupt is Acknowledged The PC value is pulled off the stack on a RETURN RETLW Or a RETFIE instruction PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions The stack operates as a 31 word by 21 bit RAM and a 5 bit stack pointer with the Stack Pointer initialized to 000008 after all Resets There is no RAM associated with Stack Pointer 000008 This is only a Reset value During a CALL type instruction causing a push onto the stack the Stack Pointer is first incremented and the RAM location pointed to by the Stack Pointer STKPTR register is written with the contents of the PC already pointing to the instruction following the CALL During a RETURN type instruction causing a pop from the stack the contents of the RAM location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer
23. j f 4 Program 0 1 Counter PC _ Xoo Pc 2 y PC 4 X Pcre X PO 8 Y Wake Event OSTS bit Set Note 1 TOST 1024 TOSC TPLL 2 ms approx These intervals are not shown to scale u BR E ie SL DS39605C page 22 2004 Microchip Technology Inc PIC18F1220 1320 3 3 1 PRI IDLE MODE This mode is unique among the three Low Power Idle modes in that it does not disable the primary system clock For timing sensitive applications this allows for the fastest resumption of device operation with its more accurate primary clock source since the clock source does not have to warm up or transition from another oscillator PRI IDLE mode is entered by setting the IDLEN bit clearing the SCS bits and executing a SLEEP instruc tion Although the CPU is disabled the peripherals continue to be clocked from the primary clock source specified in Configuration Register 1H The OSTS bit remains set in PRI IDLE mode see Figure 3 3 When a wake event occurs the CPU is clocked from the primary clock source A delay of approximately 10 us is required between the wake event and code execution starts This is required to allow the CPU to become ready to execute instructions After the wake up the OSTS bit remains set The IDLEN and SCS bits are not affected by the wake up see Figure 3 4
24. py Symbol Characteristic Min Max Units Conditions 130 TaD A D Clock Period PIC18F1X20 1 6 2065 us TOSC based VREF gt 3 0V PIC18LF1X20 3 0 200 us Tosc based VREF full range PIC18F1X20 2 0 6 0 us A D RC mode PIC18LF1X20 3 0 9 0 us A D RC mode 131 TCNV Conversion Time 11 12 TAD not including acquisition time Note 1 132 TACQ Acquisition Time Note 3 15 x us 40 C lt Temp lt 125 C 10 us 0 C lt Temp 125 C 135 Tswc Switching Time from Convert Sample Note 4 136 TAMP Amplifier Settling Time Note 2 1 us This may be used if the new input voltage has not changed by more than 1 LSb i e 5 mV 9 5 12V from the last sampled voltage as stated on CHOLD Note 1 ADRES register may be read on the following TCY cycle 2 See Section 17 0 10 Bit Analog to Digital Converter A D Module for minimum conditions when input voltage has changed more than 1 LSb 3 Thetime for the holding capacitor to acquire the New input voltage when the voltage changes full scale after the conversion AVDD to AVSS or AVss to AVDD The source impedance RS on the input channels is 500 4 Onthe next Q4 cycle of the device clock 5 Thetime of the A D clock period is dependent on the device frequency and the TAD clock divider 2004 Microchip Technology Inc DS39605C page 267 PIC18F1220 1320 NOTES DS39605C page 268 2004 Microchip Technology Inc PIC18F1220 1320 23 0 DC AN
25. Description Words Cycles Table Read label TBLRD None if TBLRD Prog Mem TBLPTR TABLAT TBLPTR No Change if TBLRD Prog Mem TBLPTR gt TABLAT TBLPTR 1 gt TBLPTR if TBLRD Prog Mem TBLPTR gt TABLAT TBLPTR 1 2 TBLPTR if TBLRD TBLPTR 1 gt TBLPTR Prog Mem TBLPTR gt TABLAT None 0000 0000 0000 10nn nn O 1 2 34 This instruction is used to read the contents of Program Memory P M To address the program memory a pointer called Table Pointer TBLPTR is used The TBLPTR a 21 bit pointer points to each byte in the program memory TBLPTR has a 2 Mbyte address range TBLPTR 0 0 Least Significant Byte of Program Memory Word TBLPTR 0 1 Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows no change post increment post decrement pre increment 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No No No operation operation operation No operation No operation No No operation Read Program operation Write Memory TABLAT TBLRD Table Read Continued Example 1 TBLRD Before Instruction TABLAT E 0x55 TBLPTR 0x00A356 MEMORY 0x00A356 0x34 After Instruction TABLAT 0x34 TBLPTR 2 0x00A357 Example 2 TBLRD Before Instruction TABLAT OxAA TBLPTR E 0x01A35
26. Lower Consumption in Key Modules The power requirements for both Timeri and the Watchdog Timer have been reduced by up to 8095 with typical values of 1 1 and 2 1 uA respectively 1 1 2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F1220 1320 family offer nine different oscillator options allowing users a wide range of choices in developing application hardware These include Four Crystal modes using crystals or ceramic resonators Two External Clock modes offering the option of using two pins oscillator input and a divide by 4 clock output or one pin oscillator input with the second pin reassigned as general I O Two External RC Oscillator modes with the same pin options as the External Clock modes An internal oscillator block which provides an 8 MHz clock 2 accuracy and an INTRC source approximately 31 kHz stable over temperature and VDD as well as a range of 6 user selectable clock frequencies from 125 kHz to 4 MHz for a total of 8 clock frequencies Besides its availability as a clock source the internal oscillator block provides a stable reference source that gives the family additional features for robust operation Fail Safe Clock Monitor This option constantly monitors the main clock source against a reference signal provided by the internal oscillator If a clock fail ure occurs the controller is switched to the internal oscillator block allowing for co
27. Operation During Code Protect The microcontroller itself can both read and write to the internal data EEPROM regardless of the state of the code protect configuration bit Refer to Section 19 0 7 8 Using the Data EEPROM The data EEPROM is a high endurance byte address able array that has been optimized for the storage of fre quently changing information e g program variables or other data that are updated often Frequently changing values will typically be updated more often than specifi cation D124 If this is not the case an array refresh must be performed For this reason variables that change infrequently such as constants IDs calibration etc Special Features of the CPU for additional information should be stored in Flash program memory A simple data EEPROM refresh routine is shown in Example 7 3 Note If data EEPROM is only used to store constants and or data that changes rarely an array refresh is likely not required See specification D124 EXAMPLE 7 3 DATA EEPROM REFRESH ROUTINE CLRF EEADR Start at address O0 BCF EECON1 CFGS Set for memory BCF EECON1 EEPGD Set for Data EEPROM BCF INTCON GIE Disable interrupts BSF EECON1 WREN Enable writes Loop Loop to refresh array BSF EECON1 RD Read current address MOVLW 55h MOVWF EECON2 Write 55h MOVLW AAh MOVWF EECON2 Write AAh BSF EECON1 WR Set WR bit
28. 12 1 Timer1 can operate in one of these modes Timer1 Operation As a timer As a synchronous counter As an asynchronous counter The operating mode is determined by the clock select bit TMR1CS T1CON 1 When TMR1CS 0 Timer1 increments every instruc tion cycle When TMR1CS 1 Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator if enabled When the Timer1 oscillator is enabled T1OSCEN is set the RB7 PGD T1OSI P1D KBI3 and RB6 T1OSO T13CKI P1C KBI2 pins become inputs That is the TRISB7 TRISB6 values are ignored and the pins read as 0 Timer1 also has an internal Reset input This Reset can be generated by the CCP module see Section 15 4 4 Special Event Trigger FIGURE 12 1 TIMER1 BLOCK DIAGRAM TMRHIF CCP Special Event Trigger Overflow Interrupt TMR1 m Synchronized Flag bit CLR Clock Input TMR1H TMR1L pmi 4 1 TMR1ON On Off T1SYNC risckmioso r 1 ac Prescaler Synchronize T1OSI Fosc 4 12 4 det xX Oscillator Internal o D ah Glock 2 Peripheral Clocks T1CKPS1 T1CKPSO TMR1CS Note 1 When enable bit T1 OSCEN is cleared the inverter and feedback resistor are turned off This eliminates power drain FIGURE 12 2 TIMER1 BLOCK DIAGRAM 16 BIT READ WRITE MODE Data Bus lt 7 0 gt 8 TMR1H LX gu BN Wri
29. Shift Clock J i i omm TX pin A Start Bit Bio Bit 1 Stop Bit lt Break en TXIF bit 2 TRMT bit C i y SENDB DS39605C page 147 2004 Microchip Technology Inc PIC18F1220 1320 16 4 EUSART Synchronous Master Mode The Synchronous Master mode is entered by setting the CSRC bit TXSTA 7 In this mode the data is transmitted in a half duplex manner i e transmission and reception do not occur at the same time When transmitting data the reception is inhibited and vice versa Synchronous mode is entered by setting bit SYNC TXSTA lt 4 gt In addition enable bit SPEN RCSTA 7 is set in order to configure the RB1 AN5 TX CK INT1 and RB4 AN6 RX DT KBIO I O pins to CK clock and DT data lines respectively The Master mode indicates that the processor trans mits the master clock on the CK line Clock polarity is selected with the SCKP bit BAUDCTL 5 setting SCKP sets the Idle state on CK as high while clearing the bit sets the Idle state as low This option is provided to support Microwire devices with this module EUSART SYNCHRONOUS MASTER TRANSMISSION