EON EN29F002 EN29F002N 2 Megabit (256K x 8-bit) Flash Memory
Contents
1. 29 002 29 002 ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages 65 C to 125 C Ambient Temperature with Power Applied 55 C to 125 G Voltage with Respect to Ground Voc Note 1 0 5 V to 7 0 V 9 OE Note 2 0 5 V to 11 5 V All other pins Note 1 0 5 V to Vec 0 5V Output Short Circuit Current Note 3 200 mA Notes 1 Minimum DC voltage on input or I O pins is 0 5 V During voltage transitions inputs may undershoot Vss to 1 0V for periods of up to 50 ns and to 2 0 V for periods of up to 20 ns See Left Figure below Maximum DC voltage on input and I O pins is V cc 0 5 V During voltage transitions input and I O pins may overshoot to Vcc 2 0 V for periods up to 20 ns See Right Figure below 2 Minimum DC input voltage on A9 pin is 0 5 V During voltage transitions 9 and may undershoot Vss to 1 0V for periods of up to 50 ns and to 2 0 V for periods of up to 20 ns See Left Figure Maximum DC input voltage on A9 and OE is 11 5 V which may overshoot to 12 5 V for periods up to 20 ns 3 No more than one output shorted to ground at a time Duration of the short circuit should not be greater than one second Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these2. L X X X X X X HI Z 7 X X X X X X H A9 A8 A6 A1 DQ 0 7 H A9 A8 A6 M AO 2 H L L X USER MODE als vis m 215 0 gm e o E x x x mx x L VID L H L MANUFACTURER MANUFACTURER ID ID READ DEVICE ID L H L H VID L H L L H X DEVICE ID T B PROTECT PROTECT SECTOR UNPROTECT L L VID H VID x H H L X X WRITE L L H H A9 A8 A6 M 0 DIN 0 7 UNPROTECT NOTES 1 L Va H Vip 11 0V 0 5V 2 X Don care either Vin or Vit TABLE 4 DEVICE IDENTIFICTION 2M FLASH MANUFACTURER DEVICE ID TABLE 8 A6 A1 0 DQ 7 0 HEX READ L L L L MANUFACTURER ID MANUFACTURER ID 7 READ H L L L MANUFACTURER ID MANUFACTURER ID 1C READ DEVICE ID L L L H DEVICE ID Top Architecture 7F READ DEVICE ID H L L H DEVICE ID Top Architecture 92 READ DEVICE ID L L L H DEVICE ID Bottom Architecture 7F READ DEVICE ID H L L H DEVICE ID Bottom Architecture 97 E 29 002 29 002 USER MODE DEFINITIONS Reset Mode 29 002 features a Reset mode that resets the program and erase operation immediately to read mode If reset RESET L is executed when program or erase operation were in progress the program or erase which was terminated should be
3. Noise Pulse Protection Noise pulses less than 5ns OE CE or WE will neither initiate a write cycle nor change the command register Logical Inhibit If or writing is inhibited To initiate a write cycle CE and WE must be a logical zero If CE WE and OE are all logical zero not recommended usage it will be considered a write Sector Protection Unprotection When the device is shipped all sectors are unprotected Each sector can be separately protected against data changes Using hardware protection circuitry enabled at user s site with external programming equipment both program and erase operations may be disabled for any specified sector or combination of sectors Verification of write protection for a specific sector can be achieved with an Auto Select ID read command at location 02h where the address bits A17 A13 select the defined sector see Table 5 A logical 1 at means a protected sector and a logical 0 means an unprotected sector The Sector Unprotect disables sector protection in all sectors in one operation to implement code changes All sectors must be placed in protection mode using the protection algorithm mentioned above before unprotection can be executed Additional details on this feature are provided in a supplement which can be obtained by contacting a representative of Eon Silicon Devices Inc E 29 002 29 002 EMBEDDED ALGORI
4. 002 Device Code can be read as 7F 92 hex for 29 002 or as 7F 97 hex for 29 002 See Table 4 All identifiers for manufacturer and device codes possess odd parity with the DQ7 defined as the parity bit Write Mode Write is used for device programming and erase through the command register This mode is selected with CE WE L and OE H The contents of the command register are the inputs to the internal state machine The command register is a set of latches used to store the commands along with the addresses and data information needed to execute that command Address latching occurs on the falling edge of WE or CE whichever occurs later and data latching occurs on the rising edge of WE or CE whichever occurs first Temporary Sector Unprotect Mode 29 002 allows protected sectors to be temporarily unprotected for making changes to data stored in a protected sector in system n a for EN29F002N To activate the temporary sector unprotect the RESET pin must be set to a high voltage of Vip 11V In this mode protected sectors can be programmed or erased by selecting the sector addresses Once the high voltage Vip is removed from RESET pin all previously protected sectors will revert to their protected state RESET Hardware Reset Mode not available on EN29F002N Resetting the EN29F002 device is performed when the RESET pin is set to Vi and kept low for at least 500ns The internal state machine w
5. Program or Erase Command Sequence AP 29 002 EN29F002N SWITCHING WAVEFORMS continued Figure 11 RESET Timing Diagram RESET Figure 12 Alternate CE Controlled Write Operation Timings las Data Polling ADDRESSES EE PAX p WE OE d m TR Ek 9 G tves Notes PA is address of the memory location to be programmed PD is data to be programmed at byte address DQ7 is the output of the complement of the data written to the device Dour is the output of data written to the device Figure indicates last two bus cycles of four bus cycle sequence o RON E 29 002 29 002 ORDERING INFORMATION EN29F002 T 45 P TEMPERATURE RANGE Blank Commercial 0 C to 70 C Industrial 40 C to 85 C PACKAGE 32 Plastic DIP J 32 Plastic PLCC T 32 Plastic TSOP SPEED 45 45ns 55 55ns 70 70ns 90 90ns BOOT BLOCK ARCHITECTURE T Top Block B Bottom Block BASE PART NUMBER EN EON Silicon Devices 29F FLASH 5V 002 256K x 8 Blank with RESET function N without RESET function E z 29 002 29 002 Revisions List A Preliminary B 2001 07 03 Table 7 lcc3 is with RESET pin at full CMOS levels Pg 13 Logical Inhibit section now says that if CE WE and OE are all logical zero not recommended usage it will be considered a write VID is everywhere chan
6. T CARE when writing Erase Suspend or Erase Resume commands 29 002 takes 0 1 15 us to suspend erase operations after receiving Erase Suspend command Check completion of erase suspend by polling DQ7 and or DQ6 29 002 ignores redundant writes of erase suspend command EN29F0002 defaults to erase suspend read mode while an erase operation has been suspended While in erase suspend read mode EN29F002 allows reading data in any sector not undergoing sector erase which is treated as standard read mode Write the Resume command 30h to continue operation of Sector erase 29 002 ignores redundant writes of the Resume command En29F002 permits multiple suspend resume operations during sector erase Sector Protect and Unprotect The hardware sector protection feature disables both program and erase operations in any sector The hardware sector unprotection feature re enables both program and erase operation in previously protected sectors Sector protection unprotection must be implemented using programming equipment The procedure requires a high voltage Vip on address pin A9 and the control pins Contact Eon Silicon Devices Inc for an additional supplement on this feature E 29 002 29 002 WRITE OPERATION STATUS DQ7 DATA Polling The EN29F002 provides DATA Polling on DQ7 to indicate to the host system the status of the embedded operations The DATA Polling feature is active during the Byte Prog
7. trsp RESET Setup Time n a for EN29F002N E 3 29 002 29 002 Table 11 ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Comments sec Excludes 00H programming prior to erasure Chip Erase Time Byte Programming Time us Excludes system level overhead Chip Programming Time 2 5 Sec Minimum 100K cycles guaranteed Erase Program Endurance 100K cycles Table 12 LATCH UP CHARACTERISTICS Parameter Description Mn Max Input voltage with respect to Vss on A9 and OE and RESET 10 12 0 V Input voltage with respect to Vss on all other pins 1 0 V Vcc 1 0 V Vcc Current 100 mA 100 mA Note These are latch up characteristics and the device should never be put under these conditions Refer to Absolute Maximum ratings for the actual operating limits Table 13 32 PIN PLCC PIN CAPACITANCE 25 C 1 0MHz Test Setup Typ Unit CIN Input Capacitance VIN 0 4 6 pF COUT Output Capacitance 0 8 12 pF CIN2 Control Pin Capacitance VIN 0 8 12 pF Table 14 32 PIN TSOP PIN CAPACITANCE 25 C 1 0MHz Test Setup Typ Unit CIN Input Capacitance 0 6 7 5 pF COUT Output Capacitance 0 8 5 12 pF CIN2 Control Pin Capacitance VIN 0 7 5 9 pF E 3 29 002 29 002 Table 15 DATA RETENTION Parameter Description Test Conditions Min Uni
8. erasable read write non volatile flash memory Organized into 256K words with 8 bits per word the 2M of memory is arranged in seven sectors with top bottom configuration including one 16K Byte Boot Sector two 8K Byte Parameter sectors and four main sectors one 32K Byte and three 64K Byte Any byte be programmed typically at 1045 The 29 002 EN29F002N features 5 0V voltage read and write operation The access times are as fast as 45ns to eliminate the need for WAIT states in high performance microprocessor systems The EN29F002 EN29F002N has separate Output Enable OE Chip Enable CE and Write Enable WE controls which eliminate bus contention issues This device is designed to allow either single sector or full chip erase operation where each sector can be individually protected against program erase operations or temporarily unprotected to erase or program The device can sustain a minimum of 100K program erase cycles on each sector TABLE 1 PIN DESCRIPTION Pin Name Function 0 17 Addresses DQ0 DQ7 Data Input Outputs CE Chip Enable OE Output Enable WE Write Enable RESET Hardware Reset n a for Sector Unprotect EN29F002N Vcc Supply Voltage 10 Vss Ground TABLE 2 BLOCK ARCHITECTURE TOP BOOT BLOCK ADDRESSES 3C000h 3FFFFh 3A000h 3BFFFh 38000h 39FFFh 30000h 37FFFh 20000h 2FFFFh 10000h 1FFFFh 00000h OFFFFh MN 4 S
9. or any other conditions above those indicated in the operational sections of this specification is not implied Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability OPERATING RANGES Commercial C Devices Ambient Temperature 0 to 70 C Industrial I Devices Ambient Temperature 40 C to 85 C Vcc Supply Voltages Voc for 5 devices 4 75 V to 5 25 V Vcc for 10 devices 4 50 V to 5 50 V Operating ranges define those limits between which the functionality of the device is guaranteed D 2 Jf ns 20n amp 20 TOM Voc zv Wee HILS V 70 ne 20 na 20 n Maximum Negative Overshoot Maximum Positive Overshoot Waveform Waveform Table 7 DC Characteristics 0 C to 70 C or 40 C to 85 EN29F002 EN29F002N C Voc 5 0V 10 ee EE Parameter Test Conditions Min Max Uni t Input Leakage e OV Vin lt Vcc 5 Output Leakage Current 0V Vout lt Vcc WA ES Supply Current read TTL Byte Vii OE Vin 30 mA f 6MHz loce Supply Current Standby TTL CE Vin 1 0 mA Icc3 Supply Current Standby RESET CE 0 2V 5 0 hi A loc4 Supply Current Program or Erase Byte 2 Chip 30 traseinprogress VIL Input Low Voltage 0 5 V VIH Input
10. repeated since data will be corrupted This pin is not available for EN29F002N Standby Mode The 29 002 EN29F002N has a CMOS compatible standby mode which reduces the current to 1uA typical It is placed in CMOS compatible standby when CE and the RESET pins are at Voc 0 5 V CE pin only for EN29F002N The device also has a TTL compatible standby mode which reduces the maximum Vcc current to 1mA It is placed TTL compatible standby when CE and RESET pins are at Another method of entering standby mode uses only the RESET pin n a for EN29F002N When RESET pin is at Vss 0 3V the device enters CMOS compatible standby with current typically reduced to lt 1 uA When RESET pin is at Vi the device enters TTL compatible standby with current reduced to lt 1mA When in standby modes the outputs a high impedance state independent of theOE input Read Mode The EN29F002 EN29F002N has two control functions which must be satisfied in order to obtain data at the outputs Chip Enable CE is the power control and should be used for device selection Output Enable OE is the output control and should be used to gate data to the output pins provided the device is selected Read is selected when both CE and OE pins are held at Vi with the WE pin held at Address access time tcc is equal to the delay from stable addresses to valid output data Assuming that addresses are stable chip ena
11. twHwxs twHwH3 Chip Erase Operation 3 3 50 Rise Time to Vip o eee trp RESET Pulse Width 900 n a for EN29F002N SEDENS 4 4 RESET Setup Time n a for EN29F002N E 3 29 002 29 002 Table 10 AC CHARACTERISTICS Write Erase Program Operations Alternate CE Controlled Writes uoa Speed Options JEDEC Standard Description i tAVAV twc Write Cycle Time Min 45 55 70 90 ns tAVEL tas Address Setup Time Min 0 0 0 0 us teLax Address Hold Time Min 35 45 45 5 DVEH tps Data Setup Time Min 20 25 80 m m tox Data Hold Time Min 0 0 0 i toes Output Enable Setup Time Min 0 0 0 0 ns toEH Output Enable Read 1 0 x ji Hold Time Toggle and 10 10 10 10 10 Data Polling lcHEL Read Recovery Time before Min 0 0 Write OE High to CE Low zs Min lwLEL tws WE SetupTime EM i ENEX Bs Min twH WE Hold Time EA tcp Write Pulse Width vn idi TEHEL Write Pulse Width High mn twuwHt twHwH1 Programming Operation Typ i Max 200 200 200 twHwHe2 twHwHe Sector Erase Operation Typ 0 9 03 twHwH3 Chip Erase Operation Typ 3 lvcs Vcc Setup Time m RM a Min 500 500 500 n tvipR Rise Time to VID lie Min 500 500 500 ns RESET Pulse Width n a for EN29F002N Min 4 4 4
12. E whichever is first The program operation is completed when EN29F002 returns the equivalent data to the programmed location Programming status may be checked by sampling data on DQ7 DATA polling or on DQ6 toggle bit Changing data from 0 to 1 requires an erase operation When programming time limit is exceeded DQ5 will produce a logical 1 and a Reset command can return the device to Read mode EN29F002 ignores commands written during Byte Programming If a hardware RESET occurs during Byte Programming data at the programmed location may get corrupted Programming is allowed in any sequence and across any sector boundary Chip Erase Command An auto Chip Erase algorithm is employed when the Chip Erase command sequence is performed Although the Chip Erase command requires six bus cycles two unlock write cycles a setup command two additional unlock write cycles and the chip erase command the user does not need to do anything else after that except check to see if the operation has completed The Auto Chip Erase algorithm automatically programs and verifies the entire memory array for an all 0 pattern prior to E 29 002 29 002 the erase Then the 29 002 will automatically time the erase pulse width verify the erase return the sequence count provide a erase status through DATA POLLING data on DQ7 is 0 during the operation and 1 when completed provided the status is not read from a
13. High Voltage Vcc 0 5 V VoL Output Low Voltage lol 2 mA 0 45 V VoH Output High Voltage TTL 2 5 mA 2 4 V Output High Voltage CMOS lou 100 pA Vcc 0 4V V Vip 9 Voltage Electronic Signature 10 5 115 V and RESET Voltage Temporary Sector Unprotect 9 and RESET Current Electronic 9 RESET Vip 100 uA Signature VLKO Supply voltage Erase and 32 4 2 V Program lock out Notes 1 RESET pin input buffer is always enabled so that it draws power if not at full CMOS supply voltages E 29 002 EN29F002N Table 8 AC CHARACTERISTICS Read only Operations Characteristics 115 Speed Options JEDEC Standard Description Test Setup 45 55 70 90 Unit tavav tre Read Cycle Time Min 45 55 70 90 ns tavav tacc Address to Output Delay CE Max 45 55 70 90 ns tELOV Chip Enable To Output Delay OE v Max 45 55 70 90 ns VIL toe Output Enable to Output Delay Max 25 30 30 35 ns tEHOZ tor Chip Enable to Output High Z Max 10 15 20 20 ns tcHoz Output Enable to Output High Z Max 10 15 20 20 ns taxax tou Output Hold Time from Min 0 0 0 0 ns Addresses CEor OE whichever occurs first in Max 20 20 20 20 us eady RESET Pin Low t
14. IZE Kbytes 29 002 EN29F002N FIGURE 1 LOGIC DIAGRAM 8 29 002 18 A0 A17 CE OE WE RESET NC on EN29F002N BOTTOM BOOT BLOCK ADDRESSES SIZE Kbytes 30000h 3FFFFh 64 20000h 2FFFFh 64 10000h 1FFFFh 64 08000h 0FFFFh 32 06000h 07FFFh 8 04000h 05FFFh 8 00000h 03FFFh 16 oa DQ0 DQ7 E 3 29 002 29 002 BLOCK DIAGRAM Block Protect Switches DQO DQ7 Vss gt RESET N A on EN29F002N Erase Voltage Generator Input Output Buffers Output Enable X Decoder Cell Matrix Address Latch FIGURE 2 PDIP N A for EN29F002N FIGURE 3 TSOP N A for EN29F002N RESET FIGURE 4 PLCC A16 A15 A12 AT Ab 5 A4 JC Cn Wh 7 A6 A5 4 2 A1 AO DQO RESET A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 DQO DQ1 DQ2 VSS PDIP Top View 1 2 3 4 5 6 7 8 TSOP EN29F002 PLCC Top View A12 A16 Vcc A17 15 RESET WE DQ2 DQ5 DQ1 VSS DQ4 DQ6 EN29F002 EN29F002N vec WE A17 A14 A13 A8 A9 11 10 DQ7 DQ6 DQ5 DQ4 DQ3 RESET is not applicable for EN29F002N A14 A13 A8 A9 A11 OE A10 DQ7 E kod EN29F002 EN29F002N TABLE 3 OPERATING MODES 2M FLASH USER MODE TABLE we RESET 9 A8 A6 A1 AO Axy DQ 0 7
15. THMS Flowchart 1 Embedded Program Write Program Command Sequence shown below Data Poll Device Last Address Yes Programming Done Increment Address Flowchart 2 Embedded Program Command Sequence See the Command Definitions section for more information Flowchart 3 Embedded Erase Write Erase Command Sequence shown below Data Polling Device or Toggle Bit Successfully Completed ERASE Done 29 002 EN29F002N E 29 002 29 002 Flowchart 4 Embedded Erase Command Sequence See the Command Definitions section for more information Chip Erase Sector Erase 5555H AAH 5555 2AAAH 55H 2AAAH SSH 5555H 80H 5555 80 5555H AAH 2AAAH 55H 5555H 10H 5555H AAH 2AAAH 55H Sector Address 30H Flowchart 5 DATA Polling Algorithm Read Data DQ7 Data No EN29F002 EN29F002N E 29 002 29 002 Flowchart 6 Toggle Bit Algorithm Read Data N 506 Toggle I DQ6 Toggle Yes E 3 29 002 29 002 Flowchart 7 Temporary Sector Unprotect Algorithm Not available for EN29F002N RESET Note 1 Perform Erase or Program Operations Temporary Block Unprotect Done Note 2 Notes 1 All protected sectors unprotected 2 All previous protected sectors are protected once again E z
16. ble access time tce is equal to the delay from stable CE to valid data at output pins Data is available at the outputs after output enable access time tog from the falling edge of OE assuming the CE has been LOW and addresses have been stable for at least tacc tog Output Disable Mode When the CE or OE is at a logic high level Viu the output from the EN29F002 EN29F002N is disabled The output pins are placed in a high impedance state Auto Select Identification Mode The manufacturer and device type can be identified by hardware or software operations This mode allows applications or programming equipment automatically matching the device with its corresponding interface characteristics To activate the Auto Select Identification mode the programming equipment must force 12 0 V 0 5V on address line A9 of the EN29F002T B Two identifier bytes can then be sequenced from the device outputs by toggling address lines AO and 8 from VI to Vin The manufacturer and device identification may also be read via the command register By following the command sequence referenced in the Command Definition Table Table 5 This method is desirable for in system identification using only 5 0V When 0 A1 V and by toggling A8 from to Vin the Manufacturer ID can be read as Eon 1C hex to identify When AO Viu A1 A6 and by toggling A8 from Vi to the E z 29 002 29
17. ctly If timing limits are exceeded reset the device See Table 6 DQ3 Sector Erase Command Timeout This device does not support multiple sector erase commands will go high immediately after the first 30h command the sixth write cycle Any extra 30h commands will be ignored or taken as a resume command if erase suspended DQ2 Erase Toggle Bit Il In the sector erase operation DQ2 will toggle with OE or CE when a read is attempted within the sector that is being erased DQ2 will not toggle if the read address is not within the sector that is selected to be erased In the chip erase operation however DQ2 will toggle with OE or CE regardless of the address given by the user This is because all sectors are to be erased See Table 6 E 29 002 29 002 Table 6 Status Register Bits po Name Logic Level Definition T Erase Complete or erase sector in Erase suspend 0 Erase On Going DATA Program Complete or POLLING DQ7 data of non erase sector during Erase Suspend 1 0 1 0 1 0 1 DQ6 Erase or Program On goin Read during Erase Suspend TOGGLE 6 BIT 1 1 1 1 1 1 1 Erase Complete 5 ERROR BIT Program or Erase Error Program or Erase On going Erase operation start Erase timeout period on going Chip Erase Erase or Erase suspend on currently addressed 1 0 1 0 1 0 1 sector When DQ5 1 Erase Error due to curr
18. d data Even if the device has completed the embedded operations and DQ7 has a valid data the data output on DQ0 DQ6 may be still invalid The valid data on DQ0 DQ7 will be read on the subsequent read attempts The flowchart for DATA Polling DQ7 is shown on Flowchart 5 The DATA Polling DQ7 timing diagram is shown in Figure 8 DQ6 Toggle Bit The EN29F002 provides a Toggle Bit on DQ6 to indicate to the host system the status of the embedded programming and erase operations See Table 6 During an embedded Program or Erase operation successive attempts to read data from the device at any address by toggling OE or CE will result in DQ6 toggling between zero and Once the embedded Program or Erase operation is complete DQ6 will stop toggling and valid data will be read on the next successive attempts During Byte Programming the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four cycle sequence For Chip Erase the Toggle Bit is valid after the rising edge of the sixth cycle sequence For Sector Erase the Toggle Bit is valid after the last rising edge of the Sector Erase Command 30h WE pulse In Byte Programming if the sector being written to is protected DQ6 will toggle for about 2us then stop toggling without the data in the sector having changed In Sector Erase or Chip Erase if all selected sectors are protected DQ6 will toggle for about 100 us The chip will then return to the rea
19. d mode without changing data in all protected sectors Toggling either CE or OE will cause DQ6 to toggle E 29 002 29 002 The flowchart for the Toggle Bit DQ6 is shown in Flowchart 6 The Toggle Bit timing diagram is shown in Figure 9 DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits internal pulse count Under these conditions DQ5 will produce a 1 The Toggle Bit DQ6 should also be checked at this time to make sure that the DQ5 is not a 1 due to the device having returned to read mode This is a failure condition which indicates that the program or erase cycle was not successfully completed DATA Polling DQ7 Toggle Bit 006 and Erase Toggle Bit 092 still function under this condition Setting the CE to will partially power down the device under those conditions The OE and WE pins will control the output disable functions as described in Table 3 The DQ5 failure condition will also appear if the user tries to program a 1 to a location that was previously programmed to a 0 In this case the device goes into Hang or Error mode out and never completes the Embedded Program Algorithm Hence the system never reads valid data on DQ7 and DQ6 never stops toggling Once the device exceeds the timing limits DQ5 will indicate a 1 Please note that this is not a device failure condition since the device was used incorre
20. ently addressed sector Program during Erase Suspend on going at current address 2 TOGGLE BIT Erase Suspend read on DQ2 non Erase Suspend Sector Notes DQ7 DATA Polling indicates the P E C status check during Program or Erase and on completion before checking bits DQ5 for Program or Erase Success DQ6 Toggle Bit remains at constant level when P E operations are complete or erase suspend is acknowledged Successive reads output complementary data on DQ6 while programming or Erase operation are on going DQ5 Error Bit set to 1 if failure in programming or erase DQ3 Sector Erase Command Timeout Bit Operation has started Only possible command is Erase suspend ES DQ2 Toggle Bit indicates the Erase status and allows identification of the erased sector E 29 002 29 002 DATA PROTECTION Power up Write Inhibit During power up the device automatically resets to READ mode and locks out write cycles Even with CE Vii WE Vi and OE the device will not accept commands on the rising edge of WE Low Vcc Write Inhibit During Vcc power up or power down the 20 002 locks out write cycles to protect against any unintentional writes If Voc lt Viko the command register is disabled and all internal program or erase circuits are disabled Under this condition the device will reset to the READ mode Subsequent writes will be ignored until gt Vi o Write
21. ged to be Vip 211 5 0 5V C 2001 07 05 VID is everywhere changed to be Vip 211 0 0 5V block changed to sector everywhere appropriate Deleted Sector Un Protect flow charts we have a supplement for that RESET VID and not VPP on first page LACTHUP gt 200mA line removed from first page Chip erase and Sector Erase command descriptions modified DQ7 DQ5 DQ3 status polling descriptions modified Table 7 and Table 12 modified Absolute Maximum Ratings section added
22. ill be reset to the read mode Any program erase operation in progress during hardware reset will be terminated and data may be corrupted If the RESET pin is tied to the system reset command the device will be automatically reset to the read mode and enable the system s microprocessor to read the boot up firmware from the FLASH memory COMMAND DEFINITIONS The operations of the EN29F002 are selected by or more commands written into the command register to perform Read Reset Memory Read ID Read Sector Protection Program Sector Erase Chip Erase Erase Suspend and Erase Resume Commands are made up of data sequences written at specific addresses via the command register The sequences for the specified operation are defined in the Command Table Table 5 Incorrect addresses incorrect data values or improper sequences will reset the device to the read mode E 29 002 29 002 Table 5 29 002 Command Definitions 555h AAh AAAh Manufacturer ID AutoSelect Device ID 4 Top Boot 555h 001 7Fh Write 15 gnd grd Command Cycles Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Sequence Req d Read Reset Addr Addr Data Addr Data Addr Read Reset 1 ReadiReset 4 885h Aah AAAR 55n Seen Fn RA RO i AutoSelect 4 555h 555h 000h 7Fh 100h 1Ch 55h 555h 90h 001 7Fh Au
23. m en EN29F002 EN29F002N 2 Megabit 256K x 8 bit Flash Memory FEATURES 5 0V x 10 for both read write operation Read Access Time 45ns 55ns 7Ons and 90ns Fast Read Access Time 70ns with Cigag 100pF 45ns 55ns with Sector Architecture One 16K byte Boot Sector Two 8K byte Parameter Sectors one 32K byte and three 64K byte main Sectors Boot Block Top Bottom Programming Architecture High performance program erase speed Byte program time 10us typical Sector erase time 500ms typical Chip erase time 3 5s typical Low Standby Current 1 CMOS standby current typical 1mA TTL standby current Low Power Active Current 30mA active read current 30mA program erase current JEDEC Standard program and erase commands GENERAL DESCRIPTION EN29F002 EN29F002N JEDEC standard DATA polling and toggle bits feature Hardware RESET Pin Single Sector and Chip Erase n a for 29 002 Sector Protection Temporary Sector Unprotect RESET Vip Sector Unprotect Mode Embedded Erase and Program Algorithms Erase Suspend Resume modes Read and program another sector during Erase Suspend Mode 0 4 um double metal double poly triple well CMOS Flash Technology Low Vcc write inhibit 3 2V 100K endurance cycle Package Options 32 pin PDIP 32 pin PLCC 32 pin TSOP Type 1 Commercial and Industrial Temperature Ranges The EN29F002 EN29F002N is a 2 Megabit electrically
24. o Read Mode n a for EN29F002N Notes For 45 55 5 0V 5 Output Load 1 TTL gate and 30pF Input Rise and Fall Times 5ns Input Rise Levels 0 0 V to 3 0 V Timing Measurement Reference Level Input and Output 1 5 V For all others Vcc 5 0V 10 Output Load 1 TTL gate and 100 pF Input Rise and Fall Times 20 ns Input Pulse Levels 0 45 V to 2 4 V Timing Measurement Reference Level Input and Output 0 8 V and 2 0 V E 3 29 002 29 002 Table 9 AC CHARACTERISTICS Write Erase Program Operations Paramete Symbols Speed Options JEDEC Standard Description 45 55 70 90 Unit tAVAV twc Write Cycle Time Min 45 55 70 90 ns tAVWL tas Address Setup Time Min 0 0 O 0 ns tay Address Hold Time Min 35 45 45 45 ns tpvwH tps Data Setup Time Min 20 25 30 45 ns twHDX tpH Data Hold Time Min 0 0 0 0 ns toes Output Enable Setup Time Min 0 0 0 0 ns toen Output Enable Read 9 0 d d ne Hold Time Toggle and Min 10 10 10 DATA Polling teHwe Read Recovery Time before win 0 0 Write OE High to WE Low tcs CE SetupTime KERA 0 0 lwHEH CE Hold Time ES 0 0 twewH twe Write Pulse Width 30 35 lwupL wPH Write Pulse Width High 20 20 twuwHt twHwut Programming Operation 7 7 tWwHwH2 Sector Erase Operation 0 3 0 3
25. protected sector and returns to the READ mode after completion of Chip Erase Sector Erase Command Sector Erase requires six bus cycles two unlock write cycles a setup command two additional unlock write cycles and the Sector Erase command Any sector may be erased by latching any address within the desired sector on the falling edge of WE while the Erase Command 30H is latched on the rising edge of WE This device does not support multiple sector erase commands Sector Erase operation will commence immediately after the first 30h command is written The first sector erase operation must finish before another sector erase command can be given The EN29F002 device automatically programs and verifies all memory locations in the selected sector for an all 0 pattern prior to the erase Unselected sectors are unaffected by the Sector Erase command EN29F002 requires no timing signals during sector erase Erase is completed when data on DQ7 becomes 1 and the device returns to the READ mode after completion of Sector Erase Erase Suspend Resume Command Erase suspend allows interruption of sector erase operations to perform data reads from sector not being erased Erase suspend applies only to Sector Erase operations EN29F002 ignores any commands during erase suspend other than the assertion of the RESET pin n a for EN29F002N or Erase Resume commands Writing erase resume continues erase operations Addresses are DON
26. ramming Sector Erase Chip Erase Erase Suspend See Table 6 When the Byte Programming is in progress an attempt to read the device will produce the complement of the data last written to DQ7 Upon the completion of the Byte Programming an attempt to read the device will produce the true data last written to DQ7 For the Byte Programming DATA polling is valid after the rising edge of the fourth WE or CE pulse in the four cycle sequence When the embedded Erase is in progress an attempt to read the device will produce a 0 at the DQ7 output Upon the completion of the embedded Erase the device will produce the 1 at the DQ7 output during the read For Chip Erase the DATA polling is valid after the rising edge of the sixth W E or CE pulse in the six cycle sequence For Sector Erase DATA polling is valid after the last rising edge of the sector erase WE or CE pulse DATA Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector Otherwise DATA polling may give an inaccurate result if the address used is in a protected sector Just prior to the completion of the embedded operations DQ7 may change asynchronously when the output enable OE is low This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time Depending on when the system samples the DQ7 output it may read the status of vali
27. t Minimum Pattern Data Retention Time 150 C 10 Years 125 20 Years AP 29 002 EN29F002N SWITCHING WAVEFORMS Figure 5 AC Waveforms for READ Operations tac gt Addresses Q Addresses Stable y Figure 6 AC Waveforms for Chip Sector Erase Operations 555H tor chip erase lwc ADDRESSES 5 AAAH X X SA UH tos t 10H for Chip Erase DATA C 69 y Voc Notes 1 SAis the sector address for sector erase AP 29 002 EN29F002N SWITCHING WAVEFORMS continued Figure 7 Program Operation Timings ADDRESSES XXXYX X Notes PA is address of the memory location to be programmed PD is data to be programmed at byte address DQ7 is the output of the complement of the data written to the device Dour is the output of data written to the device Figure indicates last two bus cycles of four bus cycle sequence Figure 8 AC Waveforms for DATA Polling During Embedded Algorithm Operations 777 DOS HIGH Z 000006 sen tsa Gu 0006 ai 252 Notes DQ Valid Data The device has completed the embedded operation AP EN29F002 EN29F002N Figure 9 AC Waveforms for Toggle Bit During Embedded Algorithm Operations Notes DQ stops toggling The device has completed the embedded operation Figure 10 Temporary Sector Unprotect Timing Diagram
28. toSelect Device ID 4 555h AAh AAAh Bottom Boot AutoSelect Sector 4 Protect Verify 555h AAh AAAh 555h Byte Program 555h AAh 55h 555h AOh PA PD Chip Erase 555h 55h 555h 80h 555 55h 555h 10h Sector Erase 555h AAh 55h 555 80h 555 AAAn 55h SA 30h Sector Erase Suspend xxxh BOh 2 2 Oo Oo amp t Sector Erase Resume xxxh 30h Notes RA Read Address address of the memory location to be read This one is a read cycle RD Read Data data read from location RA during Read operation This one is a read cycle PA Program Address address of the memory location to be programmed PD Program Data data to be programmed at location PA SA Sector Address address of the sector to be erased Address bits A17 A13 uniquely select any sector Byte Programming Command Programming the 29 002 is performed on a byte by byte basis using four bus cycle operation two unlock write cycles followed by the Program Setup command and Program Data Write cycle When the program command is executed no additional CPU controls or timings are necessary The program operation is terminated automatically by an internal timer Address is latched on the falling edge of CE or WE whichever is last data is latched on the rising edge of CE or W
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EON EN29F002 EN29F002N 2 Megabit (256K x 8 bit) Flash Memory