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ROHM BU9883FV-W Manual

1. 0 9 V Therefore the condition 2 is satisfied OPull up resistance of SCLO 3 terminal When SCLO 3 control is made at CMOS output port there is no need but in the case there is timing where SCLO 3 becomes Hi Z add a pull up resistance As for the pull up resistance one of several kO several ten kO is recommended in consideration of drive performance of output port of microcontroller www rohm com l 14 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note Cautions on microcontroller connection ORs In I2C BUS it is recommended that SDA port is of open drain input output However when to use CMOS input output of tri state to SDA port insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously Rs also plays the role of protection of SDA terminal against surge Therefore even when SDA port is open drain input output Rs can be used The following SCL SDA RPU and Rs correspond to them of each port H ACK gt SCL RPu SDA MAH tified DAE H output of microcontroller L output of EEPRO Ap gt Mi i Over current flows to SDA line by H icrocontroller EEPROM output of microcontroller and L output of EEPROM Fig 54 I O circuit diagr
2. ANN S Rs 2 Over current 1 1 gt L H output Example When Vcc 3V I 10mA fs QE Microcontroller EEPROM 10x10 Fig 57 I O circuit diagram 2 300 0 www rohm com 15 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note Ge C BUS input output circuit Olnput SCLO 3 I Fig 58 Input pin circuit diagram Olnput output SDAO 3 Fig 59 Input output pin circuit diagram Olnput WPB Fig 60 Input pin circuit diagram G Notes on power ON At power on in IC internal circuit and set VCC rises through unstable low voltage area and IC inside is not completely reset and malfunction may occur To prevent this functions of POR circuit and LVCC circuit are equipped To assure the action observe the following conditions at power on 1 Set SDA0 3 H and SCLO 3 L or H 2 Start power source so as to satisfy the recommended conditions of tr torr and Vbot for operating POR circuit R Vcc Recommended conditions of tr torr Vbot tg torr Vbot 10ms or below 10ms or longer 0 3V or below ll UAE 100ms or below 10ms or longer 0 2V or below Fig 60 Rise waveform diagram www rohm com 16 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note 3 Set SDAO 3 and SCLO 3 so as not to become Hi Z When the above conditions 1 and 2 cannot be observed take the following countermea
3. All rights reserved WP L INPUT VOLTAGE Vi V STANDBY CURRENT ke uA L INPUT VOLTAGES V 3 V wo L OUTPUT VOLTAGE2 Vo 2 V a o co o eo ES o DS 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vcc3 V Fig 9 L Input Voltage3 Vis SCL3 SDA3 0 i 2 3 4 5 6 L OUTPUT CURRENT IOL mA Fig 12 L Output Voltage2 Vaiz loi Vec2 3 0V SDA2 o ra hd a a N a OUTPUT LEAK CURRENT I o uA o 1 2 3 4 5 6 7 8 SUPPLYVOLTAGE VecO V Fig 15 WP L Input Voltage Vi4 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vec V Fig 18 OUTPUT LEAK CURRENT l o SDA0 3 0 1 2 3 4 5 6 SUPPLY VOLTAGE VccO V Fig 21 Standby Current Isgo 4 18 INPUT LEAK CURRENTO Iuo uA CURRENT CONSUMPTION L OUTPUT VOLTAGEO Voo lV L OUTPUT VOLTAGES Von V AT WRITTING Icct mA STANDBY CURRENT kg uA Technical Note 0 8 0 6 04 0 2 0 0 1 L 2 3 4 5 6 OUTPUT CURRENT Ig mA Fig 10 L Output VoltageO Voio loi Vec0 3 0V o o E 2 3 4 5 6 OUTPUT CURRENT IOL mA Fig 13 L Outnput Voltage3 Voia loi Vec3 3 0V SDA3 SUP Fig 16 2500 N o e e 2 3 4 5 6 PLY VOLTAGE Vcc0 3 V Input Leak CurrentO lj j SCLO 3 i 2 3 4 5 6 SUPPLY VOLTAGE VccO V Fig 19 Current C
4. against the possibility of physical injury fire or any other damage caused in the event of the failure of any Product such as derating redundancy fire control and fail safe designs ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed Scope or not in accordance with the instruction manual The Products are not designed or manufactured to be used with any equipment device or System which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury such as a medical instrument transportation equipment aerospace machinery nuclear reactor controller fuel controller or other safety device ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes If a Product is intended to be used for any such special purpose please contact a ROHM sales representative before purchasing If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law you will be required to obtain a license or permit under the Law Thank you for your accessing to ROHM product informations More detail product informations and catalogs are available please contact us ROHM ROHM Customer Support System SEMICONDUCTOR http www rohm com contact www rohm com 2009 ROHM Co
5. 1 1 BANK3 ODon set P1 PO 0 0 If P1 PO are set to 0 there is no target bank so this device doesn t return cknowlege OWPB terminal must be set to HIGH during Byte Write cycle and Page Write cycle and internal Write cycles If WPB is set to LOW in above condition programing doesn t work and during internal Write cycle WPB terminal set to LOW this device terminate programing and the data in programing address is not stored correctly s w s T R T R E E SLAVE 1 1st WORD 7 SLAVE F a R T si R T ADDRESS E ADDRESS n T ADDRESS A DATA n S T T TTTTTTT T T TTT TT TT SDA UNE t o 1 o o Pi ro WAT Wa t o 1 fo o Pr Po D7 bo I 1 ttt i fj t Jt i RA A RA C6 C ZG c wk K WK Fig 44 RANDOM READ CYCLE TIMING PORTO ORandom read operation allows the master to access any memory location which is appointed by P1 PO bit This operation involves a two step process First the master issue a write command which includes the start condition and the slave address field with R W set to 0 followed by the address of the word be read This procedure sets the internal address counter of this device to the desired address After the word address acknowledge is received by the master the master immediately reissues a start condition followed by the slave address field with R W the set to 1 This device will respond with an acknowledge and then t
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7. Reu The maximum value of Rpy is determined by the following factors The following VCC SDA Rpy and I correspond to them of each port 1 SDAO 3 rise time to be determined by the capacitance CBUS of bus line of Rey and SDAO 3 should be tR or below And AC timing should be satisfied even when SDAO 3 rise time is late 2 The bus electric potential CN to be determined by input leak total IL of device connected to bus at output of H to SDAO 3 bus and Rey should sufficiently secure the input H level Viu of microcontroller and EEPROM including recommended noise margin 0 2VCC BU9883FV W Microcontroller Vcc ILReu 0 2Vcc 2 Vin 0 8Vcc Viu Reu I Ex When Vec 3V 1 10 uw A Vin 0 7 Vee from 2 o IL i Bus line 0 8x3 0 7 x3 i capacity Rey 710x105 77 CBUS lt 300 kQ Fig 53 I O circuit diagram OMinimum value of Reu The minimum value of Rey is determined by the following factors The following VCC Voi lot and Reu correspond to them of each port 1 When IC outputs LOW it should be satisfied that Votmax 0 4V and lotmax 3mA Vcc Vor Vc Vor lot nes Rey Reu lo 2 Votmax 0 4V should secure the input L level Vii of microcontroller and EEPROM including recommended noise margin 0 1VCC Vormax S Vi 0 1 VCC Ex When VCC 3V Voi z0 4V loL 3mA microcontroller EEPROM ViL 0 3VCC from 1 R 3 0 4 MOT 3x10 867 Q And Vor 0 4 V Vi 0 3x3
8. VccO E SCL1 Controller SDAI O 1uF WPB WPB OUT ROHM voc OUT PC_SCL Vec2 BU9883FV W PC_SDA O 1uF SCL2 SDA2 SCLO Vcc3 SDAO SCL3 GND SDA3 E HDMI Receiver SDA3 L de SCL SINK DDC SCL SDA2 HDMI S07 Switch SDAI SDA SINK DDC SDA SCL1 Fig 39 Application circuit www rohm com 2009 ROHM Co Ltd All rights reserved 7 18 2009 04 Rev B BU9883FV W Technical Note G WRITE CYCLE TIMING SCLO WRITE DATA n twn i STOP CONDITION START CONDITION Fig 40 WRITE CYCLE TIMING WRITE OPERATION BU9883FV W has 2K bit EEPROM in each port there are three BANKs 6K bit EEPROM in this device Each BANK EEPROM can be written through PORTO There is no write operation through PORT 1 2 3 When this device is accessed throgh PORTO WPB terminal must be set to HIGH Table1 Access port and write enable BANK PortO BANK1 3 Port1 No write operation Port2 No write operation Port3 No write operation READ OPERATION Each BANK EEPROM can be read through each port The relation ship of access port and access BANK is describe Table2 Table 2 Table 3 PortO BANK1 3 PortO BANK1 3 Port No write operation Port1 BANK1 Port2 No write operation Port2 BANK2 Port3 No write operation Port3 BANK3 OWhen EEPROM access through PORTO P1 PO bits in slave address appoint access BANK Table 4 P1 PO P1 PO0 bit and access BANK
9. by changing the fixed number of external parts make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI 3 Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded LSI may be destructed Do not impress voltage and temperature exceeding the absolute maximum ratings In the case of fear exceeding the absolute maximum ratings take physical safety countermeasures such as fuses and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI 4 GND electric potential Set the voltage of GND terminal lowest at any action condition Make sure that each terminal voltage is lower than that of GND terminal 5 Terminal design In consideration of permissible loss in actual use condition carry out heat design with sufficient margin 6 Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board pay sufficient attention to LSI direction and displacement Wrong packaging may destruct LSI And in the case of shortcircuit between LSI terminals and terminals and power source terminal and GND owing to foreign matter LSI may be destructed 7 Use in a strong electromagnetic field may cause malfunction therefore evaluate design sufficiently www rohm com l 17 18 2009 04 Rev B 2009 ROHM Co Ltd All
10. 0 0 No bank selected 0 1 BANK1 1 0 BANK2 1 1 BANK3 Note When P120 P070 this device doesn t return Acknowlege ObDuring PORTO access WPB terminal must be set to HIGH then PORT1 3 accesses will be cancelled Oln accessing from PORT1 3 set WPB termianl to LOW Q DEVICE OPERATION OSTART CONDITION All commands are proceeded by the start condition which is a HIGH to LOW transition of SDAO 3 when SCLO 3 is HIGH This device continuously monitors the SDAO 3 and SCLO 3 lines for the start condition and will not respond to any command until this condition has been met OSTOP CONDITION All communications must be terminated by a stop condition which is a LOW to HIGH transition of SDAO 3when SCLO 3 is HIGH The stop condition initiates internal write cycle to write the data into memory array after write sequence The stop condition is also used to place the device into the standby power mode after read sequence A stop condition can only be issued after the transmitting device has released the bus ONOTICE ON WRITE COMMAND In Write command after transmit write data if there are no stop condition EEPROM data don t change www rohm com 8 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note ODEVICE ADDRESSING Following a START condition the master output the device address of the slave to be accessed The most significant four bits of the slave address are the d
11. L3 0 3 0 3xVCC3 V 3 0SVCC3S5 5V SCL3 SDA3 L Output VoltageO VOLO 0 4 V IOL 3 0mA 3 0 SVCCOE5 5V SDAO L Output Voltage1 VOL1 0 4 V IOL 3 0mA 3 0V SVCC1Z5 5V SDA1 L Output Voltage2 VOL2 0 4 V IOL 3 0mA 3 0 SVCC2X 5 5V SDA2 L Output Voltage3 VOL3 0 4 V IOL 3 0mA 3 0VSVCC3S5 5V SDA3 WP H Input Voltage VIHA 0 7xVCCO VCC0 0 3 V 3 0SVCCOS5 5V WPB WP L Input Voltage VIL4 0 3 0 3xVCC V 3 0SVCCOS5 5V WPB Input Leakage CurrentO ILIO 1 1 pA VIN 0 5 5V SCLO 3 Input Leakage Current ILI 55 110 230 pA WPB 5 5V VCC 5 5V Output Leakage CurrentO ILOO 1 1 pA VOUT 0 5 5 SDA0 3 CONSEENECHNES o unix Operating Current VCCO0 3 5 5V fSCL 400kHz ICC2 1 0 mA Random Read Current Read Sequential Read each port operation Standby Current ISBO i 100 uA cn Sess eee TSIN Standby Current ISB1 100 uA EE yes Sedis Standby Current ISB2 100 uA Hea E E Standby Current ISB3 100 uA acest pM KM ere OThis product is not designed for protection against radioactive rays www rohm com 2 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note EEPROM AC operating characteristics Ta 40 85 C VCC0 3 3 0 5 5V Erga Symbol 3 08 VCC0 3X5 5V Unit Min Typ Max Min Clock Frequency fscL 400 kHz Data Clock High Period tHIGH 0 6 us Data Clock Low Period tLOW 1 2 Hus SDAO0 3 and SC
12. LO 3 Rise Time tR 0 3 us SDAO0 3 and SCLO 3 Fall Time tF 0 3 us Start Condition Hold Time tHD STA 0 6 uS Start Condition Setup Time tSU STA 0 6 uS Input Data Hold Time tHD DAT 0 ns Input Data Setup Time tSU DAT 100 ns Output Data Delay Time tPD 0 1 0 9 Hs Output Data Hold Time tDH 0 1 us Stop Condition Setup Time tSU STO 0 6 us Bus Free Time tBUF 1 2 us Write Cycle Time twR 5 ms Noise Spike Width SDAO 3 and SCLO 3 tl 0 1 us WP Hold Time tHD WP 0 ns WP Setup Time tsU wP 0 1 Us WP valid time tHIGH WP 1 0 Hus 1 Not 100 TESETED Synchronous data input output timing ta puit e tHicH SCL SCL tHD STA SDA IN SDA i iw BIT ON ates BIT Z ALU Fig 1 SYNCHRONOUS DATA TIMING OSDA data is latched into the chip at the rising edge of the SCL clock This is commoness in all port OOutput date toggles at the falling edge of the SCL clock This is commoness in all port Q Characteristic data The following values are Typ ones 6 E EE z Z SE gt D N g B D E E3 E d Ej S S E E E E 2 a a a Z i Z x 0 0 3 4 5 6 0 5 6 0 3 4 5 6 SUPPLY VOLTAGE VccO V SUPPLY VOLTAGE VccO V SUPPLY VOLTAGE Vec2 V Fig 2 H Input VoltageO Vio Fig 3 H Input Voltage1 Vj Fig 4 H Input Vol
13. am Fig 55 Input output collision timing OMaximum value of Rs The maximum value of Rs is determined by the following relations The following VCC Voi Rs Reu lot and SDA correspond to them of each port 1 SDA rise time to be determined by the capacity CBUS of bus line of Rpu and SDA should be tR or below And AC timing should be satisfied even when SDA rise time is late 2 The bus electric potential to be determined by Rpu and Rs the moment when EEPROM outputs L to SDA bus should sufficiently secure the input L level Vi of microcontroller including recommended noise margin 0 1VCC Vcc Vo xRs VoL 0 1Vcc KViL RPu Rs R P ViL VoL 0 1 Vcc x R a 1 1Vcc VIL de Example When Vcc 3V ViLz0 3Vcc VoL 0 4V Rpeu 20kQ VIL yan Dp EEPROM Microcontroller from 2 COM 0 3x3 0 4 0 1x3 7 20x10 Fig 56 I O circuit diagram i 1 1x3 0 3x3 OMinimum value of Rs lt 1 67 kQ The minimum value of Rs is determined by over current at bus collision When over current flows noises in power source line and instantaneous power failure of power source may occur When allowable over current is defined as the following relation must be satisfied Determine the allowable current in consideration of impedance of power source line in set and so forth Set the over current to EEPROM 10mA or below The following VCC RPU RS and correspond to them of each port 2 ebd Vcc Rpu oioi Rs 7 Bs outpu
14. dge in internal write cycle START CONDITION START BIT SCL From y COM SDA 4t COM E OUTPUTDATA SDA IC OUTPUT DATA Acknowledge Signal ACK Signal Fig 41 ACKNOWLEDGE RESPONSE FROM RECEIVER Q PORTO access commands QFor PORTO access WPB terminal must be set to HIGH S w T R S A 1 R SLAVE 1 1st WORD d T ADDRESS E ADDRESS n DATA n 7 SDA UNE 1 0 1 10 0 er ro WAT wad D7 DO iE d qu o T le LILLLLI RA A Le C WK Kg TE d Fig 42 BYTE WRITE CYCLE TIMING PORTO OThis write commands operate EEPROM write sequence at address which is appointed by P1 PO When the master generates a STOP condition this device begins the internal write cycle to the nonvolatile array www rohm com l 9 48 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note S w T R S E SLAVE I 1st WORD T R T s T ADDRESS E ADDRESS n DATA n DATA n 7 S SDA UNE 1 0 1 0 0 Pi ro wav wad D7 DO R A A A A C C c C W K T K K ss K Fig 43 PAGE WRITE CYCLE TIMING PORTO OThis device is capable of eight byte page write operation OAfter the receipt of each word the three low order address bits are internally incremented by one The most significant address bits WA7 WAS3 remain constant if the master transmits more than 8 words OThe relationship of P1 PO inputs and access BANK is described as follows P1 PO BANK 0 0 No opearation 0 1 BANK1 1 0 BANK2
15. er must send no Acknowledge at after DO output and issue stop condition Am Ao orm voda LAVE ADDRESS DATA n DATA n x SDA LIN 1 lilo 0 PIP D7 DO D7 DO LI 1X 4 1E N 1L LOL ra l 1 LL gd WPB Fig 46 SEQUENTIAL READ CYCLE TIMING PORTO During the sequential read operation the internal address counter of this device automatically increments with each acknowledge received ensuring the data from address will be followed with the data from n 1 For read operations all bits of the address counter are incremented allowing the entire array to be read during a single operation When the counter reaches the top of the array it will roll over to the bottom of the array of BANK and continue to transmit the data OThe sequential read operation can be performed with both current read and random read PORT1 2 3 access commands SLAVE 1st WORD ADDRESS ADDRESS n SDA LINE o i flo lo o o WAT wad 1 pote trp rriis SLAVE ADDRESS DATA n HDA ma zz ADH orma vou o t oJoo o D7 DO Fig 47 RANDOM READ CYCLE TIMING PORT1 3 ORandom read operation allows the master to access any memory location of the BANK which is appointed by P1 PO This operation involves a two step process First the master issues a write command which includes the start condition and the slave address field with R W set to 0 followed by the address of the word be read This procedure sets the int
16. ernal address counter of this device to the desired address After the word address acknowledge is received by the master the master immediately reissues a start condition followed by the slave address field with R W the set to 1 This device will respond with an acknowledge and then transmit the 8 data bits stored at the addressed location If the master does not acknowledge the transmission but does generate the stop condition at this point this device discontinues transmission R E SLAVE A ADDRESS D DATA Fig 48 CURRENT READ CYCLE TIMING PORT1 3 www rohm com l 11 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note OWhen the command just before Current Read cycle is Random Read cycle or Current Read cycle each including Sequential Read cycle data of incremented last read address n th address i e n data of the n 1 th address is output When the command just before Current Read cycle is Byte Write or Page write data of latest write address is output QORandom read operation allows the master to access any memory location The BANK which is appointed by P1 PO This operation involves a two step process First the master issues a write command which includes the start condition and the slave address field with R W set to 0 followed by the address of the word be read This procedure sets the internal address counter of this device to the desired address After the word address ack
17. ess and data in succession Fig 51 Case to continuously write by acknowledge polling www rohm com l 13 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note G Command cancel by start condition and stop condition During command input by continuously inputting start condition and stop condition command can be cancelled Refer to Fig 52 However in ACK output area and during data read SDAO 3 bus may output L and in this case start condition and stop condition cannot be input so reset is not available Therefore execute software reset And when command is cancelled by start stop condition during random read cycle sequential read cycle or current read cycle internal setting address is not determined therefore it is not possible to carry out current read cycle in succession When to carry out read cycle in succession carry out random read cycle SCLO 3 SDA0 3 1 0 1 0 Start condition Stop condition Fig 52 Case of cancel by start stop condition during slave address input 1 O peripheral circuit OPull up resistance of SDAO 3 terminal SDAO0 3 is NMOS open drain so requires pull up resistance As for this resistance value RPU select an appropriate value to this resistance value from microcontroller VIL IL and VOLO 3 IOL characteristics of this IC If RPU is large action frequency is limited The smaller the RPU the larger the consumption current at action OMaximum value of
18. evice type indentifier for this device this is fixed as 1010 The next three bit specify a particular device For PORTO access that are set 0 P1 PO for PORT 1 3 access that must be set 000 The last bit of the stream determines the operation to be performed When set to 1 a read operation is selected when set to 0 a write operation is selected RW set to O sec secs os WRITE R Wsetto 1 gt gt ses READ QACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers The master or the slave will release the bus after transmitting eight bits During the ninth clock cycle the receiver will pull the SDA line LOW to Acknowledgethat the eight bits of data has been received This device will respond with an Acknowledge after recognition of a START condition and its slave address If both the device and a write operation have been selected this device will respond with an Acknowledge after the receipt of each subsequent 8 bit word In the READ mode this device will transmit eight bit of data release the SDA line and monitor the line for an Acknowledge If an Acknowledge is detected and no STOP condition is generated by the master this device will continue to transmit the data f an Acknowledge is not detected this device will terminate further data transmissions and await a STOP condition before returning to the standby mode This device dosen t return Acknouwe
19. ial data output 7 SCLO Input Serial clock input 8 VCCO Power Supply 9 VCC3 Power Supply 10 SCL3 Input Serial clock input 11 SDA3 Input output Slave and word address Serial data input serial data output 12 GND Reference voltage of all input output 13 N C Non connect terminal Don t connect each other 14 SDA2 Input output Slave and word address Serial data input serial data output 15 SCL2 Input Serial clock input 16 VCC2 Power Supply www rohm com 6 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note Q BLOCK DIAGRAM Voci PE Voltage Vcc2 amp i Detect Vcc3 X Logic LDO Low Voltage Logic 1 PORTI fiS RI CONTROL hifter BANKO 2Kbit EEPROM PORT2 iS l HDMI Sink PWR HDMI1 1 1 LEVEL 1 hifter BANK1 2Kbit EEPROM EN yo PORT3 DDC SCL1 PWR HDMI2 DDC SCL2 DDC SDA2 PWR_HDMI3 DDC SCL3 DDC SDA3 BANK2 2Kbit EEPROM CONTROL eveL o 0 I Shifter i Porto SOLO SDAO VccO VCC OUT WPB Fig 38 BLOCK DIAGRAM Veet PWR SYS
20. ition Parameter Symbol Rating Unit Supply Voltage VCC 3 0 5 5 y Input Voltage VIN 0 VCCO 3 w rohmi com 1 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note G Memory cell characteristics Ta 25 C VCC0 3 3 0 5 5V Specification Parameter Unit Min Typ Max Write Erase Cycle 1 000 000 Cycles Data Retention i 40 Years 4 Not 100 TESTED Input output capacity Ta 25 C Frequency 5MHz Parameter Symbol Min Typ Max Unit SDA pins SDAO 1 2 3 Cin 7 pF SCL pins SCLO 1 2 3 Cin2 7 pF 1 Not 100 TESTED EEPROM DC operating characteristics Unless otherwise specified Ta 40 85 C VCC0 3 3 0 5 5V Parameter Symbol Min EU Max Unit Test condition H Input VoltageO VIHO 0 7xVCCO VCC0 0 5 V 3 0S VCCOS5 5V SCLO SDAO L Input VoltageO VILO 0 3 0 3xVCCO V 3 0SVCCOS5 5V SCLO SDAO H Input Voltage1 VIH1 0 7xVCC1 VCC1 0 5 V 3 0SVCC1 5 5V SCL1 SDA1 L Input Voltage 1 VIL1 0 3 0 3xVCC1 V 3 0SVCC15 5V SCL1 SDA1 H Input Voltage2 VIH2 0 7xVCC2 VCC2 0 5 V 3 0SVCC25 5V SCL2 SDA2 L Input Voltage2 VIL2 0 3 0 3xVCC2 V 3 0SVCC25 5V SCL2 SDA2 H Input Voltage3 VIH3 0 7xVCC3 VCC3 0 5 V 3 0 8VCC3Z5 5V SCL3 SDA3 H Input Voltage3 VI
21. les of application circuits circuit constants and any other information contained herein illustrate the standard usage and operations of the Products The peripheral conditions must be taken into account when designing circuits for mass production Great care was taken in ensuring the accuracy of the information specified in this document However should you incur any damage arising from any inaccuracy or misprint of such information ROHM shall bear no responsibility for such damage The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products ROHM does not grant you explicitly or implicitly any license to use or exercise intellectual property or other rights held by ROHM and other parties ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information The Products specified in this document are intended to be used with general use electronic equipment or devices such as audio visual equipment office automation equipment commu nication devices electronic appliances and amusement devices The Products specified in this document are not designed to be radiation tolerant While ROHM always makes efforts to enhance the quality and reliability of its Products a Product may fail or malfunction for a variety of reasons Please be sure to implement in your equipment using the Products safety measures to guard
22. mmand Fig 50 a The case of dummy clock START START command input Start Dummy clockx9 Start l Normal command l NNormal command Fig 50 b The case of START 9 dummy clocks START command input SCLO 3 SDA0 3 Startx9 SCLO 3 SDA0 3 Q NNormal command l NNormal command Fig 50 c STARTx9 command input Start command from START input Acknowledge polling During internal write execution all input commands are ignored therefore ACK is not sent back During internal automatic write execution after write cycle input next command slave address is sent and if the first ACK signal sends back L then it means end of write action while if it sends back H it means now in writing By use of acknowledge polling next command can be executed without waiting for tWR 5ms When to write continuously RAW 0 when to carry out current read cycle after write slave address R W 1 is sent and if ACK signal sends back L then execute word address input and data output and so forth A During internal write First write command ACK 7 HIGH is sent back aa S S S S A T T T Slave T Slave C A Write command 9 A A K R P R address R address H T T i twr Second write command OMSL S i S A T Slave C H Slave c Word p oF ata R address m R address n address T T twr After completion of internal write ACK LOW is sent back so input next word addr
23. n Him Technical Note Memory for Plug amp Play d Pb 2 y E d IC BUS3Ports for HDMI Port Free RoHS Serial EEPROM BU9883FV W No 09002EBTO1 SEMICONDUCTOR Description BU9883FV W is for DDC 3 ports 2K x 8 bit array 3 BANK EEPROM Features 1 There are 3 BANKs 1 BANK compose of 256 word address x 8 bit EEPROM 2 There are 3 DDC interface channels and each channel can access each BANK independently from other ports 3 2K bit X 3 BANK memory bits can be accessed from write port PortO 4 Operate voltage 3 0V 5 5V 5 Built in diode for power supply from HDMI ports and system 6 Automatic erase 7 8 byte page write mode 8 Low power consumption Active 5 0V 1 2mA Typ Standby 5 0V 100ygA Max 9 DATA security 10 Write Protect pin can switch write port 11 Inhibit to WRITE at low VCC 12 Pin package SSOP16pin 13 Endurance 1 000 000 erase write cycles 14 Data retention 40 years 15 Filtered inputs in all SCL SDA for noise suppression 16 Shipment data all address FFh G Absolute maximum rating Ta 25 C Parameter Symbol Rating Unit Supply Voltage VCC 0 3 6 5 V Power Dissipation Pd 400 mW Storage Temperature Tstg 65 125 C Operating Temperature Topr 40 85 C Terminal Voltage 0 3 VCC 0 3 V 1 Degradation is done at 3 0mW C for operation above 25 C 2 The Max value of terminal voltage is not over 6 5V EEPROM recommended operating cond
24. nowledge is received by the master the master immediately reissues a start condition followed by the slave address field with R W the set to 1 This device will respond with an acknowledge and then transmit the 8 data bits stored at the addressed location If the master does not acknowledge the transmission but does generate the stop condition at this point this device discontinues transmission note If the master send Acknowredge at after DO output Sequential Read is selected and this device output next address data and master can t send stop condition so master can t discontinues transmission To stop read command the master must send no Acknowledge at after DO output and issue stop condition SLAVE ADDRESS DATA n DATA n x rrr D A D TT SDA MNE ijofli ofo o o D7 Do D7 Do LI III L 4 4 LLILLLLI x A A c K EMEN Fig 49 SEQUENTIAL READ CYCLE TIMING PORT1 3 A2 40 o gt ma voa ODuring the sequential read operation the internal address counter of this device automatically increments with each acknowledge received ensuring the data from address n will be followed with the data from n 1 For read operations all bits of the address counter are incremented allowing the entire array to be read during a single operation When the counter reaches the top of the array it will roll over to the bottom of the array and continue to transmit the data OThe sequential read operation can be performed with b
25. onsumption at Reading Icc1 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vec1 V Fig 22 Standby Current Isp 2009 04 Rev B BU9883FV W Q Characteristic data The following values are Typ ones 300 250 300 200 150 100 50 STANDBY CURRENT Ls uA 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vec2 V Fig 23 Standby Current2 Isg2 DATA CLOCK HIGH PERIOD tag us 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vec V Fig 26 Data Clock High Period tyich 800 2 e e A e N o e START CONDITION SETUP TIME tsysra us 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vec V Fig 29 Start Condition Setup Time tsusta 1000 800 600 400 OUTPUT DATA DELAY TIME tpp us 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vec V Fig 32 Output Data Delay Time tpp 400 300 200 100 NOISE SPIKE WIDTH SDAO 3 and SCLO 3 t us 0 1 2 3 4 5 6 SUPPLYVOLTAGE Vcc V Fig 35 Noise Spike Width t SDAO 3 and SCLO 3 www rohm com 2009 ROHM Co Ltd All rights reserved DATA CLOCK LOW PERIOD tiowLus STOP CONDITION SETUP TIME IsggLuA STANDBY CURRENT 250 200 150 100 SUPPLY VOLTAGE Vec3 V Fig 24 Standby Current lsgs 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vec V Fig 27 Data Clock Low Period t ow INPUT DATA HOLD TIME t
26. oth current read and random read Access Control of PORTO 1 2 3 WPB terminal controls access enable of each PORT as follows PORT SALE terminal nous PORTO not accessible Read Write PORT1 Read not accessible PORT2 Read not accessible PORT3 Read not accessible Table4 WPB terminal and port accesibility When WPB terminal is HIGH PORTO only can access this device In this case when commands from PORT 2 3 are inputted these port don t return acknowledge O When WPB terminal is LOW PORTO access is not valid but PORT 1 2 3 can access this device this device Commands from PORT1 2 3 is performs independently other port www rohm com l 12 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note Software reset Software reset is executed when to avoid malfunction after power on and to reset during command input Software reset has several kinds and 3 kinds of them are shown in the figure below Refer to Fig 50 a Fig 50 b and Fig 50 c In dummy clock input area release the SDAO 3 bus H by pull up In dummy clock area ACK output and read data 0 both L level may be output from EEPROM therefore if H is input forcibly output may conflict and over current may flow leading to instantaneous power failure of system power source or influence upon devices Dummy clockx14 Startx2 SCLO 3 1 2 13L 414 l Normal command SDA0 3 L Ll Nonnal co
27. ransmit the 8 data bits stored at the addressed location If the master does not acknowledge the transmission but does generate the stop condition at this point this device discontinues transmission S T R S A SLAVE E T R ADDRESS A 9 T D DATA P SDA 1 o 1 0 0 EINE D7 DO RA A f C WK K Fig 45 CURRENT READ CYCLE TIMING PORTO www rohm com l 10 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Technical Note OWhen the command just before Current Read cycle is Random Read cycle or Current Read cycle each including Sequential Read cycle data of incremented last read address n th address i e n data of the n 1 th address is output When the command just before Current Read cycle is Byte Write or Page write data of latest write address is output Current Read operation allows the master to access data word stored in internal address counter which is appointed by P1 PO bit This operation involves a two step process This device will respond with an acknowledge and then transmit the 8 data bits stored at the addressed location If the master does not acknowledge the transmission but does generate the stop condition at this point this device discontinues transmission note If the master send Acknowredge at after DO output Sequential Read is selected and this device output next address data and master can t send stop condition so master can t discontinues transmission To stop read command the mast
28. rights reserved BU9883FV W Technical Note G Ordering part number Part No Part No Package W Double Cell FV SSOP B16 Packaging and forming specification E2 Embossed tape and reel SSOP B16 Tape and Reel information Tape Embossed carrier tape Quantity 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand Direction of feed Direction of feed c pin Unit mm Order quantity needs to be multiple of the minimum quantity www rohm com l 18 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved Notice Notes No copying or reproduction of this document in part or in whole is permitted without the consent of ROHM Co Ltd The content specified herein is subject to change for improvement without notice The content specified herein is for the purpose of introducing ROHM s products hereinafter Products If you wish to use any such Product please be sure to refer to the specifications which can be obtained from ROHM upon request Examp
29. sures a In the case when the above condition 1 cannot be observed When SDAO 3 becomes L at power on Control SCLO 3 and SDAO 3 as shown below to make SCLO 3 and SDAO 3 H and H After Vcc becomes stable i sic gt After Vcc becomes stable lt gt toH tsupar M tsu DAT Fig 61 When SCLO 3 H and SDAO 3 L Fig 62 When SCLO 3 L and SDA0 3 L b In the case when the above condition 2 cannot be observed After power source becomes stable execute software reset P11 c In the case when the above conditions 1 and 2 cannot be observed Carry out a and then carry out b G Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power and prevents wrong write At LVCC voltage Typ 1 2V or below it prevent data rewrite VCC noise countermeasures OBypass capacitor When noise or surge gets in the power source line malfunction may occur therefore for removing these it is recommended to attach a by pass capacitor 0 1uF between IC VCCout and GND At that moment attach it as close to IC as possible And it is also recommended to attach a bypass capacitor between board VCCour and GND Cautions on use 1 Described numeric values and data are design representative values and the values are not guaranteed 2 We believe that application circuit examples are recommendable however in actual use confirm characteristics further sufficiently In the case of use
30. tage2 Vj SCLO SDAO SCL1 SDA1 SCL2 SDA2 H INPUT VOLTAGES V4 V L INPUT VOLTAGEO V o V L INPUT VOLTAGE Viu V 0 1 2 3 4 5 6 0 i 2 3 4 5 6 0 1 2 3 4 5 SUPPLY VOLTAGE Vcc3 V SUPPLY VOLTAGE VecO V SUPPLY VOLTAGE Veci V Fig 5 H Input Voltage3 Vis Fig 6 L Input VoltageO Viro Fig 7 L Input Voltage1 Vi SCL3 SDA3 SCLO SDAO SCL1 SDA1 www rohm com 3 18 2009 04 Rev B 2009 ROHM Co Ltd All rights reserved BU9883FV W Q Characteristic data The following values are Typ ones ES N L INPUT VOLTAGE2 Vi V co 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vcc2 V Fig 8 L Input Voltage2 Vii 2 SCL2 SDA2 Von V L OUTPUT VOLTAGE 0 1 2 3 4 5 6 L OUTPUT CURRENT IOL mA Fig 11 L Output Voltage1 Voii loi Voc 3 0V SDA1 WP H INPUT VOLTAGE Vy4 V 0 1 2 8 4 5 8 7 8 L OUTPUT CURRENT VccO V Fig 14 WP H Input Voltage Vi INPUT LEAK CURRENTO uA 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vec V Fig 17 Input Leak Current I WPB 1500 EE a 1000 38 e Za o8 oz 54 Ee 500 fso 7 400kHz oe Each port os operation 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vec0 3 V Fig 20 Current Consumption at Reading Icc2 www rohm com 2009 ROHM Co Ltd
31. upparins 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vcc V Fig 30 Input Data Hold Time typ par tsu sro us 0 i 2 3 4 5 6 SUPPLYVOLTAGE Vcc V Fig 33 Stop Condition Setup Time tsy sro WP SET UPTIME tsu woLus SUPPLYVOLTAGE Vec V Fig 36 WP Setup Time tgu wp 5 18 START CONDITION HOLD INPUT DATA SETUP TIME tsuparIns Technical Note CLOCK FREQUENCY fso kHz 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vec V Fig 25 Clock Frequency fso 800 TIME tup sra us 0 1 2 3 4 5 6 SUPPLY VOLTAGE Vcc V Fig 28 Start Condition Hold Time typ sta 0 i 2 3 4 5 6 SUPPLY VOLATGE Vec V Fig 31 Input Data Setup Time tsupar Write Cycle Time TIME tua ms 0 1 2 3 4 5 6 SUPPLYVOLTAGE Vec V Fig 34 Write Cycle Time twr 2009 04 Rev B BU9883FV W Q Pin configuration VCC OUT SDAO Technical Note Fig 37 Pin configuration Q PIN NAME PIN No PIN NAME I O FUNCTIONS 1 VCC1 Power Supply 2 SCL1 Input Serial clock input 3 SDA1 Input output Slave and word address Serial data input serial data output 4 WPB Input Write protect terminal 1 Write enable 0 Write disable 5 VCC OUT Terminal of diode Connect Bypass capacitor 6 SDAO Input output Slave and word address Serial data input ser

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