Home

National Semiconductor NM27P040 handbook

1. Parameter Order Number Access Time ns Parameter Order Number Access Time ns NM27P040 Q 120 120 NM27P040 QE 150 150 NM27P040 Q 150 150 NM27P040 QE 170 170 NM27P040 Q 170 170 Military Temperature Range 55 C to 125 C Vcc 5V 10 Package Types NM27P040 QXXX Q Quartz Windowed Ceramic DIP Parameter Order Number Access Time ns NM27P040 QM 150 150 NM27P040 QM 200 200 Pin Names A0 A18 Addresses CE PGM Chip Enable Program OE Output Enable 00 07 Outputs XX Don t Care During Read All packages conform to the JEDEC standard e All versions are guaranteed to function for slower speeds Absolute Maximum Ratings note 1 Operating Range If Military Aerospace specified devices are required Ran Temperatur Tolerance please contact the National Semiconductor Sales ange smperarure C Fo eranee Office Distributors for availability and specifications Commercial 0 C to 70 C 5V 10 Storage Temperature 65 C to 150 C Industrial 40 C to 85 C 5V 10 All Input Voltages except AQ with Military 55 C to 125 C 5V 10 Respect to Ground Note 10 0 6V to 7V Vpp and A9 with Respect to Ground 0 6V to 14V Vcc Supply Voltage with Respect to Ground 0 6V to 7V ESD Protection gt 2000V All Output Voltages with Respect to Gr
2. QN vationat Semiconductor NM27P040 December 1993 4 194 304 Bit 512K x 8 Processor Oriented CMOS EPROM General Description The NM27P040 is a 4096K Processor Oriented EPROM POP configured as 512K x 8 It s designed to simplify microprocessor interfacing while remaining compatible with standard EPROMs It can reduce both wait states and glue logic when the specification improvements are taken advan tage of in the system design The NM27P040 is implement ed in National s advanced CMOS EPROM process to pro vide a reliable solution and access times as fast as 120 ns The interface improvements address two areas to eliminate the need for additional devices to adapt the EPROM to the microprocessor and to eliminate wait states at the termina tion of the access cycle Even with these improvements the NM27P040 remains compatible with industry standard JEDEC pinout EPROMs The time from CE or OE being negated until the outputs are guaranteed to be in the high impedance state has been reduced to eliminate the need for wait states at the termination of the memory cycle and the data out hold time has been extended to eliminate the need to provide data hold time for the microprocessor by delaying control signals or latching and holding the data in external latches Features W Fast output turn off to eliminate wait states W Extended data hold time for microprocessor compatibility W High performance CMOS 120 ns access
3. TTL program pulse is applied to the CE PGM input A program pulse must be applied at each address location to be pro grammed The EPROM is programmed with the Fast Pro gramming Algorithm shown in Figure 1 Each Address is programmed with a series of 100 us pulses until it verifies good up to a maximum of 25 pulses Most memory cells will program with a single 100 us pulse The EPROM must not be programmed with a DC signal ap plied to the CE PGM input Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements Like inputs of the parallel EPROM may be connected together when they are pro grammed with the same data A low level TTL pulse applied to the CE PGM input programs the paralleled EPROM Program Inhibit Programming multiple EPROMs in parallel with different data is also easily accomplished Except for CE PGM all like inputs including OE of the parallel EPROMs may be common A TTL low level program pulse applied to an EPROM s CE PGM input with Vpp at 12 75V will program that EPROM A TTL high level CE PGM input inhibits the other EPROMs from being programmed Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed The verify may be performed with Vpp at 12 75V Vpp must be at Vcc except during programming and program verify AFTER PROGRAMMING Opaque labels should be placed
4. over the EPROM window to prevent unintentional erasure Covering the window will also prevent temporary functional failure due to the genera tion of photo currents MANUFACTURER S IDENTIFICATION CODE The EPROM has a manufacturer s identification code to aid in programming When the device is inserted in an EPROM programmer socket the programmer reads the code and then automatically calls up the specific programming algo rithm for the part This automatic programming control is only possible with programmers which have the capability of reading the code The Manufacturer s Identification code shown in Table Il specifically identifies the manufacturer and device type The code for NM27P040 is 8F08 where 8F designates that Functional Description Continued it is made by National Semiconductor and 08 designates a 4 Megabit 512K x 8 part The code is accessed by applying 12V 0 5V to address pin A9 Addresses A1 A8 A10 A18 and all control pins are held at Vj Address pin AO is held at Vi for the manu facturer s code and held at Vi for the device code The code is read on the eight data pins Og O Proper code access is only guaranteed at 25 C 5 C ERASURE CHARACTERISTICS The erasure characteristics of the device are such that era sure begins to occur when exposed to light with wave lengths shorter than approximately 4000 Angstroms A It should be noted that sunlight and certain types of f
5. 8 the lowest possible memory power dissipation and b complete assurance that output bus contention will not occur To most efficiently use these two control lines it is recom mended that CE PGM be decoded and used as the primary device selecting function while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device Programming CAUTION Exceeding 14V on pin 1 Vpp will damage the EPROM Initially and after each erasure all bits of the EPROM are in the 1 s state Data is introduced by selectively program ming O s into the desired bit locations Although only Io 0 s will be programmed both 15 and 0 s can be pre sented in the data word The only way to change a 0 toa 4 is by ultraviolet light erasure The EPROM is in the programming mode when the Vpp power supply is at 12 75V and OE is at Vj It is required that at least a 0 1 uF capacitor be placed across Vpp Vcc to ground to suppress spurious voltage transients which may damage the device The data to be programmed is applied 8 bits in parallel to the data output pins The levels required for the address and data inputs are TTL When the address and data are stable an active low
6. F Device Code Vin 12V 0 0 0 1 0 0 0 08 NM27P040 4 194 304 Bit 512K x 8 Processor Oriented CMOS EPROM Physical Dimensions inches millimeters 1 660 MAX 32 tf daar cea de ac mc E urs F R 0 030 0 055 UV WINDOW SIZE AND CONFIGURATION TYP DETERMINED BY DEVICE SIZE 0 050 0 060 TYP 5 010 MAX 0 590 0 620 Sos M GLASS SEALANT TYP i 0 225 MAX TYP DELIS MAX 0 125 MIN 0 015 0 060 9027400 0 008 0 012 TYP TYP TYP ogha 0 090 0 110 STE BASTDIE 0 150 MIN TYP TP 0 585 10 025 885 o pep a 9 080 0100 0 015 0 021 TYP 32 Lead EPROM Ceramic Dual In Line Package JQ Order Number NM27P040QXXX NS Package Number J32AQ J32AQ REV D LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or syst
7. em whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor N Corporation Europe 1111 West Bardin Road Fax 49 0 180 530 85 86 Arlington TX 76017 Email cnjwge tevm2 nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 180 530 85 85 Fax 1 800 737 7018 English Tel 49 0 180 532 78 32 Fran ais Tel 49 0 180 532 93 58 Italiano Tel 49 0 180 534 16 80 National Semiconductor Japan Ltd Tel 81 043 299 2309 Fax 81 043 299 2408 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel 852 2737 1600 Fax 852 2736 9960 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
8. l C 100 pF Note 8 Inputs 0 8V and 2V Input Rise and Fall Times lt 5ns Outputs 0 8V and 2V Input Pulse Levels 0 45V to 2 4V AC Waveforms Notes 6 7 and 9 ADDRESSES ADDRESSES VALID X CE PGM icr NOTES 4 5 OE tor NOTES 4 5 2 0V OUTPUT VALID OUTPUT 0 8V NOTE 3 TL D 11367 3 Note 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2 This parameter is only sampled and is not 100 tested Note 3 OE may be delayed up to tacc toe after the falling edge of CE without impacting tacc Note 4 The tpr and tcr compare level is determined as follows High to TRI STATE the measured Vou1 DC 0 10V Low to TRI STATE the measured 1 DC 0 10V Note 5 TRI STATE may be attained using OE or CE Note 6 The power switching characteristics of EPROMs require careful device decoupling It is recommended that at least 8 0 1 uF ceramic capacitor be used on every device between Vcc and GND Note 7 The outputs must be restricted to Vcc 1 0V to avoid latch up and device damage Note 8 1 TTL Gate lo 1 6 mA lou 400 100 pF inc
9. ludes fixture capacitance Note 9 Vpp may be connected to Vcc except during programming Note 10 Inputs and outputs can undershoot to 2 0V for 20 ns Max Note 11 CMOS input Vj GND 0 3V Viy Voc 0 3V Programming Waveform note 3 PROGRAM PROGRAM VERIFY 29 ADDRESSES gy ADDRESS N DATA IN STABLE DATA OUT VALID DATA ms OE TL D 11367 4 Programming Characteristics Notes 1 2 3 4 Symbol Parameter Conditions Min Typ Max Units tas Address Setup Time 1 ps toes OE Setup Time 1 ps tps Data Setup Time 1 ps Vpp Setup Time 1 ps tvcs Vcc Setup Time 1 ps taH Address Hold Time 0 ps Data Hold Time 1 ps tpr Output Enable to Output Float Delay CE PGM Vin 0 60 ns tpw Program Pulse Width 95 100 105 ps toe Data Valid from OE CE PGM Vin 100 ns Ipp Vpp Supply Current during CE PGM 30 HA Programming Pulse loc Vcc Supply Current 30 mA Ta Temperature Ambient 20 25 30 C Voc Power Supply Voltage 6 0 6 25 6 5 V Vpp Programming Supply Voltage 12 5 12 75 13 0 V tFR Input Rise Fall Time 5 ns VIL Input Low Voltage 0 0 0 45 V VIH Input High Voltage 2 4 4 0 V tin Input Timing Reference Voltage 0 8 2 0 V touT Output Timing Reference Voltage 0 8 2 0 V Note 1 National s standard product warranty applies only to devices programmed to specifications described herein Note 2 Vcc must be ap
10. luores cent lamps have wavelengths in the 3000A 4000A range The recommended erasure procedure for the EPROM is ex posure to short wave ultraviolet light which has a wave length of 2537 The integrated dose i e UV intensity X exposure time for erasure should be a minimum of 15W sec cm The EPROM should be placed within 1 inch of the lamp tubes during erasure Some lamps have a filter on their tubes which should be removed before erasure An erasure system should be calibrated periodically The distance from lamp to device should be maintained at one inch The erasure time increase as the square of the dis tance from the lamp If distance is doubled the erasure time increases by factor of 4 Lamps lose intensity as they age When a lamp is changed the distance has changed or the lamp has aged the system should be checked to make cer tain full erasure is occurring Incomplete erasure will cause symptoms that can be misleading Programmers compo nents and even system designs have been erroneously suspected when incomplete erasure was the problem SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices The supply current Icc has three segments that are of interest to the system de signer the standby current level the active current level and the transient current peaks that are produced by volt age transitions on input pins The magnitude of these tran sient cu
11. ound Note 10 Vcc 1 0V to GND 0 6V Read Operation DC Electrical Characteristics over operating range with Vpp Voc Symbol Parameter Test Conditions Min Max Units VIL Input Low Level 0 2 0 8 V ViH Input High Level 2 0 Vcc 1 V VoL Output Low Voltage lo 2 1 mA 0 4 V VoH Output High Voltage lou 2 5mA 3 5 V Isp1 Vcc Standby Current CMOS CE Vcc 0 3V 100 uA Note 11 IsB2 Vcc Standby Current CE Vin 1 mA loc Vcc Active Current CE OE Vj I O 0 mA 30 PrN f 5 MHz Ipp Vpp Supply Current Vpp Vcc 10 pA Vpp Vpp Read Voltage Voc 0 4 Voc V lii Input Load Current Vin 5 5V or GND 1 pA lio Output Leakage Current Vout 5 5V or GND 10 10 pA AC Electrical Characteristics over operating range with Vpp Voc 120 150 170 250 Symbol Parameter Units Min Max Min Max Min Max Min Max tACC Address to Output Delay 120 150 170 250 tce CE to Output Delay 120 150 170 250 toe OE to Output Delay 50 50 50 50 tpr Output Disable to 35 Note 2 Output Float Pe 29 ns tcr Chip Disable to 35 Note 2 Output Float 30 a tou Output Hold from Addresses CE or OE E T Note 2 Whichever Occurred First Capacitance 25 C f 1 MHz Note 2 Symbol Parameter Conditions Typ Max Units Cin Input Capacitance Vin OV 9 15 pF CouT Output Capacitance Vout 12 15 pF AC Test Conditions Output Load 1 TTL Gate and Timing Measurement Reference Leve
12. plied simultaneously or before Vpp and removed simultaneously or after Vpp The EPROM must not be inserted into or removed from a board with voltage applied to Vpp or Vcc Note 3 The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V Care must be taken when switching the Vpp supply to prevent any overshoot from exceeding this 14V maximum specification At least a 0 1 uF capacitor is required across Vpp Vcc to GND to suppress spurious voltage transients which may damage the device Note 4 Programming and program verify are tested with the fast Progam Algorithm at typical power supply voltages and timings Note 5 During power up the CE PGM pin must be brought high Vip either coincident with or before power is applied to Vpp Fast Programming Algorithm Flow Chart ADDR FIRST LOCATION PROGRAM ONE 100 PULSE INCREMENT X DEVICE FAILED INCREMENT ADDR LAST ADDR YES Voc Vpp 5 0V 45 DEVICE FAILED VERIFY ALL BYTES DEVICE PASSED FIGURE 1 TL D 11367 5 Functional Description DEVICE OPERATION The six modes of operation of the EPROM are listed in Ta ble It should be noted that all inputs for the six modes are at TTL levels The power supplies required are Vcc and Vpp The Vpp power supply must be at 12 75V during the three programming modes and must be at 5V in the other three modes The Vcc power sup
13. ply must be at 6 25V dur ing the three programming modes and at 5V in the other three modes Read Mode The EPROM has two control functions both of which must be logically active in order to obtain data at the outputs Chip Enable CE PGM is the power control and should be used for device selection Output Enable OE is the output control and should be used to gate data to the output pins independent of device selection Assuming that addresses are stable address access time tacc is equal to the delay from CE to output tce Data is available at the outputs tog after the falling edge of OE assuming that CE PGM has been low and addresses have been stable for at least tacc tor Standby Mode The EPROM has a standby mode which reduces the active power dissipation by over 99 from of 165 mW to 0 55 mW The EPROM is placed in the standby mode by applying a CMOS high signal to the CE PGM input When in standby mode the outputs are in a high impedance state independent of the OE input Output Disable The EPROM is placed in output disable by applying a TTL high signal to the OE input When in output disable all cir cuitry is enabled except the outputs are in a high imped ance state TRI STATE Output OR Typing Because the EPROM is usually used in larger memory ar rays National has provided a 2 line control function that accommodates this use of multiple memory connections The 2 line control function allows for
14. rrent peaks is dependent on the output capacitance loading of the device The associated Vcc transient voltage peaks can be suppressed by properly selected decoupling capacitors It is recommended that at least a 0 1 uF ceramic capacitor be used on every device between Vcc and GND This should be a high frequency capacitor of low inherent inductance In addition at least a 4 7 uF bulk electrolytic capacitor should be used between Vcc and GND for each eight devices The bulk capacitor should be located near where the power supply is connected to the array The pur pose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces Mode Selection The modes of operation of the NM27P040 are listed in Ta ble I A single 5V power supply is required in the read mode All inputs are TTL levels except for Vpp and A9 for device signature TABLE I Modes Selection pin CE PGM OE Vpp Vcc Outputs Mode Read ViL X 5 0V Note 1 Output Disable X ViH X 5 0V High Z Standby VIH X X 5 0V High Z Programming VIL DIN Program Verify VIH Vit 12 75V 6 25V Dout Program Inhibit VIH 12 75V 6 25V High Z Note 1 X can be or Vy TABLE II Manufacturer s Identification Code Pins AO A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex 12 26 21 20 19 18 17 15 14 13 Data Manufacturer Code Vi 12V 1 0 0 0 1 1 1 1 8
15. time W JEDEC standard pin configuration m Manufacturer s identification code Block Diagram OUTPUT ENABLE CHIP ENABLE AND PROGRAM LOGIC 0 18 ADDRESS INPUTS TRI STATE is a registered trademark of National Semiconductor Corporation POP is a trademark of National Semiconductor Corporation Y DECODER X DECODER DATA OUTPUTS 00 07 OUTPUT BUFFERS Y GATING 4 194 304 BIT CELL MATRIX TL D 11367 1 1995 National Semiconductor Corporation TL D 11367 RRD B30M105 Printed in U S A INOHd3 SOWNO P91uenQ 10ss8204d 8 X MZIS 8 06 6 OVOdZZINN Connection Diagrams 270080 270020 270010 A19 XX Vpp XX Vpp A16 A16 A16 A15 A15 A15 A12 A12 A12 A7 A7 A7 A6 A6 A6 A5 A5 A5 A4 A4 A4 A3 A3 A3 A2 A2 A2 A1 A1 A1 AO AO AO Oo Oo Oo O4 O4 O2 O2 O2 GND GND GND Commercial Temperature Range 0 C to 70 C Note Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27P040 pin Vcc 5V 10 DIP NM27P040 270010 270020 270080 Voc Vcc _ Vcc A18 XX PGM XX PGM A18 M7 XX A17 A17 AM A14 A14 A14 ais A13 A13 A13 AB A8 A8 A8 A A9 A9 A9 di A11 A11 A11 OE Vpp s A10 A10 A10 CE FGH CE CE CE PGM o O7 O7 07 o O6 O6 Og 0 Os Os Os o O4 O4 O4 o Os Os Os TL D 11367 2 Extended Temperature Range 40 C to 85 C 5V 10

National Semiconductor NM27P040 handbook

Contents

Download Pdf Manuals

Related Search

Related Contents