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Samsung M393B2873GB0 handbook (1)

1. 133 35 0 15 gt 128 95 8 777 32 40 974 X i o 8 H 5 E 15 M n D A D 9 2 50 o e e 1 0 max lt 54 675 N al i A B 1 27 0 10 47 00 mI A 71 00 lt 19 r X
2. 133 35 0 15 gt 128 95 8 777 32 40 974 X i o 8 H 5 E 15 M n D S A c 8 2 50 o e e 1 0 max 6 54 675 1 i A B 1 27 0 10 47 00 mI A 71 00 lt 19 r X 9 50 0 80 0 05 gt lt 1 2 i 3 80 0 2 0 15 10 9 0 4 214100 1 50 0 10 Lo lt Detail A Detail B Detail C 20 3 1 x72 DIMM populated as one physical rank of x4 DDR3 SDRAMs U E 2x 2 10 0 15 J n h d n ben gt d 3 b d 4 D J 9
3. lt lt lt lt 2 X 4409002 x X 2 lt lt 5 5 52 lt m 50085589525 lt p 49255582525 5 b 925609950 0 0 92 669958 0 c ca Kerege gg c ca lt lt lt lt lt lt lt lt lt lt lt lt gt mimmin mia ci L m 111111111 VSS v ZQ VSS w4ZQ VSS VSS w DQS8 7 48085 00 0058 1005 z 005 E VSS DM D9 lt DM D8 lt CB 3 0 A DQ 3 0 DQ 3 0 8 Sige sis SBE 82 8 5 55585 8 5 55585 vss 420 VSS 420 VSS VSS w DQS3 00 E 005 DQS3 Das 8 Das 8 vss DM D7 lt D6 lt DQ 27 24 W DQ 3 0 DQ 3 0 52 algae xxES 8 SESS SSS BISISE SESS E L4 9 9 9 d VSS 29 VSS w4ZQ VSS VSS wN DQS2 w DQSs 005
4. 133 35 0 15 gt 128 95 gt 5 4 0 9 76 10 9 18 92 203240 zi 18 93 9 74 X pee ey A 5 E 2 e 4 2 r4 1 2 50 9 1 0 m 54675 Jh p se 1 27 0 10 47 00 n 71 00 51 O 3 2 00 p 0 80 0 05 1 8 1 i 3 80 MIB 0 2 0 15 10 9 0 4 A 250 27 1 50 0 10 ee DD a Detail A Detail B Detail C 20 4 1 x72 DIMM populated as two physical ranks of x4 DDR3 SDRAMs U O EH H 1 E 2x 2 10 0 15 gt EH Hon HH Ho H H IE I I I I
5. 9 N N A B 1 27 0 10 47 00 71 00 2 00 0 80 0 05 1 1 ite N i 3 80 MIB 0 2 0 15 109 04 A 17 50 A 1 50 0 10 1 00 _ 2 Detail Detail Detail C 20 5 1 x72 DIMM populated as four physical ranks of x8 DDR3 SDRAMs U E p 7 H 2x 2 10 0 15 Ly gt A HH Hu HH H
6. Address Command and Control lines The used device is 256M x4 DDR3L SDRAM FBGA DDR3 SDRAM Part NO K4B1G0446G BY NOTE Tolerances on all dimensions 0 15 unless otherwise specified SAMSUNG ELECTRONICS 50 htt p www C cond SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 20 4 256Mbx4 based 512Mx72 Module 2 Ranks 393 51706 0 Units Millimeters
7. 133 35 50 15 je gt c S 128 95 gt e Max 4 0 c 9 9 76 10 9 18 92 E 32 40 8 93 9 74 L 1 2 o 5 E E o e UR 2 50 Q 9 1 0 ai NG 0 54 675 1 27 0 10 47 00 gt Y 71 00 gt O O 9 50 0 80 0 05 1 1 ite AN i 3 80 0 2 0 15 10 9 0 4 1 50 0 10 1 00 2 NEN EU St Detail A Detail B Detail C 20 1 1 x72 DIMM populated as one physical rank of x8 DDR3 SDRAMs 2x 2 10 0 15 M J 1 L 4 mM I 3 1 O Address Command and Control lines NOTE DRAMs indicated with dotted outline are located on the backside of the module The used device is 128M x8 DDR3L SDRAM FBGA DDR3 SDRAM Part NO KAB1G0846G BY NOTE Tolerances on all dimensions 40 15 unless otherwise specified SAMSUNG ELECTRONICS 48 htt p www C cond SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 20 2 128Mbx8 based 256Mx72 Module 2 Ranks M393B56736B0 Units Millimeters
8. I I I I I I im p I I I I CUR Address Command and Control lines The used device is 128M x8 DDR3L SDRAM FBGA DDR3 SDRAM Part NO K4B1G0846G BY NOTE Tolerances on all dimensions 0 15 unless otherwise specified SAMSUNG ELECTRONICS 52
9. DQS1 w 095 gt 00 DQS7 w4 005 5 DQS zy DM1 DQS10 v IDAS 2 TDQS Z DM7 DQS16 w TDQS 2 TDQS pig 2 29510 TDQS lt TDQS lt DQS16 TDQS lt TDQS lt DQ 15 8 A DQ 7 0 E m bQI7 0 5 DQ 63 56 A DQ 7 0 1 4 00 7 0 ZQ wks ZQ ul ZQ ioo ZQ wee az az co 2 oZ 8280565685 f 5588 i Beg 5 582 489855555 DQS0 w DQs 005 Vi DQS0 w j 05 5 DQS e DMO DQS9 w 1008 pg zi TDQS 2 0959 w TDQS 5 TDQS lt DQ 7 0 A DQI7 0 P DQI7 0 29 29 2 i 8 2 50 RSOA gt CS0 SDRAMs D 3 0 08 185 Glo o OlelolS O16 O O RSOB gt CS0 SDRAMs D 7 4 E 51 RS1A 51 SDRAMs D 12 9 017 RS1B 1 SDRAMs D 16 13 BA N 0 RBA N 0 A gt BA N 0 SDRAMs D 3 0 D 12 8 017 Ww RBA N 0 B gt BA N 0 SDRAMs D 7 4 D 16 13 A N 0 RA N O A gt A N 0 SDRAMs D 3 0 D 12 8 017 RA N 0 B gt A N 0 SDRAMs D 7 4 D 16 13 Vit 34 RAS RRASA gt RAS SDRAMs D 3 0 D 12 8 017 RRASB gt RAS SDRAMs D 7 4 D 16 13 VppsPp
10. 38 88 82 m w gg oz m gt YYxase EE 555225 5852 aa Gc c 0 14 ala 111111111 1111 00813 w Das 5 Dos 00513 v DOS gt 005 gt VSS w DM lt DM lt CB 39 36 A DQ 3 0 Be 8 4 0013 0 wks 20 2 2 9 Wee 2 8456582 5659 x 0085 w 09 5 5 w 00 2 DQS 2 wN DM DQ 43 40 v Do a 03 z 923 2 Wk 55582 Ig 5 SEXE lrosoiooox lt DQS15 w 4 DOS co DQS 5 De 2 w 005 2 005 zi w DM lt DM lt DQ 55 52 v Dopo P15 033 8 Wk nln Wk oo wxxxazZ 9 2 8836582 56 59 amp DQS6 w Das 5 pas 5 n w 0095 2 DQS w DM DM lt 00 51 48 v 06 5 924 Io ips Ux az 0 Wee vad 55504 91882 56559 amp M Vtt 50 RSOA gt CS0 SDRAMs D 3 0 D 12 0 D17 wa RSOB gt CSO SDRAMs D 7 4 D 16 13 a w RS1A gt CS1 SDRAMs D 21 18 D 30 26 D35 RS1B gt CS1 SDRAMs D 25 22 D 34 31 RBAIN 0JA gt BA N 0 SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 035 BAIN 0 Y RBA N 0 B gt BA N 0 SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 RA N 0 A gt A N 0 SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 035 i RAIN O B gt A N 0
11. DQS3 095 DQS DQS5 w DQS DQS DQS3 w DQS 5 00 5 DQS5 w 4 09 5 DQS DM3 DQS12 TDQS D3 2 TDQS D12 2 5 00514 TDQS D5 2 TDQS D14 2 DQS12 TDQS lt TDQS lt DQS14 w TDQS 5 TDQS 5 DQ 31 24 DQ 7 0 097 0 DQ 47 40 Ww DQI7 0 E 007 0 29 We Wes 20 Aux tbe 2 8 25555552 zi aisle l oxr 5550 amp i 5550 Fd DQS2 w DQS DQS DQS6 w DQs DQS 0052 w DAS 5 DQS z 0056 w Das 2 DQS 5 DM2 DQS11 8 2 TDOS Z DM6 DQS15 IDQS pe 2 109 p45 gt 00511 5 lt TDQS lt DQS15 w 5 lt TDQS lt DQ 23 16 DQ 7 0 SF 00 7 0 DQ 55 48 DQ 7 0 StF 0970 5 29 ZQ 20 oo 29 ioo wS az ae az 2 5582 2 82 i 8 55585 f 5582 iM DQS1 w 095 DQS DQS7 w 005 DOS
12. DQS DQS to DQ skew per group per access tDQSQ 200 150 125 100 ps 13 DQ output hold time from DQS DQS tQH 0 38 0 38 0 38 0 38 tCK avg 13 9 DQ low impedance time from CK CK tLZ DQ 800 400 600 300 500 250 450 225 ps 13 14 f DQ high impedance time from CK CK tHZ DQ 400 300 250 225 ps 13 14 f 1 35V 90 40 z p 417 Data setup time to DQS DQS referenced to AC160 AC levels 1 5V tDS base AC175 75 25 5 d 17 1 35V irr 160 110 5 75 2 55 ps d 17 Data hold time from DQS DQS referenced to AC levels 1 5V tDH base DC100 150 100 65 45 ps d 17 1 35V 2 440 5 90 45 25 Data setup time to DQS DQS referenced to AC levels 1 5V tDS base AC150 125 75 30 10 ps DQ and DM Input pulse width for each input tDIPW 600 490 400 360 ps 28 SAMSUNG ELECTRONICS 43 htt p www BDTI C cond SAMSUNG Registered DIMM Table 21 Timing Parameters by Speed Bin Cont Rev 1 0 DDR3L SDRAM DQS DQS differential READ Preamble tRPRE 0 9 Note 19 0 9 Note 19 0 9 Note 19 0 9 Note 19 tCK 13 19 9 09 DQS differential READ Postamble tRPST 0 3 Note 11
13. ee OUT enable the same termination resistance function on TDQS TDQS that is applied to DQS DQS When dis abled via mode register A11 0 in MR1 DM TDQS will provide the data mask function and TDQS is not used X4 X16 DRAMs must disable the TDQS function via mode register A11 0 in MR1 SA 2 0 IN These signals are tied at the system planar to either Vss or to configure the serial SPD EEPROM address range SDA lO This bidirectional pin is used to transfer data into or out of the SPD EEPROM A resistor must be connected from the SDA bus line to Vppspp on the system planar to act as a pull up SCL IN This signal is used to clock data into and out of the SPD EEPROM A resistor may be connected from the SCL bus time to Vppspp on the system planar to act as a pull up EVENT a Active Low This signal indicates that a thermal event has been detected in the thermal sensing device The system ap should guarantee the electrical level requirement is met for the EVENT pin on TS SPD part V Suppl Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from DDSPD 3 0 Volt to 3 6 Volt nominal 3 3V operation The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM When RESET IN low all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register s will be set to low level the Clock D
14. 51 20 5 128Mbx8 based 512Mx72 Module 4 Ranks 393 517356 0 52 20 5 1 x72 DIMM populated as four physical ranks of xa DDR3 52 SAMSUNG ELECTRONICS 4 htt p ww BDOTI C SAMSUNG Rev 1 0 Registered DIMM DDR3L SDRAM 1 DDR3L Registered DIMM Ordering Information M393B2873GB0 YF8 H9 KO 1GB 128Mx72 128Mx8 K4B1G0846G HY 9 1 30mm M393B5673GB0 YF8 H9 KO 2GB 256Mx72 128Mx8 K4B1G0846G HY 18 2 30mm M393B5670GBO0 YF8 H9 KO 2GB 256Mx72 256Mx4 K4B1G0446G HY 18 1 30mm M393B5170GBO0 YF8 H9 KO 4GB 512Mx72 256Mx4 K4B1G0446G HY 36 2 30mm M393B5173GB0 YF8 H9 4GB 512Mx72 128Mx8 K4B1G0846G HY 36 4 30mm NOTE 1 HP F8 H9 KO 2 F8 1066Mbps 7 7 7 H9 1333Mbps 9 9 9 KO 1600Mbps 11 11 11 DDR3 1600 11 11 11 is backward compatible to DDR3 1333 9 9 9 DDR3 1066 7 7 7 DDR3 1333 9 9 9 is backward compatible to DDR3 1066 7 7 7 2 Key Features tCK min 2 5 1 875 1 5 1 25 ns CAS Latency 6 7 9 11 nCK tRCD min 15 13 125 13 5 13 75 ns tRP min 15 13 125 13 5 13 75 ns tRAS min 37 5 37 5 36 35 ns tRC min 52 5 50 625 49 5 48 75 ns JEDEC standard 1 35V 1 28V 1 45V amp 1 5V 1 425V 1 575V Power Supply Vppo 1 35V 1 28V 1 45V amp 1 5V 1 425V 1 575V 400MHz for 800Mb sec pin
15. Serial PD Thermal sensor with SPD CAS RCASA CAS SDRAMs D 3 0 D 12 8 D17 SCL 22 1 2 RCASB gt CAS SDRAMs D 7 4 D 16 13 DD L 00 017 e 7 5 WE R RWEA WE SDRAMs D 3 0 D 12 8 D17 EVENT pix M A2 E RWEB gt WE SDRAMs D 7 4 D 16 13 CKEO G RCKEOA CKEO SDRAMs D 3 0 D8 11 RCKEOB gt SDRAMs D 7 4 VREFCA DO D17 SA0 SA1 SA2 CKE1 5 RCKE1A gt CKE1 SDRAMs D 12 9 017 T RCKE1B gt CKE1 SDRAMs D 16 13 VREFDQ DO D17 ODTO E RODTOA gt ODTO SDRAMs D 3 0 D8 gt SDRAMs D 7 4 Vss 00 017 ODT1 RODT1A ODT1 SDRAMs D 12 9 D17 RODT1A gt ODT1 SDRAMs D 16 13 gt CK SDRAMs D 3 0 D8 gt SDRAMs D 7 4 NOTE PCK1A gt CK SDRAMs D 12 9 017 1 Unless otherwise noted resistor values are 150 5 PCK1B gt CK SDRAMs D 16 13 2 RSO and RS1 alternate between the back and front sides of the DIMM 1 gt SDRAMs D 3 0 D8 3 ZQ resistors are 2400 1 For all other resistor values refer to the appropriate PCKOB CK SDRAMs D 7 4 wiring diagram PCK1A gt SDRAMs D 12 9 D17 4 See the wiring diagrams for all resistors associated with the command address PCK1B gt CK SDRAMs D 16 13
16. Vix Differential Input Cross Point Voltage relative to Vpp 2 for CK CK 150 150 mV 1 Vix Differential Input Cross Point Voltage relative to Vpp 2 for DQS DQS 150 150 mV NOTE 1 The relationbetween Vix Min Max and VSEL VSEH should satisfy following VDD 2 Vix Min VSEL 2 25mV VSEH VDD 2 Vix Max 25mV Table 8 Cross point voltage for differential input signals CK DQS 1 5V Vix Differential Input Cross Point Voltage relative to Vpp 2 for CK CK a 199 175 175 1 Vix Differential Input Cross Point Voltage relative to Vpp 2 for DQS DQS 150 150 mV NOTE 1 Extended range for Vj is only allowed for clock and if single ended clock input signals CK and CK are monotonic have a single ended swing Vse of at least 2 250 mV and the differential slew rate of CK CK is larger than 3 V ns SAMSUNG ELECTRONICS 29 htt p www BDTI C cond SAMSUNG Registered DIMM 13 4 Slew Rate Definition for Single Ended Input Signals Rev 1 0 DDR3L SDRAM See Address Command Setup Hold and Derating for single ended slew rate definitions for address and command signals See Data Setup Hold and Slew Rate Derating for single ended slew rate definitions for data signals 13 5 Slew rate definition For Differential Input Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in below
17. SCcL gt M _ oe EVENT EVENT pon 200 DODA A0 A1 A2 y NE E SA0 SA1 SA2 VREFCA 4 00 017 VREFDQ 00 017 00 017 NOTE 1 Unless otherwise noted resistor values are 150 5 2 See the wiring diagrams for all resistors associated with the command address and control bus 3 70 resistors are 2400 196 For all other resistor values refer to the appropriate wiring diagram SAMSUNG ELECTRONICS 13 Rev 1 0 DDR3L SDRAM IBA N 0 B bass w Das 2058 w DQs vss DM D4 DQ 35 32 3 0 A N OVBA N 0 DN AIN 0 B vss aa DQS17 DOS DQS17 w DQs vss DM D13 DQ 39 36 DQ S 0 AIN OyBAIN 0 B vss VSS vss VSS H N amao omza RBA N 0 B gt BA N 0 SDRAMs D 7 4 D 16 13 RA N O A gt A N 0 SDRAMs D 3 0 D 12 8 017 RA N 0 B gt A N 0 SDRAMs D 7 4 D 16 13 RRASA gt RAS SDRAMs D 3 0 D 12 8 017 RRASB gt RAS SDRAMs D 7 4 D 16 13 RCASA gt CAS SDRAMs D 3 0
18. vlo NIvasv vio Nivav VOLGOUV VOAMONV VOMOdV vOMOdV vSVOuUv vOSuv 027 x Io NIvg o NIv 1do ayo Svo D25 0 als VSS 20 DQS17 w DQS vss DM CBI7 4 A DQ 3 DQS17 w DQs VSS N ZQ DQS12 5 vss DM DQ 31 28 M DQS12 5 o o o N wn wn gt gt gt lo nIva lo nlv Io NIva fo Nlv Io NIvg o NIv 100 100 100 3X9 9 2 cy 2 QN _ Svo _svo _svo 2 pen pen q9Bag 88 28 9 8825 nalaaa nalaaa o 7 7 gt gt gt Io Nlvg Io Nlv Io NIva fo Nlv Io NIvg o NIv 1 1dO 1dO EDS ES o m CN _svo 996822 S9 88 28 88859 88 nalaaa nalaaa nalaaa Ar H NS oooormu 2 0 ODDIN OQ my 010 0 5 gt 2525 gt 00 5 15 gg 2 ala o a a Vtt 18 SAMSUNG ELECTRONICS Rev 1 0
19. eene nennen nennen nnn nnn nn 26 13 3 2 Differential Swing Requirement for Clock CK CK and Strobe DQS 5 2 26 13 3 3 Single ended Requirements for Differential 28 13 3 4 Differential Input Cross Point Voltage sss nennen nene 29 13 4 Slew Rate Definition for Single Ended Input eme eem mene 30 13 5 Slew rate definition for Differential Input 30 14 AC amp DC Output Measurement Levels PE daria 30 14 1 Single Ended AC and DC Output Levels scrinia aadik 30 14 2 Differential AC and DC Output 1 enne ner nennen 30 14 3 Single ended Output Slew Rate iiie bete arte i eS RR EE ERE RAE 31 14 4 Differential Output Slew Rate lessee cans ttn e tad Sending cence eT Lut Exe e Renee one caen Rao 32 15 10 0 5 deN ON P 33 16 IDD SPEC 5 M M 35 17 Input Output Capacitate D v 38 18 Electrical Characteristics and AC enne nennen nnne 18 1 Refresh Parameters by Device Dens
20. When Vpp and Vppg are less than 500mV may be equal to or less than 300mV 11 2 DRAM Component Operating Temperature Range ToPER Operating Temperature Range 0 to 95 1 2 3 NOTE 1 Operating Temperature is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the JEDEC document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case temperature must be main tained between 0 85 C under all operating conditions 3 Some applications require operation of the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the refresh interval tREFI to 3 9us b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 Ob and MR2 A7 1b in this case IDD6 current can be increased around 10 20 than normal Temperature range 12 AC amp DC Operating Conditions 12 1 Recommended DC Operating Conditions vallaga 1 35 1 283 1 35 1 45 V 1 2 3 1 5V 1 425 1 5 1 575 V 1 2 3 VDDQ Supply Voltage for Output d et 1 5V 1
21. pas za DQS2 w DQS 5 E DQS6 w 005 lt 0 2 29811 Ww 1008 DM6 DQS15 TDQS pg EN 00811 5 EN DQS15 w 5 lt DQ 23 16 2 4 DQ 7 0 E DQ 55 48 DQ 7 0 8 xn X62 es V Serial PD 5 582 215255532 DBSED 22 Vpp t 1 1 00 08 0051 w pas za DQS7 09 za ITI T DQS1 w DQS 5 E DQS7 w Das 5 lt 1 00810 1 2 DM7 DQS16 4 TDQS D7 EH L 00510 5 00516 w TDOS VREFCA 4 D8 DQ 15 8 A DQ 7 0 E DQ 63 56 A DQ 7 0 000 i We VREFDQ DO D8 8 8 95582 82865558 Vss D0 D8 vtt 0950 pas za 0050 w 09 E 059 w 1598 pg gt 0059 w 5 EN DQ 7 0 DQ 7 0 2 NOTE a saw 1 ZQ resistors are 2400 196 For all other resistor values refer to the appropriate 8 65505 wiring diagram vtt 50 m RS0A CSO SDRAMs D 3 0 D8 815 RSOB CSO SDRAMs D 7 4 BA N 0 4 RBA N 0 A gt BA N 0 SDRAMs D 3 0 D8 RBA N 0 B gt BA N 0 SDRAMs 07 4 A N 0 W RA N OJA gt A N 0 SDRAMs D 3 0 D8 4 2 RA N 0 B gt A N 0 SDRAMs D 7 4 RAS R RRASA RAS SDRAMs D 3 0 D8 E RRASB RAS SDRAMs D 7 4 CAS G RCASA CAS SDRAMs D 3 0 D8 RCASB gt CAS SDRAMs 0 7
22. 0 49 0 51 Vpp v 34 NOTE For input only pins except RESET Veer Vrerca DC See Overshoot and Undershoot specifications section The AC peak noise on may not allow to deviate from Vgge DC by more than 1 for reference approx 15mV is used as a simplified symbol for cA 9 1 35V DC90 P 1 5V 0 100 dc is used as a simplified symbol for Vi cA 9 1 35V DC90 P 1 5V DC100 1 2 3 4 For reference approx Vpp 2 15mV 5 6 7 is used as a simplified symbol for 175 and cA AC150 cA AC 175 value is used when 175mV is referenced and cA AC150 value is used when VREF 150mV is referenced 8 Vi ac is used as a simplified symbol for cA AC175 and cA AC150 Vi cA AC175 value is used when Vggr 175mV is referenced and Vi cA AC150 value is used when Vpe_r 150mV is referenced SAMSUNG ELECTRONICS 23 Registered DIMM Table 3 Single Ended AC and DC input levels for DQ and DM htt p www BDTI C cond SAMSUNG Rev 1 0 DDR3L SDRAM 0 90 DC input logic high Vrer 90 Vpp Vrer 90 Vpp mV 159 ViL pa DC90 DC input logic low Vss Vrer 90 Vss 90 mV 1 69 160 input logic high Vrer 160 Note 2 mV 1 2 160 input logic low Note 2 Vrer 160 mV
23. 1 Used to define a differential signal slew rate 2 for CK CK use of ADD CMD and Vperca for DQS DQS use AC of DQs and Vggrepo if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however they single ended signals CK CK DQS DQS need to be within the respective limits Vj DC max Vi DC min for single ended sig nals as well as the limitations for overshoot and undershoot Refer to overshoot and Undersheet Specification SAMSUNG ELECTRONICS 26 htt p www BDTI C conf SAMSUNC Rev 1 0 Registered DIMM D D R3L SDRAM Table 4 Allowed time before ringback tDVAC for CK CK and DQS DQS 1 35V 24 0 TBD TBD 4 0 TBD TBD 3 0 TBD TBD 2 0 TBD TBD 5 1 8 TBD TBD 2 1 6 TBD TBD E 1 4 TBD TBD 1 2 TBD TBD 1 0 TBD TBD 1 0 TBD TBD gt 4 0 75 175 4 0 57 170 3 0 50 167 2 0 38 5 163 18 34 T 162 E 1 6 29 3 161 1 4 22 159 12 13 155 1 0 0 1 150 10 150 SAMSUNG ELECTRONICS 27 htt p www BDTI C cond SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 13 3 3 Single ended Requirements for Differential Signals Each individual component of a differential signal CK DQS CK DQS has also to comply with certain requirements for sing
24. All Bank Refresh to active refresh cmd time tRFC 110 160 300 350 ns 0 lt lt 85 C 7 8 7 8 7 8 7 8 us Average periodic refresh interval tREFI 85 C lt lt 95 C 3 9 3 9 3 9 3 9 us 1 NOTE 1 Users should refer to the DRAM supplier data sheet and or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material 18 2 Speed Bins and CL tRCD tRP tRC and tRAS for Corresponding Bin 18 3 Speed Bins and CL tRCD tRP tRC and tRAS for corresponding Bin DDR3 SDRAM Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin Table 17 DDR3 800 Speed Bins Internal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 ns PRE command period tRP 15 ns ACT to ACT or REF command period tRC 52 5 ns ACT to PRE command period tRAS 37 5 9 tREFI ns CL 6 CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 Supported CL Settings 6 nCK Supported CWL Settings 5 nCK SAMSUNG ELECTRONICS 39 Registered DIMM Table 18 DDR3 1066 Speed Bins htt p www BDTI C cond SAMSUNG Rev 1 0 DDR3L SDRAM Internal read command to first data tAA 13 125 20 ns ACT to internal read or write delay time tRCD 13 125 ns PRE command period tRP 13 125 ns ACT
25. ps OUtput Inversion disabled 100 300 tdynoff Maximum re driven dynamic clock off set 80 80 ps SAMSUNG ELECTRONICS 10 Rev 1 0 htt p www C cond SAMSUNG 22 DDR3L SDRAM Registered DIMM 10 Function Block Diagram 10 1 16B 128Mx72 Module Populated as 1 rank of x8 DDR3 SDRAMs 88 8848 lt ui gjg u oz en w gg w ez 2 528828 559022 2 ea 00 111111111 LLLI LLLI 0088 w Das za DQS4 w pas za 0058 w 295 2 lt 0084 Das 8 00817 TDOS D8 Z 1 DM4DQS13 w TDQS D4 00517 TDS lt 00513 TDQS EN CB 7 0 DQ 7 0 E DQ 39 32 DQI7 0 E 55552 515655532 Das I pass Das L Thermal sensor with SPD pass 095 E 5055 v 008 scL DM3 DQS12 IDOS 2 I 0 500514 IDOS ps 21 EVENT 00512 TDQS lt 00814 w TDQS EN AO 1 A2 DQ 31 24 A DQI 7 0 m DQ 47 40 DQ 7 0 m LT alu x 2 2 SAO SA1 SA2 5 5505 PERE 55 59 amp 0052 Das za DQS6
26. 9 50 0 80 0 05 gt lt 1 2 i 3 80 0 2 0 15 10 9 0 4 21100 1 50 0 10 24 100 lt Detail A Detail B Detail C 20 2 1 x72 DIMM populated as two physical ranks of x8 DDR3 SDRAMs U E 2x 2 10 0 15 J n h d n ben gt d 3 b d L D J 9 Address Command and Control lines The used device is 128M x8 DDR3L SDRAM FBGA DDR3 SDRAM Part NO K4B1G0846G BY NOTE Tolerances on all dimensions 0 15 unless otherwise specified SAMSUNG ELECTRONICS 49 htt p www C cond SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 20 3 256Mbx4 based 256Mx72 Module 1 Rank M393B56706B0 Units Millimeters
27. TSens x Tdriftrate VSens x Vdriftrate where TSens max dRTTdT dRONdTM and VSens max dRTTdV dRONdVM define the SDRAM temperature and voltage sensitivities For example if TSens 1 5 C VSens 0 15 mV Tdriftrate 1 C sec and Vdriftrate 15 mV sec then the interval between ZQCS commands is calcu lated as 0 5 1 5 x 1 0 15 x 15 0 133 128ms 24 from 13 cycles to 50 cycles This row defines 38 parameters 25 tCH abs is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge 26 tCL abs is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge 27 The tlS base AC150 specifications are adjusted from the tlS base specification by adding an additional 100 ps of derating to accommodate for the lower alter nate threshold of 150 mV and another 25 ps to account for the earlier reference point 175 mv 150 mV 1 V ns 28 Pulse width of a input signal is defined as the width between the first crossing of and the consecutive crossing of 29 tDQSL describes the instantaneous differential input low pulse width on DQS DQS as measured from one falling edge to the next consecutive rising edge 30 tDQSH describes the instantaneous differential input high pulse width on DQS DQS as measured from one rising edge to the next consecutive falling edge 31 tDQ
28. CK SDRAMs D 43 36 BPCK1A CK SDRAMs D 71 62 BPCK1B gt CK SDRAMs D 61 54 BPCKOA gt CK SDRAMs D 53 44 BPCKOB gt CK SDRAMs D 43 36 BRCKEOB CKE1 BRCKE1A CKEO BRCKE1B gt CKEO BRODT1A gt ODT1 BRODT1B gt ODT1 BPCK1A gt SDRAMs D 71 62 BPCK1B CK SDRAMs D 61 54 Err out Rev 1 0 htt p ww cond SAMSUNG DDR3L SDRAM Registered DIMM 11 Absolute Maximum Ratings 11 1 Absolute Maximum DC Ratings Vpp Voltage on pin relative to Vss 0 4 V 1 975 V V 1 3 Voltage on pin relative to Vss 0 4 V 1 975 V V 1 3 Vin Vout Voltage on any pin relative to Vss 0 4 V 1 975 V V 1 TsrG Storage Temperature 55 to 100 1 2 NOTE 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 Vpp and must be within 300mV of each other at all times and Vref must be not greater than 0 6
29. NOTE 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When making a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as requirements from CWL setting 2 tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchronized by the DLL all possible intermediate frequencies may not be guar anteed An application should use the next smaller JEDEC standard tCK AVG value 2 5 1 875 1 5 or 1 25 ns when calculating CL nCK tAA ns tCK AVG ns rounding up to the next SupportedCL 3 tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED 4 Reserved settings are not allowed User must program a different value 5 Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 6 Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 7 Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Chara
30. and tERR mper act max is the maximum measured value of tERR nper where 2 lt n lt 12 When the device is operated with input clock jitter this parameter needs to be derated by the actual tJIT per act of the input clock output deratings are relative to the SDRAM input clock For example if the measured jitter into a DDR3 800 SDRAM has tCK avg act 2500 ps tJIT per act min 72 ps and tJIT per act max 93 ps then tRPRE min derated tRPRE min tJIT per act min 0 9 x tCK avg act tJIT per act min 0 9 x 2500 ps 72 ps 2178 ps Similarly tQH min derated tQH min tJIT per act min 0 38 x tCK avg act tJIT per act min 0 38 x 2500 ps 72 ps 878 ps Caution on the min max usage SAMSUNG ELECTRONICS 46 htt p www C cond SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 19 2 Timing Parameter Notes Actual value dependant upon measurement level definitions which are TBD Commands requiring a locked DLL are READ and RAP and synchronous ODT commands The max values are system dependent WR as programmed in mode register Value must be rounded up to next higher integer value There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI For definition of RTT turn on time tAON see Device Operation amp Timing Diagram Datasheet co N 5 For definition of RTT turn off time tAOF see Device Operation amp Timing D
31. wZQ vss vss w DQS14 wDQs 295 00514 w Das E DAS E vss DM D31 DM D30 DQ 47 44 A DQ 3 0 DQ 3 0 8 882 6 xEES BESE SSS BESE 55589 E e 9 VSS w za VSS 20 vss vss w DQS15 w DQsS DQs DQS15 w DOS 2 0095 2 vss DM 033 5 DM D32 lt DQ 55 52 A DQ 3 0 5 DQ 3 0 8 abe xe 582 gee xe 52 58 825 55585 e VSS w za vss wZQ VSS vss w DQS16 2 Das 00516 005 E DQS E vss DM D35 lt D34 lt DQ 63 60 A DQ 3 0 DQ 3 0 amp 5 5 BESE SSS BESE SS SSE L4 9 9 vtt 4 M i Integrated Thermal sensor with SPD DOSED EE SCL gt 00 071 EVENT n EVENT n SDA A0 1 a L VREFCA 7 V Serial w integrated Thermal Sensor REPOS ae Vss e e 00 071 NOTE 1 Unless otherwise noted resistor values are 15Q 5 2 See the wiring diagrams for all resistors associated with the command address and control bus 3 ZQ resistors are 2400 1 For all other resistor values refer to the appropriate wiring diagram SAMSUNG ELECTRONICS 20 Registered DIMM htt p www C cond SAMSUNG S0 CKE1 v ODTO w N ARSOA gt CS1 SDRAMs D1 D3 D5 D7 D9 D1
32. 175mV is referenced Vi 150 value is used when 150 is referenced 8 Vi ac is used as a simplified symbol for Vi 175 Vii 150 175 value is used when 175mV is referenced Vi 150 value is used when Vngr 150mvV is referenced SAMSUNG ELECTRONICS 24 htt p C cond SAMSUNG Rev 1 0 DDR3L SDRAM Registered DIMM 13 2 Tolerances dc tolerance limits and ac noise limits for the reference voltages and are illustrate in Figure 1 It shows a valid reference voltage Vrer t as a function of time stands for and Vggepg likewise Vrer DC is the linear average of Vggre t over a very long period of time e g 1 sec This average has to meet the min max requirements of Fur thermore Vggre t may temporarily deviate from Vgge DC by no more than 1 Vpp A voltage Vpp VRef DC max v VDD 2 VRef DC min Vss time Figure 1 Illustration of VREF DC tolerance and VREF ac noise limits The voltage levels for setup and hold time measurements Vj Vi DC Vi AC and DC are dependent on VREF shall be understood as Vgge DC as defined in Figure 1 This clarifies that dc variations of affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefo
33. 4GB 512Mx72 Module IDDO 1194 1360 1214 1390 mA 1 IDD1 1239 1405 1306 1453 mA 1 IDD2PO slow exit 870 900 900 940 mA IDD2P1 fast exit 942 972 972 1012 mA IDD2N 1002 1150 1032 1190 mA IDD2Q 982 1130 1022 1170 mA IDD3P 942 1080 972 1120 mA IDD3N 1208 1320 1212 1360 mA IDD4R 1419 1585 1529 1705 mA 1 IDD4W 1429 1595 1539 1715 mA 1 IDD5B 1604 1770 1689 1855 mA 1 IDD6 390 390 390 390 mA IDD7 1824 1990 2069 2245 mA 1 IDD8 390 390 390 390 mA NOTE 1 DIMM IDD SPEC is calculated with considering de actived rank IDLE is IDD2N SAMSUNG ELECTRONICS 37 Registered DIMM 17 Input Output Capacitance Table 16 Input Output Capacitance htt p www BDTI C cond SAMSUNG Rev 1 0 DDR3L SDRAM Input output capacitance Input output capacitance LI 13 2 1 2 1 2 1 2 2 F 1 2 DQ DM Das 205 TDQS 2 3 edi Input capacitance K 1 1 6 TBD TBD TBD TBD F 2 CK and CK CC 0 8 6 0 8 3 Input capacitance delta DCK 2 TBD TBD TBD TBD F 2 3 4 CK and CK CDC 0 0 15 0 0 15 p 3 Input capacitance _ 075 13 075 13 075 13 075 13 pF 236 All other input only pins Input Output capacitance delta CDDQS 0 0 2 0 0 2 TBD TBD TBD TBD F 2 3 5 008 and DAS 2 Input capacitance delia CDI_CTRL 05 05 TBD pF 2 3 7 8
34. 67 22 0054 w Das 00 0054 w Das us D DQ 39 32 W DQ 7 0 DQ 7 0 7 270 7 ox Is Is 5 6 6 22 ONO 0055 w pas O e DQS5 Das EE bos 54 DQ 47 40 W 4 DQI 7 0 7 0 70 m ZQ 851626 655465 0086 w pas 9 pas DQS6 w DQS 00 Ux DQ 55 48 W 4 DQ 7 0 DQ 7 0 7 40 BSls26 851526 DQS3 w pas O cio DQS3 bas us 888 Uit DQ 31 24 DQI7 0 DQ 7 0 fl ZQ m ZQ Vtt 34 SAMSUNG ELECTRONICS 16 DDR RS0 CSO SDRAMs D 8 0 Rev 1 0 3L SDRAM RS1 gt CS1 SDRAMs D 17 9 RS2 gt 52 SDRAMs D 26 1 8 RS3 gt CS3 SDRAMs D 35 27 WBAJ N 0 gt BA N 0 SDRAMs 04 0 D8 D 13 9 D 22 18 D 31 27 EBA N 0 gt BA N 0 SDRAMs 08 5 D 17 14 D 26 23 D 35 32 WAJ N 0 gt A N 0 SDRAMs D 4 0 08 D 13 9 D 22 18 D 31 27 EA N 0 gt A N 0 SDRAMs 0 8 5 D 17 14 D 26 23 D 35 32 WRAS gt RAS SDRAMs 0 D8 D 13 9 D 22 18 D 31 27 RAS ERAS gt RAS SDRAMs 018 5 D 17 14 D 26 23 D 35 32 NU WCAS gt CAS SDRAMs D 4 0 D8 D 13 9 D 22 18 D 31 27 ECAS gt CAS SDRAMs 018 5 D 17 14 D 26 23 D 35 32 WE 1 2 WWE gt WE SDRAMs D 4 0 D8 D 13 9 D 22 18 D 31
35. D 12 8 017 RCASB gt CAS SDRAMs D 7 4 D 16 13 RWEA gt WE SDRAMs D 3 0 D 12 8 017 RWEB gt WE SDRAMs D 7 4 D 16 13 RCKEOA gt SDRAMs D 3 0 D 12 8 D17 RCKEOB gt CKEO SDRAMs D 7 4 D 16 13 RODTOA gt SDRAMs D 3 0 D 12 8 017 gt ODTO SDRAMs D 7 4 D 16 13 PCKOA gt SDRAMs D 3 0 D 12 8 017 PCKOB gt CK SDRAMs D 7 4 D 16 13 PAR IN we RESET PCKOA gt CK SDRAMs D 3 0 D 12 8 D17 gt SDRAMs D 7 4 D 16 13 QERR Err out RST RST SDRAMs D 17 0 S 3 2 CKE1 ODT1 CK1 and CK1 are NC Unused register inputs ODT1 and CKE1 have 330 resistor to ground RBA N 0JA gt BA N 0 SDRAMs 0 3 0 D 12 8 017 htt p www C cond SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 10 4 4GB 512Mx72 Module Populated as 2 ranks of x4 DDR3 SDRAMs X lt lt lt lt lt lt lt 585558 52 lt 5506 52955558552 lt 55 91515 XxxOz xxx 255 201265 2 lt 9 ool olovo z 2 6825008 sa i4 X ad 0 a ac ac 111111111 1111 111111111 1111 DQS17 00 5 Das 5 DQS17 DAS E 009 5 00517 w 005 2 Das gt DQS17 005 2 DQS 2 55 w DM lt DM lt VSS w DM lt DM lt CB 7 4 A DQ 3 0 su
36. DDR3L SDRAM Annwn BDTI C cond SAMSUNG htt p Registered DIMM vesyg vlo Nlvasg vio Nivug voayoug vouoda vooda vsvoud vsvuud vesud vss W VSS VSS VSS VSS w VSS VSS w VSS 7 7 VISWV o NIvg fo NIv 1 Io NIvg o NIv 1 0 30 Io NIvg Io NIv 1 390 o NIva fo Nlv 1 o lt SVO O sva vlo NIvasv vio Nivav VOLGOUV VOAMONV VOMOdV vOMOdV vawuv vSVOuUv vOSuv 011 x Io NIvg o NIv 1do SV9 25 So D13 VSS 20 DQS4 w DQS VSS DQ 35 32 W Days DQS4 w DQs VSS N ZQ DQS5 w DQs vss 00 43 40 w DQS5 5 Io Nlvg Io Nlv o NIva fo Nl
37. WL 2 WR WL 2 WR BCAMRS tWRAPDEN 1 1 10 Timing of REF command to Power Down entry tREFPDEN 1 1 1 1 20 21 Timing of MRS command to Power Down entry tMRSPDEN tMOD min tMOD min tMOD min tMOD min command and BC4 PB 5 7 4 B 4 7 4 P nck ODT high time with Write command and BL8 ODTH8 6 6 6 6 nCK Asynchronous RTT turn on delay Power Down with tAONPD 2 85 2 85 2 85 2 85 is DLL frozen Asynchronous RTT turn off delay Power Down with DLL frozen tAOFPD 2 8 5 2 8 5 2 8 5 2 8 5 ns RTT turn on tAON 400 400 300 300 250 250 225 225 ps 71 RTT NOM and RTT WR turn off time from ODTLoff reference tAOF 0 3 0 7 0 3 0 7 0 3 0 7 0 3 0 7 tCK avg 8f RTT dynamic change skew tADC 0 3 0 7 0 3 0 7 0 3 0 7 0 3 0 7 tCK avg f First DQS pulse rising edge after tDQSS margining tWLMRD 40 40 40 40 _ 3 mode is programmed DQS DQS delay after 5 margining mode is pro tWLDQSEN 25 1 25 25 1 25 1 3 grammed Write leveling setup time from rising CK CK crossing 1 to rising DQS DQS crossing mE ad n 199 163 Ps Write leveling hold time from rising DQS DQS cross ing to rising CK CK crossing 325 1 245 1 195 1 165 1 ps Write leveling output delay tWLO 0 9 0 9 0 9 0 7 5 ns Write leveling output error tWLOE 0 2 0 2 0 2 0 2 ns SAMSUNG ELECTRONICS 45 htt p www C cond SAMSUNG Rev
38. 0082 v 095 E DQS E vss DM D5 DM 04 lt DQ 19 16 A DQ 3 0 E DQ 3 0 5 5 2 xxES SISISE SSE 58S BISISE SE 589 9 9 L4 VSS W4ZQ VSS w4ZQ VSS VSS DQS1 w DQSs 2 005 0051 v DAQS z DQS z vss DM D3 lt DM D2 lt DQ 11 8 W DQ 3 0 DQ 3 0 SE xe 52 xe 8 52 56 58 BISISE SS 58 VSS w 4ZQ VSS w4ZQ VSS VSS w DQS0 w DQs 00 0050 5 E 005 E VSS DM D1 lt DM DO DQ 3 0 A DQ 3 0 DQ 3 0 2 52 xs 82 8 5 55585 55 58 amp 9 9 9 9 La Vtt 34 SAMSUNG ELECTRONICS eis Rev 1 0 DDR3L SDRAM Annwn BDTI C cond SAMSUNG htt p Registered DIMM vesyg vlo Nlvasg vio Nivug voayoug vooda vsvoud vsvuud vesud vss W VSS VSS VSS VSS w VSS w VSS W 7 7 VISWV o NIvg fo NIv 1 Io NIvg o NIv 1 30
39. All control input only pins Input capacitance delta all ADD and CMD input only pins CDI ADD CMD 0 5 0 5 0 5 0 5 TBD TBD TBD TBD pF 2 3 9 10 Input output capacitance delta DI 0 0 5 0 TBD TBD TBD TBD F 2 3 11 DQ DM Das 205 TDQS TDQS a e 5 P m Input output capacitance of ZQ pin CZQ 1 3 3 TBD TBD TBD TBD pF 2 3 12 1 3 1 2 7 1 2 1 4 2 F 1 2 DQ DM 00 DAS TDAS a 3 d Input capacitance K 1 6 1 1 4 1 4 F 2 CK and CK CC 0 8 0 8 6 0 8 0 8 3 Input capacitance delta DCK 4 4 4 4 2 3 4 CK CDC 0 0 15 0 0 15 0 0 15 0 0 15 3 Input capacitance Cl 075 15 075 15 075 13 075 13 pF 236 All other input only pins Input capacitance delta CDDQS 0 0 2 0 0 2 0 0 15 0 0 15 F 2 3 5 005 and DAS Input capacitance delta CDI CTRL 05 03 05 4041 02 04 02 pF 2378 All control input only pins Input capacitance delta all ADD and CMD input only pins CDI ADD CMD 0 5 0 5 0 5 0 5 0 4 0 4 0 4 0 4 pF 2 3 9 10 Input output capacitance delta DI 0 j 0 0 0 0 2 3 11 DQ 005 005 TDQS TDQS 9 n ii us d vm 93 P P Input output capacitance of ZQ pin CZQ 1 3 3 3 3 pF 2 3 12 NOTE This parameter is Component Input Output Capacitance so that is different from Module leve
40. Das 5 pas 5 2954 w DAS 2 DQS gt VSS DM Ed DM Ed DQ 35 32 Ww DQ 3 0 Da 0 D22 m 2 olg 5 Z asia 8 sae d ot DQS16 w 00 5 Das 00516 w 005 2 DQS 22 vss DM Ed DM lt DQ 63 60 DQ 3 0 DIO E 4 DQ 3 0 D34 5 010 WES uc Ux sx az Wee oz age 51556 RES 5 DQS10 005 Das m 00510 Das a DQS gt VSS DM DM lt DQ 59 56 A DQ 3 0 277 4 DQ 3 0 D25 5 Dn 99 ure az az 48455532 28656485 Vtt Integrated Thermal sensor in SPD SCL gt EVENT EVENT 4 5 SDA AO A1 A2 SA0 SA1 SA2 Serial PD w integrated Thermal sensor Serial PD oue c 3 DO D35 VH VREFCA 4 00 035 VReEFDQ 00 035 Vss JT 1 po pss NOTE 1 See wiring diagrams for resistor values DDR3L SDRAM
41. and control bus PAR IN QERR out RESET RST RST SDRAMs D 8 0 S 3 2 CKE1 ODT1 CK1 and CK1 are NC SAMSUNG ELECTRONICS 12 htt p www BDTI C cond SAMSUNG Registered DIMM 10 3 26B 256Mx72 Module Populated as 1 rank of x4 DDR3 SDRAMs RCKEOA RODTOA A N O BA N 0 N XAIN 0JA VSS ara I RWEA Dass w DOS Dass w bas vss DM 08 CB 3 0 W 29 3 0 029517 w DGS DQS17 w DQS vss j DM D17 CB 7 4 DQ 3 0 n n 8 A N OJBA N 0 Dj DQS3 w 09 za DQS17 w Das za 0058 w Das 20 00517 Das 20 DQS3 w Das DQS17 wv DQS 0058 w Das 00517 v Das vss DM D3 210 vss 012 vss D5 vss m 014 2 DQ 27 24 W 2913 0 a DQ 31 28 DQ 0 5 43 40 W DQ 0 0917 44 DQ 0 a 5 5 5 5 wes sige wes wes sige wes 8 8 55582 8 8 55582 8 84855582 8 84855582 La gt pass w Das za 00517 w 00 za 0058 w
42. partially toggling Data IO seamless read data burst with different data between one burst and the next one DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details Refer to Component Datasheet for detail pattern Operating Burst Write Current CKE High External clock On tCK CL Refer to Component Datasheet for detail pattern BL 87 AL 0 CS High between WR Command Address IDD4W Bank Address Inputs partially toggling Data IO seamless write data burst with different data between one burst and the next one DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at HIGH Pattern Details Refer to Component Datasheet for detail pattern Burst Refresh Current IDD5B CKE High External clock On tCK CL nRFC Refer to Component Datasheet for detail pattern BL 81 AL 0 CS High between REF Command Address Bank Address Inputs partially toggling Data IO FLOATING DM stable at 0 Bank Activity REF command every nRFC Output Buffer and RTT Enabled in Mode Registers2 ODT Signal stable at 0 Pattern Details Refer to Component Datasheet for detail pattern Self Refresh Current Normal Temperature Range IDDG TCASE 0 85 C Auto Self Refresh ASR Disabled Self Refresh Tempera
43. 0 3 Note 11 0 3 Note 11 0 3 Note 11 tCK 11 13 b DQS DQS differential output high time tQSH 0 38 0 38 0 4 0 4 tCK avg 13 g DQS DQS differential output low time tQSL 0 38 0 38 0 4 0 4 tCK avg 13 g DQS DQS differential WRITE Preamble 0 9 0 9 0 9 0 9 tCK DQS DQS differential WRITE Postamble tWPST 0 3 0 3 0 3 0 3 tCK ep d rising edge output access time from rising tDQSCK 400 400 300 300 255 255 225 225 ps 13 f D DGS low impedance time Referenced rom RE 2800 400 600 300 500 250 450 225 ps 13 14 DQS DQS high impedance time Referenced from 1HZ DQS 1 400 1 300 1 250 1 225 ps 12 13 14 RL BL 2 DQS DQS differential input low pulse width tDQSL 0 45 0 55 0 45 0 55 0 45 0 55 0 45 0 55 tCK 29 31 DQS DQS differential input high pulse width tDQSH 0 45 0 55 0 45 0 55 0 45 0 55 0 45 0 55 tCK 30 31 DQS DQS rising edge to CK CK rising edge tDQSS 0 25 0 25 0 25 0 25 0 25 0 25 0 27 0 27 tCK avg DQS DQS falling edge setup time to CK CK rising edge tDSS 0 2 0 2 0 2 0 18 tCK avg c 32 DQS DQS falling edge hold time to CK CK rising edge DSH 0 2 0 2 0 2 0 18 tCK avg c 32 DLL locking time DLLK 512 512 512 512 internal READ Command to PRECHARGE Command RTP max _ _ 1 8 delay 4nCK 7 5ns 4nCK 7 5ns 4nCK 7 5ns 4nCK 7 5ns Delay from start of internal write transaction to internal WTR max 1 1 18 read command 4nCK
44. 1 2 135 AC input logic high Vngr 135 Note 2 135 2 mV 1 2 135 input logic low Note 2 Vrer 135 Note 2 Veer 135 mV 1 2 Vrerpa DC Voltage TOF DQ 0 49 Vpp 0 51 Vpp 0 49 Vpp 0 51 Vpp 34 uu x 100 input logic high 100 Vpp Vngr 100 Vpp mV 1 55 Vi po DC100 DC input logic low Vss Vrer 100 Vss Vngr 100 mV 1 69 175 input logic high Vrer 175 NOTE 2 1 mV 127 175 AC input logic low NOTE 2 Vngr 175 2 mV 128 150 input logic high Veer 150 NOTE 2 Veer 150 NOTE 2 mV 1 2 7 150 AC input logic low NOTE 2 Vrer 150 NOTE 2 Vngr 150 mV 1 2 8 Vrerpa DC PUE Voltage 0r DO 0 49 Vpp 0 51 Vpp 0 49 Vpp 0 51 Vp v 34 NOTE For input only pins except RESET Vger Vrerpa DC See Overshoot Undershoot Specification on page 18 The AC peak noise on may not allow Vggr to deviate from Vgge DC by more than 1 Vpp for reference approx 15mV is used as a simplified symbol for Vi 1 35V DC90 P 1 5 DC100 dc is used as a simplified symbol for 1 35V DC90 P 1 5V DC100 1 2 3 4 For reference approx Vpp 2 15mV 5 6 7 is used as a simplified symbol for 175 Viu 150 Viu 175 value is used when
45. 4 WE 5 RWEA gt WE SDRAMs 0 3 0 D8 T RWEB gt WE SDRAMs D 7 4 CKEQ RCKEOA gt CKEO SDRAMs D 3 0 D8 R RCKEOB CKEO SDRAMs D 7 4 ODTO RODTOA ODTO SDRAMs D 3 0 D8 RODTOB gt ODTO SDRAMs D 7 4 CKO PCKOA gt CK SDRAMs D 3 0 D8 en PCKOA CK SDRAMs D 7 4 CKO PCKOA gt CK SDRAMs D 3 0 08 PCKOA gt CK SDRAMs D 7 4 PAR_IN QERR Err out RESET BBE RST SDRAMs D 8 0 S 3 2 CKE1 ODT1 CK1 and CK1 are NC Unused register inputs ODT1 and CKE1 have a 330 ohm resistor to ground SAMSUNG ELECTRONICS 11 htt p www BDTI C cond SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 10 2 26B 256Mx72 Module Populated as 2 ranks of x8 DDR3 SDRAMs lt lt lt lt lt mm lt lt qarr eam maooomo SSE m ES TS 01 3 TIMES EME 2 keer se 2 AIA o c alice 0958 DQS DQS DQS4 w DQS DQS 0058 w 695 DQS 5 0054 w Das 5 005 5 DM8 DQS17 TDQS D8 z TDQS D17 2 DM4 DQS13 w TDQS 04 2 TDQS D13 09517 TDQS lt TDQS lt DQS13 TDQS lt TDQS 5 7 0 Ww DQ 7 0 2 1 DQI7 0 5 DQ 39 32 Ww DQ 7 0 7 0 ZQ wks ZQ wes ZQ ZQ Weve 2 Wie VOZ 9 2 algae x eae 955555552 SSeS 955555555
46. 4 09 za DQS17 w DQS 20 0058 Das 5 00517 w Das 0058 Das DQS17 w DAS 5 vss DM D2 2 vss DM D11 F4 vss DM D6 2 vss DM D15 2 DQ 19 16 W 13 0 lt DQ 23 20 C DQ 3 0 lt DQ 51 48 0913 0 5 09 55 52 C DQ 3 0 DY wre DY wre DIN were DIN wp 2 az 2 2 829 55885 55885 829 55885 0 55885 La pass w Das za DQS17 w Das za 00858 Das za DQS17 w Das za pass w Das 00517 w 805 0058 w Das S DQS17 DAS vss 0 01 210 vss DM o vss DM D7 o vss DM 016 DQ 11 8 W DQ 3 0 a DQ 15 12 0913 0 KC DQ 59 56 DQ 0 DQ 63 60 DQ 0 5 mas 7 ms nn wre eyes ayes az az 888655882 888655882 838 45582 838 5582 pass w Das za 00517 w Das za Vtt w 0058 w Das DQS17 w 095 VSS BM VSS DM Z o 50 RS0A CS0 SDRAMs D 3 0 D 12 8 017 DQ 3 0 DQ 3 0 amp 2 20974 5989 a 2 RSOB 650 SDRAMs D 7 4 D 16 13 5 W wes Wy 2 az 9 55885 829 55885 B Thermal sensor with SPD Vppspp Serial PD
47. 425 1 5 1 575 V 1 2 3 NOTE 1 Under all conditions must be less than or equal to Vpp 2 Vppq tracks with Vpp AC parameters are measured with Vpp and tied together 3 Vpp amp rating determinied by operation voltage SAMSUNG ELECTRONICS 22 htt p www BDTI C cond SAMSUNG Registered DIMM 13 AC amp DC Input Measurement Levels 13 1 AC amp DC Logic Input Levels for Single ended Signals Table 2 Single Ended AC and DC input levels for Command and Address Rev 1 0 DDR3L SDRAM CMD inputs Vin ca DC90 DC input logic high Vrer 90 Vpp mV 1 59 Vit ca DC90 DC input logic low Vss Vrer 90 mV 1 69 160 input logic high Vrer 160 Note 2 mV 1 2 Vii cA AC160 AC input logic low Note 2 Veer 160 mv 1 2 Vin ca AC135 input logic high Vngr 135 Note 2 mV 1 2 Vit ca AC135 input logic lowM Note 2 Vngr 135 mV 1 2 00 Reference Voltage for ADD 0 49 0 51 Vpp v 3 4 Viu cA DC100 DC input logic high Vrer 100 mV 1 50 cA DC100 DC input logic low Vss Vger 100 mV 1 60 Vin ca AC175 input logic high Vrer 175 Note 2 mV 1 2 7 Vit ca AC175 AC input logic low Note 2 Vngr 175 mV 1 2 8 Vin ca AC150 input logic high Vggr 150 Note 2 mV 1 2 7 Vit ca AC150 input logic low Note 2 150 mV 1 2 8 VnercA DC
48. 7 5ns 4nCK 7 5ns 4nCK 7 5ns 4nCK 7 5ns WRITE recovery time tWR 15 15 15 15 ns e Mode Register Set command cycle time MRD 4 4 4 4 nCK Mode Register Set command update delay MOD 12 15 12nCK 15ns 12nCK 15ns 500 t2nCK 15ns CAS to CAS command delay CCD 4 4 4 4 nCK Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK AVG nCK Multi Purpose Register Recovery Time tMPRR 1 1 1 1 nCK 22 ACTIVE to PRECHARGE command period tRAS See Speed Bins and CL tRCD tRP tRC and tRAS for corresponding Bin ns e ACTIVE to ACTIVE command period for 1KB size tRRD 4nCK_10ns AnCK 7 5ns 5 4nCK 6ns 5 AnCK 5 ACTIVE to ACTIVE command period for 2KB page size tRRD 4nCK_10ns 4nCK_10ns 5 Sns 4nCK 7 5ns Four activate window for 1 page size tFAW 40 37 5 30 30 ns e Four activate window for 2KB page size tFAW 50 50 45 40 ns e 1 35V prn 215 140 5 80 60 b 16 Command and Address setup time to CK CK refer enced to Viy AC Vi AC levels 1 5V tlS base 175 200 125 65 45 ps b 16 1 35V 285 210 150 130 ps b 16 Command and Address hold time from CK CK refer enced to Vi AC levels 1 5V tlH base DC100 275 200 140 120 ps b 16 1 35V 2 5 365 290 205 185 ps b 16 27 Command and Address setup time to CK CK refer e
49. In ODTO and ODT1 Selects which SDRAM bank of eight is activated BA 2 0 Input BAO BA2 define to which bank an Active Read Write or Precharge command is being applied Bank address also determines mode register is to be accessed during an MRS cycle Provided the row address for Active commands and the column address and Auto Precharge bit for Read Write commands to select one location out of the memory array in the respective bank A10 is sampled dur b d ing a Precharge command to determine whether the Precharge applies to one bank A10 LOW or all banks 10 AP 9 0 A10 HIGH If only one bank is to be precharged the bank is selected by BA A12 is also utilized for BL 4 8 di identification for BL on the fly during CAS command The address inputs also provide the op code during Mode Register Set commands DQ 63 0 CB 7 0 y o Data and Check Bit Input Output pins Active High Masks write data when high issued concurrently with input data DM 8 0 Vss Supply Power and ground for the DDR SDRAM input buffers and core logic V11 Supply Termination Voltage for Address Command Control Clock nets DQS 17 0 Positive Edge Positive line of the differential data strobe for input and output data DQS 17 0 y o Negative Edge Negative line of the differential data strobe for input and output data TDQS TDQS is applicable for X8 DRAMs only When enabled via Mode Register A11 1 in DRAM will
50. RAS 113 Vss 233 DQ62 33 DQS3 153 TDQS12 73 WE 193 50 114 0058 234 DQ63 34 DQS3 154 Vss 74 CAS 194 Vpp 115 DQ59 235 Ves 35 Vss 155 DQ30 75 Vpp 195 ODTO 116 Vss 236 VppsPD 36 DQ26 156 DQ31 76 S1 NC 196 A13 117 SAO 237 SA1 37 DQ27 157 Vss 77 ODT1 NC 197 Vpp 118 SCL 238 SDA 38 Vss 158 CB4 NC 78 198 S3 NC 119 SA2 239 Vss 39 CBO NC 159 CB5 NC 79 S2 NC 199 Vss 120 240 Vor 40 CB1 NC 160 Vss 80 Vsg 200 DQ36 41 Vss 161 3G NG 81 DQ32 201 DQ37 NOTE NC No internal Connection SAMSUNG ELECTRONICS CO Ltd reserves the right to change products and specifications without notice SAMSUNG ELECTRONICS 6 htt p www BDTI C cond SAMSUNG Registered DIMM 5 Pin Description Rev 1 0 DDR3L SDRAM CKO Clock Input positive line 1 ODT 1 0 On Die Termination Inputs 2 CKO Clock Input negative line 1 DQ 63 0 Data Input Output 64 CKE 1 0 Clock Enables 2 CB 7 0 Data check bits Input Output 8 RAS Row Address Strobe 1 DQS 8 0 Data strobes 9 CAS Column Address Strobe 1 DQS 8 0 Data strobes negative line 9 DNM 8 0 WE Write Enable 1 DOS 17 9 1 2 9 TDQS 17 9 E DQS 17 9 Data strobes negative line Termination data 000 TDQS 17 9 strobes 9 9 0 11 A 15 13 Address Inputs 2114 RFU Reserved for Future Use 2 A10 AP Address Input Autoprecharge 1 EVENT Reserved oreplional hardwa
51. RST RST SDRAMs D 35 0 Registered DIMM htt p www BDTI C cond SAMSUNG 10 5 46B 512Mx72 Module Populated as 4 ranks of x8 DDR3 SDRAMs 82 33 528828 2053 2088 gt 9 5 CECI COS 52 22 0050 w Das pas 9g DQS0 v Das uo 095 DQ 7 0 W4 Pepe 7 Is Is Oooxn 0081 w pas O pas Se 0051 Das H 098 77 DQ 15 8 M DAOI 2556 85626 DQS2 w DAS O Sg DQS2 w DQS no 00 Un DQ 23 16 W Bom DQ 7 0 2 20 686 575 8 85 DQS3 w pas O 1 pas 9g DQS3 bas us M 888 DQ 31 24 M DQ 7 0 DQ 7 0 fl ZQ F 1 ZQ BSls26 851626 0088 w pas 00 o0 DQS8 w DQS y DQS T CB 7 0 W DQ 7 0 091 0 f za ZQ Vtt 34 Qa a 850666 36666 898 89 829 86 O A A gt O A gt ox Is Is
52. Table 9 Differential input slew rate definition NE NE Varenne Vikas Differential input slew rate for rising edge CK CK and DQS DQS Vil diffmax EN DONNE Differential input slew rate for falling edge CK CK and DQS DQS ViiHdiffmin ViLdiffmax Mee i NOTE The differential signal i e CK CK and DQS DQS must be linear between these thresholds 0 ViLdiffmax delta TFdiff delta TRdiff Figure 5 Differential input slew rate definition for DOS DQS and CK CK 14 AC amp DC Output Measurement Levels 14 1 Single Ended AC and DC Output Levels Table 10 Single Ended AC and DC output levels DC output high measurement level for IV curve linearity 0 8 x VDDQ V Vom DC DC output mid measurement level for IV curve linearity 0 5 x VDDQ V Vo_ DC DC output low measurement level for IV curve linearity 0 2 x VDDQ V AC output high measurement level for output SR 0 1 x V 1 output low measurement level for output SR 0 1 x V 1 NOTE 1 The swing of 0 1 Vppq is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 400 and an effective test load of 250 to 2 14 2 Differential AC and DC Output Levels Table 11 Differential AC and DC output levels Vougis AC AC different
53. falling edge Um NOTE Output slew rate is verified by design and characterization and may not be subject to production test Table 15 Differential Output slew rate 1 35V 3 5 12 3 5 12 3 5 12 3 5 12 Vins Single ended output slew rate SRQdiff 1 5V 5 10 5 10 5 10 5 10 Vins Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output diff Differential Signals For Ron RZQ 7 setting delta TFdiff delta TRdiff Figure 7 Differential output slew rate definition SAMSUNG ELECTRONICS 32 htt p www C cond SAMSUNG Rev 1 0 Registered DIMM DDR3L SDRAM 15 IDD specification definition Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL Refer to Component Datasheet for detail pattern BL 87 AL 0 CS High between ACT and PRE IDDO Command Address Bank Address Inputs partially toggling Data IO FLOATING DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details Refer to Component Datasheet for detail pat tern Operating One Bank Active Read Precharge Current CKE High External clock On tCK nRC
54. nRAS nRCD CL Refer to Component Datasheet for detail pattern BL 87 AL 0 5 High between ACT RD IDD1 and PRE Command Address Bank Address Inputs Data IO partially toggling DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details Refer to Component Datasheet for detail pat tern Precharge Standby Current IDD2N CKE High External clock On tCK CL Refer to Component Datasheet for detail pattern BL 87 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling Data IO FLOATING DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details Refer to Component Datasheet for detail pattern Precharge Power Down Current Slow Exit IDD2P0 CKE Low External clock On tCK CL Refer to Component Datasheet for detail pattern BL 87 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATING DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Precharge Power Down Current Fast Exit IDD2P4 CKE Low External clock On tCK CL Refer to Component Datasheet for detail pattern BL 87 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATIN
55. quad rank 79 S2 NC RDIMMs not connected on single or dual rank NC Not used on UDIMMs RDIMMs 167 NC TEST input used only on bus analysis probes NC 20 used sniy on analysis 169 CKE1 Connected to the register on dual and quadrank CKE1 Used for dual rank UDIMMs not connected RDIMMs NC on single rank RDIMMs NC on single rank UDIMMs 171 A15 A15 NC Depending on device density may not be 172 A14 Connected to the register on all RDIMMs A14 connected to SDRAMS oni UDIMMS However these signals are terminated on 196 A13 A13 UDIMMs A15 not routed on some RCs E Connected to the register on quad rank 198 S3 NC RDIMMs not connected on single or dual rank NC Not used on UDIMMs RDIMMs 39 40 45 46 158 159 164 CBn Used on all RDIMMs 0 7 Nc cgn Veet on x72 MDIMMS n 0 7 not 165 used on x64 UDIMMs i pas on x soraus E E E E 212 221 230 TDQSn TDQS on x8 SDRAMs on RDIMMs n 9 17 0 8 126 135 144 DQSn Connected to DQS on x4 DRAMs TDQS on x8 153 162 204 m Not used UDIMMs 213 222 231 TDQSn SDRAMs on RDIMMs n 9 17 Connected to optional thermal sensing compo EVENT nent 187 NC on Modules without a thermal sensing Ne Moke on UDIMMS NOTE NC No internal Connection SAMSUNG ELECTRONICS 9 htt p www C cond SAMSUNG Registered DIMM 9 Registering Clock Driver Specification 9 1 Timing amp Capacitance values Re
56. 1 0 Registered DIMM DDR3L SDRAM 19 1 Jitter Notes Specific Note a Specific Note b Specific Note c Specific Note d Specific Note e Specific Note f Specific Note g Unit tCK avg represents the actual tCK avg of the input clock under operation Unit nCK represents one clock cycle of the input clock counting the actual clock edges ex tMRD 4 nCK means if one Mode Register Set command is registered at Tm another Mode Register Set command may be registered at Tm 4 even if Tm 4 Tm is 4 x tCK avg tERR 4per min These parameters are measured from a command address signal CKE CS RAS CAS WE ODT BAO 0 A1 etc transition edge to its respective clock signal CK CK crossing The spec values are not affected by the amount of clock jitter applied i e tJIT per tJIT cc etc as the setup and hold are relative to the clock signal crossing that latches the command address That is these parameters should be met whether clock jitter is present or not These parameters are measured from a data strobe signal DQS DQS crossing to its respective clock signal CK CK crossing The spec values are not affected by the amount of clock jitter applied i e tJIT per tJIT cc etc as these are relative to the clock signal crossing That is these parameters should be met whether clock jitter is present or not These parameters are measured from a data signal DM 000 DQ1 etc transition edge to its respecti
57. 1360 1342 1426 1480 1530 mA 1 IDD2PO slow exit 690 720 720 760 770 810 mA IDD2P1 fast exit 726 756 756 796 806 846 mA IDD2N 786 880 816 920 856 960 mA IDD2Q 766 860 806 900 836 940 mA IDD3P 726 810 756 850 806 900 mA IDD3N 884 960 906 1000 954 1040 mA IDD4R 1536 1630 1736 1840 1966 2070 mA 1 IDD4W 1546 1730 1746 1940 1966 2170 mA 1 IDD5B 2000 2130 2130 2260 2214 2300 mA 1 IDDG 210 210 210 210 210 210 mA IDD7 2220 2440 2780 2920 2910 3024 mA 1 IDD8 210 210 210 210 210 210 mA NOTE 1 DIMM IDD SPEC is calculated with considering de actived rank IDLE is IDD2N M393B5170GB0 4GB 512Mx72 Module IDDO 1356 1540 1376 1570 1462 1620 mA 1 IDD1 1446 1630 1558 1696 1696 1800 mA 1 IDD2PO slow exit 870 900 900 940 950 990 mA IDD2P1 fast exit 942 972 972 1012 1022 1062 mA IDD2N 1002 1150 1032 1190 1072 1230 mA IDD2Q 982 1130 1022 1170 1052 1210 mA IDD3P 942 1080 972 1120 1022 1170 mA IDD3N 1208 1320 1212 1360 1278 1400 mA IDD4R 1752 1900 1952 2110 2182 2340 mA 1 IDD4W 1762 2000 1962 2210 2182 2440 mA 1 IDD5B 2216 2400 2346 2530 2430 2570 mA 1 IDDG 390 390 390 390 390 390 mA IDD7 2436 2710 2996 3190 3126 3294 mA 1 IDD8 390 390 390 390 390 390 mA NOTE 1 DIMM IDD SPEC is calculated with considering de actived rank IDLE is IDD2N SAMSUNG ELECTRONICS 36 htt p www BDTI C conf SAMSUNG Rev 1 0 Registered DIMM DDR3L SDRAM M393B5173GB0
58. 27 EWE gt WE SDRAMs 018 5 D 17 14 D 26 23 D 35 32 E WCKEO gt SDRAMs 04 0 D 22 18 OREO M 5 gt SDRAMs 0 8 5 D 26 23 WCKE1 gt CKE1 SDRAMs D 13 9 D 31 27 eet i 5 ECKE1 gt CKE1 SDRAMs D 17 14 D 35 32 WODTO gt SDRAMs D 4 0 E EODTO gt SDRAMs 0 8 5 m WODT1 gt ODT1 SDRAMs D 22 18 w EODT1 gt ODT1 SDRAMs D 26 23 gt CK SDRAMs D 4 0 D 13 9 DRAMs D 8 5 D 26 23 DRAMs D 22 18 D 31 27 SDRAMs D 17 14 D 35 32 SDRAMs D 4 0 D 13 9 SDRAMs D 8 5 D 26 23 gt CK SDRAMs D 22 18 D 31 27 gt CK SDRAMs D 17 14 D 35 32 PAR IN QERR Er out RESET RST SDRAMs D 35 0 Thermal sensor with SPD SCL gt EVENT EVENT T SA A0 A1 A2 SA0 SA1 SA2 VppsPp Serial PD Vop 00 035 VREFCA 4 DO D35 VREFDQ DO D35 Vss 00 035 NOTE 1 Unless otherwise noted resistor values are 150 5 2 See the wiring diagrams for all resistors associated with the com mand address and control bus 3 ZQ resistors are 240Q 1 For all other resistor values refer to the appropriate wiring diagram htt p www BDTI C SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 10 6 86B 16x72 Module Populated as 4 ranks of x4 DDR3 SDRAMs
59. 3 V 2 Single ended low level for strobes NOTE 3 Vpp 2 0 175 V 2 Single ended low level for CK CK NOTE 3 Vpp 2 0 175 V 2 NOTE 1 For CK CK use AC of ADD CMD for strobes 005 DOS use AC of DQs 2 for DQs is based on Vggrepo Vin AC Vi AC for ADD CMD is based on Vprerca if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here m 3 These values are not defined however the single ended signals CK DQS DQS need to be within the respective limits Vj DC max Vi DC min for single ended sig nals as well as the limitations for overshoot and undershoot Refer to Overshoot and Undershoot Specification SAMSUNG ELECTRONICS 28 htt p www BDTI C cond SAMSUNG Registered DIMM 13 3 4 Differential Input Cross Point Voltage Rev 1 0 DDR3L SDRAM To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK and DQS DQS must meet the requirements in below table The differential input cross point voltage Vix is measured from the actual cross point of true and complement signal to the mid level between of Vpp and Vss Figure 4 Definition Table 7 Cross point voltage for differential input signals CK DQS 1 35V Vpp 2 CK DQS Vss
60. 5 00510 w Das 2 09 z 00510 Das a Das vss w DM DM VSS DM DM DQ 15 12 A DQ 3 0 DIO E DQ 3 0 D25 DQ 11 8 DQ 3 0 Di E DQ 3 0 wilt 90 mI 24 z 4 wes 22 2 az 1 Wee raz Wee oz debe sis 88 eee 55882 585 55552 488855882 DQS0 DOS pas 5 20950 w DAS oH pas 5 DQS0 w 005 E DQS 2 0050 w DAS 005 zi VSS w DM DM lt VSS w DM DM lt DQ 3 0 M 0013 0 E 0013 0 5 DQ 7 4 4 4 DQ 3 0 D2 E 3 0 627 5 We 019 DES az oz xxx 5 2 Wye 2 94855552 588955552 88555555 5555504 vit 4 vtt 4 SAMSUNG ELECTRONICS 14 htt p www C cond SAMSUNG Rev 1 0 Registered DIMM 0988298 m 2292 629929 2 XIXI ac ac 8 c 010 c c LLILLILLLI LIII DQS14 pas pas 5 59514 w Das 2 Das 2 VSS DM lt DM 44 we Dapo PM SL boog 032 a 2555582 65255582 DQS4 w
61. 533 2 for 1066Mb sec pin 667MHz fox for 1333Mb sec pin 800MHz fo for 1600Mb sec pin 8 independent internal bank Programmable CAS Latency 6 7 8 9 10 11 Programmable Additive Latency Posted CAS 0 CL 2 or CL 1 clock Programmable CAS Write Latency CWL 5 DDR3 800 6 DDR3 1066 7 DDR3 1333 and 8 DDR3 1600 8 bit pre fetch Burst Length 8 Interleave without any limit sequential with starting address 000 only 4 with tCCD 4 which does not allow seamless read or write either On the fly using A12 or MRS Bi directional Differential Data Strobe Internal self calibration Internal self calibration through ZQ pin RZQ 240 ohm 1 On Die Termination using ODT pin Average Refresh Period 7 8us at lower then 85 3 9us at 85 lt Tease lt 95 Asynchronous Reset 3 Address Configuration 256Mx4 1Gb based Module 0 13 0 9 11 BAO BA2 A10 AP 128Mx8 1Gb based Module 0 13 0 9 BAO BA2 A10 AP SAMSUNG ELECTRONICS 5 Registered DIMM 4 Registered DIMM Pin Front si side Back side htt p www C cond SAMSUNG Rev 1 0 DDR3L SDRAM 1 VREFDQ 121 Vss 42 Dass 162 82 0033 202 Vss 2 Vsg 122 DQ4 43 Dass 163 Vss 83 Vss 203 E cg 3 DQO 123 DQ5 44 Vss 164 CB6 N
62. 600 Speed Bins 13 75 Rev 1 0 DDR3L SDRAM Intermal read command to first data tAA 13 125 8 20 ns ACT to internal read or write delay time tRCD f ns PRE command period tRP ns ACT to ACT or REF command period tRC 22 ns ACT to PRE command period tRAS 35 9 tREFI ns CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 tCK AVG Reserved ns 1 2 3 4 7 CWL 7 8 tCK AVG Reserved ns 4 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 4 7 CWL 7 tCK AVG Reserved ns 1 2 3 4 7 CWL 8 Reserved ns 4 CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 tCK AVG Reserved ns 1 2 3 4 7 CWL 8 Reserved ns 1 2 3 4 CWL 5 6 tCK AVG Reserved ns 4 CL 9 CWL 7 tCK AVG 1 5 1 875 ns 1 2 3 4 7 CWL 8 tCK AVG Reserved ns 1 2 3 4 CWL 5 6 tCK AVG Reserved ns 4 CL 10 CWL 7 tCK AVG 1 5 1 875 ns 1 2 3 7 CWL 8 tCK AVG Reserved ns 1 2 3 4 M CWL 5 6 7 tCK AVG Reserved ns 4 CWL 8 tCK AVG 1 25 1 5 ns 1 2 3 8 Supported CL Settings 6 7 8 9 10 11 nCK Supported CWL Settings 5 6 7 8 nCK SAMSUNG ELECTRONICS 41 htt p www C cond SAMSUNG Rev 1 0 Registered DIMM DDR3L SDRAM 18 3 1 Speed Bin Table Notes Absolute Specification 1 35V 1 28V 1 45V amp 1 5V 1 425V 1 575V
63. 6Mx72 Module Populated as 2 ranks of x8 DDR3 SDRAMS 12 10 3 2GB 256Mx72 Module Populated 1 rank of x4 DDR3 13 10 4 4GB 512Mx72 Module Populated as 2 ranks of 4 DDR3 14 10 5 4GB 512Mx72 Module Populated as 4 ranks of x8 DDR3 5 16 10 6 8GB 16 72 Module Populated as 4 ranks of x4 DDR3 5 5 17 11 Absolute Ratings ENERINEEENUTOINOTNIUTMIM m 22 11 1 Absolute Maximum DG Ratings icri vanne e dnce c doe ended eo 22 11 2 DRAM Component Operating Temperature 22 12 AC amp DC Operating Condltloris 2 cicero rotten taret eran dae 22 12 1 Recommended DC Operating 22 13 AC amp DC Input Measurement 23 13 1 AC amp DC Logic Input Levels for Single ended 23 13 2 25 13 3 AC and DC Logic Input Levels for Differential Signals mme 26 13 3 1 Differential Signals Definition 012 202 00 2
64. 9 D21 D23 D25 D27 ARSOB gt CS1 SDRAMs D11 D13 D15 D17 D29 D31 D33 D35 ARS1A CSO SDRAMs 00 D2 D4 D6 D8 D18 D20 D22 D24 D26 ARS1B gt CS0 SDRAMs D10 D12 D14 D16 D28 D30 D32 D34 I 0 gt BA N 0 SDRAMs D 9 0 D 27 18 ARBA N 0 B gt BA N 0 SDRAMs D 17 10 D 35 28 I ARA N 0 A gt A N 0 SDRAMs 0 9 0 D 27 18 ARA N 0 B gt A N 0 SDRAMs D 17 10 D 35 28 I ARRASA gt RAS SDRAMs 0 9 0 D 27 18 ARRASB gt RAS SDRAMs D 17 10 D 35 28 I ARCASA gt CAS SDRAMs 0 9 0 D 27 18 ARCASB gt CAS SDRAMs D 17 10 D 35 28 I ARWEA gt WE SDRAMs 09 0 D 27 18 ARWEB gt WE SDRAMs D 17 10 D 35 28 I ARCKEOA gt CKE1 SDRAMs D1 D3 05 D7 D9 D19 D21 D23 D25 D27 SDRAMs D11 D13 D15 D17 D29 D31 D33 D35 I ARCKE1A gt SDRAMs DO D2 D4 D6 08 D18 D20 D22 D24 D26 ARCKE1B gt CKEO SDRAMs 010 012 014 016 D28 D30 D32 D34 SDRAMs D1 D3 D5 D7 D9 D19 D21 D23 D25 ARODTOB gt ODT1 SDRAMs 011 013 015 017 D29 D31 D33 D35 ARCKEOB gt CKE1 ARODTOA gt ODT1 gt gt SDRAMs D 9 0 APCKOB gt SDRAMs D 17 10 APCK1A gt SDRAMs 0 27 18 APCK1B gt SDRAMs D 35 28 gt SDRAMs D 9 0 gt SDRAMs D 17 10 APCK1A gt SDRAMs D 27 18 APC
65. C 84 5954 204 TDOS13 4 001 124 Vss 45 CB2 NC 165 CB7 NC 85 DQS4 205 Vss 5 Vss 125 46 CB3 NC 166 Vss 86 Vss 206 DQ38 6 DQSO 126 5059 47 Vss 167 NC TEST 87 DQ34 207 DQ39 7 DQSO 127 Vss 48 Vr NC 168 RESET 88 DQ35 208 Vss 8 Vss 128 DQ6 KEY 89 Vss 209 DQ44 9 DQ2 129 DQ7 49 Vr NC 169 CKE1 NC 90 DQ40 210 DQ45 10 DQ3 130 Vss 50 CKEO 170 Vpp 91 DQ41 211 Vas 11 Vss 131 DQ12 51 Vpp 171 NC 92 Vss 212 Ee 12 DQ8 132 DQ13 52 BA2 172 NC 93 DQS5 213 50514 13 DQ9 133 Vss 53 Err_Out NC 173 Vpp 94 DQS5 214 Vss 14 Vss 134 54 174 12 95 Vss 215 DQ46 15 DQS1 135 750510 55 11 175 9 96 DQ42 216 DQ47 16 DQS1 136 Vss 56 176 97 DQ43 217 Vss 17 Vss 137 DQ14 57 Vpp 177 98 Vss 218 DQ52 18 DQ10 138 DQ15 58 A5 178 A6 99 DQ48 219 DQ53 19 0011 139 Vss 59 A4 179 100 DQ49 220 Vss 20 Vss 140 DQ20 60 180 101 221 p 21 DQ16 141 0021 61 A2 181 A1 102 DQS6 222 TDOS15 22 DQ17 142 Ves 62 Vpp 182 Vpp 103 56 223 Vss 23 Vss 143 RE 63 NC CK1 183 Vpp 104 Vss 224 DQ54 24 DQS2 144 TDOS11 64 NC CK1 184 CKO 105 DQ50 225 DQ55 25 DQS2 145 Vss 65 185 CKO 106 DQ51 226 Vss 26 Vss 146 DQ22 66 Vpp 186 Vpp 107 Vss 227 DQ60 27 DQ18 147 DQ23 67 VREFCA 187 EVENT NC 108 DQ56 228 DQ61 28 DQ19 148 Vss 68 In 188 AO 109 DQ57 229 Vss 29 Vss 149 DQ28 69 Vpp 189 Vpp 110 Vss 230 5 30 0024 150 DQ29 70 A10 AP 190 BA1 111 DQS7 231 759516 31 DQ25 151 Vss 71 BAO 191 Vpp 112 DQS7 232 Vss 32 Vss 152 pe ig 72 Vpp 192
66. G DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Precharge Quiet Standby Current IDD2Q CKE High External clock On tCK CL Refer to Component Datasheet for detail pattern BL 87 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATING DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Active Standby Current IDD3N CKE High External clock On tCK CL Refer to Component Datasheet for detail pattern BL 87 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling Data IO FLOATING DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details Refer to Component Datasheet for detail pattern Active Power Down Current IDD3P CKE Low External clock On tCK CL Refer to Component Datasheet for detail pattern BL 87 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATING DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Operating Burst Read Current CKE High External clock On tCK CL Refer to Component Datasheet for detail pattern BL 87 AL 0 CS High between RD Command Address IDD4R Bank Address Inputs
67. I I e I I I I I I m FE O O N Address Command and Control lines The used device is 256M x4 DDR3L SDRAM FBGA DDR3 SDRAM Part NO K4B1G0446G BY NOTE Tolerances on all dimensions 0 15 unless otherwise specified SAMSUNG ELECTRONICS Bis htt p www C cond SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 20 5 128Mbx8 based 512Mx72 Module 4 Ranks M393B51736B0 Units Millimeters 133 35 0 15 lt gt 128 95 S lt lt 9 76 10 9 18 92 3240 pus 41 974 X ee n mm A 2 50 1 0 max m 54 675 9 50 1 30 00 0 15 L Register f
68. K1B gt CK SDRAMs D 35 28 RST n Err_out RST SDRAMs D 71 0 SAMSUNG ELECTRONICS 21 BA N 0 A N 0 RAS CKE1 ODT1 as c PAR IN RESET RST n Rev 1 0 DDR3L SDRAM BRS2A CS1 SDRAMs 045 047 049 051 053 D63 D65 D67 D69 D71 BRS2B gt CS1 SDRAMs D37 039 041 043 D55 D57 D59 D61 BRS3A gt CS0 SDRAMs D44 046 048 050 052 D62 D64 D66 D68 D70 BRS3B gt CSO SDRAMs D36 D38 D40 D42 D54 D56 D58 D60 BRBA N O A gt BA N 0 SDRAMs D 53 44 D 71 62 BRBA N 0 B gt BA N 0 SDRAMs D 43 36 D 61 54 BRA N O A gt A N 0 SDRAMs D 53 44 D 71 62 BRA N 0 B gt A N 0 SDRAMs D 43 36 D 61 54 BRRASA gt RAS SDRAMs D 53 44 D 71 62 BRRASB gt RAS SDRAMs D 43 36 D 61 54 BRCASA gt CAS SDRAMs D 53 44 D 71 62 BRCASB gt CAS SDRAMs D 43 36 D 61 54 BRWEA gt WE SDRAMs D 53 44 D 71 62 BRWEB gt WE SDRAMs D 43 36 D 61 54 BRCKEOA gt 1 SDRAMs 045 047 049 051 053 D63 D65 D67 D69 D71 SDRAMs D37 D39 D41 D43 D55 D57 D59 D61 SDRAMs D44 D46 D48 D50 D52 D62 D64 D66 D68 D70 SDRAMs 036 038 040 042 054 056 058 060 SDRAMs 045 047 049 051 053 63 065 067 069 071 SDRAMs 037 039 041 043 055 057 059 061 gt CK SDRAMs D 53 44 BPCKOB
69. Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting NOTE 1 In two cased a maximum slew rate of 6V ns applies for a single DQ signal within a byte lane Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low of low to high while all remaining DQ signals in the same byte lane are static i e they stay at either high or low Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction i e from low to high or high to low respectively For the remaining DQ signal switching into the opposite direction the regular maximum limit of 5 V ns applies SAMSUNG ELECTRONICS delta TFdiff delta TRdiff Vonait AC Figure 6 Single ended output slew rate definition 31 htt p www C conf SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 14 4 Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo gif AC and for differential signals as shown in below Table 14 Differential Output slew rate definition V al AC V oy gil AC Differential output slew rate for rising edge Voiai AC Vougit AC Differential output slew rate for
70. Reset Exit 10ns 10ns 10ns 10ns ODT high time without write command or with write Exit Power Down with DLL on to any valid com max max max max mand Exit Precharge Power Down with DLL tXP 3nCK 3nCK frozen to commands not requiring a locked DLL 7 5ns 7 5ns 3nCK 6ns 3nCK 6ns i oie 10nCK 10nCK 10nCK 2 quiring 24ns 24ns 24ns 24ns max max max max CKE minimum pulse width tCKE 3nCK 3nCK 3nCK 3nCK 5ns 7 5ns 5 625ns 5 625ns Command pass disable delay tCPDED 1 1 1 1 nCK Power Down Entry to Exit Timing tPD tCKE min 9 tREFI tCKE min 9 tREFI tCKE min 9 tREFI tCKE min 9 tREFI tCK 15 Timing of ACT command to Power Down entry tACTPDEN 1 1 1 1 nCK 20 Timing of PRE command to Power Down entry tPRPDEN 1 1 1 1 nCK 20 Timing of RD RDA command to Power Down entry tRDPDEN 4 1 RL 4 1 RL 4 1 RL 4 1 pce WL 4 WL 4 WL 4 WL 4 fee ceo WRPDEN WR WR tWRI nCK 9 tCK avg tCK avg tCK avg tCK avg Timing of WRA command to Power Down entry WL 4 WL 4 WL 4 WL 4 WR BL8OTF BL8MRS 4 IWRAPDEN 1 WR 1 2 WR 1 3 1 nck 10 2 2 2 WL 2 commandito Power Down WRPDEN WR tWRY tWRY tWRY nCK 9 tCK avg tCK avg tCK avg tCK avg Timing of WRA command to Power Down entry WL 2 WR WL 2 WR
71. SDRAMs 0 7 4 D 16 13 D 25 22 D 34 31 wl RRASA gt RAS SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 035 RRASB gt RAS SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 RCASA gt CAS SDRAMs D 4 0 D8 D 13 9 D 22 18 0131 27 CAS wv RCASB gt CAS SDRAMs D 8 5 D 17 14 D 26 23 D 35 32 WE 12 RWEA gt WE SDRAMs D 4 0 D8 D 13 9 D 22 18 D 31 27 RWEB gt WE SDRAMs 0 8 5 D 17 14 D 26 23 D 35 32 RCKEOA gt SDRAMs D 3 0 D 12 8 017 SEED M 5 RCKEOB gt SDRAMs D 7 4 D 16 13 gt CKE1 SDRAMs 0 21 18 D 30 26 035 CREE S 77 RCKEIB CKE1 SDRAMs D 25 22 0134 31 H RODTOA gt SDRAMs 013 0 D 12 8 017 gt SDRAMs 07 4 D 16 13 2 ZQ pins of each SDRAM are connected to individual RZQ resistors 240 1 ohms SAMSUNG ELECTRONICS 15 RODT1A gt ODT1 SDRAMs D 21 18 D 30 26 035 RODT1B gt ODT1 SDRAMs D 25 22 D 34 31 gt CK SDRAMs D 3 0 D 12 8 D17 gt CK SDRAMs D 7 4 D 16 13 _ 1 gt CK SDRAMs D 21 18 D 30 26 035 PCK1B gt SDRAMs D 25 22 D 34 31 gt SDRAMs D 3 0 D 12 8 017 gt CK SDRAMs D 7 4 D 16 13 _ gt CK SDRAMs D 21 18 D 30 26 035 394 PCK1B gt CK SDRAMs D 25 22 D 34 31 PAR_IN ERR OUT RESET
72. SH act tDQSL act 1 act with tXYZ act being the actual measured value of the respective timing parameter in the application 32 tDSH act tDSS act 1 tCK act with tXYZ act being the actual measured value of the respective timing parameter in the application SAMSUNG ELECTRONICS Ja htt p www C cond SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 20 Physical Dimensions 20 1 128Mbx8 based 128Mx72 Module 1 Rank M393B28736B0 Units Millimeters
73. WL For BC4 fixed by MRS Rising clock edge 2 clock cycles after WL 19 The maximum read preamble is bound by tLZDQS min on the left side and tDQSCK max on the right side See Device Operation amp Timing Diagram Datasheet 20 CKE is allowed to be registered low while operations such as row activation precharge autoprecharge or refresh are in progress but power down IDD spec will not be applied until finishing those operations 21 Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN min is satisfied there are cases where additional time such as tXPDLL min is also required See Device Operation amp Timing Diagram Datasheet 22 Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function 23 One ZQCS command can effectively correct a minimum of 0 5 96 ZQCorrection of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the Output Driver Voltage and Temperature Sensitivity and ODT Voltage and Temperature Sensitivity tables The appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters One method for calculating the interval between ZQCS commands given the temperature Tdriftrate and voltage Vdriftrate drift rates that the SDRAM is sub ject to in the application is illustrated The interval could be defined by the following formula ZQCorrection
74. cterization 8 For devices supporting optional downshift to CL 7 and CL 9 tAA tRCD tRP min must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333 CL9 devices supporting downshift to DDR3 1066 CL7 should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600 CL 11 devices supporting downshift to DDR3 1333 CL9 or DDR3 1066 CL7 should program 13 125 ns in SPD bytes for tAAmin Byte16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36ns 13 125ns for DDR3 1333 CL9 and 48 125ns tRASmin tRPmin 35ns 13 125ns for DDR3 1600 CL11 SAMSUNG ELECTRONICS dns htt p www BDTI C SAMSUNG Registered DIMM 19 Timing Parameters by Speed Grade Table 21 Timing Parameters by Speed Bin Rev 1 0 DDR3L SDRAM Minimum Clock Cycle Time DLL off mode 8 8 8 8 ns 6 Average Clock Period tCK avg See Speed Bins Table ps Clock Period tCK abs urrgeomax ipenn uperi PS Average high pulse width tCH avg 0 47 0 53 0 47 0 53 0 47 0 53 0 47 0 53 tCK avg Average low pulse width tCL avg 0 47 0 53 0 47 0 53 0 47 0 53 0 47 0 53 tCK avg Clock Period Jitt
75. er tJIT per 100 100 90 90 80 80 70 70 ps Clock Period Jitter during DLL locking period tJIT per Ick 90 90 80 80 70 70 60 60 ps Cycle to Cycle Period Jitter tJIT cc 200 180 160 140 ps Cycle to Cycle Period Jitter during DLL locking period JIT cc Ick 180 160 140 120 ps Cumulative error across 2 cycles ERR 2per 147 147 132 132 118 118 103 103 ps Cumulative error across 3 cycles ERR 3per 175 175 157 157 140 140 122 122 ps Cumulative error across 4 cycles ERR 4per 194 194 175 175 155 155 136 136 ps Cumulative error across 5 cycles ERR 5per 209 209 188 188 168 168 147 147 ps Cumulative error across 6 cycles ERR 6per 222 222 200 200 177 177 155 155 ps Cumulative error across 7 cycles ERR 7per 232 232 209 209 186 186 163 163 ps Cumulative error across 8 cycles ERR 8per 241 241 217 217 193 193 169 169 ps Cumulative error across 9 cycles ERR 9per 249 249 224 224 200 200 175 175 ps Cumulative error across 10 cycles tERR 10per 257 257 231 231 205 205 180 180 ps Cumulative error across 11 cycles tERR 11per 263 263 237 237 210 210 184 184 ps Cumulative error across 12 cycles tERR 12per 269 269 242 242 215 215 188 188 ps Cumulative error across n 13 14 49 50 cycles tERR nper ps 24 Absolute clock HIGH pulse width tCH abs 0 43 0 43 0 43 0 43 tCK avg 25 Absolute clock Low pulse width tCL abs 0 43 0 43 0 43 0 43 tCK avg 26
76. htt p www BDTI C SAMSUNG M393B2873GB0 M393B5673GB0 M393B5670GB0 M393B5173GB0 M393B5170GB0 240pin Registered DIMM based on 16b G die 8FBGA with Lead Free 8 Halogen Free RoHS compliant SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS INFORMATION AND SPECIFICATIONS WITHOUT NOTICE Products and specifications discussed herein are for reference purposes only All information discussed herein is provided on an AS IS basis without warranties of any kind This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics No license of any patent copyright mask work trademark or any other intellectual property right is granted by one party to the other party under this document by implication estoppel or other wise Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply For updates or additional information about Samsung products contact your nearest Samsung office All brand names trademarks and registered trademarks belong to their respective owners c 2010 Samsung Electronics Co Ltd All rights reserved SAMSUNG ELECTRONICS X htt p www BDTI C cond SAMSUNG Regi
77. iagram Datasheet tWR is defined in ns for calculation of tWRPDEN it is necessary to round up tWR tCK to the next integer 10 WR in clock cycles as programmed in MRO 11 The maximum read postamble is bound by tDQSCK min plus tQSH min on the left side and tHZ DQS max on the right side See Device Operation amp Timing Diagram Datasheet 12 pond deratings are relative to the SDRAM input clock When the device is operated with input clock jitter this parameter needs to be derated y 13 Value is only valid for RON34 14 Single ended signal parameter Refer to chapter 8 and chapter 9 for definition and measurement method 15 tREFI depends on Toper 16 tlS base and tiH base values are for 1V ns CMD ADD single ended slew rate and 2V ns CK CK differential slew rate Note for DQ and DM signals Vrer DC VggeDQ DC For input only pins except RESET Vgge DC VggeCA DC See Address Command Setup Hold and Derating on component datasheet 17 tDS base and tDH base values are for 1V ns DQ single ended slew rate and 2V ns DQS DQS differential slew rate Note for DQ and DM signals Vrer DC VgggDQ DC For input only pins except RESET Vgge DC VggeCA DC See Data Setup Hold and Slew Rate Derating on component datasheet 18 Start of internal write transaction is defined as follows For BL8 fixed by MRS and on the fly Rising clock edge 4 clock cycles after WL For BC4 on the fly Rising clock edge 4 clock cycles after
78. ial output high measurement level for output SR 0 2x AC differential output low measurement level for output SR 0 2x NOTE 1 The swing of 0 2xVppq is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 400 and an effective test load of 250 to 2 at each of the differential outputs SAMSUNG ELECTRONICS 30 htt p www BDTI C cond SAMSUNG Registered DIMM 14 3 Single ended Output Slew Rate Rev 1 0 DDR3L SDRAM With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo AC and for single ended signals as shown in below Table 12 Single ended Output slew rate definition Single ended output slew rate for rising edge VoL AC AC Delta TRse Single ended output slew rate for falling edge AC Delta TFse NOTE Output slew rate is verified by design and characterization and may not be subject to production test Table 13 Single ended output slew rate Single ended output slew rate SRQse 1 35V 1 75 51 1 75 51 1 75 51 1 75 51 V ns 1 5V 2 5 2 5 2 5 2 5 V ns Description SR Slew
79. ity 18 2 Speed Bins and CL tRCD tRP tRC and tRAS for Corresponding 39 18 3 Speed Bins and CL tRCD tRP tRC and tRAS for corresponding Bin 39 18 34 Speed Tabl Notes 228 258548444 4 2404 44 perte ei secca 42 19 Timing Parameters by Speed Grade sse 43 19 1 4 5 46 19 2 Timing Parameter Notes PE c 47 20 5 5 che 48 20 1 128Mbx8 based 128Mx72 Module 1 Rank 393 28736 0 48 20 1 1 x72 DIMM populated as one physical rank of x8 DDR3 SDRAMS eee eee 48 SAMSUNG ELECTRONICS ide htt p www C cond SAMSUNG Rev 1 0 Registered DIMM DDR3L SDRAM 20 2 128Mbx8 based 256Mx72 Module 2 Ranks 393 56736 0 49 20 2 1 x72 DIMM populated as two physical ranks of x8 DDR3 SDRAMS 49 20 3 256Mbx4 based 256Mx72 Module 1 Rank 393 56706 0 50 20 3 1 x72 DIMM populated as one physical rank of x4 DDR3 5 50 20 4 256Mbx4 based 512Mx72 Module 2 Ranks 393 51706 0 51 20 4 1 x72 DIMM populated as two physical ranks of x4 DDR3 SDRAMS
80. k off CK and CK LOW CKE FLOATING CS Command Address Bank Address Data FLOATING ODT Signal FLOATING SAMSUNG ELECTRONICS 298 htt p www C cond SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM NOTE 1 Burst Length BL8 fixed by MRS set MRO A 1 0 00B 2 Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 011B RTT Wr enable set MR2 A 10 9 10B 3 Precharge Power Down Mode set A12 0B for Slow Exit or A12 1B for Fast Exit 4 Auto Self Refresh ASR set MR2 A6 OB to disable or 1B to enable feature 5 Self Refresh Temperature Range SRT set MR2 A7 0B for normal or 1B for extended temperature range Refer to DRAM supplier data sheet and or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device VDD and VDDQ are merged on module PCB DIMM IDD SPEC is measured with Qoff condition IDDQ values are not considered 7 IDD current measure method and detail patterns are described on DDR3 component datasheet SAMSUNG ELECTRONICS 34 Registered DIMM 16 IDD SPEC Table htt p www BDTI C cond SAMSUNG M393B2873GB0 1GB 128Mx72 Module Rev 1 0 DDR3L SDRAM IDDO 870 955 890 985 958 1035 mA 1 IDD1 915 1000 982 1048 1075 1152 mA 1 IDD2PO slo
81. l Capacitance 1 Although the DM TDQS and TDQS pins have different functions the loading matches DQ and DQS 2 This parameter is not subject to production test It is verified by design and characterization The capacitance is measured according to JEP147 PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER VNA with Vpp Vss Vsso applied and all other pins floating except the pin under test CKE RESET and ODT as necessary Vpp Vppa 1 5V VgiAs Vpp 2 and on die termination off Absolute value of CCK CCK Absolute value of CIO DQS CIO DQS CDI applies to ODT CS and Cl applies to ODT CS A0 A15 BAO BA2 RAS CAS WE CDI CTRL CI CTRL 0 5 CI CLK CI CLK 2 CDI ADD applies to A0 A15 BAO BA2 RAS CAS and WE 10 CDI ADD CMD CI ADD CMD 0 5 CI CLK CI CLK 11 CDIO CIO DQ DM 0 5 CIO DQS CIO DQS 12 Maximum external load capacitance on ZQ pin 5pF SAMSUNG ELECTRONICS This parameter applies to monolithic devices only stacked dual die devices are not covered here 38 htt p www BDTI C conf SAMSUNC Rev 1 0 Registered DIMM D D R3L SDRAM 18 Electrical Characteristics and AC timing 0 C lt Tcase 95 C 1 35V 1 28V 1 45V amp 1 5V 1 425V 1 575V Vpp 1 35V 1 28V 1 45V amp 1 5V 1 425V 1 575V 18 1 Refresh Parameters by Device Density
82. le ended signals CK and CK have to approximately reach max approximately equal to the ac levels Vi AC Vj AC for ADD CMD signals in every half cycle DQS DQS have to reach Vseymin max approximately the ac levels Vj AC Vi AC for DQ signals in every half cycle proceeding and follow ing a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if Vij150 AC Vi 150 AC is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK Vpp VsEH min Vpp 2 or Vppo 2 CK or DOS VsEL max ss time Figure 3 Single ended requirement for differential signals Note that while ADD CMD DQ signal requirements are with respect to the single ended components of differential signals have a requirement with respect to Vpp 2 this is nominally the same The transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach max Vsgumin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Table 6 Single ended levels for CK DQS CK DQS Single ended high level for strobes Vpp 2 0 175 NOTE 3 V 2 Single ended high level for CK Vpp 2 0 175 NOTE
83. nced to Vi AC Vi AC levels 1 5 tlS base AC150 350 275 190 170 ps b 16 27 Control amp Address Input pulse width for each input tIPW 900 780 620 560 ps 28 Power up and RESET calibration time tZGinitl 512 512 512 512 nCK Normal operation Full calibration time tZQoper 256 256 256 256 nCK Normal operation short calibration time tZQCS 64 64 64 64 nCK 23 SAMSUNG ELECTRONICS 44 Registered DIMM htt p www BDTI C SAMSUNG Table 21 Timing Parameters by Speed Bin Cont Rev 1 0 DDR3L SDRAM Exit Reset from CKE HIGH to a valid command tXPR max 5nCK tRFC 10ns max 5nCK t max 5nCK tRFC 10ns max 5nCK t max 5nCK tRFC 10ns max 5nCK t max 5nCK tRFC 10ns Refresh to commands not requiring a locked 8 REC 1 1 RFC 1 tae _ 10ns 10ns 10ns Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK min tDLLK min tDLLK min tDLLK min nCK Minimum CKE low width for Self refresh entry to exit tCKESR tCKE min tCKE min 1 tCKE min tCKE min 1 timing 1tCK 1tCK 1tCK 1tCK Valid Clock Requirement after Self Refresh Entry tCKSRE max 5nCK E max 5nCK 1 max 5nCK max 5nCK 1 SRE or Power Down Entry PDE 10ns 10ns 10ns 10ns Valid Clock Requirement before Self Refresh Exit tCKSRX max 5nCK max 5nCK max 5nCK max 5nCK _ SRX or Power Down Exit or
84. re temperature 1 sensing YS Memory bus test toll Not Connected and Not A12 BC Address Input Burst chop 1 TEST Usable on DIMMs 1 BA 2 0 SDRAM Bank Addresses 3 RESET Register and SDRAM control pin 1 SCL Serial Presence Detect SPD Clock Input Vpp Power Supply 22 SDA SPD Data Input Output 1 Vss Ground 59 SA 2 0 SPD Address Inputs 3 VREFDQ Reference Voltage for DQ 1 Par In Parity bit for the Address and Control bus 1 VREFCA Reference Voltage for CA 1 Er Out doen error found on the Address and Control 1 Vir Termination Voltage 4 Vppspp SPD Power 1 Total 240 NOTE Vpp and Vppg pins are tied common to a single power plane on these designs 6 0N DIMM Thermal Sensor SCL gt gt SDA EVENT WP EVENT R1 00 SAO SA1 SA2 uis SAO SA1 SA2 NOTE 1 All Samsung RDIMM support Thermal sensor on DIMM 2 When the SPD and the thermal sensor are placed on the module R1 is placed but R2 is not When only the SPD is placed on the module R2 is placed but R1 is not Table 1 Temperature Sensor Characteristics 75 lt Ta 95 0 5 1 0 B 40 Ta 125 1 0 2 0 20 lt lt 125 2 0 3 0 Resolution 0 25 LSB SAMSUNG ELECTRONICS htt p www BDTI C cond SAMSUNG Rev 1 0 Registered DIMM D D R3L SDRAM 7 Input Output Functional Description EESTI ONES OG CKO Input 5 Positive line of the differential pair of s
85. re the time to which setup and hold is measured System timing and voltage budgets need to account for Vgge DC deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with ac noise Timing and voltage effects due to ac noise on Vggr up to the specified limit 1 of Vpp are included in DRAM timings and their associated deratings SAMSUNG ELECTRONICS 25 htt p www BDTI C cond SAMSUNG Registered DIMM 13 3 AC and DC Logic Input Levels for Differential Signals 13 3 1 Differential Signals Definition lt tDVAC A Viy DIFF AC MIN Viy4 DIFF MIN Differential Input Voltage i e DQS DQS CK CK 0 0 half cycle Vi DIFF MAX Vi DIFF AC MAX tDVAC Figure 2 Definition of differential ac swing and time above ac level tDVAC 13 3 2 Differential Swing Requirement for Clock CK CK and Strobe DQS 005 time Rev 1 0 DDR3L SDRAM differential input high 0 18 NOTE 3 0 20 NOTE 3 V 1 Vii dift differential input low NOTE 3 0 18 NOTE 3 0 20 V 1 differential input high ac 2 x Veer NOTE 3 2 x Viy AC Vref NOTE 3 5 differential input low ac NOTE 3 2 x Vi AC Veer NOTE 3 2x Vi Veer V NOTE
86. river will remain synchronized with the input clock Par In IN Parity bit for the Address and Control bus 1 Odd Even Out OUT Parity error detected on the Address and Control bus A resistor may be connected from Err Out mu bus line to Vpp on the system planar to act as a pull up TEST Used by memory bus analysis tools unused NC on memory DIMMs SAMSUNG ELECTRONICS 8 Registered DIMM htt www C cond SAMSUNG 8 Pinout Comparison Based On Module Additional connection for Termination Voltage for Rev 1 0 DDR3L SDRAM component V 48 49 Address Command Control Clock nets NG Termination Voltage for Address Command Con Termination Voltage for Address Command Con 120 240 Vit Vir trol Clock nets trol Clock nets 53 Err Out Connected to the register on all RDIMMs NC Not NC NC Not used on UDIMMs used on UDIMMs 63 NC CK1 i Not used on RDIMMs Used for 2 rank UDIMMs not used on single rank 64 NC CK1 UDIMMs but terminated 68 Par In Connected to the register on all RDIMMs NC Not used on RDIMMs 76 1 Connected to the register on all RDIMMs 51 Used jor dal rane UDIMMs not connected on single rank UDIMMs Connected to the register on dual and quadrank Used for dual rank UDIMMs not connected id SETS RDIMMs NC on single rank RDIMMs BERN on single rank UDIMMs _ Connected to the register on
87. stered DIMM Revision History Revision No History Draft Date 1 0 First Release Nov 2010 SAMSUNG ELECTRONICS 2 Rev 1 0 DDR3L SDRAM Remark Editor S H Kim htt p www C cond SAMSUNG Rev 1 0 Registered DIMM DDR3L SDRAM Table Of Contents 240 Registered DIMM based 16b G die 1 DDR3L Registered DIMM Ordering 5 2 FOAUWISS 5 3 Address Conflguratlon es eoa ie retro e Ert Her ERR Euch 5 4 Registered DIMM Pin Configurations Front side Back 6 T 7 6 ON DIMM Thetmal Sensor c RE 7 Input Output Functional 1 16 1 a ida aeaiia aN 8 8 Pinout Comparison Based On Module 9 9 Registering Clock Driver Specification 10 9 1 Timing amp Capacitance values ssnin rnnr Fac Focal 10 9 2 Clock driver ChanactenStes REN 10 10 BIOCK Dia o rz 11 10 1 1GB 128 72 Module Populated as 1 rank of x8 DDR3 11 10 2 2GB 25
88. to ACT or REF command period tRC 50 625 ns ACT to PRE command period tRAS 37 5 9 tREFI ns T CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 5 CWL 6 tCK AVG Reserved ns 1 2 3 4 CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 4 8 Chad CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 Supported CL Settings 6 7 8 nCK Supported CWL Settings 5 6 nCK Table 19 DDR3 1333 Speed Bins Internal read command to first data tAA 13 5 13 125 8 20 ns ACT to internal read or write delay time tRCD 13 5 13 125 8 ns PRE command period tRP 13 5 13 125 8 ns ACT to ACT or REF command period tRC 49 5 49 125 8 ns ACT to PRE command period tRAS 36 9 tREFI ns CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 6 CL 6 CWL 6 tCK AVG Reserved ns 1 2 3 4 6 CWL 7 tCK AVG Reserved ns 4 CWL 5 tCK AVG Reserved ns 4 CL 7 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 4 6 CWL 7 tCK AVG Reserved ns 1 2 3 4 CWL 5 tCK AVG Reserved ns 4 CL 8 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 6 CWL 7 tCK AVG Reserved ns 1 2 3 4 CL 9 CWL 5 6 tCK AVG Reserved ns 4 CWL 7 tCK AVG 1 5 1 875 ns 1 2 3 4 8 Pied CWL 5 6 tCK AVG Reserved ns 4 CWL 7 tCK AVG Reserved ns 1 2 3 Supported CL Settings 6 7 8 9 nCK Supported CWL Settings 5 6 7 nCK SAMSUNG ELECTRONICS 40 Registered DIMM htt p www BDTI C cond SAMSUNG Table 20 DDR3 1
89. ture Range SRT Normal CKE Low External clock Off CK and CK LOW CL Refer to Component Datasheet for detail pattern BL 87 AL 0 CS Command Address Bank Address Data lO FLOATING DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal FLOATING Self Refresh Current Extended Temperature Range 1 9 IDD6ET TCASE 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended CKE Low External clock Off CK and CK LOW CL Refer to Component Datasheet for detail pattern BL 87 AL 0 CS Command Address Bank Address Data IO FLOATING DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal FLOATING Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD nRRD nFAW CL Refer to Component Datasheet for detail pattern BL 81 AL CL 1 CS High IDD7 between ACT and RDA Command Address Bank Address Inputs partially toggling Data IO read data bursts with different data between one burst and the next one DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different addressing Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details Refer to Component Datasheet for detail pattern RESET Low Current 2 2 IDD8 RESET Low External cloc
90. u DQ 3 0 D35 S CB 3 0 A DQ 3 0 Ds 21 14 DQ 3 0 26 e NIN mis z 00100 we oja mis z oo wE ic Ux az alg Wie oz xxx oe 925555552 8 5585 69 assi 55585 DQS12 w Das 5 pas DQS12 w DAS 5 DOS 5 DQS12 DQS 2 DQS 2 DQS12 w 005 2i DQS 2 VSS w DM lt DM lt VSS DM lt DM lt DQ 31 28 DQ 3 0 DUE 2 r3 DQ 3 0 D30 DQ 27 24 DQ 3 0 D3 E D9Q 3 0 D21 OI Wo ul az Wee oz 17 Wee x oz 2888585 48555535 585555552 489855535 DQS11 w pas 5 Das 5 00511 w Das 5 09 5 00511 w 005 2 DQS 00511 w 005 gt 09 gt VSS w DM Ed DM Ed VSS w DM Ed DM Ed DQ 23 20 A DQ 3 0 DU 8 4 0013 0 D29 2 DQ 19 16 DQ 3 0 nz 4 DQ 3 0 D20 2 n n it amd uks wez n n LIEST az 2 xx ae 5 82 558 555555552 5585 DQS10 w Das pas DQS10 Das pas
91. v 100 100 390 3o gt _ 895 SV9 g g 2 996822 S9 98 9 Naaaa Naaaa 00 OO Os Q t r 0 6 0010 00 00100 gt alg 5 5 98 2 B 5 aa a Vtt 19 SAMSUNG ELECTRONICS Registered DIMM htt p www BDTI C cond SAMSUNG Rev 1 0 DDR3L SDRAM 1552 lt lt 2 lt lt lt lt gt 50055580522 lt 59005550535 5 p 55509 55500 co 5 co lt gt 80303 01 mim m m cn A m 111111111 LI VSS wZQ vss wZQ vss vss w 00513 09 Das 09513 wDQs E Das E 55 0 029 5 DM D28 DQ 39 36 W DQ 3 0 B DQ 3 0 0 0 5 ojo 58585 55585 9 9 9 VSS w Za vss
92. v 1 0 DDR3L SDRAM fclock Input Clock Frequency application frequency 300 670 MHz teu tcr Pulse duration CK CK HIGH or LOW 0 4 1 LOW ive ti i t tACT Inputs active time4 before RESET is taken HIGH DCSOM HIGH 8 CK tsu Setup time Input valid before CK CK 100 ps ty Hold time Input to remain Valid after CK 175 CK Propagation delay single bit switching CK CK to output 0 65 1 0 ns output disable time 1 2 Clock pre launch 0 5 ipis CK CK to output float output disable time 3 4 Clock pre launch 0 25 output enable time 1 2 Clock pre launch 0 5 ten CK CK to output driving tek output enable time 3 4 Clock pre launch 0 25 Ci DATA Data Input Capacitance 15 25 Cjy CLOCK Data Input Capacitance 2 3 pF Reset Input Capacitance 5 3 9 2 Clock driver Characteristics Cycle to cycle period jitter 0 40 ps Stabilization time 6 us trayn Dynamic phase offset 50 50 ps tcksk Clock Output skew 50 ps Yn Clock Period jitter 40 40 ps tit hper Half period jitter 50 50 ps TN Qn Output to clock tolerance Standard 1 2 Clock Output Inversion enabled 100 200 T ae Pre Launch OUtput Inversion disabled 100 300 Output Inversion enabled 100 200 task Output clock tolerance 3 4 Clock Pre Launch
93. ve data strobe signal DQS DQS crossing For these parameters the DDR3 SDRAM device supports tnPARAM nCK RU tPARAM ns tCK avg ns which is in clock cycles assuming all input clock jitter specifications are satisfied For example the device will support tnRP RU tRP tCK avg which is in clock cycles if all input clock jitter specifications are met This means For DDR3 800 6 6 6 of which tRP 15ns the device will support tnRP RU tRP tCK avg 6 as long as the input clock jitter specifications are met i e Precharge com mand at Tm and Active command at Tm 6 is valid even if Tm 6 Tm is less than 15ns due to input clock jitter When the device is operated with input clock jitter this parameter needs to be derated by the actual tERR mper act of the input clock where 2 lt m lt 12 output deratings are relative to the SDRAM input clock For example if the measured jitter into a DDR3 800 SDRAM has tERR mper act min 7 172 ps and tERR mper act max 7 193 ps then tDQSCK min derated tDQSCK min tERR mper act max 400 ps 193 ps 593 ps and tDQSCK max der ated tDQSCK max tERR mper act min 400 ps 172 ps 572 ps Similarly tLZ DQ for DDR3 800 derates to tLZ DQ min derated 800 ps 193 ps 993 ps and tLZ DQ max derated 400 ps 172 ps 572 ps Caution on the min max usage Note that tERR mper act min is the minimum measured value of tERR nper where 2 lt n lt 12
94. w exit 600 630 630 670 680 720 mA IDD2P1 fast exit 618 648 648 688 698 738 mA IDD2N 678 745 708 785 748 825 mA IDD2Q 658 725 698 765 728 805 mA IDD3P 618 675 648 715 698 765 mA IDD3N 722 780 753 820 792 860 mA IDD4R 1095 1180 1205 1300 1345 1440 mA 1 IDD4W 1105 1190 1215 1310 1345 1450 mA 1 IDD5B 1280 1365 1365 1450 1422 1490 mA 1 IDD6 120 120 120 120 120 120 mA IDD7 1500 1585 1745 1840 1830 1935 mA 1 IDD8 120 120 120 120 120 120 mA NOTE 1 DIMM IDD SPEC is calculated with considering de actived rank IDLE is IDD2N M393B5673GB0 2GB 256Mx72 Module IDDO 978 1090 998 1120 1066 1170 mA 1 IDD1 1023 1135 1090 1183 1183 1287 mA 1 IDD2PO slow exit 690 720 720 760 770 810 mA IDD2P1 fast exit 726 756 756 796 806 846 mA IDD2N 786 880 816 920 856 960 mA IDD2Q 766 860 806 900 836 940 mA IDD3P 726 810 756 850 806 900 mA IDD3N 884 960 906 1000 954 1040 mA IDD4R 1203 1315 1313 1435 1453 1575 mA 1 IDD4W 1213 1325 1323 1445 1453 1585 mA 1 IDD5B 1388 1500 1473 1585 1530 1625 mA 1 IDD6 210 210 210 210 210 210 mA IDD7 1608 1720 1853 1975 1938 2070 mA 1 IDD8 210 210 210 210 210 210 mA NOTE 1 DIMM IDD SPEC is calculated with considering de actived rank IDLE is IDD2N SAMSUNG ELECTRONICS 35 Registered DIMM htt p www BDTI C cond SAMSUNG M393B5670GB0 2GB 256Mx72 Module Rev 1 0 DDR3L SDRAM IDDO 1140 1270 1160 1300 1246 1350 mA 1 IDD1 1230
95. ystem clock inputs that drives input to the on DIMM Clock Driver AUR Negative DT CKO Input Edge Negative line of the differential pair of system clock inputs that drives the input to the on DIMM Clock Driver CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers CKE 1 0 Input Active High land output drivers of the SDRAMs Taking LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation all banks idle or ACTIVE POWER DOWN row ACTIVE in any bank Enables the associated SDRAM command decoder when low and disables decoder when high When decoder is disabled new commands are ignored and previous operations continue These input signals also disable all outputs except CKE and ODT of the register s on the DIMM when both inputs are high When both S 1 0 are high all register outputs except CKE ODT and Chip select remain in the previous state For modules supporting 4 ranks S 3 2 operate similarly to S 1 0 for a second set of reg ister outputs S 3 0 Input Active Low ODTT 1 0 Input Active High On Die Termination control signals When sampled at the positive rising edge of the clock CAS RAS and WE define the operation to be exe RAS CAS WE Input Active Low cuted by the SDRAM VREFDQ Supply Reference voltage for DQ0 DQ63 and 7 VREFCA Supply Reference voltage for A0 A15 BAO BA2 RAS CAS WE SO S1 CKEO CKE1 Par

Samsung M393B2873GB0 handbook (1)

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