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MICROCHIP MCP6021/1R/2/3/4 Data Sheet

1. 14 Lead SOIC 150 mil MCP6024 Example XXXXXXXXXX MCP60241SL XXXXXXXXXX A rymy M 0331256 MCP6024 OR E SL 3 0549256 14 Lead TSSOP MCP6024 Example XXXXXX 6024E AN 0331 O NNN 256 UU 2006 Microchip Technology Inc DS21685C page 19 MCP6021 1R 2 3 4 5 Lead Plastic Small Outline Transistor OT SOT 23 El pi D n 1 a c a A2 L Al Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 Pitch p 038 0 95 Outside lead pitch basic p1 075 1 90 Overall Height A 035 046 057 0 90 1 18 1 45 Molded Package Thickness A2 035 043 051 0 90 1 10 1 30 Standoff A1 000 003 006 0 00 0 08 0 15 Overall Width E 102 110 118 2 60 2 80 3 00 Molded Package Width 1 059 064 069 1 50 1 63 1 75 Overall Length D 110 116 122 2 80 2 95 3 10 Foot Length L 014 018 022 0 35 0
2. 10 Falling Vos 5 5V 9 Rising Vpp 5 5V gt Von 5 5V T 5 i 7 gt Von 2 5V NI 6 2 gt o gt s 5 551 1 Falling 2 5V Or NC 83 Rising 2 5V EN 1 5 gt 0 50 25 0 25 50 75 100 125 04 o DE iM old Ambient Temperature C Frequency Hz FIGURE 2 25 Slew Rate vs Temperature FIGURE 2 28 Maximum Output Voltage Swing vs Frequency 0 1000 0 1000 f 1 kHz G 100 V V BWmeas 22 kHz te Vyp 5 0V 1 lt 0 0100 G 100 V V F Z 0 0100 4G 10 V V gt HP ES H i a L I G 10 V V I E 00010 24 F 0 0010 1G 1 Vw f 20 kHz 7 BWyeas 80 kHz G PE Vyp 5 0V 0 0001 4 0 0001 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 Output Voltage Vp p Output Voltage Vp p FIGURE 2 26 Total Harmonic Distortion FIGURE 2 29 Total Harmonic Distortion plus Noise vs Output Voltage with f 1 kHz plus Noise vs Output Voltage with f 20 kHz 6 135 Voo 5 0V 5 S 54 G 42 VN S 130 gt 4 Vout 8 8 Vin 125 WA i gt 2 _ 3 2 7 55 120 5 O 9 115 m YA 8 110 1 5 1 V V 0 10 20 30 40 50 60 70 80 90 100 MRE age 100k 1M Time 10 ps div Freguency Hz FIGURE 2 27 The MCP6021 1R 2 3 4 FIGURE 2 30 Channel to Chan
3. TABLE 3 1 PIN FUNCTION TABLE MCP6021 oC MCP6021 MCP6021R mu MSOP SOT 23 5 SOT 23 5 MCP6022 MCP6023 MCP6024 Symbol Description TSSOP Note 1 Note 2 Note 1 6 1 1 1 6 1 Vout Voura Analog Output op amp A 2 4 4 2 2 2 Vina Inverting Input op amp A 3 3 3 3 3 3 Vint Vinat Non inverting Input op amp 7 5 2 8 7 4 Vpp Positive Power Supply 2 mE 5 5 ViNB Non inverting Input op amp B 6 6 VINB Inverting Input op amp B 7 7 VOUTB Analog Output op amp B 8 Vourc Analog Output op amp C m 9 ViNC Inverting Input op amp C 10 VINGI Non inverting Input op amp C 4 2 5 4 4 11 Vss Negative Power Supply 12 VINDE Non inverting Input op amp D 13 Vinp Inverting Input op amp D 14 VouTD Analog Output op amp D 5 5 m VREF Reference Voltage 8 CS Chip Select 1 8 1 No Internal Connection Note 1 The MCP6021 in the 8 pin MSOP package is only available for E temp Extended Temperature parts The MCP6021 in the 8 pin TSSOP package is only available for I temp Industrial Temperature parts 2 The MCP6021R is only available in the 5 pin SOT 23 package and for E temp Extended Temperature parts 3 1 The op amp output pins are low impedance voltage sources
4. NNN XXXX YYWW Legend XX X Customer specific information Y Year code last digit of calendar year YY Year code last 2 digits of calendar year WW Week code week of January 1 is week 01 NNN Alphanumeric traceability code Pb free JEDEC designator for Matte Tin Sn This package is Pb free The Pb free JEDEC designator be found the outer packaging for this package Note Inthe event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information NENNEN DS21685C page 18 2006 Microchip Technology Inc MCP6021 1R 2 3 4 Package Marking Information Continued 14 Lead PDIP 300 mil MCP6024 Example 1 1 1 1 1 1 1 1 1 1 XXXXXXXXXXXXXX MCP6024 I P N XXXXXXXXXXXXXX Q YYWWNNN AS 0331256 LT LT LI LI LT LT LI LT LT LT LT LT LT LI 1 1 MCP6024 E P e3 AS 0549256 LI LI U U LI LI U OR
5. Ca EDT Re FIGURE 4 4 Non inverting gain circuit with parasitic capacitance The largest value of Rg in Figure 4 4 that should be used is a function of noise gain see Gy Section 4 3 Capacitive Loads and Figure 4 5 shows results for various conditions Other compensation techniques may be used but they tend to be more complicated to the design 100k Gy gt 1 V V Cg 7 pF A E Ce 20 pF E x Maximum Q Cg 50pF J Ca 100 pF 4 per ey ay 100 1 10 Noise Gain Gy V V FIGURE 4 5 Non inverting gain circuit with parasitic capacitance 45 MCP6023 Chip Select CS The MCP6023 is a single amplifier with chip select CS When CS is high the supply current is less than 10 nA typ and travels from the CS pin to Vss with the amplifier output being put into a high impedance state When CS is low the amplifier is enabled If CS is left floating the amplifier may not operate properly Figure 1 1 and Figure 2 39 show the output voltage and supply current response to a CS pulse 4 6 MCP6021 and MCP6023 Reference Voltage The single op amps MCP6021 and MCP6023 not in the SOT 23 5 package have an internal mid supply reference voltage connected to the pin see Figure 4 6 The MCP6021 has CS internally tied to Vas whic
6. Time 200 ns div Time 200 ns div FIGURE 2 32 Small Signal Non inverting FIGURE 2 35 Small Signal Inverting Pulse Pulse Response Response za G 1 V V G 1VV 4 5 ai 4 5 zn Rp 1kQ _ 4 0 _ 4 0 3 5 3 5 S 3 0 3 0 S 25 25 3 2 0 5 20 jum P 0 5 X 0 5 S 0 0 0 0 Time 500 ns div Time 500 ns div FIGURE 2 33 Large Signal Non inverting FIGURE 2 36 Large Signal Inverting Pulse Pulse Response Response DS21685C page 10 2006 Microchip Technology Inc MCP6021 1R 2 3 4 Note Unless otherwise indicated Ta 25 Vpp 2 5V to 5 5V Vss GND Vom 2 Vout Vpn 2 RL 10 kQ to Vpp 2 and C 60 pF 50 50 c E 40 40 Representative Part gt 30 30 ti a b 4 Vpp 5 5V gt 0 z t s 10 8 10 Vyp 2 5V 3 5 8 2 8 20 lt 30 lt 0 40 40 50 50 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 50 25 0 25 50 75 100 125 Power Supply Voltage V Ambient Temperature C FIGURE 2 37 Veer Accuracy vs Supply FIGURE 2 40 VREF Accuracy vs Voltage MCP60
7. Controlling Parameter Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side BSC Basic Dimension Theoretically exact value shown without tolerances See ASME Y14 5M REF Reference Dimension usually without tolerance for information purposes only See ASME Y14 5M JEDEC Equivalent MO 187 Revised 07 21 05 Drawing No C04 111 DS21685C page 24 2006 Microchip Technology Inc E 1 m 3 m 3 m 3 m m D m J m n 2 no ri Do E Lt 14 Lead Plastic Dual In line 300 mil PDIP MCP6021 1R 2 3 4 3 Ag B1 _ Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p 100 2 54 Top to Seating Plane A 140 155 170 3 56 3 94 4 32 Molded Package Thickness A2 115 130 145 2 92 3 30 3 68 Base to Seating Plane A1 015 0 38 Shoulder to Shoulder Width E 300 313 325 7 62 7 94 8 26 Molded Package Width 240 250 260 6 10 6 35 6 60 Overall Length D 740 750 760 18 80 19 05 19 30 Tip to Seating Plane L 125 130 135 3 18 3 30 3 43 Lead Thickness c 008 012 015 0 20 0 29 0 38 Upper Lead Width 1
8. 2006 Microchip Technology Inc MCP6021 1R 2 3 4 AC ELECTRICAL CHARACTERISTICS Electrical Specifications Unless otherwise indicated Ta 25 C Vip 2 5V to 5 5V Vss GND Vem Vpp 2 Vout Vpp 2 RL 10 to Vpp 2 and C 60 pF Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP 10 MHz Phase Margin at Unity Gain PM ES 65 G 1 Settling Time 0 2 tsETTLE 250 ns G 1 Vour 100 mVp p 7 0 V us Total Harmonic Distortion Plus Noise f 1 kHz G 1 V V THD N 0 00053 Vour 0 25V to 3 25V 1 75V 1 50Vpx Vpp 5 0V BW 22 kHz f 1 kHz G 1 VV 6009 THD N 0 00064 Vout 0 25V to 3 25V 1 75V 1 50Vpx Vpp 5 0V BW 22 kHz f 1kHz G 1 V V THD N 0 0014 Vout 4 Vpp 5 0V BW 22 kHz f 1kHz G 10 V V THD N 0 0009 Vout 4Vp p 5 0V BW 22 kHz f 1 kHz G 100 V V THD N 0 005 Vout 4Vp p Vpp 5 0V BW 22 kHz Noise Input Noise Voltage Eni 2 9 uVp p f 0 1 Hz to 10 Hz Input Noise Voltage Density eni 8 7 nV VHz f 10 kHz Input Noise Current Density ini 3 fA VHz f 1 kHz MCP6023 CHIP SELECT CS ELECTRICAL CHARACTERISTICS Electrical Specifications Unless otherwise indicated Ta 25 C Vip 2 5V to 5 5V Vss GND Vem Vpp 2 Vout Vpp
9. Analog Outputs 3 2 The op amp non inverting and inverting inputs are high impedance CMOS inputs with low bias currents Analog Inputs 3 3 VREF Output MCP6021 and MCP6023 Mid supply reference voltage provided by the single op amps except in SOT 23 5 package This is an unbuffered resistor voltage divider internal to the part 34 CS Digital Input This is a CMOS Schmitt triggered input that places the part into a low power mode of operation 3 5 The positive power supply pin Vpp is 2 5V to 5 5V higher than the negative power supply pin Vss For normal operation the other pins are at voltages between Vss and Vpp Power Supply Vss and Vpp Typically these parts are used in a single positive supply configuration In this case Vas is connected to ground and Vpp is connected to the supply Vpp will need a local bypass capacitor typically 0 01 UF to 0 1 uF within 2 mm of the Vpp pin These parts need to use a bulk capacitor typically 1 UF or larger within 100 mm of the Vpp pin it can be shared with nearby analog parts DS21685C page 12 2006 Microchip Technology Inc MCP6021 1R 2 3 4 4 0 APPLICATIONS INFORMATION The MCP6021 1R 2 3 4 family of operational amplifiers are fabricated on Microchip s state of the art CMOS process They are unity gain stable and suitable for a wide range of general purpose applications 4 1 Rail to Rail Input The MCP6021 1R 2 3 4 amplifier family i
10. C W Thermal Resistance 8L SOIC OJA 163 C W Thermal Resistance 8L MSOP OJA 206 C W Thermal Resistance 8L TSSOP Oya 124 C W Thermal Resistance 14L PDIP Oya 70 C W Thermal Resistance 14L SOIC 120 C W Thermal Resistance 14L TSSOP OJA 100 C W Note 1 The industrial temperature devices operate over this extended temperature range but with reduced performance In any case the internal junction temperature Ty must not exceed the absolute maximum specification of 150 C High Z Amplifier On Vout High Z Iss 50 nA typ 1 MA 50 nA typ los 10 nA typ 10 nA typ 10 nA typ FIGURE 1 1 Timing diagram for the CS pin on the MCP6023 DS21685C page 4 2006 Microchip Technology Inc MCP6021 1R 2 3 4 2 0 TYPICAL PERFORMANCE CURVES Note The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only The performance characteristics listed herein are not tested or guaranteed In some graphs or tables the data presented may be outside the specified operating range e g outside specified power supply range and therefore outside the warranted range Note Unless otherwise indicated Ta 25 C Vpp 2 5V to 5 5V Vss GND Vom Vpp 2 Vout Vpn 2 RL 10 kQ to Vpp 2 and
11. Guard Ring ViN Vint MEN FIGURE 4 10 Layout Example Guard Ring 1 Non inverting Gain and Unity Gain Buffer a Connectthe guard ring to the inverting input pin Vin this biases the guard ring to the common mode input voltage b Connect the non inverting pin Vin to the input with a wire that does not touch the PCB surface 2 Inverting Figure 4 10 and Transimpedance Gain Amplifiers convert current to voltage such as photo detectors a Connect the guard ring to the non inverting input pin Vin This biases the guard ring to the same reference voltage as the op amp s input e g Vpp 2 or ground b Connect the inverting pin to the input with a wire that does not touch the PCB surface 4 10 High Speed PCB Layout Due to their speed capabilities a little extra care in the PCB Printed Circuit Board layout can make a significant difference in the performance of these op amps Good PC board layout techniques will help you achieve the performance shown in Section 1 0 Elec trical Characteristics and Section 2 0 Typical Per formance Curves while also helping you minimize EMC Electro Magnetic Compatibility issues Use a solid ground plane and connect the bypass local capacitor s to this plane with minimal length traces This cuts down inductive and capacitive crosstalk 2006 Microchip Technology Inc DS21
12. 045 058 070 1 14 1 46 1 78 Lower Lead Width B 014 018 022 0 36 0 46 0 56 Overall Row Spacing eB 310 370 430 7 87 9 40 10 92 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 001 Drawing No C04 005 2006 Microchip Technology Inc DS21685C page 25 MCP6021 1R 2 3 4 14 Lead Plastic Small Outline SL Narrow 150 mil SOIC 1 2 n O 1 Y FON 3 kai Al B Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p 050 1 27 Overall Height A 053 061 069 1 35 1 55 1 75 Molded Package Thickness A2 052 056 061 1 32 1 42 1 55 Standoff A1 004 007 010 0 10 0 18 0 25 Overall Width E 228 236 244 5 79 5 99 6 20 Molded Package Width E1 150 154 157 3 81 3 90 3 99 Overall Length D 337 342 347 8 56 8 69 8 81 Chamfer Distance h 010 015 020 0 25 0 38 0 51 Foot Length L 016 033 050 0 41 0 84 1 27 Foot Angle 0 4 8 0 4 8 Lead Thickness c 008 009
13. 25 Vpp 2 5V to 5 5V Vss GND Vem 2 Vout 2 RL 10 kQ to Vpp 2 and C 60 pF 130 120 22 Vpp 5 5V amp S 120 115 Vpp 5 5V S 110 3 gn 8 PT h ine 8 105 8 Vpp 2 5V 9 100 5 100 O go ri 9 Q 8 80 90 100 1k 10k 100k 50 25 0 25 50 75 100 125 Load Resistance Q Ambient Temperature C FIGURE 2 19 DC Open Loop Gain vs FIGURE 2 22 DC Open Loop Gain vs Load Resistance Temperature 120 14 105 a m Vom Vpp 2 5 12 Gain Bandwidth 9 3 3 5 5V 2 10 75 100 8 55 8 LE 60 Z 35 i gt 90 Vos 2 5V 9 6 Phase Margin G 1 45 3 8 mo 30 9 8 5 E a 70 9 2 5 0V e 0 00 0 05 0 10 0 15 0 20 0 25 0 30 0 0 Output Voltage Headroom V 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 Voo OF Vor Vss Common Mode Input Voltage V FIGURE 2 20 Small Signal DC Open Loop FIGURE 2 23 Gain Bandwidth Product Gain vs Output Voltage Headroom Phase Margin vs
14. 60 pF 100 50 o S 50 o gt 100 150 5 200 Von 5 0V 250 0 50 25 0 25 50 75 100 125 Ambient Temperature Vom 2 Input Offset Voltage uV e 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Output Voltage V FIGURE 2 7 Temperature Input Offset Voltage vs FIGURE 2 10 Output Voltage Input Offset Voltage vs 1 000 100 10 Input Noise Voltage Density nV VHz 0 1 1 10 100 1k 10k 100k 1M Frequency Hz FIGURE 2 8 Input Noise Voltage Density vs Frequency 100 room PSRR 90 15 PSRR 9 80 c 70 tc 2 60 pall E 50 CMRR 8 40 30 W 20 DN 100 1k 10k 100k 1M Frequency Hz FIGURE 2 9 CMRR 5 vs Frequency 24 22 Von 5 0V 2
15. Common Mode Input Voltage 10 100 14 105 9 90 5 80 2 12 Gain Bandwidth Product 90 m 2 7 70 2 10 f 75 6 ja 60 Eq 8 5 GBWP Vy 5 5V 50 35 Phase Margin G 2 9 lt 4 GBWP Vo 2 5V 40 8 E 3 Vp 2 5V 30 m 4 i 30 g 24 Vpp 5 5V 20 8 5 Voo 5 0V e o 1 10 Vom Vpp 2 a 0 0 0 0 50 25 0 25 50 75 100 125 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 Ambient Temperature C Output Voltage V FIGURE 2 21 Gain Bandwidth Product FIGURE 2 24 Gain Bandwidth Product Phase Margin vs Temperature Phase Margin vs Output Voltage DS21685C page 8 2006 Microchip Technology Inc MCP6021 1R 2 3 4 Note Unless otherwise indicated Ta 25 Vpp 2 5V to 5 5V Vss GND Vcow Vpp 2 Vout 2 RL 10 kQ to Vpp 2 and C 60 pF
16. Overall Row Spacing eB 310 370 430 7 87 9 40 10 92 Mold Draft Angle u 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 001 Drawing No C04 018 D 271 1 11 2006 Microchip Technology Inc DS21685C page 21 MCP6021 1R 2 3 4 8 Lead Plastic Small Outline SN Narrow 150 mil SOIC __ 1 B L A1 Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p 050 1 27 Overall Height A 053 061 069 1 35 1 55 1 75 Molded Package Thickness A2 052 056 061 1 32 1 42 1 55 Standoff Al 004 007 010 0 10 0 18 0 25 Overall Width E 228 237 244 5 79 6 02 6 20 Molded Package Width 1 146 154 157 3 71 3 91 3 99 Overall Length D 189 193 197 4 80 4 90 5 00 Chamfer Distance h 010 015 020 0 25 0 38 0 51 Foot Length L 019 025 03
17. claims suits or expenses resulting from such use No licenses are conveyed implicitly or otherwise under any Microchip intellectual property rights QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV ISO TS 16949 2002 Trademarks The Microchip name and logo the Microchip logo Accuron dsPIC KEELOQ microID MPLAB PIC PICmicro PICSTART PRO MATE PowerSmart rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U S A and other countries AmpLab FilterLab Migratable Memory MXDEV MXLAB PICMASTER SEEVAL SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U S A Analog for the Digital Age Application Maestro dsPICDEM dsPICDEM net dsPICworks ECAN ECONOMONITOR FanSense FlexROM fuzzyLAB In Circuit Serial Programming ICSP ICEPIC Linear Active Thermistor MPASM MPLIB MPLINK MPSIM PICkit PICDEM PICDEM net PICLAB PICtail PowerCal Powerlnfo PowerMate PowerTool Real ICE rfLAB rfPICDEM Select Mode Smart Serial SmartTel Total Endurance UNI O WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U S A and other countries SQTP is a service mark of Microchip Technology Incorporated in the U S A All other trademarks mentioned herein are property of their respective companies 2006 Microchip Technology Incorporated Printed in the U S A All Rights Reser
18. 19 0 25 0 30 Mold Draft Angle Top a 0 5 10 0 5 10 Mold Draft Angle Bottom B 0 5 10 0 5 10 Controlling Parameter Notes Dimensions D and E1 do not include mold flash or protrusions JEDEC Equivalent MO 153 Drawing No C04 086 Mold flash or protrusions shall not exceed 005 0 127mm per side Revised 07 21 05 2006 Microchip Technology Inc DS21685C page 23 MCP6021 1R 2 3 4 8 Lead Plastic Micro Small Outline Package MS MSOP S E i p x n O 1 EO Me Y ii gus Le YA p Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch 026 BSC 0 65 BSC Overall Height A 043 1 10 Molded Package Thickness A2 030 033 037 0 75 0 85 0 95 Standoff A1 000 006 0 00 0 15 Overall Width E 193 BSC 4 90 BSC Molded Package Width E1 118 BSC 3 00 BSC Overall Length D 118 BSC 3 00 BSC Foot Length L 016 024 031 0 40 0 60 0 80 Footprint Reference F 037 REF 0 95 REF Foot Angle 0 8 0 8 Lead Thickness c 003 006 009 0 08 0 23 Lead Width B 009 012 016 0 22 0 40 Mold Draft Angle Top 5 15 5 15 Mold Draft Angle Bottom 5 15 5 15
19. 2 RL 10 to Vpp 2 and CL 60 pF Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold Low Vit Vss 02Vpp V CS Input Current Low lost 1 0 0 01 CS Vss cs High Specifications CS Logic Threshold High Vin 0 8 Voo Vpp V CS Input Current High lcsH 001 20 JA CS Vpp GND Current lss 2 005 CS Vpp Amplifier Output Leakage lo LEAK x 0 01 JA CS Vpp cs Dynamic Specifications CS Low to Amplifier Output Turn on Time ton 2 10 us G 1 CS 0 2Vpp to Vout 0 45Vpp time CS High to Amplifier Output High Z Time Lm 0 01 ps 1 Vss CS 0 8Vpp to Vour 0 05Vpp time Hysteresis VHYST 0 6 m V Vpp 5 0 Internal Switch 2006 Microchip Technology Inc DS21685C page 3 MCP6021 1R 2 3 4 TEMPERATURE CHARACTERISTICS Electrical Specifications Unless otherwise indicated Vpp 2 5V to 5 5V and Vss GND Parameters Sym Min Typ Max Units Conditions Temperature Ranges Industrial Temperature Range 40 85 C Extended Temperature Range Ta 40 125 C Operating Temperature Range Ta 40 125 C Note 1 Storage Temperature Range Ta 65 150 C Thermal Package Resistances Thermal Resistance 5L SOT 23 OJA 256 C W Thermal Resistance 8L PDIP 85
20. 20 f 18 _ 16 N SI 14 f 1 kHz gz 12 10 aan 8 f 10 kHz 6 5 4 2 0 1 Q Tr NN M c s st DD W Common Mode Input Voltage V FIGURE 2 11 Input Noise Voltage Density vs Common Mode Input Voltage PSRR CMRR dB e 50 25 0 25 50 75 100 125 Ambient Temperature C CMRR PSRR vs FIGURE 2 12 Temperature DS21685C page 6 2006 Microchip Technology Inc MCP6021 1R 2 3 4 Note Unless otherwise indicated Ta 25 Vpp 2 5V to 5 5V Vss GND Vom Vpp 2 Vout Vpn 2 RL 10 kQ to Vpp 2 and C 60 pF 10 000 2 Vpp 5 5V Ip Ta 125 gt 2 rer EN c g og los Ta 125 5 o pi 1004 lp Ta 85 5 TT MUN 8i AN los Ta 85 5 o 1 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Common Mode Input Voltage V 10 000 1 000 100 10 Input Bias Offset Currents pA 1 los 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature C
21. C 60 pF 24 22 20 18 16 14 12 10 8 6 4 2 0 Percentage of Occurances 1192 Samples 4 Parts OV H Ta 40 C to 85 Input Offset Voltage Drift uV C FIGURE 2 4 Industrial Temperature Parts Input Offset Voltage Drift 16 o 1192 Samples 8 14 1 Parts Vom OV 1 5 12 25 8 10 9 5 8 6 4 5 2 0 ER Ur rc 22 who dO Input Offset Voltage uV FIGURE 2 1 Input Offset Voltage Industrial Temperature Parts 24 22 E Temp 438 Samples 9 20 Parts Vpp 5 0V 5 18 Vom OV 8 16 TA 25 C 14 5 12 o 10 S 8 5 6 9 4 2 D 0 1 O O O O O o TON u QU Toy IGN Input Offset Voltage uV 24 22 20 18 16 14 12 10 8 6 4 2 0 Percentage of Occurance
22. FIGURE 2 13 Input Bias Offset Currents vs Common Mode Input Voltage FIGURE 2 16 Input Bias Offset Currents vs Temperature 1 2 1 1 ne 125 85 C Ta 425 C us 40C 0 2 0 1 H ZI 0 0 i 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Power Supply Voltage V Quiescent Current mA amplifier 10 Von 5 5V Quiescent Current mA amplifier e o Vom Von 0 5V 50 25 0 25 50 75 100 125 Ambient Temperature C FIGURE 2 14 Quiescent Current vs Supply Voltage FIGURE 2 17 Quiescent Current vs Temperature 35 t 30 5 S 25 nw 3 20 SEs r 2 125 o 10 85 C 5 25 o 5 5 40 C o 0 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Supply Voltage V Open Loop Gain dB a Open Loop Phase 1 210 10 100 1k 10k 100k 1M 10M 100M Frequency Hz FIGURE 2 15 Output Short Circuit Current vs Supply Voltage FIGURE 2 18 Open Loop Gain Phase vs Frequency 2006 Microchip Technology Inc DS21685C page 7 MCP6021 1R 2 3 4 Note Unless otherwise indicated Ta
23. Parts Vos 250 250 Vom OV Vpp 5 0V Extended Temperature Parts Vos 2 5 2 5 mV Vom OV Vpp 5 0V Ta 40 to 125 C Input Offset Voltage Temperature Drift AVos ATA 3 5 puV C Ta 40 C to 125 C Power Supply Rejection Ratio PSRR 74 90 dB Vom 0V Input Current and Impedance Input Bias Current IB 1 E pA Industrial Temperature Parts IB 30 150 pA Ta 85 C Extended Temperature Parts IB 640 5 000 pA Ta 125 Input Offset Current los M 1 PA Common Mode Input Impedance 2 101416 Q pF Differential Input Impedance ZIFF 101313 O IpF Common Mode Common Mode Input Range VcMR 0 3 Vpp 0 3 V Common Mode Rejection Ratio CMRR 74 90 dB Vpp 5 Vom 0 3V to 5 3V CMRR 70 85 dB Vpp 5V Vem 3 0V to 5 3V CMRR 74 90 dB Vpp 5 Vom 0 3V to 3 0V Voltage Reference MCP6021 and MCP6023 only VREF Accuracy VREF Vpp 2 VREF_ACC 50 E 450 mV VREF Temperature Drift AVREF ATA 100 uv C Ta 40 to 125 C Open Loop Gain DC Open Loop Gain Large Signal AOL 90 110 dB Vom OV Vout Vss 0 3V to Vpp 0 3V Output Maximum Output Voltage Swing VoL 15 Vpp 20 mV 0 5V output overdrive Output Short Circuit Current Isc 30 mA Vpp 2 5V lac 22 mA Vpp 5 5V Power Supply Supply Voltage Vs 2 5 5 5 V Quiescent Current per Amplifier la 0 5 1 0 1 35 mA l9 0 DS21685C page 2
24. 0 0 48 0 62 0 76 Foot Angle 9 0 4 8 0 4 8 Lead Thickness c 008 009 010 0 20 0 23 0 25 Lead Width B 013 017 020 0 33 0 42 0 51 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom B 0 12 15 0 12 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 012 Drawing No C04 057 DS21685C page 22 2006 Microchip Technology Inc MCP6021 1R 2 3 4 8 Lead Plastic Thin Shrink Small Outline ST 4 4 mm TSSOP E1 LA PENS L La 1 3 A2 Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p 026 0 65 Overall Height A 039 041 043 1 00 1 05 1 10 Molded Package Thickness A2 033 035 037 0 85 0 90 0 95 Standoff A1 002 004 006 0 05 0 10 0 15 Overall Width E 246 251 256 6 25 6 38 6 50 Molded Package Width E1 169 173 ATT 4 30 4 40 4 50 Molded Package Length D 114 118 122 2 90 3 00 3 10 Foot Length L 020 024 028 0 50 0 60 0 70 Foot Angle 9 0 4 8 0 4 8 Lead Thickness 004 006 008 0 09 0 15 0 20 Lead Width B 007 010 012 0
25. 010 0 20 0 23 0 25 Lead Width B 014 017 020 0 36 0 42 0 51 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom B 0 12 15 0 12 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 012 Drawing No C04 065 DS21685C page 26 2006 Microchip Technology Inc MCP6021 1R 2 3 4 14 Lead Plastic Thin Shrink Small Outline ST 4 4 mm TSSOP ae L bs 1 L Al A2 Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch 026 BSC 0 65 BSC Overall Height A 039 041 043 1 00 1 05 1 10 Molded Package Thickness A2 033 035 037 0 85 0 90 0 95 Standoff A1 002 004 006 0 05 0 10 0 15 Overall Width E 246 251 256 6 25 6 38 6 50 Molded Package Width 1 169 173 177 4 30 4 40 4 50 Molded Package Length D 193 197 201 4 90 5 00 5 10 Foot Length L 020 024 028 0 50 0 60 0 70 Foot Angle 9 0 4 8 0 4 8 Lead Thickness c 004 006 008 0 09 0 15 0 20 Lead Width B 007 010 012 0 19 0 25 0 30 Mold
26. 21 and MCP6021R are available in SOT 23 5 The single MCP6021 single MCP6023 and dual MCP6022 are available in 8 lead PDIP SOIC and TSSOP The Extended Temperature single MCP6021 is available in 8 lead MSOP The quad MCP6024 is offered in 14 lead PDIP SOIC and TSSOP packages The MCP6021 1R 2 3 4 family is available in Industrial and Extended temperature ranges It has a power supply range of 2 5V to 5 5V Package Types MCP6021 MCP6022 SOT 23 5 PDIP SOIC TSSOP 5 Voutalt A 8 Vpp Vss 2 Vina L2 F 17 Vout Vint 3 4 Vin Vina 3 2 6 V NB V V MCP6021R 5514 5 VINB SOT 23 5 MCP6023 PDIP SOIC TSSOP Vout l 5 33 Vpp 2 NC 1 8JCS Vint 3 4jVw 2H gt 7 Vpp 6 MCP6021 v 3 eur PDIP SOIC ssl4 S MSOP TSSOP MCP6024 PDIP SOIC TSSOP NC 1 8 NC Vine EHX Vp Voura 7114 Vourb Vint 3 eal 6 Vour VIN 2 wa Vino V e 4 5 Vrer 12 VIND Vop 4 11 Vss 5 10 Vinct Vine 6 NT v Vinc VourB 7 8 Voutc 2006 Microchip Technology Inc DS21685C page 1 MCP6021 1R 2 3
27. 21 and MCP6023 only Temperature MCP6021 and MCP6023 only 1 6 1 6 Op Op Amp _ Op Amp a LA turns on here shuts off here 1 4 1 2 12 2s gt y 0 52 10 52 1 0 14 Hysteresis z 0 8 CS swept ale Hysteresis S 0 8 CS swept t high to low 5 high to low AG lt 0 6 9 3 06 CS swept 1 5 Vo 25V cs swept E ya Von 55V low to high G 1 VV low to high G 2 1 VIV 0 2 FV 1 25V 0 2 V4 2 75V 0 0 0 0 0 0 0 5 1 0 1 5 2 0 2 5 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Chip Select Voltage V Chip Select Voltage V FIGURE 2 38 Chip Select CS Hysteresis FIGURE 2 41 Chip Select CS Hysteresis MCP6023 only with Vpp 2 5V MCP6023 only with Vpp 5 5V 5 5 50 Vpp 5 0V 4 5 G 1V V 4 E CS Voltage Vin Vss 5 4 0 4 g 35 gt S 3 0 Vout 2 25 ty or d 2 15 Output Output 5 utpu utpu 590 10 1 Output High Z A 0 5 0 0 0 5 Time 5 us div FIGURE 2 39 Chip Select CS to Amplifier Output Response Time MCP6023 only vee X X A H jn n i NON 2006 Microchip Technology Inc DS21685C page 11 MCP6021 1R 2 3 4 3 0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3 1
28. 3 E SN Extended temperature 8LD SOIC Package OT Plastic Small Outline Transistor SOT 23 5 lead a MCP6024 I SL Industrial temperature MCP6021 E Temp MCP6021R E Temp 14LD SOIC MS Plastic MSOP 8 lead b MCP6024 E SL Extended temperature MCP6021 E Temp 14LD SOIC P Plastic DIP 300 mil Body 8 lead 14 lead MCP6024T E ST Tape and Reel SN Plastic SOIC 150mil Body 8 lead Extended temperature SL Plastic SOIC 150 mil Body 14 lead 14LD TSSOP ST Plastic TSSOP 8 lead MCP6021 1 Temp MCP6022 E Temp MCP6023 I Temp E Temp ST Plastic TSSOP 14 lead 2006 Microchip Technology Inc DS21685C page 31 MCP6021 1R 2 3 4 NOTES DS21685C page 32 2006 Microchip Technology Inc Note the following details of the code protection feature on Microchip devices Microchip products meet the specification contained in their particular Microchip Data Sheet Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets Most likely the person doing so is engaged in theft of intellectual property Mi
29. 4 1 0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings 1 MSS uiis ain ede eee 7 0V All Inputs and Outputs Vgg 0 3V to Vpp 0 3V Difference Input Voltage pp Vssl Output Short Circuit Current continuous Current at Input Pins cece eee 2 mA Current at Output and Supply Pins 30 mA Storage 65 C to 150 C Junction Temperature 150 C ESD Protection on all pins HBM MM gt 2 kV 200V DC ELECTRICAL CHARACTERISTICS T Notice Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Electrical Specifications Unless otherwise indicated Ta 25 Vip 2 5V to 5 5V Vss GND Vem Vpp 2 Vout Vpp 2 and 10 to Vpp 2 Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage Industrial Temperature Parts Vos 500 m 500 Voy 0 Extended Temperature
30. 45 0 55 Foot Angle f 0 5 10 0 5 10 Lead Thickness c 004 006 008 0 09 0 15 0 20 Lead Width B 014 017 020 0 35 0 43 0 50 Mold Draft Angle Top a 0 5 10 0 5 10 Mold Draft Angle Bottom b 0 5 10 0 5 10 Controlling Parameter Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 005 0 127mm per side EIAJ Equivalent SC 74A Drawing No C04 091 Revised 09 12 05 DS21685C page 20 2006 Microchip Technology Inc MCP6021 1R 2 3 4 8 Lead Plastic Dual In line P 300 mil PDIP Et a lil pes pe Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch 100 2 54 Top to Seating Plane A 140 4155 170 3 56 3 94 4 32 Molded Package Thickness A2 115 130 145 2 92 3 30 3 68 Base to Seating Plane Al 015 0 38 Shoulder to Shoulder Width E 300 313 325 7 62 7 94 8 26 Molded Package Width 1 240 250 260 6 10 6 35 6 60 Overall Length D 360 373 385 9 14 9 46 9 78 Tip to Seating Plane L 125 130 135 3 18 3 30 3 43 Lead Thickness c 008 012 015 0 20 0 29 0 38 Upper Lead Width B1 045 058 070 1 14 1 46 1 78 Lower Lead Width B 014 018 022 0 36 0 46 0 56
31. 685C page 15 MCP6021 1R 2 3 4 Separate digital from analog low speed from high speed and low power from high power This will reduce interference Keep sensitive traces short and straight Separating them from interfering components and traces This is especially important for high frequency low rise time signals Sometimes it helps to place guard traces next to victim traces They should be on both sides of the victim trace and as close as possible Connect the guard trace to ground plane at both ends and in the middle for long traces Use coax cables or low inductance wiring to route signal and power to and from the PCB 4 11 Typical Applications 4 11 1 A D CONVERTER DRIVER AND ANTI ALIASING FILTER Figure 4 11 shows a third order Butterworth filter that can be used as an A D converter driver It has a band width of 20 kHz and a reasonable step response It will work well for conversion rates of 80 ksps and greater it has 29 dB attenuation at 60 kHz 1 0 nF 8 45kQ 14 7kQ 33 2ko 602 OMAN AAA 1 2nF 100 pF O FIGURE 4 11 A D converter driver and anti aliasing filter with a 20 kHz cutoff frequency This filter can easily be adjusted to another bandwidth by multiplying all capacitors by the same factor Alternatively the resistors can all be scaled by another common factor to adjust the bandwidth 4 11 2 OPTICAL DETECTOR AMPLIFIER
32. 73 6509 ASIA PACIFIC Australia Sydney Tel 61 2 9868 6733 Fax 61 2 9868 6755 China Beijing Tel 86 10 8528 2100 Fax 86 10 8528 2104 China Chengdu Tel 86 28 8676 6200 Fax 86 28 8676 6599 China Fuzhou Tel 86 591 8750 3506 Fax 86 591 8750 3521 China Hong Kong SAR Tel 852 2401 1200 Fax 852 2401 3431 China Qingdao Tel 86 532 8502 7355 Fax 86 532 8502 7205 China Shanghai Tel 86 21 5407 5533 Fax 86 21 5407 5066 China Shenyang Tel 86 24 2334 2829 Fax 86 24 2334 2393 China Shenzhen Tel 86 755 8203 2660 Fax 86 755 8203 1760 China Shunde Tel 86 757 2839 5507 Fax 86 757 2839 5571 China Wuhan Tel 86 27 5980 5300 Fax 86 27 5980 5118 China Xian Tel 86 29 8833 7250 Fax 86 29 8833 7256 ASIA PACIFIC India Bangalore Tel 91 80 4182 8400 Fax 91 80 4182 8422 India New Delhi Tel 91 11 5160 8631 Fax 91 11 5160 8632 India Pune Tel 91 20 2566 1512 Fax 91 20 2566 1513 Japan Yokohama Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Gumi Tel 82 54 473 4301 Fax 82 54 473 4302 Korea Seoul Tel 82 2 554 7200 Fax 82 2 558 5932 or 82 2 558 5934 Malaysia Penang Tel 60 4 646 8870 Fax 60 4 646 5086 Philippines Manila Tel 63 2 634 9065 Fax 63 2 634 9069 Singapore Tel 65 6334 8870 Fax 65 6334 8850 Taiwan Hsin Chu Tel 886 3 572 9526 Fax 886 3 572 6459 Taiwan Kaohsiung Tel 886 7 536 4818 Fax 886 7 536 4803 Taiwan T
33. Draft Angle Top a 12 REF 12 REF Mold Draft Angle Bottom B 12 REF 12 REF Controlling Parameter Notes Dimensions and E1 do not include mold fla sh or protrusions Mold flash or protrusions shall not exceed 005 0 127mm per side BSC Basic Dimension Theoretically exact value shown without tolerances See ASME Y14 5M REF Reference Dimension usually without tole rance for information purposes only See ASME Y14 5M JEDEC Equivalent MO 153 AB 1 Drawing No C04 087 Revised 08 17 05 _ FS a 2006 Microchip Technology Inc DS21685C page 27 MCP6021 1R 2 3 4 NOTES DS21685C page 28 2006 Microchip Technology Inc MCP6021 1R 2 3 4 APPENDIX A REVISION HISTORY Revision C March 2006 The following is the list of modifications 1 Added SOT 23 5 package option for single op amps MCP6021 and MCP6021R E temp only 2 Added MSOP 8 package option for E temp single op amp 6021 3 Corrected package drawing on front page for dual op amp MCP6022 4 Clarified spec conditions Isc PM and THD N in Section 2 0 Typical Performance Curves 5 Added Section 3 0 Pin Descriptions 6 Updated Section 4 0 Applications informa tion for THD N unused op amps and gain peaking discussions 7 Corrected and updated package marking infor mation in Section 6 0 Packaging Informa tion 8 Added Appendix A REVISION HISTORY Revision B
34. Figure 4 12 shows the MCP6021 op amp used as a transimpedance amplifier in a photo detector circuit The photo detector looks like a capacitive current source so the 100 resistor gains the input signal to a reasonable level The 5 6 pF capacitor stabilizes this circuit and produces a flat frequency response with a bandwidth of 370 kHz 5 6 pF Photo ju Detector 100 kQ gt 8 e 0 toopr LPS e 2 MCP6021 L O z Vpp 2 FIGURE 4 12 Transimpedance Amplifier for an Optical Detector DS21685C page 16 2006 Microchip Technology Inc MCP6021 1R 2 3 4 5 0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6021 1R 2 3 4 family of op amps 5 1 SPICE Macro Model The latest SPICE macro model available for the MCP6021 1R 2 3 4 op amps is on Microchip s web site at www microchip com This model is intended as an initial design tool that works well in the op amp s linear region of operation at room temperature Within the macro model file is information on its capabilities Bench testing is a very important part of any design and cannot be replaced with simulations Also simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves 5 2 FilterLab Software Microchip s FilterLab software is an innovative tool that simplifies analog acti
35. MICROCHIP MCP6021 1R 2 3 4 Rail to Rail Input Output 10 MHz Op Amps Features Rail to Rail Input Output Wide Bandwidth 10 MHz typ Low Noise 8 7 nV VHz at 10 kHz typ Low Offset Voltage Industrial Temperature 500 uV max Extended Temperature 250 UV max Mid Supply VREF MCP6021 and MCP6023 Low Supply Current 1 mA typ Unity Gain Stable Power Supply Range 2 5V to 5 5V Temperature Range Industrial 40 C to 85 C Extended 40 C to 125 C Typical Applications Automotive Driving A D Converters Multi Pole Active Filters Barcode Scanners Audio Processing Communications DAC Buffer Test Equipment Medical Instrumentation Available Tools SPICE Macro Model at www microchip com FilterLab software at www microchip com Typical Application Total Harmonic Distortion 0 00053 typ G 1 Photo iud Detector 100 kQ e O e 0 100 pF _ 2 MCP6021 Vpp 2 Transimpedance Amplifier Description The MCP6021 MCP6021R MCP6022 MCP6023 and MCP6024 from Microchip Technology Inc are rail to rail input and output op amps with high performance Key specifications include wide bandwidth 10 MHz low noise 8 7 nV VHz low input offset voltage and low distortion 0 00053 THD N The MCP6023 also offers a Chip Select pin CS that gives power savings when the part is not in use The single MCP60
36. November 2003 Second Release of this Document Revision A November 2001 Original Release of this Document 2006 Microchip Technology Inc DS21685C page 29 MCP6021 1R 2 3 4 NOTES DS21685C page 30 2006 Microchip Technology Inc MCP6021 1R 2 3 4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information e g on pricing or delivery refer to the factory or the listed sales office PART NO X XX Examples li d a MCP6021T E OT Tape and Reel Device Temperature Package Extended temperature Range 5LD SOT 23 b MCP6021 E P Extended temperature 8LD PDIP Device MCP6021 Single Op Amp c MCP6021 E SN Extended temperature MCP6021T Single Op Amp 8LD SOIC Tape and Reel for SOT 23 SOIC TSSOP MSOP a MCP6021RT E OT Tape and Reel MCP6021R Single Op Amp Extended temperature MCP6021RT Single Op Amp 5LD SOT 23 MCP6022 Onan a MCP6022 I P Industrial temperature MCP6022T Dual Op Amp 8LD PDIP Tape and Reel for SOIC and TSSOP b MCP6022 E P Extended temperature MCP6023 Single Op Amp w CS 8LD PDIP MCP6023T Single Op Amp w CS c MCP6022T E ST Tape and Reel Tape and Reel for SOIC and TSSOP Extended temperature MCP6024 Quad Op Amp 8LD TSSOP MCP6024T Quad Op Amp Tape and Reel for SOIC and TSSOP a MCP6023 I P Industrial temperature 8LD PDIP b MCP6023 E P Extended temperature Temperature Range 40 C to 85 C 8LD PDIP 40 C to 125 C c MCP602
37. aipei Tel 886 2 2500 6610 Fax 886 2 2508 0102 Thailand Bangkok Tel 66 2 694 1351 Fax 66 2 694 1350 EUROPE Austria Wels Tel 43 7242 2244 399 Fax 43 7242 2244 393 Denmark Copenhagen Tel 45 4450 2828 Fax 45 4485 2829 France Paris Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Munich Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Milan Tel 39 0331 742611 Fax 39 0331 466781 Netherlands Drunen Tel 31 416 690399 Fax 31 416 690340 Spain Madrid Tel 34 91 708 08 90 Fax 34 91 708 08 91 UK Wokingham Tel 44 118 921 5869 Fax 44 118 921 5820 02 16 06 DS21685C page 34 2006 Microchip Technology Inc
38. crochip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act If such acts allow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications MICROCHIP MAKES NO REPRESENTATIONS OR WAR RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED WRITTEN OR ORAL STATUTORY OR OTHERWISE RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ITS CONDITION QUALITY PERFORMANCE MERCHANTABILITY OR FITNESS FOR PURPOSE Microchip disclaims all liability arising from this information and its use Use of Microchip devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless Microchip from any and all damages
39. h always keeps the op amp on and always provides a mid supply reference With the MCP6023 taking the CS pin high conserves power by shutting down both the op amp and the VREF circuitry Taking the CS pin low turns on the op amp and circuitry Z soka CS o gt Vss CS tied internally to Vgg for MCP6021 FIGURE 4 6 Simplified internal VREF circuit MCP6021 and MCP6023 only See Figure 4 7 for a non inverting gain circuit using the internal mid supply reference The DC blocking capacitor Cg also reduces noise by coupling the op amp input to the source Re Re ANN 9 VW Vout Vin FIGURE 4 7 Non inverting gain circuit using MCP6021 and MCP6023 only DS21685C page 14 2006 Microchip Technology Inc MCP6021 1R 2 3 4 To use the internal mid supply reference for an inverting gain circuit connect the VREF pin to the non inverting input as shown in Figure 4 8 The capacitor helps reduce power supply noise on the output Re Vin O e O Vout FIGURE 4 8 Inverting gain circuit using Veer MCP6021 and MCP6023 only If you don t need the mid supply reference leave the VREF pin open 4 7 Supply Bypass With this family of operational amplifiers the power supply pin Vpp for single supply should have a local bypass capacitor i e 0 01 UF to 0 1 pF withi
40. n 2 mm for good high frequency performance It also needs a bulk capacitor i e 1 UF or larger within 100 mm to provide large slow currents This bulk capacitor can be shared with nearby analog parts 4 8 Unused Op Amps An unused op amp in a quad package MCP6024 should be configured as shown in Figure 4 9 These circuits prevent the output from toggling and causing crosstalk Circuit A can use any reference voltage between the supplies provides a buffered DC voltage and minimizes the supply current draw of the unused op amp Circuit B uses the minimum number of compo nents and operates as a comparator it may draw more current MCP6144 A MCP6144 B Vpp Vpp R Vpp ml _ R be FIGURE 4 9 Unused Op Amps 4 9 PCB Surface Leakage In applications where low input bias current is critical PCB printed circuit board surface leakage effects need to be considered Surface leakage is caused by humidity dust or other contamination on the board Under low humidity conditions a typical resistance between nearby traces is 10120 A 5V difference would cause 5 pA of current to flow which is greater than the MCP6021 1R 2 3 4 family s bias current at 25 C 1 pA typ The easiest way to reduce surface leakage is to use a guard ring around sensitive pins or traces The guard ring is biased at the same voltage as the sensitive pin Figure 4 10 shows an example of this type of layout
41. nel family shows no phase reversal under overdrive Separation vs Frequency MCP6022 and MCP6024 only TE 2006 Microchip Technology Inc DS21685C page 9 MCP6021 1R 2 3 4 Note Unless otherwise indicated Ta 25 Vpp 2 5V to 5 5V Vss GND Vow Vpp 2 Vout 2 RL 10 kQ to Vpp 2 and C 60 pF 1 000 10 os 9 Vor Vss 8t EU EE 88 mum 8 5 100 2 6 SS 2 5 Vpp 9 50 4 gt 6 10 Vor Vss 28 3 52 57 8 8 2 6 x Vpp 8 gt 1 1 Am 0 0 01 0 1 1 10 50 25 0 25 50 75 100 125 Output Current Magnitude mA Ambient Temperature C FIGURE 2 31 Output Voltage Headroom FIGURE 2 34 Output Voltage Headroom vs Output Current vs Temperature G 1 G 1 V V 1 Z 5 5 jE 18 2 g gt gt dm imn E a 5
42. o the PMOS input differential pairs This change in Vog will increase the distortion if the input voltage includes this transition region This transition occurs between Vpp 1 0V and Vip 2 0V depending on Vpp and temperature 4 2 Rail to Rail Output The Maximum Output Voltage Swing is the maximum swing possible under a particular output load According to the specification table the output can reach within 20 mV of either supply rail when RL 10 See Figure 2 31 and Figure 2 34 for more information concerning typical performance 4 3 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps As the load capacitance increases the feedback loop s phase margin decreases and the closed loop bandwidth is reduced This produces gain peaking in the frequency response with overshoot and ringing in the step response When driving large capacitive loads with these op amps e g gt 60pF when G 1 a small series resistor at the output Riso in Figure 4 2 improves the feedback loop s phase margin stability by making the load resistive at higher frequencies The bandwidth will be generally lower than the bandwidth with no capacitive load Vin O4 Riso MCP602X CL FIGURE 4 2 Output resistor Rigo stabilizes large capacitive loads Figure 4 3 gives recommended Riso values for different capacitive loads and gains The x axis is the no
43. rmalized load capacitance C Gy where Gy is the circuit s noise gain For non inverting gains Gy and the Signal Gain are equal For inverting gains Gy is 1 Signal Gain e g 1 V V gives Gy 2 V V 1 000 F Gn gt 1 S 8 4 5 10 10 10 100 1 000 10 000 Normalized Capacitance C Gy pF FIGURE 4 3 Recommended Rigo values for capacitive loads 2006 Microchip Technology Inc DS21685C page 13 MCP6021 1R 2 3 4 After selecting Riso for your circuit double check the resulting frequency response peaking and step response overshoot Modify Risos value until the response is reasonable Evaluation on the bench and simulations with the MCP6021 1R 2 3 4 Spice macro model are helpful 4 4 Gain Peaking Figure 2 35 and Figure 2 36 use Re 1 to avoid frequency response gain peaking and step response overshoot The capacitance to ground at the inverting input Cg is the op amp s common mode input capacitance plus board parasitic capacitance Ca is in parallel with which causes an increase gain at high frequencies for non inverting gains greater than 1 V V unity gain Cg also reduces the phase margin of the feedback loop for both non inverting and inverting gains Vin O Vout
44. s E Temp 438 Samples Parts Vem OV TA 40 C to 125 1 T T T T T e N N e e A s 1 r qA Input Offset Voltage Drift uV C FIGURE 2 2 Input Offset Voltage Extended Temperature Parts 500 400 2 5V Input Offset Voltage m 4 KI NN 300 400 05 0 0 0 5 10 1 5 20 2 5 3 0 Common Mode Input Voltage V FIGURE 2 3 Input Offset Voltage vs Common Mode Input Voltage with 2 5V FIGURE 2 5 Input Offset Voltage Drift Extended Temperature Parts 500 40 C d Dra 425 C gt 200 0 100 1 gt 0 F 2 100 200 5 300 TU 400 500 O 1 o Q QN M c st st D 0 Common Mode Input Voltage V FIGURE 2 6 Input Offset Voltage vs Common Mode Input Voltage with 5 5V 2006 Microchip Technology Inc DS21685C page 5 MCP6021 1R 2 3 4 Note Unless otherwise indicated Ta 25 Vpp 2 5V to 5 5V Vss GND Vem Vpp 2 Vout Vpn 2 RL 10 kQ to Vpp 2 and C
45. s designed to not exhibit phase inversion when the input pins exceed the supply voltages Figure 2 27 shows an input volt age exceeding both supplies with no resulting phase inversion The input stage of the MCP6021 1R 2 3 4 family of devices uses two differential input stages in parallel one operates at low common mode input voltage Vcm while the other operates at high Vem With this topology the device operates with up to 0 3V past either supply rail Vgg 0 3V to Vpp 0 3V at 25 C The amplifier input behaves linearly as long as Voy is kept within the specified Vomp limits The input offset voltage is measured at both Vss 0 3V and Vpp 0 3V to ensure proper operation Input voltages that exceed the input voltage range VcmR can cause excessive current to flow in or out of the input pins Current beyond 2 mA introduces possible reliability problems Thus applications that exceed this rating must externally limit the input current with an input resistor Rin as shown in Figure 4 1 2X RIN MCP60 Vout Vin OA Maximum expected Vin Vpp An gt 2 mA Vss Minimum expected 2 Fin 2 2mA FIGURE 4 1 limits the current flow into an input pin Total Harmonic Distortion Plus Noise THD N can be affected by the common mode input voltage Voy As shown in Figure 2 3 and Figure 2 6 the input offset voltage Vog is affected by the change from the NMOS t
46. ve filter using op amps design It is available free of charge from our web site at www microchip com The FilterLab software tool provides full schematic diagrams of the filter circuit with component values It also outputs the filter circuit in SPICE format which can be used with the macro model to simulate actual filter performance 2006 Microchip Technology Inc DS21685C page 17 MCP6021 1R 2 3 4 6 0 PACKAGING INFORMATION 6 1 Package Marking Information 5 Lead SOT 23 MCP6021 MCP6021R Example E temp Device E Temp Code MCP6021 EYNN XXNN HY25 MCP6021R EZNN Note Applies to 5 Lead SOT 23 8 Lead PDIP 300 mil Example EE EE 1 ELI T EI XXXXXXXX MCP6021 MCP6021 XXXXXNNN I P256 OR E Pe3256 VYWW 0331 0549 0 LI LILI LI LT LJ LILI LT LJ LILI 8 Lead SOIC 150 mil Example XXXXXXXX MCP6021 MCP6021E XXXXYYWW I SN0331 OR SN 3 0549 o Su o M256 o D256 8 Lead MSOP Example 8 Lead TSSOP
47. ved LA Printed on recycled paper Microchip received ISO TS 16949 2002 quality system certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona and Mountain View California in October 2003 The Company s quality system processes and procedures are for its PICmicro 8 bit MCUs KEELOG code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchip s quality system for the design and manufacture of development systems is ISO 9001 2000 certified 2006 Microchip Technology Inc DS21685C page 33 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480 792 7277 Technical Support http support microchip com Web Address www microchip com Atlanta Alpharetta GA Tel 770 640 0034 Fax 770 640 0307 Boston Westborough MA Tel 774 760 0087 Fax 774 760 0088 Chicago Itasca IL Tel 630 285 0071 Fax 630 285 0075 Dallas Addison TX Tel 972 818 7423 Fax 972 818 2924 Detroit Farmington Hills MI Tel 248 538 2250 Fax 248 538 2260 Kokomo Kokomo IN Tel 765 864 8360 Fax 765 864 8387 Los Angeles Mission Viejo CA Tel 949 462 9523 Fax 949 462 9608 San Jose Mountain View CA Tel 650 215 1444 Fax 650 961 0286 Toronto Mississauga Ontario Canada Tel 905 673 0699 Fax 905 6

MICROCHIP MCP6021/1R/2/3/4 Data Sheet

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