TEXAS INSTRUMENTS TLV5604 2.7-V TO 5.5-V 10-BIT 3- S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN handbook
Contents
1. SUPPLY CURRENT SUPPLY CURRENT vs vs TEMPERATURE TEMPERATURE 4 Vpp 3V VREF 1 024 V 3 5F Vo Full Scale Fast Mode 3 E 2 5 2 zm 2 a 2 Ki Slow Mode 1 5 a 2 Slow Mode 1 0 5 40 20 0 20 40 60 80 100 40 20 0 20 40 60 80 100 T Temperature C T Temperature C Figure 6 Figure 7 TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION vs vs FREQUENCY FREQUENCY Vref 1 V dc 1 V p p Sinewave Output Full Scale Vref 1 V dc 1 V p p Sinewave Output Full Scale THD Total Harmonic Distortion dB 0 5 10 20 30 50 100 0 5 10 20 30 50 100 f Frequency kHz f Frequency kHz Figure 8 Figure 9 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 9 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION AND NOISE TOTAL HARMONIC DISTORTION AND NOISE VS VS FREQUENCY FREQUENCY Vref 1 V dc 1 V p p Sinewave Output Full Scale Vref 1 V dc 1 V p p Sinewave Output Full Scale Slow Mode THD Total Harmonic Distortion And Noise dB THD Total Harmonic Distortion And Noise dB2. 0 5 10 20 30 50 100 f Frequency kHz f Frequency kHz Figure 10 Figure 11 SUPPLY CURRENT vs TIME WHEN ENTERING POWER DOWN MODE 4000 3500 3000 2500 2000 5 1500 a 1000 500 0 0 200 400 600 800 1000 t Time ns Figure 12 35 TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 INL Integral Nonlinearity LSB DNL Differential Nonlinearity LSB TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY 0 2 Vpp 5 V Vref 2 V CLK 1 MHz 0 0 2 0 4 0 6 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 Digital Code Figure 13 DIFFERENTIAL NONLINEARITY DD 5 Vref 2 V LK 1 MHz 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 Digital Code Figure 14 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 11 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 APPLICATION INFORMATION general function The TLV5604 is a 10 bit single supply DAC based on a resistor string architecture The devi
3. 35 TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 electrical characteristics over recommended operating free air temperature range unless otherwise noted continued digital input timing requirements IN NoM MAX uwr 165 5 Setup time CS low before FSU tsu FS CK Setup time FS low before first negative SCLK edge ns t Setup time sixteenth negative SCLK edge after FS low on which bit DO is sampled before 10 Su C16 FS rising edge of FS S Setup time The first positive SCLK edge after DO is sampled before CS rising edge If FS tsu C16 CS isusedinstead of the SCLK positive edge to update the DAC then the setup time is between 10 the FS rising edge and CS rising edge twH Pulse duration SCLK high twL Pulse duration SCLK low tsu D Setup time data ready before SCLK falling edge 8 thiD Hold time data held valid after SCLK falling edge twH FS Pulse duration FS high PARAMETER MEASUREMENT INFORMATION SCLK DIN 4 9 tsu FS CK tsu C16 CS 4 lt gt tsu cs Fs cs 4 9 twH FS tsucie FS 0 9 FS Figure 1 Timing Diagram 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO
4. all else fails stop here hang there 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 17 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 APPLICATION INFORMATION Interrupt Service Routines intl ret int23 ret timer_isr do nothing and return do nothing and return iosr stat IOSR store IOSR value into variable space load acc with iosr status reset IOl LDAC low set IOl LDAC high reset IOO CS low load rolling pointer to accumulator add pointer to table start to get a pointer for next DAC a sample add 8 to get to DAC C pointer add 8 to get to DAC B pointer add 8 to get to DAC D pointer set arO as current AR DACa ptr points to DAC a sample get DAC a sample into accumulator DACa_control OR in DAC A control bits in lacl iosr_stat and OFFFDh sacl temp i out temp IOSR or 0002h sacl temp out temp IOSR d and OFFFEh sacl temp s out temp IOSR lacl r ptr add sinevals sacl DACa ptr add 08h sacl DACc ptr add 08h sacl DACb ptr add 08h sacl DACd ptr mar ar0 DAC A lar lacl or sacl temp out temp SDTR Send data We must wait for transmission to complete before writing next word to the SDTR TLV
5. ds 02000h sinevals word 00800h word 0097Ch word 00AE9h word 00C3Ah 00D61h word 00E53h 00F07h word OOF76h word 00F9Ch OOF76h 00F07h word 00E53h word 00D61h 00C3Ah 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 15 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 APPLICATION INFORMATION word 00517 word 00684 word OOAE9h word 0097Ch word 00800h word 00684h 00517h word 003C6h word 0029Fh word 001ADh word 000F9h word 0008Ah word 00064h word 0008Ah word 000F9h word 001ADh word 0029Fh word 003C6h word 00517h word 00684h word 00800h word 0097Ch word OOAE9h word 00C3Ah word O0D61h word 00E53h word 00F07h word 00F76h word OOF9Ch word 00F76h word 00F07h word 00E53h word O0D61h 00C3Ah word OO0AE9h word 0097Ch word 00800h word 00684h word 00517h word 003C6h word 0029Fh word 001ADh word 000F9h word 0008Ah 00064h word 0008Ah word 000F9h word 001ADh word 0029Fh 003C6h h h i Main Program OS ee i a n ps 1000h entry start disable interrupts p C P setc INTM disable maskable interrupts Splk O0ffffh IFR clear all interrupts splk 0004h IMR timer interrupts
6. 31 then wrap back round store rolling pointer wait long enough for this configuration of MCLK CLKOUT1 rate load acc with iosr status set I00 CS high re enable interrupts return from interrupt 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 19 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 APPLICATION INFORMATION TLV5604 interfaced to MCS951 microcontroller hardware interfacing Figure 18 shows an example of how to connect the TLV5604 to an MCS951 Microcontroller The serial DAC input data and external control signals are sent via I O Port 3 of the controller The serial data is sent on the RxD line with the serial clock output on the TxD line Port 3 bits 3 4 and 5 are configured as outputs to provide the DAC latch update LDAC chip select CS and frame sync FS signals for the TLV5604 The active low power down pin PD of the TLV5604 is pulled high to ensure that the DACs are enabled MCS 51 TLV5604 VOUTA VOUTB VOUTC VOUTD Vss Figure 18 TLV5604 Interfaced with MCS951 software The example is the same as for the TMS320C203 in this datasheet but adapted for a MCS 51 controller It generates a differential in phase sine signal between the VOUTA and VOUTB pins and it s quadrature cosine signal as the differential signal betveen VOUTC and VOUTD The on chip timer is
7. MAX A MIN 4040047 D 10 96 NOTES A All linear dimensions in inches millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 006 0 15 Falls within JEDEC MS 012 com 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 25 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 MECHANICAL DATA PW R PDSO G PLASTIC SMALL OUTLINE PACKAGE 14 PIN SHOWN 0 15 NOM eere ime Seating Plane ma 20 MAX 8 15 0 10 4040064 08 96 NOTES All linear dimensions in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 15 Falls within JEDEC MO 153 35 TEXAS INSTRUMENTS 26 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product
8. TEVOGOAN usui tre Eh eee 40 C to 85 C Storage temperature range Tstg ose rs bb Datus bao eb Kesh dg wnt 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C t Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 recommended operating conditions Nox uni 5 V supply 4 5 5 5 5 Supply voltage AVpp DVpp SV sup 34 V High level digital input voltage VIH DV DD a Low level digital input voltage VIL DY DD L 3 5 V supply see Note 1 2 048 AVpp 1 5 Reference voltage Vref to REFINAB REFINCD terminal 3 V supply see Note 1 0 1 004 AVpp 1 5 Operating free air temperature NOTE 1 Voltages greater than AVpp 2 will cause output saturation for large DAC codes electrical characteristics over recommended operating free air temperature range unless otherwise noted static DA
9. a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated product or service and is an unfair and deceptive business practice is not responsible or liable for any such statements Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2002 Texas Instruments Incorporated
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11. periods of a sine function A rolling pointer is used to address the table location in the first period of this waveform from which the DAC A samples are read The samples for the other 3 DACs are read at an offset to this rolling pointer DAC Function Offset from rolling pointer A sine 0 B inverse sine 16 cosine 8 D inverse cosine 24 The on chip timer is used to generate interrupts at a fixed rate The interrupt service routine first pulses LDAC low to update all DACs simultaneously with the values which were written to them in the previous interrupt Then all 4 DAC values are fetched and written out through the synchronous serial interface Finally the rolling pointer is incremented to address the next sample ready for the next interrupt 1998 Texas Instruments Incorporated I O and memory mapped regs TSE GaP TP A we SS include regs asm jump vectors ps Oh b start b intl b int23 b timer_isr E variables temp equ 0060h ripen equ 0061 iosr stat equ 0062h DACa ptr 0063h DACb_ptr equ 0064h DACc_ptr equ 0065h DACd_ptr equ 0066h poe ae poe CONS aS ys apy TV tg ge ee Rs ee Se PF a DAC control bits to be OR ed onto data all fast mode DACa control equ 01000h DACb control equ 05000h DACc_control equ 09000h DACd control equ 0d000h F tables H I STS
12. used to generate interrupts at a fixed frequency The related interrupt service routine pulses LDAC low to update all 4 DACs simultaneously then fetches and writes the next sample to all 4 DACs The samples are stored as a look up table which describes one full period of a sine wave The serial port of the controller is used in Mode 0 which transmits 8 bits of data on RxD accompanied by a synchronous clock on TxD Two writes concatenated together are required to write a complete word to the TLV5604 The CS and FS signals are provided in the required fashion through control of IO port 3 which has bit addressable outputs MCS is a registered trademark of Intel Corporation 20 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 APPLICATION INFORMATION Processor 80C51 Description This program generates a differential in phase sine on OUTA OUTB and it s quadrature cosine as a differential signal on OUTC OUTD 1998 Texas Instruments Incorporated Sm EAM A a ee Lai mr Cl ee a NAME GENIQ MAIN SEGMEN CODE ISR SEGMEN CODE SINTBL SEGMEN CODE VAR1 SEGMEN DATA STACK SEGMEN IDATA c UAM Code start at address 0 jump to start dp cu MD MEME M EU
13. 5604 interface does not allow the use of burst mode with the full packet rate as we need a CLKX ve edge to clock in last bit before FS goes high again to allow SPI compatibility rpt nop 016h DAC B lar lacl or sacl out rpt nop 18 wait long enough for this configuration of MCLK CLKOUT1 rate DACb ptr points to DAC a sample get DAC a sample into accumulator DACb_control OR in DAC B control bits temp temp SDTR 016h Send data wait long enough for this configuration of MCLK CLKOUT1 rate 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 sacl sacl nop now take CS lacl or sacl out clrc ret end APPLICATION INFORMATION DACc_ptr DACc_control temp temp 016h SDTR DACd ptr get DAC a sample into accumulator temp temp r ptr 1h 001Fh r ptr 016h SDTR high again iosr stat 0001h temp temp intm IOSR DACd control ar0 points to DAC a sample get DAC a sample into accumulator OR in DAC C control bits send data wait long enough for this configuration of MCLK CLKOUT1 rate ar0 points to DAC a sample OR in DAC D control bits send data load rolling pointer to accumulator increment rolling pointer count 0
14. 604 has to be considered also data format The 16 bit data word for the TLV5604 consists of two parts Control bits D15 D12 New DAC value D11 D0 14 D13 D12 Dit Dio p9 pe p7 pe ps o4 D2 D DO X don t care SPD Speed control bit 1 fast mode 0 gt slow mode PWR Power control bit 1 power down 0 normal operation 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 13 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 APPLICATION INFORMATION In power down mode all amplifiers within the TLV5604 are disabled A particular DAC A B C D of the TLV5604 is selected by A1 and AO within the input word TLV5604 interfaced to TMS320C203 DSP Hardware interfacing Figure 17 shows an example of how to connect the TLV5604 to a TMS320C203 DSP The serial port is configured in burst mode with FSX generated by the TMS320C203 to provide the Frame Sync FS input to the TLV5604 Data is transmitted on the DX line with the serial clock input on the CLKX line The general purpose input output port bits IOO and IO1 are used to generate the Chip Select CS and DAC Latch Update LDAC inputs to the TLV5604 The active low Power Down PD is pulled high all the time to ensure the DACs are enabled TMS320C203 TLV5604 VOUTA VOUTB VOUTC VOUTD
15. ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 am a AS TYPICAL CHARACTERISTICS LOAD REGULATION LOAD REGULATION 0 35 0 20 Vpp 5 Vpp 3 VREF 2 V 0 18 VREF 1 V 0 30 Full Scale Vo Full Scale 0 16 gt 0 25 gt 0 14 5 V Slow Mode Sink M 3 V Slow Mode Sink o S 0 12 2 020 E gt 5 V Fast Mode Sink t 0 10 2 2 3 V Fast Mode Sink 2 015 5 008 l 1 0 10 0 06 0 04 0 05 0 02 0 0 0 02 0 04 01 02 04 08 1 2 4 0 0 01 0 02 0 05 0 1 0 2 05 0 8 1 Load Current Load Current mA Figure 2 Figure 3 LOAD REGULATION LOAD REGULATION 4 002 4 00 3 998 3 V Fast gt gt 3 996 l S 9 5 3 994 5 2 5 amp 3 992 3 99 DS DS 3 988 5 V 3 986 VREF 2 V Vo Full Scale Scale 3 984 0 0 02 0 04 01 02 04 08 1 2 4 0 0 01 0 02 0 05 0 1 0 2 05 08 1 Load Current mA Load Current mA Figure 4 Figure 5 EXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 Ipp Supply Current mA THD Total Harmonic Distortion dB TLV5604 2 7 V TO 5 5 V 10 BIT 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 TYPICAL CHARACTERISTICS
16. C C DAC B next DAC B codes should be taken from 16 bytes 8 samples further on in the sine tabl this gives an inverted sine function MOV A R7 pointer in R7 ADD A 0FH add 15 already done one INC ANL A 03FH wrap back round to 0 if gt 64 MOV R7 A pointer back in R7 Ne Ne Ne Ne MOVC A DPTR get DAC B msb from the table ORL 02H Set control bits to DAC B address C LSB TX JNB TI C LSB TX wait for DAC C 15 transmit to complete SETB 1 toggle FS CLR T1 CLR TI Clear for new transmit MOV SBUF A and send out the msb of DAC B get DAC B LSB INC R7 increment the pointer in R7 MOV A R7 to get the next byte from the table MOVC A DPTR which is the lsb of this sample now in ACC B MSB TX JNB TI B MSB TX wait for transmit to complete CLR TI Clear for new transmit MOV SBUF A and send out the lsb of DAC B 35 TEXAS INSTRUMENTS 22 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 DAC D next DAC D codes should be taken from 16 bytes APPLICATION INFORMATION add 15 already done one INC wrap back round to 0 if gt 64 get DAC D msb from the table set control bits to DAC D address 8 samples wait for DAC lsb transmit to complete and send out the msb of DAC D increment the poin
17. C specifications Integral nonlinearity INL end point adjusted LSB Differential nonlinearity DNL LSB 75 Zero scale error offset error at zero scale Zero scale error temperature coefficient TS Gain error temperature coefficient See Note 7 PSRR Power supply rejection ratio See Notes 8 and 9 ain NOTES 2 Therelative accuracy or integral nonlinearity INL sometimes referred to as linearity error is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors 3 The differential nonlinearity DNL sometimes referred to as differential error is the difference between the measured and ideal 1LSB amplitude change of any two adjacent codes Monotonic means the output voltage changes in the same direction or remains constant as a change in the digital input code Zero scale error is the deviation from zero voltage output when the digital input code is zero Zero scale error temperature coefficient is given by Ezs TC 75 Tmax EZS Tmin l Vret x 108 Tmax Tmin Gain error is the deviation from the ideal output 2Vrer 1 LSB with an output load of 10 excluding the effects of the zero error Gain temperature coefficient is given by EG EG Tmax EG Tmin l Vret 108 Tmax Tmin Zero scale error rejection ratio EZS RR is measured by varying the AVpp from 5 0 5 V and 3 0 3 V and measuring the proportion of this
18. DSP XFO XF1 FSX DX CLKX e Figure 15 TMS320 Interface 35 TEXAS INSTRUMENTS 12 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 APPLICATION INFORMATION serial interface continued If there is no need to have more than one device on the serial bus then CS can be tied low Figure 16 shows an example of how to connect the TLV5604 to a TMS320 SPI or Microwire port using only three pins TMS320 TLV5604 TLV5604 DSP FSX DX Microwire TLV5604 1 0 SO CLKX SK Figure 16 Three Wire Interface Notes on SPI and Microwire Before the controller starts the data transfer the software has to generate a falling edge on the I O pin connected to FS If the word width is 8 bits SPI and Microwire two write operations must be performed to program the TLV5604 After the write operation s the DAC output is updated automatically on the next positive clock edge following the sixteenth falling clock edge serial clock frequency and update rate The maximum serial clock frequency is given by 1 20 MHz SCLKmax twH min The maximum update rate is 1 1 25 MHz Hein tutem UPDATEmax Note that the maximum update rate is a theoretical value for the serial interface since the settling time of the TLV5
19. MM CSEG AT 0 LUMP start Execution starts at address 0 on power up poe ee ee EE MEM Code in the timerO interrupt vector pac lecce ete e M ic Re cose eM See CSEG AT OBH LUMP timerOisr Jump vector for timer 0 interrupt is 000Bh Global variables need space allocated Temp ptr RSEG VARI DS 1 DS 1 rolling ptr Interrupt service routine for timer 0 interrupts RSEG ISR timer Oisr PUSH PSW PUSH ACC CLR INTL SETB INT1 CLR TO H cycle lsb pairs 64 bytes rolling ptr z DAC Function Offset from P A sine 0 B inverse sine C cosine sD inverse cosine MOV DPTR Sinevals MOV R7 rolling ptr MOV A R7 MOVC A A DPTR CLR T MOV SBUF A INC R7 MOV R7 A A DPTR POST OFFICE 655303 DALLAS TEXAS 75265 incrementing by 2 bytes this routine pulse LDAC low to latch all 4 previous values at the same time 1st thing done in timer isr gt fixed period set CS low The signal to be output on each DAC is a sine function of a sine wave is held in a table sinevals as 32 samples of msb We have one pointer which rolls round this table 1 sample on each interrupt at the end of The DAC samples are read at an offset to this rolling pointer rolling ptr set DPTR to the start of the table of sine signal valu
20. ND Each supply is independent of the other and can be any value between 2 7 V and 5 5 V The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3 V supply also used on pins DVpp and DGND with the DACs operating on a 5 V supply Of course the digital and analog supplies can be tied together Theresistor string output voltage is buffered by a x2 gain rail to rail output buffer The buffer features a Class AB output stage to improve stability and reduce settling time A rail to rail output stage and a power down mode makes it ideal for single voltage battery based applications The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation The settling time is chosen by the control bits within the 16 bit serial input string A high impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal REFINAB and REFINCD allow DACs A and B to have a different reference voltage then DACs C and D The device implemented with a CMOS process is available in 16 terminal SOIC and TSSOP packages The TLV5604C is characterized for operation from 0 C to 70 C The TLV5604l is characterized for operation from 40 C to 85 Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor prod
21. TACK 1 CLR A MOV SCON A MOV TMOD 02H MOV THO 038H SETB INTL SETB 1 SETB 0 SETB ETO SETB EA MOV rolling ptr A SETB TRO always JMP always RET first set Stack Pointer set serial port 0 to mode 0 set timer 0 to mode 2 auto reload set THO for 5 kHs interrupts set LDAC 1 Set FS set CS H HP enable timer 0 interrupts enable all interrupts set rolling pointer to O0 start timer O0 while 1 Table of 32 sine wave samples used as DAC data RS sinevals DW DW END EG SINTBL 01000H 0903EH 05097H 0305CH e UJ e I 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 MECHANICAL DATA D R PDSO G PLASTIC SMALL OUTLINE PACKAGE 14 PIN SHOWN 0 050 1 27 0 020 0 51 P s 0 014 0 35 0 010 0 25 8 0 008 0 20 0 244 6 20 0 228 5 80 0 157 4 00 0 150 3 81 0 010 0 25 7 0 044 1 12 0 016 0 40 l pes Plane Y 1 HEHHEHHB E omy Sh 069 1 75 MAX 0 004 0 10 0 004 0 PINS DIM A
22. TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 Four 10 Bit D A Converters Hardware Power Down 10 nA Programmable Settling Time Software Power Down 10 nA of 3 us or 9 us Typ Simultaneous Update TMS320 Q SPI and Microwire Compatible Serial Interface applications Internal Power On Reset Battery Powered Test Instruments Low Power Consumption Digital Offset and Gain Adjustment RE aA ae a M 2 zu e Industrial Process Controls Reference Input Buffers Machine ane Control Devices Voltage Output Range 2 the Reference gt sotmmunicanons Input Voltage Arbitrary Waveform Generation Monotonic Over Temperature D OR PW PACKAGE Dual 2 7 V to 5 5 V Supply Separate Digital TOP VIEW and Analog Supplies description The TLV5604 is a quadruple 10 bit voltage output digital to analog converter DAC with a flexible 4 wire serial interface The 4 wire serial interface allows glueless interface to TMS320 SPI QSPI and Microwire serial ports The TLV5604 is programmed with a 16 bit serial word comprised of a DAC address individual DAC control bits and a 10 bit DAC value The device has provision for two supplies one digital supply for the serial interface via pins DVpp and DGND and one for the DACs reference buffers and output buffers via pins AVpp and AG
23. Vss Figure 17 TLV5604 Interfaced with TMS320C203 Software The application example generates a differential in phase sine signal between the VOUTA and VOUTB pins and it is quadrature cosine signal as the differential signal between VOUTC and VOUTD The on chip timer is usedto generate interrupts at a fixed frequency The related interrupt service routine pulses LDAC low to update all 4 DACs simultaneously then fetches and writes the next sample to all 4 DACs The samples are stored in a look up table which describes two full periods of a sine wave The synchronous serial port of the DSP is used in burst mode In this mode the processor generates an FS pulse preceding the MSB of every data word If multiple contiguous words are transmitted a violation of the tsu C16 FS timing requirement will occur To avoid this the program waits until the transmission of the previous word has been completed 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 APPLICATION INFORMATION Processor TMS320C203 runnning at 40 MHz Description This program generates a differential in phase sine on OUTA OUTB and it s quadrature cosine as a differential signal on OUTC OUTD The DAC codes for the signal samples are stored as a table of 64 12 bit values describing 2
24. ce consists of aserial interface speed and power down control logic a reference input buffer a resistor string and a rail to rail output buffer The output voltage full scale determined by external reference is given by 2 REF SORE IV Where REF is the reference voltage and CODE is the digital input value within the range of 049 to 2 1 where n 10 bits The 16 bit data word consisting of control bits and the new DAC value is illustrated in the data format section A power on reset initially resets the internal latches to a defined state all bits zero serial interface Explanation of data transfer First the device has to be enabled with CS set to low Then a falling edge of FS starts shifting the data bit per bit starting with the MSB to the internal register on the falling edges of SCLK After 16 bits have been transferred or FS rises the content of the shift register is moved to the DAC latch which updates the voltage output to the new level The serial interface of the TLV5604 can be used in two basic modes Four wire with chip select Three wire without chip select Using chip select four wire mode it is possible to have more than one device connected to the serial port of the data source DSP or microcontroller The interface is compatible with the TMS320 family Figure 15 shows an example with two TLV5604s connected directly to a TMS320 DSP TLV5604 TLV5604 CS FS DIN SCLK CS FS DIN SCLK TMS320
25. es R7 holds the pointer into the sine table get DAC A msb msb of DAC A is in the ACC transmit it set FS low send it out the serial port increment the pointer in R7 to get the next byte from the table which is the lsb of this sample now in ACC 5 TEXAS INSTRUMENTS 21 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 APPLICATION INFORMATION A MSB TX JNB TI A MSB TX wait for transmit to complete CLR Clear for new transmit MOV SBUF A and send out the lsb of DAC A DAC C next DAC C codes should be taken from 16 bytes 8 samples further on in the sine table this gives a cosine function MOV A R7 pointer in R7 ADD A 0FH add 15 already done one INC ANL A 03FH wrap back round to 0 if gt 64 MOV R7 A pointer back in R7 MOVC A A DPTR get DAC C msb from the table ORL A 01H Set control bits to DAC C address A LSB TX JNB TI A LSB TX wait for DAC 15 transmit to complete SETB 1 toggle FS CLR T1 CLR TI clear for new transmit MOV SBUF A and send out the msb of DAC C INC R7 increment the pointer in R7 MOV A R7 to get the next byte from the table MOVC A A DPTR which is the 15 of this sample now in ACC C MSB JNB TI C MSB TX wait for transmit to complete CLR TI clear for new transmit MOV SBUF A and send out the lsb of DA
26. o DESCRIPTION NAME NO of favo 16 massey S S ES s pi eese nemen O poo ef pw a 1 Serai mampt 1 a e Frame sync input The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out to the TLV5604 Power down pin Powers down all DACs overriding their individual power down settings and all output stages This terminal is active low Load DAC When the LDAC signal is high no DAC output updates occur when the input digital data is read into the serial interface The DAC outputs are only updated when LDAC is low REFINAB 15 Votagereterence puttorDAOeAandB O O O O 310 i VotamerweremeewputtorDAOsCandD pum 4 oum OUTC 12 DACC output OUTD 11 o DACD output absolute maximum ratings over operating free air temperature range unless otherwise noted t Supply voltage DVpp AVpp to GND sssusssssssssssee Rh 7M Supply voltage difference AVpp to DVpp 0 0 00 2 8 V to 2 8 V Digital input voltage range erae IRR 0 3 V to DVpp 0 3 V Reference input voltage range 0 3 V to AVpp 0 3 V Operating free air temperature range Ta TLV5604C 0 C to 70 C
27. pply current See Figure 12 10 i 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 electrical characteristics over recommended operating free air temperature range unless otherwise noted continued analog output dynamic performance PARAMETER TEST CONDITIONS UNIT 100 10 Output slew rate Vo 10 to 90 Vref 2 048 V 1024 V NEN To 0 5 LSB 100 pF ts Output settling time RL 10kQ See Notes 12 and 14 To 0 5 LSB C 100 pF Output settling time code to code 10 See Note 13 Signal to noise ratio Sinewave generated by DAC Reference voltage 1 024 at 3 V and 2 048 at 5 V S N D Signal to noise distortion fs 400 KSPS Total harmonic Distortion fouT 1 1 kHz sinewave C 100 pF RL 10 ko SFDR Spurious free dynamic range BW 20 kHz NOTES 12 Settling time is the time for the output signal to remain within 0 5LSB of the final measured value for a digital input code change of 020 hex to 3FF hex or 3FF hex to 020 hex 13 Settling time is the time for the output signal to remain within 0 5LSB of the final measured value for a digital input code change of one count 1FF hex to 200 hex 14 Limits are ensured by design and characterization but are not production tested
28. signal imposed on the zero code output voltage 9 Gain error rejection ratio EG RR is measured by varying the AVpp from 5 0 5 V and 3 0 3 V dc and measuring the proportion of this signal imposed on the full scale output voltage after subtracting the zero scale change ppm C CON dix 35 TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 electrical characteristics over recommended operating free air temperature range unless otherwise noted continued individual DAC output specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vo Voltage output RL 10 0 AVpp 0 4 Output load regulation accuracy RL 2 vs 10 0 1 0 25 S rs voltage reference input REFINAB REFINCD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT C Input capacitance REFIN 1 Vpp at 1 kHz 1 024 V dc pp Reference feed through see Note 11 Reference input bandwidth REFIN 0 2 Vpp 1 024 V dc NOTES 10 Reference input voltages greater than Vpp 2 will cause output saturation for large DAC codes 11 Reference feedthrough is measured at the DAC output with an input code 000 hex and a Vref REFINAB or REFINCD input 1 024 1 Vpp at 1 kHz digital inputs 00 011 CS WEB LDAC PD IDD Power supply current m Power down su
29. ter in R7 to get the next byte from the table which is the lsb of this sample wait for transmit to complete this gives an inverted cosine function MOV A R7 pointer in R7 ADD 0FH ANL A 03FH H MOV R7 A pointer back in R7 MOVC A A DPTR ORL A 03H B LSB TX JNB TI B LSB TX SETB 1 toggle FS CLR TL CLR TE clear for new transmit MOV SBUF A INC R7 MOV A R7 MOVC A A DPTR D MSB TX JNB TI D MSB TX CLR TI Clear for new transmit MOV SBUF A increment the rolling pointer to point to the next sample and send out the lsb of DAC D ready for the next interrupt MOV A rolling ptr ADD A 02H ANL A 03FH MOV rolling ptr A D LSB TX JNBTI D LSB TX CLR der SETB 1 SETB 0 POP ACC POP PSW RETI add 2 to the rolling pointer wrap back round to 0 if gt 64 store in memory again now in ACC wait for DAC D lsb transmit to complete clear for next transmit FS high CS high further on in the sine table Stack needs definition RSI DS EG STACK 10h 16 Byte Stack 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 23 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 24 APPLICATION INFORMATION Main program code RSEG MAIN start MOV SP S
30. ucts and disclaimers thereto appears at the end of this data sheet SPI and QSPI are trademarks of Motorola Inc Microwire is a trademark of National Semiconductor Corporation PRODUCTION DATA information is current as of publication date Copyright 2002 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments Jj standard warranty Production processing does not necessarily include testing of all parameters EXAS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 AVAILABLE OPTIONS TA SOIC TSSOP D PW 0 C to 70 C TLV5604CD TLV5604CPW 40 C to 85 C TLV5604ID TLV5604IPW functional block diagram REFINAB 15 Power On Reset Serial 14 44 Bit DIN Input Data Register and Contro 2 2 Bit 2 Register Control 2 pala Power Down 7 Latch Speed Control FS peed Contro 5 Select pce m ye 2 SCLK Control aa _ 6 Logi Y CS gic ae AGND DGND LDAC Uv 35 TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 Terminal Functions TERMINAL y
31. unmasked 35 TEXAS INSTRUMENTS 16 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV5604 2 7 V TO 5 5 V 10 3 uS QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS176B DECEMBER 1997 REVISED JULY 2002 APPLICATION INFORMATION set up the timer period CLKOUT1 period Ne Ne Ne Ne Ne Ne Ne Ne Ne timer period set by values in PRD and TDDR X 1 PRD X 1 TDDR examples for TMS320C203 with 40 MHz main clock Timer rate TDDR PRD 80 kHz 9 24 18h 50 kHz 9 39 27h prd_val equ 0018h tcr val equ 0029h Splk 0000h temp out temp TIM splk prd_val temp out temp PRD splk tcr_val temp out temp TCR clear timer set PRD set TDDR and TRB 1 for auto reload SSPCR FSM 1 Burst mode Configure IO0 1 as outputs to be 100 CS and set high 101 LDAC and set high in temp ASPCR configure as output lacl temp or 0003h sacl temp out temp ASPCR in temp IOSR set them high lacl temp or 0003h sacl temp out temp IOSR set up serial port for SSPCR TXM 1 Transmit mode generate FSX SSPCR MCM 1 Clock mode internal clock source f Splk 0000Eh temp out temp SSPCR splk 0002Eh temp out temp SSPCR reset transmitter reset the rolling pointer lacl 000h sacl r_ptr enable interrupts erre INTM enable maskable interrupts loop forever ext idle wait b next for interrupt
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TEXAS INSTRUMENTS TLV5604 2.7 V TO 5.5 V 10 BIT 3 S QUADRUPLE DIGITAL TO ANALOG CONVERTERS WITH POW