TEXAS INSTRUMENTS TLV2606 DATA SHEET
Contents
1. TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 features Buffered High Impedance Reference Input 10 Bit Voltage Output DAC Voltage Output Range 2 Times the Programmable Settling Time vs Power Input Voltage Consumption Monotonic Over Temperature 3 us in Fast Mode Available in MSOP Package 9 us in Slow Mode Ultra Low Power Consumption applications 900 uW Typ in Slow Mode at 3 V Digital Servo Control Loops 2 1 mW Typ in Fast Mode at 3 V Differential Nonlinearity 0 2 LSB Typ Compatible With TMS320 and SPI Serial Ports Power Down Mode 10 nA Digital Offset and Gain Adjustment Industrial Process Conirol Machine and Motion Conirol Devices Mass Storage Devices description D OR DGK PACKAGE TOP VIEW The TLV5606 is a 10 bit voltage output digital to analog converter DAC with a flexible 4 wire serial interface The 4 wire serial interface allows glueless interface to TMS320 SPI QSPI and Microwire serial ports The TLV5606 is pro grammed with a 16 bit serial string containing 4 control and 10 data bits Developed for a wide range of supply voltages the TLV5606 can operate from 2 7 V to 5 5 V The resistor string output voltage is buffered by a x2 gain rail to rail output buffer The buffer features a Class AB output stage to improve stability and reduce settling time The settling2. Zero scale error temperature coefficient is given by Ezs TC Ezs Tmax Ezs Tmin l Vret X 106 Tmax Tmin Gain error is the deviation from the ideal output 2Vref 1 LSB with an output load of 10 excluding the effects of the zero error Gain temperature coefficient is given by EG TC EG Tmax EG Tmin l Vret 108 Tmax Tmin COND output specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vo Voltage output range RL 10 0 AVpp 0 1 of FS Output load regulation accuracy RL 2 vs 10 0 1 0 25 reference input REF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5 Input capacitance Reference input bandwidth REFIN 0 2 Vpp 1 024 V dc Fast Reference feed through REFIN 1 Von at 1 kHz 1 024 V dc see Note 10 75 dB NOTE 10 Reference feedthrough is measured at the DAC output with an input code 0x000 digital inputs PARAMETER TEST CONDITIONS MAX UNIT High level digital input current Viz VDD Low level digital input current T Input capacitance TEST 435 TEXAS INSTRUMENTS 4 WWW TI COM TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 operating characteristics over recommended operating free air temperature range unless otherwise noted analog output dynamic performance PARAMETER TEST CONDITIONS MIN UNIT ts FS Output set
3. gt 025 1 1 3 V Slow Mode SINK w Mode SINK S 02 9 5 5 5 0 08 B 0 15 o 3 V Fast Mode SINK o 0 06 Lou 2 SCH 0 04 0 05 0 02 0 0 t 0 0 01 0 02 0 05 0 1 0 2 0 5 1 2 0 0 02 0 00 0 1 0 2 0 4 1 2 4 Load Current mA Load Current mA Figure 4 Figure 5 d TEXAS INSTRUMENTS WWW TI COM 7 TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 TYPICAL CHARACTERISTICS lpp Supply Current mA THD Total Harmonic Distortion dB SUPPLY CURRENT VS FREE AIR TEMPERATURE Vpp 3V Vref 1 V Full Scale r E Ipp Supply Current mA Slow Mode 25 0 25 40 70 85 TA Free Air Temperature C 125 Figure 6 TOTAL HARMONIC DISTORTION VS FREQUENCY Vref 1 V dc 1 V p p Sinewave Output Full Scale THD Total Harmonic Distortion dB 0 8 0 6 0 4 0 2 55 40 SUPPLY CURRENT VS FREE AIR TEMPERATURE 5 Vref 2 V Full Scale r T TT 25 0 25 40 70 85 TA Free Air Temperature C 125 Figure 7 TOTAL HARMONIC DISTORTION VS FREQUENCY Vref 1 V dc 1 V p p Sinewave Output Full Scale 0 5 00 20 30 0 0 5 10 20 30 50 100 f Frequency kHz f Frequency kHz Figure 8 Figure 9 T EX
4. flash or protrusion Falls within MO 187 variation AA da TEXAS INSTRUMENTS www ti com MECHANICAL DATA D R PDSO G8 PLASTIC SMALL OUTLINE PACKAGE Pin 1 Index Area 0 020 0 51 0 012 0 31 410 010 0 25 0 050 1 27 Y be 0 25 0 069 1 75 Max 0 004 0 10 C 0 004 0 10 Gauge Plane Seating Plane 0 010 0 25 4040047 2 F 07 2004 NOTES All linear dimensions are in inches millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 006 0 15 Falls within JEDEC MS 012 variation AA 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specificati
5. k k k I O and memory mapped regs include regs asm P vectors INT23 TIM ISR d TEXAS INSTRUMENTS WWW TI COM 13 TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 APPLICATION INFORMATION PRR RRR RRR KR KERR ke echec ke K K he ke e K he ke he he ke e he ke ke ce he ke e che ke ke he he ke e he ke ke ce he ke e he he che he ke e he ke ce he ke che he kc che he ke ce he ke ke ce he ke e he ke e he he e e ke ke Main Program PRR RRR k k k ke k k he ke e ke ke k e he e e he he k k he ke e he ke k he he k e che ke k k he k e he ke k k he e e he he k che he k e he k k k he k e he ke e che he k e he ke e k he k e he ke e ke ke e k kk k ps 1000h entry start disable interrupts setc INTM disable maskable interrupts Splk HOffffh IFR splk 0004h IMR set up the timer to interrupt ever 205uS splk 0000h 60h splk 00FFh 61h out 61h PRD out 60h TIM splk 0c2fh 62h out 62h TCR Configure SSP to use internal clock internal frame sync and burst mode splk 0CCOEh 63h out 63h SSPCR splk 0CC3Eh 63h out 63h SSPCR splk 0000h 64h set initial DAC value enable interrupts lrg INTM enable maskable interrupts loop forever next idle wait for interrupt b next all else fails stop here done b done hang there p RRR RRR KKK KK kk KK K
6. lh Wd P d aA a aen M Us ELA ado du aw AM IU E ON n y l U M NUNT IK W Ua WII ln om 0 08 B 0 12 0 16 0 20 0 512 1024 Digital Code Figure 14 d TEXAS INSTRUMENTS 10 WWW TI COM TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 APPLICATION INFORMATION general function The TLV5606 is a 10 bit single supply DAC based on a resistor string architecture The device consists of a serial interface speed and power down control logic a reference input buffer a resistor string and a rail to rail output buffer The output voltage full scale determined by external reference is given by 2 REF CODE IV where REF is the reference voltage and CODE is the digital input value within the range of 049 to 2 1 where n 10 bits The 16 bit data word consisting of control bits and the new DAC value is illustrated in the data format section A power on reset initially resets the internal latches to a defined state all bits zero serial interface Explanation of data transfer First the device has to be enabled with CS set to low Then a falling edge of FS starts shifting the data bit per bit starting with the MSB to the internal register on the falling edges of SCLK After 16 bits have been transferred or FS rises the content of the shift register is moved to the DAC latch which
7. time of the DAC is programmable to allow the designer to optimize speed versus power dissipation The settling time is chosen by the control bits within the 16 bit serial input string A high impedance buffer is integrated on the REFIN terminal to reduce the need for a low source impedance drive to the terminal Implemented with a CMOS process the TLV5606 is designed for single supply operation from 2 7 V to 5 5 V The device is available in an 8 terminal SOIC package The TLV5606C is characterized for operation from 0 to 70 The TLV5606l is characterized for operation from 40 C to 85 AVAILABLE OPTIONS PACKAGE SMALL S msopt D DGK 0 C to 70 TLV5606CD TLV5606CDGK 40 C to 85 TLV5606ID TLV5606IDGK t Available in tape and reel as the TLV5606CDR TLV5606IDR TLV5606CDGKR and the TLV5606IDGKR Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include b TEXAS Copyright 2002 2004 Texas Instruments Incorporated testing of all parameters INSTRUMENTS WWW TI COM 1 TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL T
8. to make the necessary connections In applications where only one synchronous serial peripheral is used the interface can be simplified even further by pulling CS low all the time as shown in the figure TMS320C203 TLV5606 VDD RLOAD Figure 17 TLV5606 to DSP Interface software No setup procedure is needed to access the TLV5606 The output voltage can be set using just a single command out data addr SDTR where data addr points to an address location holding the control bits and the 12 data bits providing the output voltage data SDTR is the address of the transmit FIFO of the synchronous serial port The following code shows how to use the timer of the TMS320C203 as a time base to generate a voltage ramp with the TLV5606 A timer interrupt is generated every 205 us The corresponding interrupt service routine increments the output code stored at 0x0064 for the DAC adds the DAC control bits to the four most significant bits and writes the new code to the TLV5606 The resulting period of the saw waveform is 4096 x 205 E 6 s 0 84 s skkkxkxkxkxkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkk kkkkkkkkk xkkkkxk Title Ramp generation with TLV5606 Version 1 0 DSP TI TMS320C203 1998 Texas Instruments Incorporated PRR RR k k KR KKK RK KK RK KK KKK KKK KKK KKK KK KK KK k k k k k k k k k ke k ke k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck k k k k k
9. AS INSTRUMENTS WWW TI COM THD Total Harmonic Distortion And Noise dB TOTAL HARMONIC DISTORTION AND NOISE VS FREQUENCY Vref 1 V dc 1 V p p Sinewave Output Full Scale TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 TYPICAL CHARACTERISTICS VS FREQUENCY Vref 1 V dc 1 V p p Sinewave Output Full Scale TOTAL HARMONIC DISTORTION AND NOISE Slow Mode 0 5 10 20 30 f Frequency kHz Figure 10 THD Total Harmonic Distortion And Noise dB 50 100 0 SUPPLY CURRENT VS 5 10 20 30 f Frequency kHz Figure 11 TIME WHEN ENTERING POWER DOWN MODE 900 800 700 600 500 400 300 l pp Supply Current A 200 100 0 0 100 200 300 400 500 600 700 800 900 1000 T Time ns Figure 12 d TEXAS INSTRUMENTS WWW TI COM 50 100 TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY ERROR INL Integral Nonlinearity LSB eo o 0 5 a 1 0 0 512 1024 Digital Code Figure 13 DIFFERENTIAL NONLINEARITY ERROR m U 0 20 gt 0 16 0 12 8 0 08 5 0 04 LI 2 0 00
10. AS INSTRUMENTS WWW TI COM sinevals END RSEG DS RSEG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW STACK 10h SP STACK 1 A SCON A TMOD 02H THO 0C8H T1 TO ETO EA rolling ptr A TRO always SINTBL 01000H 0903CH 05094H 0305CH 0B084H 070C8H OFOEOH OFO66H 0F038H OFO6CH OFOEOH 070C8H 0B084H 0305CH 05094H 0903CH 01000H 06020H OA0E8H 0C060H 040F8H 080B4H 0009CH 00050H 00024H 00050H 0009CH 080B4H 040F8H 0C060H OAOE8H 06020H TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 APPLICATION INFORMATION 16 Byte Stack first set Stack Pointer set set set set FS 1 set CSB 1 enable timer 0 interrupts enable all interrupts serial port 0 to mode 0 timer 0 to mode 2 auto reload THO for 16 67 kHs interrupts Set rolling pointer to 0 Start timer 0 d TEXAS INSTRUMENTS WWW TI COM 17 TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 APPLICATION INFORMATION linearity offset and gain error using single ended supplies When an amplifier is operated from a single supply the voltage offset can still be either positive or negative With a positive offset the output voltage changes
11. K RK KK ck KK e ck KK RK KK RK KK ke ke ke ck kk KK kk KK ck kk kk RK c kck ck ck kk kk kk kk kk kk kk kk kk ck ckck k k k k k Interrupt Service Routines PRR RR RRR RK K ke he ke e he KK RRR e K he khe he e e he ke ke e he ke e he ke ke he he ke e he ke ke ce he ke e he he sk che he ke e he ke ce he ke che he ke che he ke ce he ke ke ce he kc e he ke e he ke e e kkk INT1 ret do nothing and return INT23 ret do nothing and return TIM ISR lacl 64h restore counter value to ACC add 4h increment DAC value and KOFFCh mask 4 MSBs sacl 64h Store 12 bit counter value or 4000h set DAC control bits sacl 65h store DAC value out 65h SDTR send data clre intm re enable interrupts ret END 14 d TEXAS INSTRUMENTS WWW TI COM TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 APPLICATION INFORMATION TLV5606 interfaced to MCS519 microcontroller hardware interfacing Figure 18 shows an example of how to connect the TLV5606 to an MCS519 compatible microcontroller The serial DAC input data and external control signals are sent via I O port of the controller The serial data is sent on the RxD line with the serial clock output on the TxD line P3 4 and P3 5 are configured as outputs to provide the chip select and frame sync signals for the TLV5606 MCS51 Controller TLV5606 VDD Figure 18 TLV5606 to MCS519 Controller I
12. O ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 functional block diagram REFIN Serial Input Register Update Speed Power Down Logic Serial digital data input Frame sync Digital input used for 4 wire serial interfaces such as the TMS320 DSP interface DAC analog output Reference analog input voltage Serial digital clock input VDD Positive power supply d TEXAS INSTRUMENTS WWW TI COM TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 absolute maximum ratings over operating free air temperature range unless otherwise noted t Supply voltage Vpp to AGND ssssssesssesese ror RII 7M Reference input voltage range 0 3V to Vpp 0 3V Digital input voltage range 0 3 V to Vpp 0 3 V Operating free air temperature range Ta TLV5606C 0 to 70 NEIE uas eee tete atrae 40 to 85 Storage temperature range Jeng isis nnne 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at t
13. ax Ezs Vppmin Vppmax 3 Power supply rejection ratio at full scale is measured by varying Vpp and is given by PSRR 20 log Eg Vppmax Eg Vppmin Vppmax d TEXAS INSTRUMENTS WWW TI COM 3 TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 electrical characteristics over recommended operating free air temperature range unless otherwise noted continued static DAC specifications 10 Cj 100 pF DNL Differential nonlinearity Ezs Zero scale error offset error at zero scale Zero scale error temperature coefficient EG Gain error Note 8 voltage Gain error temperature coefficient See Note 9 ppm C NOTES 4 The relative accuracy or integral nonlinearity INL sometimes referred to as linearity error is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors Tested from code 10 to code 1023 5 The differential nonlinearity DNL sometimes referred to as differential error is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes Monotonic means the output voltage changes in the same direction or remains constant as a change in the digital input code Tested from code 10 to code 1023 Zero scale error is the deviation from zero voltage output when the digital input code is zero
14. cution starts at address 0 on power up JMP timerOisr Jump vector for timer 0 interrupt is 000Bh Define program variables RSEG ISR timerOisr PUSH PSW PUSH ACC CLR TO set CSB low CLR TL set FS low The signal to be output on the dac is a sine function One cycle of a sine wave is held in a table 9 sinevals as 32 samples of msb lsb pairs 64 bytes The pointer rolling ptr rolls round the table of samples incrementing by 2 bytes 1 sample on each interrupt at the end of this routine MOV DPTR Sinevals set DPTR to the start of the table of sine signal values MOV A rolling ptr ACC loaded with the pointer into the sine table MOVC A A DPTR get msb from the table ORL A 00H set control bits MOV SBUF A Send out msb of data word MOVA rolling ptr move rolling pointer in to ACC INC A increment ACC holding the rolling pointer MOVC A A DPTR which is the lsb of this sample now in ACC MSB TX JNB TI MSB TX wait for transmit to complete CLR TEE Clear for new transmit MOV SBUF A and send out the lsb LSB TX JNB TI LSB TX wait for lsb transmit to complete SETB TL set FS 1 CLR TEE Clear for new transmit MOV A rolling ptr load ACC with rolling pointer INC A increment the ACC twice to get next sample INC A ANL A 03FH wrap back round to 0 if gt 64 MOV rolling ptr A move value held in ACC back to the rolling pointer SETB TO CSB high POP ACC POP PSW RETI 16 d TEX
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16. fter the write operation s the DAC output is updated automatically on the next positive clock edge following the sixteenth falling clock edge serial clock frequency and update rate The maximum serial clock frequency is given by 1 f E 20 MHz SCLKmax tyH mim The maximum update rate is _ 1 _ fUPDATEmax 1 25 MHz 18 S twL min The maximum update rate is a theoretical value for the serial interface since the settling time of the TLV5606 has to be considered also data format The 16 bit data word for the TLV5606 consists of two parts Control bits D15 D12 New DAC value D11 D2 D12 Dit oto D9 D7 De ps D4 ps D2 Dt Do x so w x 9 0 X don t care SPD Speed control bit 1 fast mode 0 gt slow mode PWR Power control bit 1 power down 0 normal operation In power down mode all amplifiers within the TLV5606 are disabled d TEXAS INSTRUMENTS 12 WWW TI COM TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 APPLICATION INFORMATION TLV5606 interfaced to TMS320C203 DSP hardware interfacing Figure 17 shows an example how to connect the TLV5606 to a TMS320C203 DSP The serial interface of the TLV5606 is ideally suited to this configuration using a maximum of four wires
17. hese or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability recommended operating conditions Supply voltage V VoD 5V voltage pply 9e VDD Vo 3V MSS DVpp 2 7 V High level digital input voltage Vu DVpp 5 5 V o DVpp 2 7 V Low level digital input voltage Vu DVpp 5 5V Reference voltage Vret to REFIN terminal Vpp 5 V see Note 1 Reference voltage Vret to REFIN terminal Vpp 3 V see Note 1 AGND 1 024 Vpp 1 5 Load resistance RL Load capacitance CL TLVE6060 Operating free air temperature TA TLV56081 20 85 NOTE 1 Due to the x2 output buffer a reference input voltage gt Vpp 2 causes clipping of the transfer function electrical characteristics over recommended operating free air temperature range unless otherwise noted power supply PARAMETER TEST CONDITIONS UNIT Vpp 5 V VREF 2 048 V No load All inputs AGND or Vpp DAC latch 0x800 Vpp 3 V VREF 1 024 V No load IDD Power supply current All inputs AGND or Vpp DAC latch 0x800 Power down supply current see Figure 12 ower su rejection ratio REMIS Full scale See Note Power on threshold voltage POR p c EE WCS NOTES 2 Power supply rejection ratio at zero scale is measured by varying Vpp and is given by PSRR 20 log Ezs Vppm
18. nterface software The example program puts out a sine wave on the OUT pin The on chip timer is used to generate interrupts at a fixed frequency The related interrupt service routine fetches and writes the next sample to the DAC The samples are stored in a lookup table which describes one full period of a sine wave The serial port of the controller is used in mode 0 which transmits 8 bits of data on RxD accompanied by a synchronous clock on TxD Two writes concatenated together are required to write a complete word to the TLV5606 The CS and FS signals are provided in the required fashion through control of I O port 3 which has bit addressable outputs ekkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxk Title Ramp generation with TLV5606 Version 1 0 MCU INTEL MCS519 1998 Texas Instruments Incorporated ekkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkxk NAME GENSINE MAIN SEGMENT CODE ISR SEGMENT CODE SINTBL SEGMENT CODE VAR1 SEGMENT DATA STACK SEGMENT IDATA Code start at address 0 jump to start CSEG AT 0 MCS is a registered trademark of Intel Corporation d TEXAS INSTRUMENTS WWW TI COM 15 TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 APPLICATION INFORMATION JMP start Exe
19. o not perform well and should not be used The two ground planes should be connected together at the low impedance power supply source The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane A 0 1 uF ceramic capacitor bypass should be connected between Vpp and AGND and mounted with short leads as close as possible to the device Use of ferrite beads may further isolate the system analog supply from the digital power supply Figure 20 shows the ground plane layout and bypassing technique Analog Ground Plane Figure 20 Power Supply Bypassing d TEXAS INSTRUMENTS WWW TI COM TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity INL The relative accuracy or integral nonlinearity INL sometimes referred to as linearity error is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors differential nonlinearity DNL The differential nonlinearity DNL sometimes referred to as differential error is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes M
20. on the first code change With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage The output amplifier attempts to drive the output to a negative voltage However because the most negative supply rail is ground the output cannot drive below ground and clamps the output at 0 V The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage resulting in the transfer function shown in Figure 19 Output Voltage 0v Negative Ba DAC Offset P d Figure 19 Effect of Negative Offset Single Supply This offset error not the linearity error produces this breakpoint The transfer function would have followed the dotted line if the output buffer could drive below the ground rail For a DAC linearity is measured between zero input code all inputs 0 and full scale code all inputs 1 after offset and full scale are adjusted out or accounted for in some way However single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function So the linearity is measured between full scale code and the lowest code that produces a positive output voltage power supply bypassing and ground management Printed circuit boards that use separate analog and digital ground planes offer the best system performance Wire wrap boards d
21. onotonic means the output voltage changes in the same direction or remains constant as a change in the digital input code zero scale error Ezs Zero scale error is defined as the deviation of the output from 0 V at a digital input value of 0 gain error Eq Gain error is the error in slope of the DAC transfer function signal to noise ratio distortion S N D S N D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc The value for S N D is expressed in decibels spurious free dynamic range SFDR SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth The value for SFDR is expressed in decibels total harmonic distortion THD THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels d TEXAS INSTRUMENTS WWW TI COM 19 MECHANICAL DATA DGK S PDSO G8 PLASTIC SMALL OUTLINE PACKAGE EN A 1 4 3 10 2 90 EEE 210 L 1 10 MAX Bi 4073329 D 12 03 NOTES All linear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold
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23. tling time full scale See Note 11 us Ge RL 10ka CL 100pF RL 10kQ 100 pF 31 A See Note 13 Se E Glitch energy Code transition from Ox7FF to 0x800 CT S N Signal to noise S N D Signal to noise distortion fs 400 KSPS fout 1 1 kHz TET e RL 10 ko C 100 pF THD Total harmonic distortion BW 20 kHz Spurious free dynamic range NOTES 11 Settling time is the time for the output signal to remain within 0 5 LSB of the final measured value for a digital input code change of 0x080 to Ox3FF or Ox3FF to 0x080 Not tested ensured by design 12 Settling time is the time for the output signal to remain within 0 5 LSB of the final measured value for a digital input code change of one count Code change from Ox1FF to 0x200 Not tested ensured by design 13 Slew rate determines the time it takes for a change of the DAC output from 10 to 90 full scale voltage digital input timing requirements pa NOM MAX UNIT isCS FS _ Setup time CS low before FSI tsu FS CK Setup time FS low before first negative SCLK edge ons t Setup time sixteenth negative edge after FS low on which bit DO is sampled before rising su C1 6 FS edge of FS Setup time sixteenth positive SCLK edge first positive after DO is sampled before CS rising tsu C16 CS edge If FS is used instead of the sixteenth positive edge to update the DAC then the setup time is between the FS rising edge and CS rising edge EEN M me
24. updates the voltage output to the new level The serial interface of the TLV5606 can be used in two basic modes Four wire with chip select Three wire without chip select Using chip select four wire mode it is possible to have more than one device connected to the serial port of the data source DSP or microcontroller The interface is compatible with the TMS320 family Figure 15 shows an example with two TLV5606s connected directly to a TMS320 DSP TLV5606 TLV5606 CS FS DIN SCLK CS FS DIN SCLK TMS320 DSP SEO XF1 FSX DX CLKX e Figure 15 TMS320 Interface d TEXAS INSTRUMENTS WWW TI COM 11 TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 APPLICATION INFORMATION serial interface continued If there is no need to have more than one device on the serial bus then CS can be tied low Figure 16 shows an example of how to connect the TLV5606 to a TMS320 SPI or Microwire port using only three pins TMS320 TLV5606 TLV5606 DSP FSX Microwire TLV5606 y o DX CLKX SO SK Figure 16 Three Wire Interface Notes on SPI and Microwire Before the controller starts the data transfer the software has to generate a falling edge on the I O pin connected to FS If the word width is 8 bits SPI and Microwire two write operations must be performed to program the TLV5606 A
25. wwmsKW O EE 79 Ce mo Fodimedareovgaesakame e ooo 0 we Wo 35 TEXAS INSTRUMENTS WWW TI COM 5 TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 PARAMETER MEASUREMENT INFORMATION twL twH SCLK 1 2 3 4 5 15 16 4 tsu FS CK tsu c16 cs MR cs 4 amp twH Fs tsu C16 Fs HN gt Figure 1 Timing Diagram d TEXAS INSTRUMENTS 6 WWW TI COM TLV5606 2 7 V TO 5 5 V LOW POWER 10 BIT DIGITAL TO ANALOG CONVERTERS WITH POWER DOWN SLAS259B DECEMBER 1999 REVISED APRIL 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE OUTPUT VOLTAGE VS vs LOAD CURRENT LOAD CURRENT 2 004 4 01 3 V Slow Mode SOURCE VDD 3V Vpp 5V Vref 1 V Vref 2 V 2 002 Full Scale 4 005 Full Scale gt 2 V Fast Mode SOURCE 4 5 V Fast Mode SOURCE S 1 998 S 3 995 5 5 a 1 996 3 99 5 5 1 1 994 3 985 S S 1 992 3 98 1 990 3 975 0 0 01 0 02 0 05 0 1 02 05 1 2 0 0 02 0 00 01 02 04 1 2 4 Load Current mA Load Current mA Figure 2 Figure 3 OUTPUT VOLTAGE OUTPUT VOLTAGE VS VS LOAD CURRENT LOAD CURRENT 0 2 0 35 Vpp 3V 0 18 Ver 1 V Zero Code 0 3 0 16 gt 0 14
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