Home

ATMEL AT89C55WD handbook (1)

1. D1 C 0 51 0 020 45 MAX 3X COMMON DIMENSIONS Unit of Measure mm Notes 1 This package conforms to JEDEC reference MS 018 Variation AC 2 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 010 0 254 mm per side Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line 3 Lead coplanarity is 0 004 0 102 mm maximum 1 270 TYP 10 04 01 TITLE DRAWING NO REV AMEL e 2 44 1 44 lead Plastic J leaded Chip Carrier PLCC 5 aware AMEL 1921 3 05 AMEL 39 3 40P6 PDIP E SEATING PLANE immu dm di IL 2 COMMON DIMENSIONS 09 159 Unit of Measure Da mo SYMBOL MIN NOM 1 0 381 52 070 15 240 13 462 0 356
2. In the Counter function the register is incremented in response to a 1 to 0 transition at its corre sponding external input pin T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since two machine cycles 24 oscillator periods are required to recognize 1 to 0 transition the maximum count rate is 1 24 of the oscillator frequency To ensure that a given level is sampled at least once before it changes the level should be held for at least one full machine cycle In the capture mode two options are selected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 is a 16 bit timer or counter which upon overflow sets bit TF2 in T2CON This bit can then be used to generate an interrupt If EXEN2 1 Timer 2 performs the same operation but a 1 to 0 transi tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L respectively In addition the transition at T2EX causes bit EXF2 T2CON to be set The EXF2 bit like TF2 can generate an interrupt The capture mode is illus trated in Figure 12 1 12 2 Auto reload Up or Down Counter 1921C MICRO 3 05 Timer 2 can be programmed to count up or down when configured in its 16 b
3. P3 0 015 29 28 I NC TXD P3 1 7 27 ALE PROG INTO P3 2 18 26 INT1 P3 3 9 25 0 P2 7 A15 TO P3 4 10 24 P2 6 A14 T1 P3 5 C 11 23 P2 5 13 II Ill 00000000000 enaragerane a zt E 5 2 2 44J 44 lead PLCC A 2 8588 EE lt lt 54 om gt gt P1507 39 1 P0 4 1 6 08 38 5 ADS P1 7 09 37 5 P0 6 AD6 RST 10 36 P0 7 AD7 P3 0 L 11 35 1 EA VPP NCL 12 NC TXD P3 1 13 33 ALE PROG INTO P3 2 114 32 PSEN P3 3 15 31 P2 7 A15 TO P3 4 C 16 30 1 P2 6 A14 1 23 5 1170 29 O P2 5 A13 QI QI QNI orOWu nooaoo wcos 2 2 A aa ERO 000 0 EC SUR ES 2 3 40P6 40 lead PDIP T2 P1 0 1 40 1 2 P1 1 O 2 39 5 P0 0 ADO P1203 38 AD1 P1 3 04 37 0 P0 2 P1 405 36 1 P0 3 AD3 P1 5 06 35 5 P0 4 P1 6 7 34 1 5 AD5 P1 7L 8 33 1 PO 6 AD6 09 32 5 0 7 AD7 P3 0 O 10 31 LI EA VPP TXD P3 1 11 30 ALE PROG INTO P3 2 12 29 1 PSEN INT1 P3 3 13 28 5 P2 7 A15 TO P3 4 C 14 27 P2 6 A14 T1 P3 5 015 26 O P2 5 A13 WR P3 6 1
4. C2 1 XTAL2 C1 7 XTAL1 GND Note C1 C2 30 pF x 10 pF for Crystals 40 pF 10 pF for Ceramic Resonators Figure 18 2 External Clock Drive Configuration NC XTAL2 EXTERNAL OSCILLATOR SIGNAL Table 18 1 Status of External Pins During Idle Power down Modes Program EN Mode Memory ALE PSEN PORTO PORT1 PORT2 Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 Float Data Data Data AMEL 1921 3 05 AMEL 19 Program Memory Lock Bits AT89C55WD has three lock bits that can be left unprogrammed U or can be programmed P to obtain the additional features listed in the following table Table 19 1 Lock Bit Protection Modes Program Lock Bits LB1 LB2 LB3 Protection Type 1 U U U No program lock features MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is 5 sampled latched reset and further programming of the Flash memory is disabled 3 P P U Same as mode 2 but verify is also disabled 4 P P P Same as mode 3 but external execution is also disabled When lock bit 1 is programmed the logic level at the EA pin is sampled and latched during reset If the device is powered up without a res
5. AMEL RCAP2L UP COUNTING RELOAD VALUE gt TIMER 2 INTERRUPT COUNT DIRECTION 1 UP 0 DO T2EX PIN 13 AMEL 13 Baud Rate Generator 14 Timer 2 is selected as the baud rate generator by setting and or T2CON Table 5 2 Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function Setting RCLK and or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 13 1 The baud rate generator mode is similar to the auto reload mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and 2 which are preset by software The baud rates in Modes 1 3 are determined by Timer 275 overflow rate according to the fol lowing equation Modes 1 and 3 Baud Rates Timer 2 Overfow Rate The Timer can be configured for either timer or counter operation In most applications it is con figured for timer operation CP T2 0 The timer operation is different for Timer 2 when it is used as a baud rate generator Normally as a timer it increments every machine cycle at 1 12 the oscillator frequency As a baud rate generator however it increments every state time at 1 2 the oscillator frequency The baud rate formula is given below Modes 1 and3 _ Oscillator Frequency Baud Rate 32 x 65536 RCAP2H RC
6. ter IDLE mode With WDIDLE bit enabled the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE The UART in the AT89C55WD operates the same way as the UART in the AT89C51 and AT89C52 For more detailed information on the UART operation please click on the document link below http www atmel com dyn resources prod documents DOCA4316 PDF Timer 0 and Timer 1 in the AT89C55WD operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52 For further information on the timers operation please click on the document link below http www atmel com dyn resources prod documents DOCA4316 PDF 10 AT89C55WD meme 1921C MICRO 3 05 12 2 12 1 Capture Mode Timer 2 is a 16 bit Timer Counter that can operate as either a timer or an event counter The type of operation is selected by bit C T2 in the SFR T2CON shown in Table 5 2 Timer 2 has three operating modes capture auto reload up or down counting and baud rate generator The modes are selected by bits in T2CON as shown in Table 5 2 Timer 2 consists of two 8 bit registers TH2 and TL2 In the Timer function the TL2 register is incremented every machine cycle Since a machine cycle consists of 12 oscillator periods the count rate is 1 12 of the oscillator frequency Table 12 1 Timer 2 Operating Modes TCLK CP RL2 TR2 MODE 0 0 1 16 bit Auto Reload 0 1 1 16 bit Capture 1 X 1 Baud Rate Generator X X 0 Off
7. C Package Type 44A 44 lead Thin Plastic Gull Wing Quad Flatpack TQFP 44 lead Plastic J leaded Chip Carrier PLCC 40P6 40 pin 0 600 Wide Plastic Dual Inline Package PDIP AMEL s 1921C MICRO 3 05 AMEL 39 Package Information 39 1 44A TQFP PIN 1 IDENTIFIER COMMON DIMENSIONS Unit of Measure mm Notes 1 This package conforms to reference MS 026 Variation ACB 2 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 0 25 mm per side Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch 3 Lead coplanarity is 0 10 mm maximum 0 80 TYP 10 5 2001 TITLE DRAWING NO IMEL 2529 44 lead 10 10 Body Size 1 0 mm Body Thickness 44A A me Jose 95181 og mm Lead Pitch Thin Profile Plastic Quad Flat Package TQFP B 89 55 1921C MICRO 3 05 39 2 44J PLCC 1 14 0 045 X 45 PIN NO 1 11410 0485 X45 IDENTIFIER 0 318 0 0125 0 191 0 0075 e
8. 3 05 Every code byte the Flash array be programmed by using the appropriate combination of control signals The write operation cycle is self timed and once initiated will automatically time itself to completion Most major worldwide programming vendors offer support for the Atmel AT89 microcontroller series Please contact your local programming vendor for the appropriate software revision ATMEL AMEL Table 21 1 Flash Programming Modes me P3 4 P2 5 0 P1 7 0 ALE EA 0 7 0 Mode Vec RST PSEN PROG Vpp P2 6 P2 7 P3 3 P3 6 P3 7 Data Address 1 Tta Code H L 12V L H H H Din 14 A138 A70 Data a a G de H L H H 12V L L L H H Dour 14 A13 8 A7 0 2 Write lock Bit 75501 L 12V H H H H H x x x x 1 V UNA 2 Wite Lock MEM L 12V H H H L L x x x x 2 V 2 Write Lock Bit L 12V H L H H L x x x x 3 V UNA 2 Read Lock Bit ead Lock Bits EU T L H H H H L H L X X X 1 2 3 4 6 5 3 H L 12V H L H L L x x x x V Read Atmel ID 5V H L H H L L L L L 1EH x XX0000 00H Device 5V H L H H L L L L L 55H x XX 0001 00H ce Device 5V H L H H L L L L L 06H X XX0010 00H Notes 1 Write Code Data requires a 200 ns PROG pulse 2 Write Lock Bits requires a 100 us PROG pulse 3 Chip Erase requires a 200 ns 500 ns PROG pulse 4 RDY B
9. as inputs As inputs Port 1 pins that are externally being pulled low will source current 1 because of the internal pull ups In addition P1 0 and P1 1 can be configured to be the timer counter 2 external count input P1 0 T2 and the timer counter 2 trigger input P1 1 T2EX respectively as shown in the follow ing table Port 1 also receives the low order address bytes during Flash programming and verification Port Pin Alternate Functions P1 0 T2 external count input to Timer Counter 2 clock out P1 1 T2EX Timer Counter 2 capture reload trigger and direction control Port 2 is an 8 bit bi directional I O port with internal pull ups The Port 2 output buffers can sink source four TTL inputs When 1s are written to Port 2 pins they are pulled high by the inter nal pull ups and can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current 1 because of the internal pull ups Port 2 emits the high order address byte during fetches from external program memory and dur ing accesses to external data memory that use 16 bit addresses MOVX DPTR In this application Port 2 uses strong internal pull ups when emitting 1s During accesses to external data memory that use 8 bit addresses MOVX Port 2 emits the contents of the P2 Special Function Register Port 2 also receives the high order address bits and some control signals during Flash program ming and verificatio
10. negative transition on T2EX and EXEN2 1 EXF2 When Timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software EXF2 does not cause an interrupt in up down counter mode DCEN 1 RCLK Receive clock enable When set causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3 RCLK 0 causes Timer 1 overflow to be used for the receive clock TCLK Transmit clock enable When set causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3 TCLK 0 causes Timer 1 overflows to be used for the transmit clock EXEN2 Timer 2 external enable When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX TR2 Start Stop control for Timer 2 TR2 1 starts the timer Timer or counter select for Timer 2 C T2 0 for timer function C T2 1 for external event counter falling edge triggered Capture Reload select CP RL2 1 causes captures to occur on negative transitions at T2EX if EXEN2 1 CP RL2 0 CP RL2 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at 2 when EXEN2 1 When either RCLK or TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 over
11. peripherals remain active The mode is invoked by software The content of the on chip RAM and all the special functions regis ters remain unchanged during this mode The idle mode can be terminated by any enabled interrupt or by a hardware reset Note that when idle mode is terminated by a hardware reset the device normally resumes pro gram execution from where it left off up to two machine cycles before the internal reset algorithm takes control On chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset the instruction following the one that invokes idle mode should not write to a port pin or to external memory 18 Power down Mode In the Power down mode the oscillator is stopped and the instruction that invokes Power down is the last instruction executed The on chip RAM and Special Function Registers retain their values until the Power down mode is terminated Exit from Power down can be initiated either by a hardware reset or by an enabled external interrupt Reset redefines the SFRs but does not change the on chip RAM The reset should be activated before is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize 18 AT89C55WD meme 1921C MICRO 3 05 Figure 18 1 Oscillator Connections
12. 1 041 Notes 1 This package conforms to reference MS 011 Variation AC 2 Dimensions D and E1 do not include mold Flash or Protrusion 3 048 Mold Flash or Protrusion shall not exceed 0 25 mm 0 010 0 203 _ 15 494 2 540 09 28 01 TITLE DRAWING REV 2325 Orchard Parkway 40P6 40 lead 0 600 15 24 mm Wide Plastic Dual AIMEL San Jose CA 95131 Inline Package PDIP AT89C55WD 1921C MICRO 3 05
13. 10 us teteh PROG Width 0 2 1 us tavav Address to Data Valid c ENABLE Low to Data Valid 48 Data Float After ENABLE 0 48 TGugi PROG High to BUSY Low 1 0 us twc Byte Write Cycle Time 80 us 24 AT89C55WD mememe 1921C MICRO 3 05 23 Flash Programming and Verification Waveforms P10 P7 PROGRAMMING VERIFICATION P20 P25 ADDRESS ADDRESS P3 4 PORT 0 K J ALE PROG EAN pp P2 7 ENABLE P3 0 _ RDY BSY 24 Lock Bit Programming iuc A Setup Data Setup 100 us ALE PROG 6 5 Voc 4 5V to 5 5V Wait 10 ms to reload new lock bit status 25 Parallel Chip Erase Mode DRX 200 ns 200 ns ALE PROG DC DC P3 lt 0 gt Erase Erase Erase Erase Voc 6 5V Voc 4 8V to 5 5V Wait 10 ms before reprogramming AMEL 1921 3 05 25 AMEL 26 Absolute Maximum Ratings Operating Temperature 55 C to 125 C Storage Temperature 65 C to 150 C Voltage on Any Pin with Respect to Ground 1 0V to 7 0V Maximum Operating Voltage 6 6V DC Output 15 0 NOTICE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam age
14. 35 Shift Register Mode Timing Waveforms INSTRUCTION 0 1 2 3 4 5 6 T 8 WRITE SBUF Y OUTPUT DATA SET TI 1 CLEAR SET 36 AC Testing Input Output Waveforms 0 5V 05 0 2 0 9V TEST POINTS 0 2 Voc 0 1V 0 45V Note 1 AC Inputs during testing are driven at 0 5V for a logic 1 and 0 45V for logic 0 Timing measurements are made at min for a logic 1 and max for a logic 37 Float Waveforms Timing Reference Points Note 1 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs port pin begins to float when a 100 mV change from the loaded Vo Vo level occurs 30 AT89C55WD meme 38 Ordering Information 38 1 Standard Package Speed Power MHz Supply Ordering Code Package Operation Range AT89C55WD 24AC 44A Commercial AT89C55WD 24JC 44J 0 C to 70 C AT89C55WD 24PC 40P6 24 4 0V to 5 5V AT89C55WD 24AI 44A Industrial AT89C55WD 24JI 44J 40 C to 85 C AT89C55WD 24PI 40P6 AT89C55WD 33AC 44A Camel 33 4 5V to 5 5V AT89C55WD 33JC 44J 0 C to 70 C AT89C55WD 33PC 40P6 38 2 Green Package Option Pb Halide free Speed Power MHz Supply Ordering Code Package Operation Range AT89C55WD 24AU 24 4 0V to 5 5V AT89C55WD 24JU a AT89C55WD 24PU 40P6 Industrial 40 C to 85
15. 6 25 1 P2 4 A12 RD P3 7 C 17 24 1 P2 3 A11 XTAL2 18 23 0 P2 2 10 XTAL1 19 22 2 1 A9 GND O 20 21 0 P2 0 A8 2 AT89C55WD mme AT89C55WD 3 Block Diagram 0 7 2 0 2 7 ADDRESS REGISTER STACK POINTER BUFFER PC INCREMENTER PROGRAM COUNTER PSEN TIMING INSTRUCTION EA Vpp CONTROL REGISTER RST LJ 3 0 7 AMEL 3 1921C MICRO 3 05 AMEL 4 Pin Description 4 1 4 2 4 3 4 4 4 5 4 VCC GND Port 0 Port 1 Port 2 Supply voltage Ground Port 0 is 8 bit open drain bi directional port As output port each can sink eight TTL inputs When 1s are written to port 0 pins the pins be used as high impedance inputs Port 0 can also be configured to be the multiplexed low order address data bus during accesses to external program and data memory In this mode PO has internal pull ups Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur ing program verification External pull ups are required during program verification Port 1 is an 8 bit bi directional I O with internal pull ups The Port 1 output buffers sink source four TTL inputs When 1s are written to Port 1 pins they are pulled high by the inter nal pull ups and can be used
16. 6 5V Pulse ALE PROG once duration of 200 500 ns Wait for 150 ms Power Vcc down and up to 6 5V Pulse ALE PROG once duration of 200 500 ns Wait for 150 ms 7 Power down and up Data Polling The AT89C55WD features Data Polling to indicate the end of a write cycle During a write cycle an attempted read of the last byte written will result in the complement of the writ ten data on 0 7 Once the write cycle has been completed true data is valid on all outputs and the next cycle may begin Data Polling may begin any time after a write cycle has been initiated Ready Busy The progress byte programming can also be monitored by the RDY BSY output signal P3 0 is pulled low after ALE goes high during programming to indicate BUSY P3 0 is pulled high again when programming is done to indicate READY Program Verify If lock bits LB1 and LB2 have not been programmed the programmed code data can be read back via the address and data lines for verification The status of the individual lock bits can be directly verified by reading them back Reading the Signature Bytes The signature bytes are read by the same procedure as a nor mal verification of locations 000H 100H and 200H except that P3 6 and P3 7 must be pulled to a logic low The values returned are as follows 000H 1EH indicates manufactured by Atmel 100H 55H 200H 06H indicates 89C55WD 21 Programming Interface 1921
17. AP2L where RCAP2H RCAP2L is the content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer Timer 2 as a baud rate generator is shown in Figure 13 1 This figure is valid only if RCLK or TCLK 1 in T2CON Note that a rollover in TH2 does not set TF2 and will not generate an inter Note too that if EXEN2 is set a 1 to 0 transition in T2EX will set EXF2 but will not cause reload from RCAP2H RCAP2L to TH2 TL2 Thus when Timer 2 is in use as a baud rate gen erator T2EX can be used as an extra external interrupt Note that when Timer 2 is running TR2 1 as a timer in the baud rate generator mode TH2 or TL2 should not be read from or written to Under these conditions the Timer is incremented every state time and the results of a read or write may not be accurate The RCAP2 registers may be read but should not be written to because a write might overlap a reload and cause write and or reload errors The timer should be turned off clear TR2 before accessing the Timer 2 or RCAP2 registers AT89C55WD mmm 1921C MICRO 3 05 AT89C55WD Figure 13 1 Timer 2 in Baud Rate Generator Mode TIMER 1 OVERFLOW NOTE OSC FREQ IS DIVIDED BY 2 NOT 12 3 C T2 1 T2 PIN TRANSITION DETECTOR 14 Programmable Clock Out A 50 duty cycle clock can be programmed to come out on P1 0 as shown in Figure 14 1 This pin besides being a
18. BDTIC www bdtic com ATMEL Features Compatible with MCS 51 Products 20K Bytes of Reprogrammable Flash Memory Endurance 1000 Write Erase Cycles 4V to 5 5V Operating Range Fully Static Operation 0 Hz to 33 MHz Three level Program Memory Lock 256 x 8 bit Internal RAM 32 Programmable Lines Three 16 bit Timer Counters Eight Interrupt Sources Programmable Serial Channel Low power Idle and Power down Modes Interrupt Recovery from Power down Mode Hardware Watchdog Timer Dual Data Pointer Power off Flag Green Pb Halide free Packaging Option 1 Description The AT89C55WD is a low power high performance CMOS 8 bit microcontroller with 20K bytes of Flash programmable read only memory and 256 bytes of RAM The device is manufactured using Atmel s high density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pinout The on chip Flash allows the program memory to be user programmed by a conventional nonvolatile memory programmer By combining a versatile 8 bit CPU with Flash on a monolithic chip the Atmel AT89C55WD is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications The AT89C55WD provides the following standard features 20K bytes of Flash 256 bytes of RAM 32 I O lines three 16 bit timer counters a six vector two level interrupt architecture a full duplex se
19. N 4 tavwL gt e PORT 2 2 0 P2 7 OR 8 A15 FROM A8 A15 FROM PCH 1921C MICRO 3 05 31 External Data Memory Write Cycle ALE gt PSEN N 14 twi wn WR ede 7 tovwx 0 A7 FROM DATA OUT A7 FROM PCL 14 tavwe gt 2 P2 0 P2 7 OR 8 A15 FROM DPH 8 15 32 External Clock Drive Waveforms 0 5V 0 2 Voo OAV 0 45V 33 External Clock Drive Symbol Parameter Min Max Units tec Oscillator Frequency 0 33 MHz Clock Period 30 ns toucx High Time 12 ns Low Time 12 ns Rise Time 5 ns Fall Time 5 ns ATMEL 2 1921 3 05 AMEL 34 Serial Port Timing Shift Register Mode Test Conditions The values in this table are valid for 4 0V to 5 5V and Load Capacitance 80 pF 12 MHz Osc Variable Oscillator Symbol Parameter Min Max Min Max Units tax Serial Port Clock Cycle Time 1 0 2 Hs tevxH Output Data Setup to Clock Rising Edge 700 133 ns Output Data Hold After Clock Rising Edge 50 80 5 Input Data Hold After Clock Rising Edge 0 0 ns Clock Rising Edge to Input Data Valid 700 10 133 5
20. SY signal is output on P3 0 during programming 1921C MICRO 3 05 Figure 21 1 Programming the Flash Memory 4 5V to 5 5V AT89C55WD 0 0 17 0000H 4FFFH P2 0 P2 5 A14 P3 4 P2 6 SEE FLASH P2 7 PROG PROGRAMMING P3 3 MODES TABLE P3 6 P3 7 XTAL2 Vin Vpp 3 33MHz c RDY BSY Figure 21 2 Verifying the Flash Memory 4 5V to 5 5V AT89C55WD Q appr AT pig piz 0000H AFFFH 8 13 PGM DATA 2 0 2 5 USE 10K B P3 4 PULL UPS P2 6 SEE FLASH P2 7 PROGRAMMING P3 3 MODES TABLE P3 6 v P3 7 XTAL2 3 33 2 Note Programming address line A14 P3 4 is not the same as the external memory address line A14 P2 6 AMEL 2 1921 3 05 AMEL 22 Flash Programming and Verification Characteristics 20 C to 30 C 4 5V to 5 5V Symbol Parameter Min Max Units Vpp Programming Supply Voltage 11 5 12 5 V lpp Programming Supply Current 10 mA loc Supply Current 30 mA 1 Oscillator Frequency 3 33 MHz tuer Address Setup to PROG Low 48tci ci tenax Address Hold After PROG 48 tov Data Setup to PROG Low 48tci Data Hold After PROG 48 P2 7 ENABLE High to Vpp 48tci cL tone Setup to PROG Low 10 us Vpp Hold After PROG
21. bles the interrupt Symbol Position Function Disables all interrupts If EA 0 no interrupt is acknowledged If EA EA IE 7 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit IE 6 Reserved ET2 IE 5 Timer 2 interrupt enable bit ES IE 4 Serial Port interrupt enable bit ET1 IE 3 Timer 1 interrupt enable bit EX1 IE 2 External interrupt 1 enable bit ETO IE 1 Timer 0 interrupt enable bit EXO IE 0 External interrupt O enable bit User software should never write 1s to reserved bits because they may be used in future AT89 products Figure 15 1 Interrupt Sources INT1 Ud IE1 1921C MICRO 3 05 AMEL 16 Oscillator Characteristics 17 Idle Mode XTAL1 and XTAL2 are the input and output respectively of an inverting amplifier that can be configured for use as an on chip oscillator as shown in Figure 18 1 Either a quartz crystal or ceramic resonator may be used To drive the device from an external clock source XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 18 2 There are no requirements on the duty cycle of the external clock signal since the input to the internal clock ing circuitry is through a divide by two flip flop but minimum and maximum voltage high and low time specifications must be observed In idle mode the CPU puts itself to sleep while all the on chip
22. e WDT is defaulted to disable from exiting reset To enable the WDT a user must write 01EH and OE1H in sequence to the WDTRST register SFR location 0A6H When the WDT is enabled it will increment every machine cycle while the oscillator is running The WDT time out period is dependent on the external clock frequency There is no way to disable the WDT except through reset either hardware reset or WDT overflow reset When WDT over flows it will drive an output RESET HIGH pulse at the RST pin ATMEL AMEL 8 Using the WDT To enable the WDT a user must write 01EH and 0E1H in sequence to the WDTRST register SFR location 0A6H When the WDT is enabled the user needs to service it by writing 01EH and OE1H to WDTRST to avoid a WDT overflow The 13 bit counter overflows when it reaches 8191 1FFFH and this will reset the device When the WDT is enabled it will increment every machine cycle while the oscillator is running This means the user must re initialize the WDT at least every 8191 machine cycles To re initialize the WDT the user must write 01EH and OE1H to WDTRST WDTRST is a write only register The WDT counter cannot be read or written When WDT overflows it will generate an output RESET pulse at the RST pin The RESET pulse duration is 98 where TOSC 1 FOSC To make the best use of the WDT it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT res
23. ed to Voc program fetches to addresses 0000H through 4FFFH are directed to internal memory and fetches to addresses 5000H through FFFFH are to external memory The AT89C55WD implements 256 bytes of on chip RAM The upper 128 bytes occupy a parallel address space to the Special Function Registers That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space When an instruction accesses an internal location above address 7FH the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space Instructions that use direct addressing access SFR space For example the following direct addressing instruction accesses the SFR at location which is P2 MOV data Instructions that use indirect addressing access the upper 128 bytes of RAM For example the following indirect addressing instruction where RO contains OAOH accesses the data byte at address OAOH rather than P2 whose address is MOV RO data Note that stack operations are examples of indirect addressing so the upper 128 bytes of data RAM are available as stack space 7 Hardware Watchdog Timer One time Enabled with Reset out 1921 3 05 WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets The WDT consists of a 13 bit counter and the WatchDog Timer Reset WDTRST SFR Th
24. et 9 WDT During Power down and Idle 10 UART 11 Timer 0 and 1 In Power down mode the oscillator stops which means the WDT also stops While in Power down mode the user does not need to service the WDT There are two methods of exiting Power down mode by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power down mode When Power down is exited with hardware reset servicing the WDT should occur as it normally does whenever the AT89C55WD is reset Exiting Power down with an interrupt is significantly different The interrupt is held low long enough for the oscillator to stabilize When the interrupt is brought high the interrupt is serviced To prevent the WDT from resetting the device while the interrupt pin is held low the WDT is not started until the interrupt is pulled high It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power down To ensure that the WDT does not overflow within a few states of exiting Power down it is best to reset the WDT just before entering Power down Before going into the IDLE mode the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled The WDT keeps counting during IDLE WDIDLE bit 0 as the default state To prevent the WDT from resetting the AT89C55WD while IDLE mode the user should always set up a timer that will periodically exit IDLE service the WDT and reen
25. et the latch initializes to a random value and holds that value until reset is activated The latched value of EA must agree with the current logic level at that pin in order for the device to function properly 20 Programming the Flash AT89C55WD is shipped with the on chip Flash memory array ready to be programmed The programming interface needs a high voltage 12 volt program enable signal and is compatible with conventional third party Flash or EPROM programmers The AT89C55WD code memory array is programmed byte by byte Programming Algorithm Before programming the AT89C55WD the address data and con trol signals should be set up according to the Flash programming mode table and Figures 21 1 and 21 2 To program the AT89C55WD take the following steps Input the desired memory location on the address lines Input the appropriate data byte on the data lines Activate the correct combination of control signals Raise EA Vpp to 12V Pulse ALE PROG once to program a byte in the Flash array or the lock bits The byte write cycle is self timed and typically takes no more than 50 us Repeat steps 1 through 5 changing the address and data for the entire array or until the end of the object file is reached N 20 AT89C55WD mmm Chip Erase Sequence Before the AT89C55WD be reprogrammed a Chip Erase operation needs to be performed To erase the contents of the AT89C55WD follow this sequence Raise to
26. flow 1921 3 05 AMEL AMEL Table 5 3 AUXR Auxiliary Register AUXR Address 8EH Reset Value Not Bit Addressable WDIDLE DISRTO DISALE Bit 7 6 5 4 3 2 1 0 Reserved for future expansion DISALE Disable Enable ALE DISALE Operating Mode 0 ALE is emitted at a constant rate of 1 6 the oscillator frequency 1 ALE is active only during a MOVX or MOVC instruction DISRTO Disable Enable Reset out DISRTO Operating Mode 0 Reset pin is driven High after WDT times out 1 Reset pin is input only WDIDLE Disable Enable WDT in IDLE mode WDIDLE Operating Mode 0 WDT continues to count in IDLE mode 1 WDT halts counting in IDLE mode Table 5 4 AUXR1 Auxiliary Register 1 AUXR1 Address A2H Reset Value Not Bit Addressable DPS Bit 7 6 5 4 3 2 1 0 Reserved for future expansion DPS Data Pointer Register Select DPS 0 Selects DPTR Registers DPOL DPOH 1 Selects DPTR Registers DP1L DP1H 8 AT89C55W D 1921C MICRO 3 05 6 Memory Organization The MCS 51 devices have a separate address space for Program and Data Memory Up to 64 Kbytes each of external Program and Data Memory can be addressed 61 Program Memory 6 2 Data Memory If the EA pin is connected to GND all program fetches are directed to external memory On the AT89C55WD if EA is connect
27. he count A logic 1 at T2EX makes Timer 2 count up The timer will overflow at OFFFFH and set the TF2 bit This overflow also causes the 16 bit value in RCAP2H and RCAP2L to be reloaded into the timer registers TH2 and TL2 respectively A logic 0 at T2EX makes Timer 2 count down The timer underflows when TH2 and TL2 equal the values stored in RCAP2H RCAP2L The underflow sets the TF2 bit and causes OFFFFH to be reloaded into the timer registers The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution In this operating mode EXF2 does not flag an interrupt Figure 12 2 Timer 2 Auto Reload Mode DCEN O OSC 12 OVERFLOW PIN TIMER 2 INTERRUPT TF2 TRANSITION DETECTOR T2EX PIN CONTROL EXEN2 12 89 55 0 1921C MICRO 3 05 12 2 T2MOD Address Not Bit Addressable T2MOD Timer 2 Mode Control Register Reset Value XXXX T20E DCEN Bit 7 6 5 3 1 0 Symbol Function implemented reserved for future T20E Timer 2 Output Enable bit DCEN When set this bit allows Timer 2 to be configured as an up down counter Figure 12 3 Timer 2 Auto Reload Mode DCEN 1 TOGGLE 1921 3 05 OFFH OFFH DOWN COUNTING RELOAD VALUE 7 OVERFLOW gt amp VA RCAP2H
28. it auto reload mode This feature is invoked by the DCEN Down Counter Enable bit located in the SFR T2MOD see Table 12 2 Upon reset the DCEN bit is set to 0 so that timer 2 will default to count up When DCEN is set Timer 2 can count up or down depending on the value of the T2EX pin AMEL AMEL Figure 12 1 Timer Capture Mode osc 12 oo TH2 TF2 OVERFLOW 5 T2 PIN CAPTURE RCAP2H RCAP2L TRANSITION DETECTOR TIMER 2 INTERRUPT TEXPN c oo gt EXF2 CONTROL EXEN2 Figure 12 2 shows Timer 2 automatically counting up when DCEN O In this mode two options are selected by bit EXEN2 T2CON If EXEN2 0 Timer 2 counts up to OFFFFH and then sets the TF2 bit upon overflow The overflow also causes the timer registers to be reloaded with the 16 bit value in RCAP2H and RCAP2L The values in Timer in Capture Mode RCAP2H RCAP2L are preset by software If EXEN2 1 a 16 bit reload can be triggered either by an overflow or by a 1 to 0 transition at external input T2EX This transition also sets the EXF2 bit Both the TF2 and EXF2 bits can generate an interrupt if enabled Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 12 2 In this mode the T2EX pin controls the direction of t
29. mory This pin is also the program pulse input PROG during Flash programming In normal operation ALE is emitted at a constant rate of 1 6 the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped dur ing each access to external data memory If desired ALE operation can be disabled by setting bit O of SFR location 8EH With the bit set ALE is active only during a MOVX or MOVC instruction Otherwise the pin is weakly pulled high Setting the ALE disable bit has no effect if the microcontroller is in external execution mode Program Store Enable is the read strobe to external program memory When the AT89C55WD is executing code from external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory ATMEL s AMEL 4 10 EA VPP External Access Enable EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note however that if lock bit 1 is programmed EA will be internally latched on reset EA should be strapped to for internal program executions This pin also receives the 12V programming enable voltage Vpp during Flash programming 4 11 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit 4 12 XTAL2 Output from the inverting o
30. n AT89C55WD mmm 1921C MICRO 3 05 4 6 47 RST 4 8 1921 3 05 Port 3 is 8 bit bi directional I O with internal pull ups The Port 3 output buffers sink source four TTL inputs When 1s are written to Port 3 pins they are pulled high by the inter nal pull ups and can be used as inputs As inputs Port 3 pins that are externally being pulled low will source current 1 because of the pull ups Port 3 receives some control signals for Flash programming and verification Port 3 also serves the functions of various special features of the AT89C55WD as shown in the following table Port Pin Alternate Functions P3 0 RXD serial input port P3 1 TXD serial output port P3 2 INTO external interrupt 0 P3 3 external interrupt 1 P3 4 TO timer 0 external input P3 5 T1 timer 1 external input P3 6 WR external data memory write strobe P3 7 RD external data memory read strobe Reset input A high on this pin for two machine cycles while the oscillator is running resets the device This pin drives High for 98 oscillator periods after the Watchdog times out The DISRTO bit in SFR AUXR address 8EH can be used to disable this feature In the default state of bit DISRTO the RESET HIGH out feature is enabled Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external me
31. regular I O pin has two alternate functions It can be programmed to input the external clock for Timer Counter 2 or to output 50 duty cycle clock ranging from 61 Hz to 4 MHz for a 16 MHz operating frequency TIMER 2 EXF2 INTERRUPT CONTROL EXEN2 To configure the Timer Counter 2 as a clock generator bit C T2 T2CON 1 must be cleared and bit T2MOD 1 must be set Bit TR2 T2CON 2 starts and stops the timer The clock out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers RCAP2H RCAP2L as shown in the following equation Oscillator Frequency lock Out F AxXI6R536 RCAP2H RCAPOLY Clock Out Frequency 7 7 65636 RCAP2H RCAPAL In the clock out mode Timer 2 roll overs will not generate an interrupt This behavior is similar to when Timer 2 is used as a baud rate generator It is possible to use Timer 2 as a baud rate gen erator and a clock generator simultaneously Note however that the baud rate and clock out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L ATMEL 1921C MICRO 3 05 AMEL Figure 14 1 Timer 2 Clock Out Mode TL2 TH OSC 8 BITS 8 BITS TR2 RCAP2L RCAP2H C T2 BIT piof N 2 IN 24 T2OE T2MOD 1 TRANSITION DETECTOR T2EX 15 Interrupts 2 AT89C55WD ha
32. rial port on chip oscillator and clock circuitry In addition the AT89C55WD is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes The Idle Mode stops the CPU while allowing the RAM timer counters serial port and interrupt system to con tinue functioning The Power down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next external interrupt or hardware reset ATMEL 8 bit Microcontroller with 20K Bytes Flash AT89C55WD 1921C MICRO 3 05 AIMEL NE 2 Pin Configurations 2 1 44 44 lead TQFP 5 TEN _ 33223 SANTIS OO0ccco amp Z gt ox B titi NA 319929885983 15 1 33 1 P0 4 1 6 2 32 PO 5 AD5 P1 7 03 31 1 P0 6 AD6 RSTO 4 30 P0 7 AD7
33. s a total six interrupt vectors two external interrupts INTO and 1 three timer interrupts Timers 0 1 and 2 and the serial port interrupt These interrupts are all shown in Figure 15 1 Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE IE also contains a global disable bit EA which disables all interrupts at once Note that Table 5 shows that bit position IE 6 is unimplemented User software should not write a 1 to this bit position since it may be used in future AT89 products Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON Nei ther of these flags is cleared by hardware when the service routine is vectored to In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt and that bit will have to be cleared in software 16 AT89C55WD 1921 3 05 The Timer 0 and Timer 1 flags TF1 set at S5P2 of the cycle which the timers overflow The values are then polled by the circuitry in the next cycle However the Timer 2 flag TF2 is set at S2P2 and is polled in the same cycle in which the timer overflows Table 15 1 Interrupt Enable IE Register MSB LSB EA 2 5 Enable 1 enables the interrupt Enable Bit 0 disa
34. scillator amplifier 5 Special Function Registers A map of the on chip memory area called the Special Function Register SFR space is shown in Table 5 1 Table 5 1 AT89C55WD SFR Map and Reset Values OF8H OFFH OFOH B OF7H 00000000 0 8 0E7H OD8H ODFH PSW DEH 0D7H T2MOD RCAP2L RCAP2H TL2 TH2 00000000 XXXXXX00 00000000 00000000 00000000 00000000 0C7H E OBFH XX000000 P3 OBOH 11111111 0 7 IE OAFH 0X000000 P2 AUXR1 WDTRST OAOH 11111111 XXXXXXXX SCON SBUF 98H 00000000 9FH P1 11111111 m TCON TMOD TLO TL1 THO AUXR a 00000000 00000000 00000000 00000000 00000000 00000000 XXXO00XXO Bn PO SP DPOL DPOH DP1H PCON 11111111 00000111 00000000 00000000 00000000 00000000 0XXX0000 1921C MICRO 3 05 Note that not all of the addresses are occupied and unoccupied addresses mented on the chip Read accesses to these addresses will in general return random data and write accesses will have an indeterminate effect User software should not write 1s to these unlisted locations since they may be used in future products to invoke new features In that case the reset or inactive values of the new bits will always be 0 Timer 2 Registers Control and s
35. st Freq 1 MHz 25 10 12 2 25 loc Idle Mode 12 MHz 6 5 mA Power down Mode Voc 5 5V 100 Notes 1 Under steady state non transient conditions lo must be externally limited as follows Maximum per port pin 10 mA Maximum per 8 bit port Port 0 26 mA Ports 1 2 3 15 mA Maximum total lo for all output pins 71 mA If lg exceeds the test condition Vg may exceed the related specification Pins not guaranteed to sink current greater than the listed test conditions 2 Minimum for Power down is 2V 26 AT89C55WD m 1921C MICRO 3 05 28 Characteristics Under operating conditions load capacitance for Port 0 ALE PROG and PSEN 100 pF load capacitance for all other outputs 80 pF 28 1 External Program and Data Memory Characteristics 12 MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min Max Units Oscillator Frequency 0 33 MHz tu ALE Pulse Width 127 40 ns Address Valid to ALE Low 43 25 5 Address Hold After ALE Low 48 25 5 ALE Low to Valid Instruction In 233 4 65 ns tup ALE Low to PSEN Low 43 25 ns Pulse Width 205 45 ns tery PSEN Low to Valid Instruction In 145 60 ns Input Instruc
36. tatus bits are contained in registers T2CON shown in Table 5 2 and T2MOD shown in Table 5 2 for Timer 2 The register pair RCAP2H RCAP2L are the Capture Reload registers for Timer 2 in 16 bit capture mode or 16 bit auto reload mode Interrupt Registers The individual interrupt enable bits are in the IE register Two priorities can be set for each of the six interrupt sources in the IP register Dual Data Pointer Registers To facilitate accessing both internal and external data memory two banks of 16 bit Data Pointer Registers are provided DPO at SFR address locations 82H 83H at 84H 85H Bit DPS 0 SFR 1 selects and DPS 1 selects The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register Power Off Flag The Power Off Flag POF is located at bit 4 PCON 4 in the PCON SFR POF is set to 1 during power up It can be set and reset under software control and is not affected by reset Table 5 2 T2CON Timer Counter 2 Control Register T2CON Address 0 8 Reset Value 0000 0000B Bit Addressable TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 7 6 5 4 3 2 1 0 Symbol Function Timer 2 overflow set by Timer 2 overflow and must be cleared by software 2 will not be set when either RCLK 1orTCLK 1 Timer 2 external flag set when either a capture or reload is caused by a
37. tion Hold After PSEN 0 0 ns tpx z Input Instruction Float After PSEN 59 25 5 tpxav PSEN to Address Valid 75 8 ns taviv Address to Valid Instruction In 312 5 80 ns teraz PSEN Low to Address Float 10 10 ns RD Pulse Width 400 100 ns WR Pulse Width 400 100 ns tai pv RD Low to Valid Data In 252 90 ns Data Hold After RD 0 0 ns taupz Data Float After RD 97 28 ns tiipy ALE Low to Valid Data In 517 8 150 5 Address to Valid Data 585 9tc 165 5 ALE Low to RD WR Low 200 300 50 50 ns tavwL Address to RD or WR Low 203 4 75 ns tovwx Data Valid to WR Transition 23 30 ns Data Valid to WR High 433 130 ns Tan Data Hold After WR 33 25 ns RD Low to Address Float 0 0 ns RD or WR High to ALE High 43 123 tore 725 tote 25 ns ATMEL 1921 3 05 AMEL 29 External Program Memory Read Cycle 7 ALE lt gt PSEN PORT 0 INSTRIN gt gt gt taviv gt PORT 2 A8 A15 30 External Data Memory Read Cycle ALE I tavu 0 0 A7 FROM OR DATA gt A7 FROM PCL X INSTR I
38. to the device This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 27 DC Characteristics The values shown in this table are valid for T4 40 C to 85 C and 4 0V to 5 5V unless otherwise noted Symbol Parameter Condition Min Max Units Input Low Voltage Except EA 0 5 0 2 0 1 Input Low Voltage 0 5 0 2 0 3 Vin Input High Voltage Except XTAL1 RST 0 2 0 9 0 5 Input High Voltage XTAL1 RST 0 7 Voc Voct0 5 V VoL Output Low Voltage Ports 1 2 3 lg 1 6 mA 0 45 Vout Output Low Voltage Port 0 ALE PSEN lg 3 2 0 45 60 10 2 4 V us ALE SSEN 25 uA 0 75 10 pA 0 9 Vec V 7800 pA Vec 5V 10 2 4 V 2 Mode loui 909 80 pA 0 9 Voc lu Logical 0 Input Current Ports 1 2 3 Vin 0 45 50 lu Logical 1 to 0 Transition Current Ports 1 2 3 Vin 2V Voc 5V 10 650 lu Input Leakage Current Port 0 EA 0 45 lt Vin lt Vcc 10 RRST Reset Pulldown Resistor 10 30 Te

ATMEL AT89C55WD handbook (1)

Contents

Download Pdf Manuals

Related Search

Related Contents