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LINEAR TECHNOLOGY LTC1090 Manual

1. Time Time vs Source Resistance 100k 10 E RFILTER gt VREF Vin 4 Vec 5V Critter fF 5 0 TO 5V INPUT STEP E o x mud gt 1k 1 R e SOURCE IN 100 e 10 0 1 n 10 100 1000 10k 100 1k 10k CYCLE TIME us LTC1090 TPC17 Rsource LTC1090 TPC18 MAXIMUM Rgj reg REPRESENTS THE FILTER RESISTOR VALVE AT WHICH 0 1LSB SHIFT CHANGE IN FULL SCALE ERROR FROM ITS VALUE 0 IS FIRST DETECTED Ofc 8 LI Wye LIC 1090 TYPICAL PERFORMANCE CHARACTERISTICS Digital Input Logic Threshold vs Input Channel Leakage Current Supply Voltage vs Temperature Noise Error vs Reference Voltage 4 1000 2 0 Ty 25 C Pad LTC1090 NOISE 200uV PEAK TO PEAK E aw GUARANTEED p 1 5 3 8 z 25 700 4 600 1 25 2 9 a 500 8 1 0 400 x z 0 75 g 300 ON CHANNEL S 05 S 200 OFF CHANNELS P amp 100 iR 4 8 0 25 4 5 6 7 8 9 10 50 25 0 25 50 75 100 125 0 2 1 5 SUPPLY VOLTAGE Vc V AMBIENT TEMPERATURE Ta C REFERENCE VOLTAGE
2. Supply Current vs Supply Voltage Supply Current vs Temperature Reference Current vs Temperature 6 14 0 6 REF OPEN Vper 5V ACLK 2MHz 5 1 2 05 CS Ty 25 C Em 2 8 10 04 gt gt g c 08 amp 03 cc cc 2 2 2 LLI c zi 2 06 2 02 REF OPEN e 0 ACLK 2MHz m 0 4 F acy amp 01 Voc 5V 0 2 0 4 5 6 8 9 10 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 SUPPLY VOLTAGE V AMBIENT TEMPERATURE Ta C AMBIENT TEMPERATURE T C LTC1090 TPCO1 LTC1090 TPC02 LTC1090 Unadjusted Offset Error vs Linearity Error vs Reference Change in Gain Error vs Reference Voltage Voltage Reference Voltage 10 1 25 M 4125 ML L L Vec 5V Voc 5V E Voc 5V a 9 gt gt sg 10 _ amp 10 ai 8 5 6 2 0 75 a 0 75 a 4 cc a B a z 4 amp 05 05 c x 2 mos E 3 x 2 2 amp 0 25 0 25 5 x 0 0 gt 70 0 2 1 0 5 0 0 1 2 3 4 5 0 1 2 3 4 5 REFERENCE VOLTAGE Veer V REFERENCE VOLTAGE V REFERENCE VOLTAGE V LTC1090 04 LTC1090 05 LTC1090 TPCOG Change in Gain Error vs Supply Offset Error vs Supply Voltage Linearity Error vs
3. 0 496 0 512 n 12 598 13 005 20 19 18 17 16 15 14 13 12 11 1 1 0 394 0 419 10 007 10 643 Y 0 291 0 299 5 7 391 7 595 1 2 3 4 5 6 7 8 9 10 0 093 0 104 0 037 0 045 0 010 0 029 2262 2642 0 940 1 143 0254 0 737 45 g lt 2 362 2 642 0 8 TYP 0 050 0 009 0 013 1 270 E 0 004 0 012 0 229 0 330 NOTE 1 BSC 0 102 0 305 0 016 0 050 0014 0019 0 406 1 270 0 356 0 482 20 WIDE 1098 TYP NOTE 1 PIN 1 IDENT NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS DIMENSION DOES NOT INCLUDE MOLD FLASH MOLD FLASH SHALL NOT EXCEED 0 006 0 152mm PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH INTERLEAD FLASH SHALL NOT EXCEED 0 010 0 254mm PER SIDE 1090fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable TAR However no responsibility is assumed for its use Linear Technology Corporation makes no represen TECHNOLOGY tation that the interconnection of its circuits as described herein will not infringe on existing patent rights LIC 1090
4. Sign Location 77 B10 B9 B8 B7 B6 B5 B4 B3 LSB Location 87 B2 B1 BO filled with Os Diy words for LTC1090 MSBF MUX Addr UNI Word Length ODD SIGN Din 1 0 0 1 1 1 1 1 1 Din 2 0 1 1 1 1 1 1 1 Din 3 0 0 1 1 1 1 1 1 LTC1090 TAOS Sneak A Bit Code for the LTC1090 Using the MC68HC05C4 MNEMONIC DESCRIPTION LDA 4550 Configuration data for SPCR STA 0A Load configuration data into 0A LDA Configuration data for port C DDR STA 06 Load configuration data into port C DDR BSET 0 02 Make sure CS is high JSR READ Dummy read configures LTC1090 for next read JSR Read CH6 with respect to CH7 JSR READ Read CH7 with respect to CH6 JSR CHK SIGN Determines which reading has valid data converts to 2 s complement and stores in RAM Sneak A Bit Code for the 1701090 Using the MC68HC05C4 MNEMONIC DESCRIPTION READ LDA 3F Load D y word for LTC1090 into ACC JSR TRANSFER Read LTC1090 routine LDA 60 Load MSBs from LTC1090 into ACC STA 71 Store MSBs in 71 LDA 61 Load LSBs from LTC1090 into ACC STA 72 Store LSBs in 72 RTS Return READ LDA 7 Load D y word for LTC1090 into ACC JSR TRANSFER Read LTC1090 routine LDA 60 Load MSBs from LTC1090 into ACC STA 73 Store MSBs in 73 LDA 61 Load LSBs from LTC1090 into ACC STA 74 Store LSBs in 74 RTS Return TRANSFER BCLR 0 02 CS goes low STA 0C Load D y into SPI Start trans
5. wired together unless otherwise noted Note 3 5V OV V OV for unipolar mode and 5V for bipolar mode ACLK 2 0MHz SCLK 0 5MHz unless otherwise specified Note 4 These specs apply for both unipolar and bipolar modes In bipolar mode one LSB is equal to the bipolar input span 2Vper divided by 1024 For example when Vper 5V 1LSB bipolar 2 5V 1024 9 77mV Vote 5 Linearity error is specified between the actual end points of the A D transfer curve Vote 6 Total unadjusted error includes offset gain linearity multiplexer and hold step errors Vote 7 Two on chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below or one diode drop above Vcc Be careful during testing at low Vcc levels 4 5V as high level reference or analog inputs 5V can cause this input diode to conduct especially at elevated temperatures and cause errors for inputs near full scale This spec allows 50mV forward bias of either diode This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV the output code will be correct To achieve an absolute OV to 5V input voltage range will therefore require a minimum supply voltage of 4 950V over initial tolerance temperature variations and loading Vote 8 Channel leakage current is measured after the channel selection Vote
6. Circuit for the LTC1090 5 Vin CLOCK IN 1MHz MAX 1761090 TA03 SNEAK A BIT The LTC1090 s unique ability to software select the polar ity of the differential inputs and the output word length is used to achieve one more bit of resolution Using the circuit below with two conversions and some software a 2 s complement 10 bit sign word is returned to memory inside the MPU The MC68HC05C4 was chosen as an example however any processor could be used Two 10 bit unipolar conversions are performed the first over 0 to 5V span and the second over a 0 to 5 span by reversing the polarity of the inputs The sign of the input is determined by which of the two spans contained it Then the resulting number ranging from 1023 to 1023 decimal is converted to 2 s complement notation and stored in RAM Scope Trace of LTC1090 Quick Look Circuit Showing A D Output of 0101010101 155g DEGLITCHER MSB LSB FILLS TIME B9 BO ZERO SNEAK A BIT Circuit OTHER CHANNELS OR SNEAK A BIT INPUTS 5V TO 5V SNEAK A BIT is a trademark of Linear Technology Corp 10uF LTC1090 TA04 1090fc LI 23 LIC 1090 TYPICAL APPLICATION SNEAK A BIT Vin 5V 5V Vin CH6 cem negem SOFTWARE 1ST CONVERSION ov ov ov o CH7 5V 5V Y 2ND CONVERSION SNEAK A BIT Code Dour from LTC1090 in MC68HC05C4 2047 STEPS
7. ECHNOLOGY FEATURES Software Programmable Features Unipolar Bipolar Conversions 4 Differential 8 Single Ended Inputs MSB or LSB First Data Sequence Variable Data Word Length m Built In Sample and Hold Single Supply 5V 10V or 5V Operation m Direct 4 Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports m 30kHz Maximum Throughput Rate KEY SPECIFICATIONS Resolution 10 Bits m Total Unadjusted Error LTC1090A 1 2LSB Max Conversion Time 22us m Supply Current 2 5 Max 1 0mA 4J LTC and LT are registered trademarks of Linear Technology Corporation LTCMOS is a trademark of Linear Technology Corp CAD LIC 1090 single Chip 10 Bit Data Acquisition System DESCRIPTION 11071090 is a data acquisition component which contains a serial 1 0 successive approximation A D con verter It uses LTCMOS switched capacitor technology to perform either 10 bit unipolar or 9 bit plus sign bipolar A D conversions The 8 channel input multiplexer can be configured for either single ended or differential inputs or combinations thereof An on chip sample and hold is included for all single ended input channels The serial 1 0 is designed to be compatible with industry standard full duplex serial interfaces It allows either MSB or LSB first data and automatically provides 2 s complement output coding in the bipolar mode The output data word can be programmed for a length of 8 10 12 or 1
8. Serial Port Microprocessors Most synchronous serial formats contain a shift clock SCLK and two data lines one for transmitting and one for receiving In most cases data bits are transmitted on the falling edge of the clock SCLK and captured on the rising edge However serial port formats vary among MPU manufacturers as to the smallest number of bits that can be sent one group e g 4 bit 8 bit or 16 bit transfers They also vary as to the order in which the bits are transmitted LSB or MSB first The following examples show how the LTC1090 accommodates these differences National MICROWIRE COP420 The COP420 transfers data MSB first and in 4 bit incre ments nibbles This is easily accommodated by setting the LTC1090 to MSB first format and 12 bit word length The data output word is then received by the COP420 in three 4 bit blocks with the final two unused bits filled with zeroes by the LTC1090 Hardware and Software Interface to National Semiconductor COP420 Processor LTC1090 COP420 ANALOG INPUTS Dour from LTC1090 stored in COP420 RAM MSB Location A B9 B8 B7 B6 first 4 bits Location A 1 B5 B4 B2 second 4 bits LSB Location A 2 B1 BO BO third 4 bits B9 is MSB in unipolar or sign bit in bipolar MNEMONIC DESCRIPTION LEI Enable SIO SC Set Carry flag 00 GO is set to CS goes low LDD Load first 4 bits of Diy to ACC XAS Swap ACC with SIO reg Star
9. V LTC1090 TPC19 LTC1090 TPC20 LTC1090 TPC21 APPLICATIONS INFORMATION LTC1090 is a data acquisition component which DIGITAL CONSIDERATIONS contains the following functional blocks d Sertai 1 10 bit successive approximation capacitive A D converter The LTC1090 communicates with microprocessors and other external circuitry via a synchronous full duplex 2 Analog multiplexer MUX four wire serial interface see Operating Sequence The 3 Sample and hold S H shift clock SCLK synchronizes the data transfer with each bit being transmitted on the falling SCLK edge 4 Synchronous full duplex serial interface and captured on the rising SCLK edge in both transmit 5 Control and timing logic ting and receiving systems The data is transmitted and received simultaneously full duplex Operating Sequence Example Differential Inputs CH3 to CH2 Bipolar MSB First and 10 Bit Word Length 4 8 10 SCLK SGL Din DIFF E sEL1 sELo UNI MsBH wL1 wLo DON T CARE SHIFT CONFIGURATION SHIFT A D RESULT OUT AND WORD IN NEW CONFIGURATION WORD IN LTC1090 101 1090fc 7 LINEAR LIC 1090 APPLICATIONS INFORMATION Data transfer is initiated by a falling chip select CS signal After the falling CS is recognized an 8 bit input word is shifted into the Diy input which configures the LTC1090 for the next conversion Simultaneously the result o
10. 0 1uF CERAMIC DISK V should be bypassed with a 0 1uF ceramic disk For single supply applications V can be tied to the ground plane Itisalso recommended that pin 13 REF and pin 9 COM be tied directly to the ground plane All analog inputs should be referenced directly to the single point ground Digital inputs and outputs should be shielded from and or routed away from the reference and analog circuitry LTC1090 Al15 Figure 6 Example Ground Plane for the LTC1090 VERTICAL 0 5mV DIV Figure 6 shows an example of an ideal ground plane design for a two sided board Of course this much ground plane HORIZONTAL 10ps DIV will not always possible but users should strive to get Figure 7 Poor Vcc Bypassing Noise and Ripple as close to this ideal as possible can Cause A D Errors 2 Bypassing For good performance must be free of noise and ripple Any changes in the Vcc voltage with respect to analog ground during a conversion cycle can induce errors or noise in the output code noise and ripple be kept below 1mV by bypassing the Vcc pin directly to the analog ground plane with a 4 7uF tantalum with leads as shortas possible Figures 7 and 8 show the effects of good and poor Vcc bypassing VERTICAL 0 5mV DIV HORIZONTAL 10us DIV Figure 8 Good Vec Bypassing Keeps Noise and Ripple on Vcc Below 1mV 18 LI Wye LIC 1090 APPLICATIONS INFORMATION 3 Analog Inputs Because of
11. 9 To minimize errors caused by noise at the chip select input the internal circuitry waits for two ACLK falling edges after a chip select falling edge is detected before responding to control input signals Therefore no attempt should be made to clock an address in or data out until the minimum chip select setup time has elapsed LIC 1090 TEST CIRCUITS On and Off Channel Leakage Current 5V ON CHANNELS OFF CHANNELS LTC1090 01 Voltage Waveforms for Doyr Delay Time typo SCLK 11701090 TC02 Voltage Waveforms for ten and tgis Dout WAVEFORM 1 SEE NOTE 1 Dout WAVEFORM 2 SEE NOTE 2 NOTE 1 WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2 WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTP Load Circuit for tgis and ten TEST POINT 5 WAVEFORM 2 a WAVEFORM 1 LTC1090 04 UT CONTROL LTC1090 03 Load Circuit for typo tr and ty 1 4V TEST POINT LTC1090 05 1090fc 5 LTC 1090 PIN FUNCTIONS PIN FUNCTION DESCRIPTION 1 8 CHO to CH7 Analog Inputs The analog inputs must be free of noise with respect to AGND 9 COM Common The common pin defines the zero reference point for all single ended inputs It must be free of noise and i
12. a change of state on the CS input the LTC1090 waits for two falling edges of the ACLK before recognizing a valid chip select One indication of CS low recognition is the line becoming active leaving the Hi Z state Note that the deglitching applies to both the rising and falling CS edges HIGH Z VALID OUTPUT LOW CS RECOGNIZED INTERNALLY HIGH Z Dour HIGH CS RECOGNIZED INTERNALLY LTC1090 107 12 LIC 1090 APPLICATIONS INFORMATION 8 Bit Word Length lt tSMPL gt t conv cs SCLK FLELELELELELELEI SB Dour THE LAST TWO BITS MSB FIRST 89 88 87 B6 BS 84 82 ARE TRUNCATED LSB FIRST B1 B5 B7 LTC1090 AI08A 10 Bit Word Length tSMPL CS SCLK 1 10 5 Dout FIRST B9 6 5 2 SB LSB B2 5 Be Be LTC1090 Al08B 12 Bit Word Length tsmpL CS SCLK 1 0 12 5 FILL SB Dour LSB FIRST B1 BA 5 Bs BO LTC1090 AIO8C 16 Bit Word Length ni tSMPL CS SCLK 1 10 16 D E FILL 89 B8 5 ZEROES 5 D LSB FIRST B1 B2 Be Bs gt p IN UNIPOLAR MODE THES
13. selected each conversion type are shown in the figures below Unipolar Transfer Curve UNI 1 A 11111111114 11411111101 0000000001 0000000000 N OV 1LSB Vngp 2L9B VREF Vie 1LSB LTC1090 105 Vin Bipolar Transfer Curve UNI 0 A 01111111114 01111111104 VreF 1LSB 0000000001 115 0000000000 1 1 1 1 1 VREF 1 T T1111111111 Vngr 2LSB 0 118 71000000001 11000000000 LTC1090 106 1090fc LT unen 11 LIC 1090 APPLICATIONS INFORMATION Unipolar Output Code UNI 1 INPUT VOLTAGE OUTPUT CODE INPUT VOLTAGE Vrer 1111111111 1LSB 4 9951V 1111111110 2LSB 4 99021 0000000001 1LSB 0 0049V 0000000000 oV oV Bipolar Output Code UNI 0 INPUT VOLTAGE OUTPUT CODE INPUT VOLTAGE Vrer 0111111111 1LSB 4 9902V 0111111110 2LSB 4 98051 0000000001 1LSB 0 0098V 0000000000 0 1111111111 115 0 0098V 1111111110 2LSB 0 0195V 1000000001 Veer 1LSB 4 9902V 1000000000 Veer 5 000V MSB First LSB First Format MSBF The output data of the LTC1090 is programmed for MSB first or LSB first sequence using the MSBF bit For MSB first output data the input word clocked to the LTC1090 should always contain a logical one in the sixth bit location M
14. the capacitive redistribution A D conversion techniques used the analog inputs of the LTC1090 have capacitive switching input current spikes These current spikes settle quickly and do not cause a problem However if large source resistances are used or if slow settling op amps drive the inputs care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins Source Resistance The analog inputs of the LTC1090 look like a 60pF capaci tor in series with a 5000 resistor Roy as shown in Figure 9 gets switched between the selected and inputs once during each conversion cycle Large external source resistors and capacitances will slow the settling of the inputs It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within the allowed time 4TH SCLK Roy 5002 LAST SCLK 7 CIN Sn LTC1090 1101090 Al16 Figure 9 Analog Input Equivalent Circuit SAMPLE MUX ADDRESS INPUT MUST SETTLE DURING THIS TIME Input Settling This input capacitor is switched onto the input during the sample phase see Figure 10 The sample phase starts at the 4th SCLK cycle and lasts until the falling edge of the last SCLK the 8th 10th 12th or 16th SCLK cycle depending on the selected word length The voltage on the input must settle comple
15. 0 023 0 045 0 584 1 143 0 220 0 310 0 025 HALF LEAD 5588 7874 0 635 OPTION RAD TYP 0 045 0 068 1 143 1 727 FULL LEAD OPTION 0 005 0 300 BSC 0 127 5 080 0 762 BSC MIN MAX 0 015 0 060 0 381 1 524 LI Er BT x 0 008 0 018 awe 0 203 0 457 gt 0 125 E 8 175 0 045 0 065 0 100 NOTE LEAD DIMENSIONS APPLY TO SOLDER DIP PLATE MIN 1 143 1 851 2 54 OR TIN PLATE LEADS 0 014 0 026 BSC 0 356 0 660 20 1298 OBSOLETE PACKAGE 1090fc LI MYR 2o LIC 1090 PACKAGE DESCRIPTION N Package 20 Lead PDIP Narrow 300 Inch Reference LTC DWG 05 08 1510 0 255 0 015 6 477 0 381 0 300 0 325 _ 0 130 0 005 0045 0065 7 620 8 255 8 302 0 127 1 143 1 651 0 020 A 0 508 Y Y MIN Eg 0 065 0 009 0 015 1 lt i 1 m 1 651 0 229 0 381 TYP Y 40 035 955 0050 0125 0005 00 x 0 018 0 003 EI 8175 0 127 0 54 gt 0457 40 076 8 255 20281 IN MIN BSC 457 t 0 THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0 010 INCH 0 254mm N20 1098 20 17 LIC 1090 PACKAGE DESCRIPTION SW Package 20 Lead Plastic Small Outline Wide 300 Inch Reference LTC DWG 05 08 1620
16. 6 bits This allows easy interface to shift registers and a variety of processors The LTC1090A is specified with total unadjusted error including the effects of offset linearity and gain errors less than 0 5LSB The LTC1090 is specified with offset and linearity less than 0 5LSB but with a gain error limit of 2LSB for applications where gain is adjustable or less critical TYPICAL APPLICATION FOR 8051 CODE SEE APPLICATIONS INFORMATION SECTION LTC1090 MPU e g 8051 DIFFERENTIAL INPUT BIPOLAR INPUT SERIAL DATA LINK UNIPOLAR f INPUT Linearity Plot ERROR LSBs 0 512 1024 OUTPUT CODE 1090fc 1 LIC 1090 ABSOLUTE MAXIMUM RATINGS Notes 1 and 2 Supply Voltage Voc to GND or V 12V Negative Supply Voltage V 6V to GND Voltage Analog and Reference V7 0 3V to Vec 0 3V Digital 0 3V to 12V Digital Outputs 0 3V to Vec 0 3V Power 01551 500mW Operating Temperature Range LTC1090AC LTC10906C 40 to 85 C LTC1090AM LTC1090M OBSOLETE 55 C to 125 C Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 10 5 300 C PACKAGC ORDER INFORMATION ORDER
17. AXIMUM ACLK FREQUENCY REPRESENTS THE ACLK FREQUENCY AT WHICH A 0 1LSB SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 2MHz VALVE IS FIRST DETECTED LTC1090 TPC16 Change in Linearity Error vs Temperature 0 6 Vee 5V VREF 0 5 F ACLK 2MHz 25 0 2 50 75 100 125 AMBIENT TEMPERATURE T LTC1090 TPC11 0 50 MAGNITUDE OF LINEARITY CHANGE ALINEARITY LSBs Maximum Conversion Clock Rate vs Reference Voltage 5 1 Voc 5V Ta 25 C 4 e amp a 3 amp mE o 2 lt gt 1 lt 0 0 1 2 3 4 5 REFERENCE VOLTAGE V LTC1090 TPC14 Maximum Filter Resistor vs Cycle MAGNITUDE OF GAIN CHANGE AGAIN LSBs MAXIMUM ACLK FREQUENCY MHz Change in Gain Error vs Temperature 8 5 Vngr 5V 05 F ACLK 2MHz 04 0 3 02 0 1 0 o 50 25 0 25 50 75 100 125 AMBIENT TEMPERATURE T LTC1090 TPC12 Maximum Conversion Clock Rate vs Supply Voltage 4 5 6 7 8 9 10 SUPPLY VOLTAGE Vgc V LTC1090 TPC15 Sample and Hold Acquisition
18. C 4 Rotate right into ACC 4 MOV R3 A Store LSBs in R3 SETB P1 3 SCLK goes high CLR P1 3 SCLK goes low SETB P1 4 CS goes high from LTC1090 stored 8051 RAM MOV R5 07H Load counter DELAY DJNZ R5 DELAY Delay for LTC1090 to perform MSB conversion AJMP CONTINUE Repeat program R2 B9 B8 B7 B6 B5 B4 B3 B2 LSB R3 BO 0 0 0 0 0 0 B9 is MSB in unipolar or sign bit in bipolar 210 OUTPUT P 3 WIRE SERIAL SERIAL aui INTERFACE TO OTHER 05 1101090 1701090 PERIPHERALS 117010905 8 CHANNELS 8 CHANNELS CHANNELS LTC1090 14 MPU Figure 5 Several LTC1090 s Sharing One 3 Wire Serial Interface 1090fc AL MYR 17 LTC 1090 APPLICATIONS INFORMATION 6 Sharing the Serial Interface The LTC1090 can share the same 3 wire serial interface with other peripheral components or other LTC1090s see Figure 5 In this case the CS signals decide which LTC1090 is being addressed by the MPU 4 7uF TANTALUM ANALOG CONSIDERATIONS 1 Grounding The LTC1090 should be used with an analog ground plane and single point grounding techniques Pin 11 AGND should be tied directly to this ground plane Pin 10 DGND can also be tied directly to this ground plane because minimal digital noise is generated within the chip itself ANALOG GROUND Pin 20 Vcc should be bypassed to the ground plane with PLANE 4 7uF tantalum with leads as short as possible Pin 12
19. E BITS ARE FILLED WITH ZEROES IN BIPOLAR MODE THE SIGN BIT IS EXTENDED INTO THESE LOCATIONS Figure 2 Data Output Doyr Timing with Different Word Lengths 1090fc AC ure 13 LTC 1090 APPLICATIONS INFORMATION 4 CS Low During Conversion In the normal mode of operation CS is brought high Dour line will become active with the first output bit Then during the conversion time see Figure 3 The serial port the data transfer can begin as normal ignores any SCLK activity while CS is high The LTC1090 will also operate with CS low during the conversion Inthis 5 Microprocessor Interfaces mode SCLK must remain low during the conversion aS 101090 can interface directly without external hard shown in Figure 4 After the conversion is complete the ware to most popular microprocessor MPU synchronous SHIFT MUX SAMPLE SHIFT RESULT OUT ADDRESS ANALOG T 40 TO 44 ACLK CYCLES 1 AND NEW ADDRESS IN i m IN INPUT CS SGL SEL SEL SGL SEL Din Loire 909 1 0 un user wio DON T CARE 000 1 E UNI user was wie B9 B8 B7 B6 BS B4 B3 B2 BO B9 B8 B7 B6 BS B4 B3 B2 B1 BO 11701090 109 Figure 3 CS High During Conversion SHIFT SAMPLE ANALOG INPUT SCLK LELFLELFLIELELELE LT sotx must remain ow LELILFLELELFELELELI I SGL SEL SEL SGL SEL Din aire 220 1 0 funi wi wo DON T CARE aire 0007 1 seu UNI
20. PART CHO Voc NUMBER CH1 ACLK LTC1090ACN LTC1090CN OUT LTC1090CSW CH6 REF CH7 COM V DGND AGND SW PACKAGE N PACKAGE 20 LEAD PLASTIC SO WIDE 20 LEAD PDIP 150 C 70 C W 110 C 90 C W J PACKAGE LTC1090AMJ 20 m a LTC1090MJ LTC1090ACJ LTC1090CJ OBSOLETE PACKAGE Consider the SW or N Package for Alternate Source 1101090 Consult LTC Marketing for parts specified with wider operating temperature ranges RECOMMENDED OPERATING CONDITIONS LTC1090 LTC1090A SYMBOL PARAMETER CONDITIONS MIN MAX UNITS Vec Positive Supply Voltage V 0V 4 5 10 V Negative Supply Voltage Voc 5V 5 5 0 Shift Clock Frequency Vcc 5V 0 1 0 MHz TACLK A D Clock Frequency Voc 5V 25 C 0 01 2 0 MHz 85 C 0 05 2 0 125 C 0 25 2 0 Total Cycle Time See Operating Sequence 10 SCLK Cycles 48 ACLK thes Hold Time CS Low After Last SCLK Voc 5V 0 ns thpi Hold Time D y After SCLKT Voc 5V 150 ns 1065 Setup Time CS4 Before Clocking in First Address Bit Note 9 Voc 5V 2 ACLK Cycles Tus tsupi Setup Time D y Stable Before SCLKT Vec 5V 400 ns tWHACLK ACLK High Time Vcc 5V 127 ns twractk ACLK Low Time Voc 5V 200 ns twues CS High Time During Conversion Voc 5V 44 ACLK Cycles 2 LIC 1090 CONVERTER AND MULTIPLEXER CHARACTERISTICS The denotes specifications which apply over the full operatin
21. RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1290 8 Channel Configurable 5V 12 Bit ADC Pin Compatible with LTC 1090 LTC1391 Serial Controlled 8 to 1 Analog Multiplexer Low Ron Low Power 16 Pin SO and SSOP Package LTC1594L LTC1598L 4 8 Channel 3V Micropower 12 Bit ADC Low Power Small Size LTC1850 LTC1851 10 Bit 12 Bit 8 Channel 1 25Msps ADCs 5V Programmable MUX and Sequencer LTC1852 LTC1853 10 Bit 12 Bit 8 Channel 400ksps ADCs 3V or 5V Programmable MUX and Sequencer LTC2404 LTC2408 24 Bit 4 8 Channel No Latency AX ADC 4ppm INL 10ppm Total Unadjusted Error 200uA LTC2424 LTC2428 20 Bit 4 8 Channel No Latency AX ADC 1 2ppm Noise 8ppm INL Pin Compatible with LTC2404 LTC2408 No Latency is a trademark of Linear Technology Corporation Linear Technology Corporation 1630 McCarthy Blvd Milpitas CA 95035 7417 408 432 1900 FAX 408 434 0507 e www linear com 1090fc LW TP 0902 1K REV C PRINTED IN USA TECHNOLOGY LINEAR TECHNOLOGY CORPORATION 1990
22. Remains Valid After SCLK 1 50 ns tf Dour Fall Time See Test Circuits e 90 300 ns ns tr Dour Rise Time See Test Circuits e 60 300 ns ns Cin Input Capacitance Analog Inputs Channel 65 pF Off Channel 5 pF Digital Inputs 5 pF 1090fc 3 LIC 1090 DIGITAL AND DC ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range otherwise specification are 25 C Note 3 LTC1090 LTC1090A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Vin High Level Input Voltage Voc 5 25V e 20 V VIL Low Level Input Voltage Vec 4 75V 0 8 High Level Input Current Vin Vec e 2 5 uA li Low Level Input Current Vin OV 2 5 High Level Output Voltage Vec 4 75V lg 100A 4 7 V Vec 4 75V lo 360 e 24 4 0 V VoL Low Level Output Voltage Vec 4 75V lp 1 6mA e 0 4 V loz Hi Z Output Leakage Vout CS High 3 uA Vout OV CS High e 3 uA ISoURCE Output Source Current Vout OV 10 mA ISINK Output Sink Current Vout 10 mA lec Positive Supply Current CS High REF Open 1 0 2 5 Reference Current Vner 5V e 0 5 1 0 mA Negative Supply Current CS High 5V e 1 50 Note 1 Absolute Maximum Ratings are those values beyond which the life of a device may be impaired Vote 2 voltage values are with respect to ground with DGND AGND and
23. SBF bit Likewise for LSB first output data the input word clocked to the LTC1090 should always contain a zero the MSBF bit location The MSBF bit in a given D y word will control the order of the next Doyr word The MSBF bit affects only the order of the output data word The order of the input word is unaffected by this bit MSBF OUTPUT FORMAT 0 LSB First 1 MSB First Word Length WL1 WLO The last two bits of the input word WL1 WLO program the output data word length of the LTC1090 Word lengths of 8 10 12 or 16 bits can be selected according to the following table The WL1 and WLO bits in a given Diy word control the length of the present not the next word and WLO are never don tcares and must besetfor the correct Doyr word length even when a dummy Diy word is sent On any transfer cycle the word length should be made equal to the number of SCLK cycles sent by the MPU WL1 WLO OUTPUT WORD LENGTH 0 0 8 Bits 0 1 10 Bits 1 0 12 Bits 1 1 16 Bits Figure 2 shows how the data output Dour timing can be controlled with word length selection and MSB LSB first format selection 3 Deglitcher A deglitching circuit has been added to the Chip Select input of the LTC1090 to minimize the effects of errors caused by noiseonthatinput This circuit ignores changes in state on the CS input that are shorter in duration than 1 ACLK cycle After
24. Supply Voltage Voltage 1 25 0 5 Vggr 4V Vggr 4V 4V ACLK 2MHz ACLK 2MHz ACLK 2MHz 10 Vos 1 25mV Vcc 5V _ 10 E 0 25 n wn 2 ec 20 75 0 75 0 e ecc z S 05 05 0 25 im z e z z zi lt 0 25 0 25 5 05 0 0 4 5 6 7 8 9 10 4 5 6 7 8 9 10 4 5 6 7 8 9 10 SUPPLY VOLTAGE V SUPPLY VOLTAGE V SUPPLY VOLTAGE V LTC1090 07 LTC1090 TPC08 LTC1090 09 1090fc 7 LINEAR 7 LTC 1090 TYPICAL PERFORMANCE CHARACTERISTICS Change in Offset Error vs Temperature Fa 06 Veg 5V d VREF 5V 05 F ACLK 2MHz lt 04 03 72 02 e LL 04 E S 0 lt amp 50 25 0 2 50 75 100 125 AMBIENT TEMPERATURE T LTC1090 TPC10 Maximum Conversion Clock Rate vs Temperature MAXIMUM ACLK FREQUENCY MHz Vngr 5V L 0 50 25 0 25 50 75 100 125 AMBIENT TEMPERATURE LTC1090 TPC13 Maximum Conversion Clock Rate vs Source Resistance 5 Voc 5V i Vngr 5V 4 Ta 25 C 4 E c d a 3 oc gt Vin 2r lt 2 1 gt gt lt 2 i SOURCE 0 10 100 1k 10k RsouncE 9 M
25. ation STA Start next SPI cycle t NOP 6 NOPs for timing BSET C0 is set CS goes high LDA Load contents of SPI status reg into ACC LDA Load LTC1090 Dour from SPI data reg into ACC byte 2 STA Load LTC1090 Dour into RAM location A 1 Hitachi Synchronous SCI HD63705 The HD63705 transfers serial data in 8 bit increments LSB first To accommodate this the LTC1090 is programmed for 16 bit word length and LSB first format The 10 bit output data is received by the processor as two 8 bit bytes LSB first The LTC1090 fills the final 6 unused bits afterthe MSB with zeroes in unipolar mode and with the sign bit in bipolar mode Hardware and Software Interface to Hitachi HD63705 Processor LTC1090 HD63705 ANALOG INPUTS Dour from LTC1090 stored in HD63705 RAM LSB Location A B7 B6 B5 B4 B2 byte 1 Sign lt Location A 1 B9 B9 B9 B9 B9 B9 B9 B8 byte2 Bipolar LSB Location A B7 B5 B2 BO byte 1 MSB Location A 1 0 0 0 0 0 08988 byte2 Unipolar LICI000 Ala MNEMONIC DESCRIPTION LDA Load word for LTC1090 into ACC from RAM BCLR n CO cleared CS goes low STA Load word for LTC1090 into SCI data reg from ACC and start clocking data LSB first 1 6 NOPs for timing LDA Load contents of SCI data reg into ACC byte 1 Start next SCI cycle STA Load LTC1090 Doyr word into RAM Location NOP Tim
26. f the previous conversion is output on the Dour line At the end ofthe data exchange the requested conversion begins and CS should be brought high After the conversion is complete and the results will be available on the next data transfer cycle As shown below the result of a conversion is delayed by one CS cycle from the input word requesting it Multiplexer MLIX Address The first four bits of the input word assign the MUX configuration for the requested conversion For a given channel selection the converter will measure the voltage between the two channels indicated by the and signs in the selected row of Table 1 Note that in differential mode SGL DIFF 0 measurements are limited to four adjacent input pairs with either polarity In single ended mode all input channels are measured with respect to COM Figure 1 shows some examples of multiplexer assignments Table 1 Multiplexer Channel Selection Diy Diy Word Diy Word 2 Diy Word Dour Dour Word 0 Dour Word 1 Dour Word 2 MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION T SGL ODD SELECT Data phe ND Data e WD oy DIFF sien 1 0 1 2 5 6 7 Transfer Conversion Transfer Conversion Teien sana o o jlo 30 e 2 Input Data Word i aM The LTC1090 8 bit input da
27. fer LOOP 1 TST 0B Test status of SPIF BPL LOOP 1 Loop to previous instruction if not done LDA 0C Load contents of SPI data reg into ACC STA 0C Start next cycle STA 60 Store MSBs in 60 LOOP 2 TST 0B Test status of SPIF BPL LOOP 2 Loop to previous instruction if not done BSET 0 02 CS goes high LDA 0C Load contents of SPI data reg into ACC STA 61 Store LSBs in 61 RTS Return CHK SIGN LDA 73 Load MSBs of read into ACC ORA 74 Or ACC MSBs with LSBs of read BEQ MINUS If result is 0 goto minus CLC Clear carry ROR 73 Rotate right 73 through carry ROR 74 Rotate right 74 through carry LDA 73 Load MSBs of read into ACC STA 77 Store MSBs in RAM location 77 LDA 74 Load LSBs of read into ACC STA 87 Store LSBs in RAM location 87 BRA END Goto end of routine MINUS CLC Clear carry ROR 71 Shift MSBs of read right ROR 72 Shift LSBs of read right COM 71 1 s complement of MSBs COM 72 1 s complement of LSBs LDA 72 Load LSBs into ACC ADD 01 Add 1 to LSBs STA 72 Store ACC in 72 CLRA Clear ACC ADC 71 Add with carry to MSBs Result in ACC STA 71 Store ACC in 71 STA 77 Store MSBs in RAM location 77 LDA 72 Load LSBs in ACC STA 87 Store LSBs in RAM location 87 END RTS Return 24 LIC 1090 PACKAGE DESCRIPTION J Package 20 Lead CERDIP Narrow 300 Inch Hermetic Reference LTC DWG 05 08 1110 1 060 lt gt CORNER LEADS OPTION B3 4 PLCS
28. g inputs with an op amp it is important that the op amp settle within the allowed time see Figure 10 Again the and input sampling times can be extended as described above to accommo date slower op amps Most op amps including the LT1006 and LT1013 single supply op amps can be made to settle well even with the minimum settling windows of 4us input and 2us input which occur at the maximum clock rates ACLK 2MHz and SCLK 1 MHz Figures 11 and 12 show examples of adequate and poor op amp settling VERTICAL 5mV DIV HORIZONTAL 1us DIV Figure 11 Adequate Settling of Op Amp Driving Analog Input VERTICAL 5mV DIV HORIZONTAL 2us DIV Figure 12 Poor Op Amp Settling can Cause A D Errors RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 13 For large values of Cr e g 1uF the capacitive input switching currents are averaged into a net DC current Therefore a filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor The magnitude of the DC current is approximately Ipc 60pF x and is roughly propor tional to Viy When running at the minimum cycle time of 33us the input current equals 9uA at Viy 5V In this case afilter resistor of 50 2 will cause 0 1LSB of full scale error If a larger filter resistor must be used errors can be eliminated by increasing the cycle time as s
29. g temperature range otherwise specifications are 25 C Note 3 LTC1090A LTC1090 PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Offset Error Note 4 0 5 0 5 LSB Linearity Error Notes 4 and 5 e 0 5 0 5 LSB Gain Error Note 4 1 0 2 0 LSB Total Unadjusted Error Veer 5 000V 1 0 LSB Notes 4 and 6 Reference Input Resistance 10 10 Analog and REF Input Range Note 7 V7 0 05V to Vec 0 05V V On Channel Leakage Current On Channel 5V e 1 1 uA Note 8 Off Channel On Channel 1 uA Off Channel 5V Off Channel Leakage Current On Channel 5V e 1 1 uA Note 8 Off Channel On Channel 0V 1 1 uA Off Channel 5V AC ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range otherwise specification are 25 C Note 3 LTC1090 LTC1090A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tacc Delay Time From CS to Doyr Data Valid Note 9 2 ACLK Cycles Analog Input Sample Time See Operating Sequence 5 SCLK Cycles tconv Conversion Time See Operating Sequence 44 ACLK Cycles tapo Delay Time SCLK to Data Valid See Test Circuits 250 450 ns ldis Delay Time 657 to Doyr Hi Z See Test Circuits e 140 300 ns ns len Delay Time 2nd CLK4 to Doyr Enabled See Test Circuits e 150 400 ns ns tho Time Output Data
30. herefore the maximum ACLK frequency should be reduced when low values of Vpgr are used This is shown in the typical curve of Maximum Conversion Clock Rate vs Reference Voltage Offset with Reduced The offset of the LTC1090 has a larger effect on the output code when the A D is operated with reduced reference voltage The offset which is typically a fixed voltage becomes a larger fraction of an LSB as the size of the LSB is reduced The typical curve of Unadjusted Offset Error vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of Vos For example Vos of 0 5mV which is 0 1LSB with a 5V reference becomes 0 5LSB with a 1V reference and 2 5LSBs with a 0 2V reference If this offset is unacceptable it can be corrected digitally by the receiving system or by offsetting the input to the LTC1090 Noise with Reduced Vper The total input referred noise of the LTC1090 can be reduced to approximately 200uV peak to peak using a ground plane good bypassing good layout techniques and minimizing noise on the reference inputs This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced The typical curve of Noise Error vs Reference Voltage shows the LSB contribution of this 200uV of noise For operation with a 5V reference the 200uV noise is only 0 04LSB peak to peak In this case the LTC1090 noise will contribu
31. hown in the typical curve of Maximum Filter Resistor vs Cycle Time Rura D LTC1090 LTC1090 AI18 Figure 13 RC Input Filtering Input Leakage Current Input leakage currents can also create errors if the source resistance gets too large For instance the maximum input leakage specification of 1uA at 125 C flowing through a source resistance of 1kQ will cause a voltage drop of 1mV or 0 2LSB This error will be much reduced at lower temperatures because leakage drops rapidly see typical curve of Input Channel Leakage Current vs Temperature Noise Coupling into Inputs High source resistance input signals gt 500 are more sensitive to coupling from external sources Itis preferable to use channels near the center of the package i e CH2 to CH7 for signals which have the highest output resistance because they are essentially shielded by the pins on the package ends DGND and CHO Grounding any unused inputs especially the end pin CHO will also reduce outside coupling into high source resistances 4 Sample and Hold Single Ended Inputs The LTC1090 provides a built in sample and hold S amp H function for all signals acquired in the single ended mode COM pin grounded This sample and hold allows the LTC1090 to convert rapidly varying signals see typical curve of S amp H Acquisition Time vs Source Resistance The input voltage is sampled during the teyp time as shown in Figure 10 The sampling inter
32. ing __ BSET n CO set CS goes high LDA Load contents of SCI data reg into ACC byte 2 STA Load LTC1090 word into RAM Location A 1 1090fc LIC 1090 APPLICATIONS INFORMATION Parallel Port Microprocessors 8051 Code MNEMONI DESCRIPTION When interfacing the LTC1090 to an MPU which has a T E L parallel port the serial signals are created on the port with software Three MPU port lines are programmed to create CLR P1 3 SCLK goes low the CS SCLK and D y signals for the LTC1090 A fourth SETB P1 4 CS goes high port line reads the line An example is made of the CONTINUE MOV A 0DH 1 1 101090 is MOV R4 08 Load counter Intel 8051 NOP Delay for deglitcher LOOP MOV C P1 1 Read data bit into carry To interface to the 8051 the LTC1090 is programmed for RLCA Rotate data bit into ACC MSB first format and 10 bit word length The 8051 gener MOV P1 2 C Output Diy bit to LTC1090 ates CS SCLK and D y on three port lines and reads Dout SETB P1 3 SCLK goes high the fourth CLR P1 3 SCLK goes low on DJNZ R4 LOOP Next bit MOV R2 A Store MSBs in R2 Hardware and Software Interface to Intel 8051 Processor MOV C P1 1 Read data bit into carry CLR A Clear ACC ne Rotate data bit into SETB P1 3 SCLK goes high CLR P1 3 SCLK goes low MOV C P1 1 Read data bit into carry RRC A Rotate right into AC
33. its peak value would have to be 150mV 5 Reference Inputs The voltage between the reference inputs of the LTC1090 defines the voltage span of the A D converter The refer ence inputs look primarily like a 10kQ resistor but will have transient capacitive switching currents due to the switched capacitor conversion technique see Figure 14 During each bit test of the conversion every 4 ACLK cycles a capacitive current spike will be generated on the reference pins by the A D These current spikes settle quickly and do not cause a problem However if slow settling circuitry is used to drive the reference inputs care must be taken to insure that transients caused by these current spikes settle completely during each bit test of the conversion When driving the reference inputs three things should be kept in mind 1 The source resistance driving the reference inputs should be low less than 19 to prevent DC drops caused by the 1mA maximum reference current Ing Transients on the reference inputs caused by the capacitive switching currents must settle completely during each bit test each 4 ACLK cycles Figures 15 and 16 show examples of both adequate and poor settling Using a slower ACLK will allow more time for the reference to settle However even at the maximum ACLK rate of 2MHz most references and op amps can be made to settle within the 2us bit time It is recommended that the i
34. nput be tied directly to the analog ground plane If REF is biased ata voltage other than ground the voltage must not change during a conversion cycle This voltage must also be free of noise and ripple with respect to analog ground EVERY 4 ACLK CYCLES Ron We 3 LTC1090 VREF REF LTC1090 A119 Figure 14 Reference Input Equivalent Circuit VERTICAL 0 5mV DIV HORIZONTAL 1us DIV Figure 15 Adequate Reference Settling 1090fc 21 LIC 1090 APPLICATIONS INFORMATION VERTICAL 0 5mV DIV HORIZONTAL 1us DIV Figure 16 Poor Reference Settling Can Cause A D Errors 6 Reduced Reference Operation The effective resolution of the LTC1090 can be increased by reducing the input span of the converter The LTC1090 exhibits good linearity and gain over a wide range of reference voltages see typical curves of Linearity and Gain Error vs Reference Voltage However care must be taken when operating at low values of because of the reduced LSB step size and the resulting higher accuracy requirement placed onthe converter The following factors must be considered when operating at low Vggr values 1 Conversion speed ACLK frequency 2 Offset 3 Noise Conversion Speed with Reduced VREF With reduced reference voltages the LSB step size is reduced and the LTC1090 internal comparator overdrive is reduced With less overdrive more time is required to perform a conversion T
35. s usually tied to the analog ground plane 10 DGND Digital Ground This is the ground for the internal logic Tie to the ground plane 11 AGND Analog Ground AGND should be tied directly to the analog ground plane 12 V Negative Supply Tie to most negative potential in the circuit Ground in single supply applications 13 14 Reference Inputs The reference inputs must be kept free of noise with respect to AGND 15 CS Chip Select Input A logic low on this input enables data transfer 16 Digital Data Output The A D conversion result is shifted out of this output 17 Din Data Input The A D configuration word is shifted into this input 18 SCLK Shift Clock This clock synchronizes the serial data transfer 19 ACLK A D Conversion Clock This clock controls the A D conversion process 20 Vcc Positive Supply This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane BLOCK DIAGRAM INPUT SHIFT REGISTER ANALOG INPUT MUX OUTPUT SHIFT D REGISTER SAMPLE AND HOLD 10 BIT CAPACITIVE DAC CONTROL B AND CS TIMING REF REF LTC1090 001 LIC 1090 TYPICAL PERFORMANCE CHARACTERISTICS
36. ser we wo Dour B9 B8 B7 B6 BS B4 B3 B2 BO B9 88 87 B6 B5 B4 B3 B2 B1 BO SHIFT RESULT OUT 40 TO 44 ACLK CYCLES gt lt AND NEW ADDRESS IN LTC1090 Al10 Figure 4 CS Low During Conversion 14 LY une LIC 1090 APPLICATIONS INFORMATION serial formats See Table 2 If an MPU without a serial interface is used then 4 of the MPU s parallel portlines can be programmed to form the serial link to the LTC1090 Included here are three serial interface examples and one example showing a parallel port programmed to form the serial interface Table 2 Microprocessors with Hardware Serial Interfaces Compatible with the LTC1090 PART NUMBER TYPE OF INTERFACE Motorola 680552 53 SPI MC68HC11 SPI MC68HC05 SPI RCA CDP68HC05 SPI Hitachi HD6305 SCI Synchronous HD63705 SCI Synchronous HD6301 SCI Synchronous HD63701 SCI Synchronous HD6303 SCI Synchronous National Semiconductor COP400 Family MICROWIRE COP800 Family MICROWIRE PLUST NS8050U MICROWIRE PLUS HPC16000 Family MICROWIRE PLUS Texas Instruments TMS7002 Serial Port TMS7042 Serial Port TMS70C02 Serial Port TMS70C42 Serial Port TMS32011 Serial Port TMS32020 Serial Port Requires external hardware Contact LTC Marketing for interface information for processors not on this list tMICROWIRE and MICROWIRE PLUS are trademarks of National Semiconductor Corp
37. ta word is clocked into theDiy H H input on the first eight rising SCLK edges after chip select is recognized Further inputs on the Djy pin are then USE Rn ignored until the next CS cycle The eight bits of the input UN NE ae word are defined as follows ae SS DL oW sl 11 4 4 Unipolar SE Wore iud OR MUX ADDRESS SINGLE ENDED CHANNEL SELECTION DF osen um mser wer wio DE SIGN Pi 11 2 5 6 7 0 MUX Address MSB First 0 LSB First 1 0 0 1 0 1 0 0 11 14 00 11 01 1 4 1 0 13 11 10 LIC 1090 APPLICATIONS INFORMATION 4 Differential 8 Single Ended Combinations of Differential and Single Ended CHANNEL CHANNEL CHANNEL 0 0 1 1 0 1 2 23 3 t 231 4 l 5 45 6 7 t 67 COM 5 1101090 AI048 Changing the MUX Assignment On the Fly LTC1090 Al04C LTC1090 AI04A COM UNUSED 1ST CONVERSION 2ND CONVERSION LTC1090 1040 LTC1090 104 Figure 1 Examples of Multiplexer Options on the LTC1090 Unipolar Bipolar UNI The fifth input bit UNI determines whether the conver inputvoltage When UNI isa logical zero a bipolar conver sion will be unipolar or bipolar When UNI is alogicalone sion will result The input span and code assignment for a unipolar conversion will be performed on the
38. te virtually no uncertainty to the output code However for reduced references the noise may become asignificant fraction of an LSB and cause undesirable jitter in the output code For example with a 1V reference this same 200uV noise is 0 2LSB peak to peak This will reduce the range of input voltages over which a stable output code can be achieved by 0 2L SB If the reference is further reduced to 200mV the 200uV noise becomes equal to one LSB and a stable code may be difficult to achieve Inthis case averaging readings may be necessary This noise data was taken in a very clean setup Any setup induced noise noise or ripple on Vcc Veer Vin or V7 will add to the internal noise The lower the reference voltage to be used the more critical it becomes to have a clean noise free setup 22 LIC 1090 TYPICAL APPLICATION A Quick Look Circuit for the 1701090 Users can get a quick look at the function and timing of the LTC1090 by using the following simple circuit REF and Din are tied to Vcc selecting a 5V input span CH7 as a single ended input unipolar mode MSB first format and 16 bit word length ACLK and SCLK are tied together and driven by an external clock CS is driven at 1 64 the clock rate by the 004520 and Doyr outputs the data All other pins are tied to a ground plane The output data from the Dour pin can be viewed on an oscilloscope which is set up to trigger on the falling edge of CS A Quick Look
39. tely within this sample time Minimizing Rsource and C1 will improve the input settling time If large input source resistance must be used the sample time can be increased by using a slower SCLK frequency or selecting a longer word length With the minimum possible sample time of 4us Rsgurce lt 2k and C1 20pF will provide adequate settling Input Settling Atthe end ofthe sample phase the input capacitor switches to the input and the conversion starts see Figure 10 During the conversion the input voltage is effectively held by the sample and hold and will not affect the conversion result However it is critical that the input voltage be free of noise and settle completely during the first four ACLK cycles of the conversion time Minimizing Rsgurce and C2 will improve settling time If large inputsource resistance must be used the time allowed for settling can be extended by using a slower ACLK frequency At the maximum ACLK rate of 2MHz Rsgurce lt 1kQ and C2 lt 20pF will provide adequate settling HOLD SHIFTED IN siis 15 SCLK 1 2 3 4 ACLK eee 1 2 3 4 15 BIT INPUT MUST SETTLE DURING THIS TIME 4 INPUT INPUT N LTC1090 A17 Figure 10 and Input Settling Windows 1090fc 19 LIC 1090 APPLICATIONS INFORMATION Input Op Amps When driving the analo
40. ts SK Clk LDD Load 2nd 4 bits of Dy to ACC NOP Timing XAS Swap first 4 bits from A D with ACC SK continues XIS Put first 4 bits in RAM location A NOP Timing XAS Swap 2nd 4 bits from A D with ACC SK continues XIS Put 2nd 4 bits in RAM location A 1 RC Clear Carry NOP Timing XAS Swap 3rd 4 bits from A D with ACC SK off XIS Put 3rd 4 bits in RAM location A 2 061 00 is set to 1 CS goes high LEI Disable SIO 1090fc 15 LIC 1090 APPLICATIONS INFORMATION Motorola SPI MC68HC05C4 The MC68HC05C4 transfers data first and in 8 bit increments Programming the LTC1090 for MSB first format and 16 bit word length allows the 10 bit data output to be received by the MPU as two 8 hit bytes with the final 6 unused bits filled with zeroes by the LTC1090 Hardware and Software Interface to Motorola MC68HC05C4 Processor LTC1090 MC68HCO5C4 ANALOG INPUTS Dour from LTC1090 stored in MC68HCO5C4 RAM MSB Location A B9 B8 B7 B6 B5 2 byte 1 LSB Location A 1 B1 BO 0 0 0 0 0 0 byte2 B9 is MSB in unipolar or sign bit in bipolar LTC1090 2 MNEMONIC DESCRIPTION BCLR n CO is cleared CS goes Low LDA Load D y for LTC1090 into ACC STA Load Diy from ACC to SPI data reg Start SCK t NOP 8 NOPs for timing LDA Load contents of SPI status reg into ACC LDA Load LTC1090 Dour from SPI data reg into ACC byte 1 STA Load LTC1090 Doyr into RAM loc
41. val begins after the fourth 1090fc 20 LIC 1090 APPLICATIONS INFORMATION MUX address bit is shifted in and continues during the remainder of the data transfer On the falling edge of the final SCLK the S amp H goes into hold mode and the conver sion begins The voltage will be held on either the 8th 10th 12th or 16th falling edge of the SCLK depending on the word length selected Differential Inputs With differential inputs or when the COM pin is not tied to ground the A D no longer converts just a single voltage but rather the difference between two voltages In these cases the voltage on the selected inputis still sampled and held and therefore may be rapidly time varying just as in single ended mode However the voltage on the se lected input must remain constant and be free of noise and ripple throughout the conversion time Otherwise the differencing operation may not be performed accurately The conversion time is 44 ACLK cycles Therefore a change in the input voltage during this interval can input this error would be VERROR Vpeak X 2 X x X f 44 Where f is the frequency of the input voltage Vpga Is its peak amplitude and fac is the frequency of the ACLK In most cases Vennon will not be significant For a 60Hz signal on the input to generate a 1 4LSB error 1 25mV with the converter running at ACLK 2MHz

LINEAR TECHNOLOGY LTC1090 Manual

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