ANALOG DEVICES +3 Volt Serial Input Complete 12-Bit DAC AD8300 handbook
Contents
1. 300 C Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ORDERING GUIDE Package Package Model INL Temp Description Options AD8300AN 7 XIND 8 Lead P DIP N 8 AD8300AR nif XIND 8 Lead SOIC SO 8 NOTES XIND 40 C to 85 C The AD8300 contains 630 transistors The die size measures 72 mil x 65 mil PIN CONFIGURATIONS SO 8 Plastic DIP 5 ME EIS er cus ICD SDI 4 5 LD PIN DESCRIPTIONS Function Positive power supply input Specified range of operation 2 7 V to 5 5 V Chip Select active low input Disables shift register loading when high Does not affect LD operation Clock input positive edge clocks data into shift register Serial Data Input input data loads directly into the shift register MSB first Load DAC register strobes active low Transfers shift register data to DAC register See Truth Table I for operation Asynchro nous active low input Resets DAC register to zero condition Asynchronous active low input Analog and Digital Ground DAC voltage output 2 0475 V full scale with 0 5 mV per bit An internal tempera ture stabilized refer2. REV A C1968a 0 5 99 PRINTED IN U S A
3. bits to zero causing the Vour to become zero volts This func tion is useful for power on reset or system failure recovery to a known state D A CONVERTER SECTION The internal DAC is a 12 bit device with an output that swings from GND potential to 0 4 volt generated from the internal band gap voltage see Figure 20 It uses a laser trimmed segmented R 2R ladder which is switched by N channel MOSFETs The output voltage of the DAC has a constant resistance indepen dent of digital input code The DAC output is internally con nected to the rail to rail output op amp AMPLIFIER SECTION The internal DAC s output is buffered by a low power con sumption precision amplifier This low power amplifier contains a differential PNP pair input stage that provides low offset volt age and low noise as well as the ability to amplify the zero scale DAC output voltages The rail to rail amplifier is configured with a gain of approximately five in order to set the 2 0475 volt full scale output 0 5 mV LSB See Figure 20 for an equivalent circuit schematic of the analog section BANDGAP 1 2V REF 12 BIT DAC 0 4V 0 4V Vour PT fo FS Figure 20 Equivalent AD8300 Schematic of Analog Portion The op amp has a 2 us typical settling time to 0 4 of full scale There are slight differences in settling time for negative slewing signals versus positive Also negative transition settling time to within the last 6 LSB of zero volts has an extended
4. rights of third parties na ME No license is granted by implication or patent rights of Analog Devices WWW dZSC 6 3 Volt Serial Input Complete 12 Bit DAC AD8300 FUNCTIONAL BLOCK DIAGRAM A double buffered serial data interface offers high speed three wire DSP and microcontroller compatible inputs using data in SDD clock CLK and load strobe LD pins A chip select CS pin simplifies connection of multiple DAC packages by enabling the clock input when active low Additionally a CLR input sets the output to zero scale at power on or upon user demand The AD8300 is specified over the extended industrial 40 C to 85 C temperature range AD8300s are available in plastic DIP and low profile 1 5 mm height SO 8 surface mount packages INL LINEARITY ERROR LSB a WA i NN M uada ee TT tit 0 1024 2048 3072 4096 DIGITAL INPUT CODE Decimal Figure 2 Linearity Error vs Digital Code and Temperature One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 O Analog Devices Inc 1999 AD8300 SPECIFICATIONS 3 V OPERATION e v 5 v 10 406 lt T lt 85 C unless otherwise noted Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Zero Scale Error Full Scale Voltage Full Scale Tempco ANALOG OUTPUT Output Current Source Output Current Sink Load Re
5. Lj O AD8303 O L ANALOG DEVICES FEATURES Complete 12 Bit DAC No External Components Single 3 Volt Operation 0 5 mV Bit with 2 0475 V Full Scale 6 us Output Voltage Settling Time Low Power 3 6 mW Compact SO 8 1 5 mm Height Package APPLICATIONS Portable Communications Digitally Controlled Calibration Servo Controls PC Peripherals GENERAL DESCRIPTION The AD8300 is a complete 12 bit voltage output digital to analog converter designed to operate from a single 3 volt sup ply Built using a CBCMOS process this monolithic DAC offers the user low cost and ease of use in single supply 3 volt systems Operation is guaranteed over the supply voltage range of 2 7 V to 5 5 V making this device ideal for battery oper ated applications The 2 0475 V full scale voltage output is laser trimmed to maintain accuracy over the operating temperature range of the device The binary input data format provides an easy to use one half millivolt per bit software programmability The voltage outputs are capable of sourcing 5 mA AVFS lt 1 LSB DATA FFFy PROPER OPERATION WHEN Vpp SUPPLY VOLTAGE ABOVE MINIMUM SUPPLY VOLTAGE Volts 0 01 0 1 1 0 10 OUTPUT LOAD CURRENT mA Figure 1 Minimum Supply Voltage vs Load REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its uoo nor far anu infrinen monte of patents or other
6. N a Vpp 5V 10 z CIMT TILT TTI n CONAN HT z os VoD 3V 10 ail z N CCH E MIELE TCC TN 0 10 100 1k 10k 100k 1M FREQUENCY Hz Figure 8 Power Supply Rejection vs Frequency CODE 800g TO 7FFH Figure 11 Midscale Transition Performance HORIZONTAL 1j s DIV Figure 6 Detail Settling Time ewin HORIZONTAL 20us DIV Figure 9 Large Signal Settling Time ecc I ECT ANNE 0 5ps DIV Figure 12 Digital Feedthrough vs Time AD8300 TUE gt INL ZS FS ss 300 UNITS Vpp 3V FREQUENCY 0 1 0 1 2 3 4 5 6 TOTAL UNADJUSTED ERROR mV Figure 13 Total Unadjusted Error Histogram NO LOAD ss 300 UNITS NORMALIZED TO 25 C Vout DRIFT mV 55 35 15 5 TEMPERATURE C 25 45 65 85 105 125 Figure 16 Full Scale Voltage Drift vs Temperature www dzsc NO LOAD ss 300 UNITS NORMALIZED TO 25 C Vout DRIFT mV 9 55 35 15 5 25 45 65 85 105 125 TEMPERATURE C Figure 14 Zero Scale Voltage Drift vs Temperature 1 10 100 1k 10k 100k FREQUENCY Hz NOISE DENSITY V Hz Figure 17 Output Voltage Noise Density vs Frequency ss 135 UNITS nan S FULL SCALE DATA FFFij o N dL LLLI Lic ZERO SCALE DATA 000g 0 _ zero scate nta on 0 100 200 300 400 500 600 HOURS OF OPERATION AT 150 C 2 NOMINAL VOLTAGE CHANGE mV o Figure 19 Long Term Drift Accelerated by Burn In Ipp
7. SUPPLY CURRENT mA FREQUENCY Vpssssv it HEN UA ES ytt ET E E E D Vi OV 60 20 20 60 100 140 TEMPERATURE C Figure 15 Supply Current vs Temperature DATA FFFH TA 40 TO 85 C 0 50 40 30 20 10 0 TEMPERATURE COEFFICIENT ppm C 10 20 30 40 Figure 18 Full Scale Output Tempco Histogram REV A AD8300 Table I Control Logic Truth Table CS CLK CLR LD DAC Register Function H X H H No Effect Latched L L H H No Effect Latched L H H H No Effect Latched L T H H Shift Register Data Advanced One Bit Latched T L H H No Effect Latched H X H V No Effect Updated with Current Shift Register Contents H X H L No Effect Transparent H X L X No Effect Loaded with All Zeros H X T H No Effect Latched All Zeros NOTES 1 T Positive Logic Transition Negative Logic Transition X Don t Care 2 Do not clock in serial data while LD is LOW 3 Data loads MSB first OPERATION The AD8300 is a complete ready to use 12 bit digital to analog converter Only one 3 V power supply is necessary for opera tion It contains a 12 bit laser trimmed digital to analog converter a curvature corrected bandgap reference rail to rail output op amp serial input register and DAC register The serial data interface consists of a serial data input SDI clock CLK and load strobe pins LD with an active low CS strobe In addition an asynchronous CLR pin will set all DAC register
8. d versus operating Vpp supply voltage Figure 22 Equivalent Digital Input ESD Protection Unipolar Output Operation This is the basic mode of operation for the AD8300 The AD8300 has been designed to drive loads as low as 400 Q in parallel with 500 pF The code table for this operation is shown in Table II APPLICATIONS INFORMATION See DAC8512 data sheet for additional application circuit ideas Hexadecimal Number in DAC Register FFF 801 800 TFF 000 Table II Unipolar Code Table Decimal Number in DAC Register OUTLINE DIMENSIONS 8 Lead SOIC SO 8 0 1968 5 00 0 1890 aaoi Analog Output Voltage 2 0475 1 0245 1 0240 1 0235 0 0000 Dimensions shown in inches and mm V nu A 8 5 0 1574 4 00 L 0 2440 6 20 0 1497 3 80 171 4 0 2284 5 80 Y L AH HH E iii a 0 0196 0 50 0 0500 1 27 i BSC ial 0 0099 0 25 9 0 0688 1 75 0 0098 0 25 v 0 0532 135 0 0040 0 10 4 4 ike se SEATING 0 0192 0 49 0 0098 0 25 0 9 0500 1 27 PLANE 0 0138 0 35 0 0075 0 19 0 0160 0 41 8 Lead Plastic DIP N 8 0 430 10 92 ap 0 280 7 11 0 240 6 10 PIN 17 0 325 8 25 0 300 7 62 0 015 0 381 0 210 TYP 0 195 4 95 5 33 0 115 2 93 MAX 0 160 4 06 0 115 2 93 gt a J 0 130 3 30 i MIN 0 015 0 381 0 022 0 558 0 070 1 77 SEATING 45 0 0 022 0 598 0 008 0 204 0 014 0 356 0 045 1 15 PLANE
9. ence maintains a fixed full scale voltage independent of time tem perature and power supply variations SDI Dn A pio A po A pe A pz A po j ps X pa A ps A pe X oi A po j CLK lcLRw 1LSB ERROR BAND Figure 3 Timing Diagram CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8300 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD Proce ties 705 0500000007374 9 avoid performance degradation or loss of functionality WWW dzsc EE ESD SENSITIVE DEVICE REV A Typical Performance Characteristics AD8300 OUTPUT CURRENT mA 1 OUTPUT VOLTAGE Volts Figure 4 lout VS Vout BROADBAND NOISE 200pV DIV TIME 100ys DIV Figure 7 Broadband Noise m 2 0 EV A SUPPLY CURRENT mA 2 3 4 LOGIC VOLTAGE Volts Figure 10 Supply Current vs Logic Input Voltage 2H le WWW dZSC a Fo T pee LI Lem 0 5 DATA FFFy 0 5 2 5 TA 40 TO 85 C TL LU po o ol ENPANN Pt tt 0 1 2 3 4 5 6 Vpp SUPPLY VOLTAGE Volts e LOGIC THRESHOLD VOLTAGE o e Figure 5 Logic Input Threshold Voltage vs Vpp 50 t ATA il m 45 E T
10. gulation Output Resistance to GND Capacitive Load LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance INTERFACE TIMING SPECIFICATIONS Clock Width High Clock Width Low Load Pulsewidth Data Setup Data Hold Clear Pulsewidth Load Setup Load Hold Select Deselect AC CHARACTERISTICS Voltage Output Settling Time Output Slew Rate DAC Glitch Digital Feedthrough SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE Positive Supply Current Ipp Pprss PSS Power Dissipation Power Supply Sensitivity NOTES LSB 0 5 mV for 0 V to 2 0475 V output range Note 1 Bits t1 2 LSB Monotonic t 1 2 LSB Data 000g 1 2 mV Data FFFy 2 0475 Volts Notes 3 4 16 ppm C Data 800g AVoutr 5 LSB 5 mA Data 800g AVour 5 LSB 2 mA Ri 200 Q to oo Data 800g 1 5 5 LSB Data 000g 30 Q No Oscillation 500 pF To 0 2 of Full Scale To 1 LSB of Final Value Data 000g to FFFg to 000g DNL 1 LSB Vpp 3 V Vir 0 V Data 000g Vpp 3 6 V Vy 2 3 V Data FFFy Vpp 3 V Vg 0 V Data 000g AVpp 5 The first two codes 0004 0015 are excluded from the linearity error measurement Includes internal voltage reference error These parameters are guaranteed by design and not subject to production testing All input control signals are specified with tg tp 2 ns 10 to 90 of 3 V and timed from a voltage level of 1 6 V The se
11. ion To 0 2 of Full Scale To 1 LSB of Final Value Data 000g to FFFy to 000g DNL lt 1 LSB Vpp 5 V Vg 0 V Data 000g Vpp 5 5 V Viz 2 3 V Data FFFy Vpp 5 V Vin 0 V Data 000g AVpp 10 The first two codes 00043 0015 are excluded from the linearity error measurement Includes internal voltage reference error These parameters are guaranteed by design and not subject to production testing All input control signals are specified with tg tp 2 ns 10 to 90 of 5 V and timed from a voltage level of 1 6 V The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground Some devices exhibit double the typical settling time in this 6 LSB region Specifications subject to change without notice 3 AD8300 ABSOLUTE MAXIMUM RATINGS Vpp tOSIINID Luoous ede ead v4 eee seater 0 3 V 7 V Logic Inputs to GND 42 222 RE es 0 3 V 7 V Vout to GND isa ded edevesnreaedas ews 0 3 V Vpp 0 3 V Iouyr Short Circuit to GND 2 464 54 sar es 50 mA Package Power Dissipation Ty Max T4 0r4 Thermal Resistance Oja 8 Lead Plastic DIP Package N 8 103 C W 8 Lead SOIC Package SO 8 158 C W Maximum Junction Temperature Tj Max 150 C Operating Temperature Range 40 C to 85 C Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 10 secs
12. logic and the low noise tight matching of the complementary bipolar transistors good analog accuracy is achieved For power consumption sensitive applications it is important to note that the internal power consumption of the AD8300 is strongly dependent on the actual logic input voltage levels present on the SDI CLK CS LD and CLR pins Since these inputs are standard CMOS logic structures they contribute static power dissipation dependent on the actual driving logic AD8300 Vou and VoL voltage levels Consequently for optimum dissipa tion use of CMOS logic versus TTL provides minimal dissipa tion in the static state A Vy 0 V on the logic input pins provides the lowest standby dissipation of 1 2 mA with a 3 3 V power supply As with any analog system it is recommended that the AD8300 power supply be bypassed on the same PC card that contains the chip Figure 8 shows the power supply rejection versus fre quency performance This should be taken into account when using higher frequency switched mode power supplies with ripple frequencies of 100 kHz and higher One advantage of the rail to rail output amplifiers used in the AD8300 is the wide range of usable supply voltage The part is fully specified and tested over temperature for operation from 2 7 V to 5 5 V If reduced linearity and source current capa bility near full scale can be tolerated operation of the AD8300 is possible down to 2 1 volts The minimum operati
13. ng supply voltage versus load current plot in Figure 2 provides information for operation below Vpp 2 7 V TIMING AND CONTROL The AD8300 has a separate serial input register from the 12 bit DAC register that allows preloading of a new data value MSB first into the serial register without disturbing the present DAC output voltage value Data can only be loaded when the CS pin is active low After the new value is fully loaded in the serial input register it can be asynchronously transferred to the DAC register by strobing the LD pin The DAC register uses a level sensitive LD strobe that should be returned high before any new data is loaded into the serial input register At any time the contents of the DAC resister can be reset to zero by strobing the CLR pin which causes the DAC output voltage to go to zero volts All of the timing requirements are detailed in Figure 3 along with Table I Control Logic Truth Table All digital inputs are protected with a Zener type ESD protection structure Figure 22 that allows logic input voltages to exceed the Vpp supply voltage This feature can be useful if the user is loading one or more of the digital inputs with a 5 V CMOS logic input voltage level while operating the AD8300 on a 3 3 V power supply If this mode of interface is used make sure that the VoL of the 5 V CMOS meets the Vg input requirement of the AD8300 operating at 2 V See Figure 5 for the effect on digital logic input threshol
14. settling time See the ascillascan e nhotos in the typical performances section OUTPUT SECTION The rail to rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply Figure 21 shows an equivalent output schematic of the rail to rail amplifier with its N channel pull down FETs that will pull an output load directly to GND The output sourcing current is provided by a P channel pull up device that can source current to GND terminated loads Figure 21 Equivalent Analog Output Circuit The rail to rail output stage achieves the minimum operating supply voltage capability shown in Figure 2 The N channel output pull down MOSFET shown in Figure 21 has a 35 Q on resistance which sets the sink current capability near ground In addition to resistive load driving capability the amplifier has also been carefully designed and characterized for up to 500 pF capacitive load driving capability REFERENCE SECTION The internal curvature corrected bandgap voltage reference is laser trimmed for both initial accuracy and low temperature coefficient Figure 18 provides a histogram of total output per formance of full scale vs temperature which is dominated by the reference performance POWER SUPPLY The very low power consumption of the AD8300 is a direct result of a circuit design optimizing use of a CBCMOS process By using the low power characteristics of the CMOS for the
15. ttling time specification does not apply for negative going transitions within the last 6 LSBs of ground Some devices exhibit double the typical settling time in this 6 LSB region Specifications subject to change without notice REV A AD8300 9 V OPERATI ON Vy 9 V 10 40 C lt T lt 85 C unless otherwise noted Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Zero Scale Error Full Scale Voltage Full Scale Tempco ANALOG OUTPUT Output Current Source Output Current Sink Load Regulation Output Resistance to GND Capacitive Load LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance INTERFACE TIMING SPECIFICATIONS Clock Width High Clock Width Low Load Pulsewidth Data Setup Data Hold Clear Pulsewidth Load Setup Load Hold Select Deselect AC CHARACTERISTICS Voltage Output Settling Time Output Slew Rate DAC Glitch Digital Feedthrough SUPPLY CHARACTERISTICS Power Supply Range Vpp RANGE Positive Supply Current Ipp Power Dissipation Ppiss Power Supply Sensitivity PSS NOTES 11 LSB 0 5 mV for 0 V to 2 0475 V output range Note 1 12 Bits 2 1 2 2 LSB Monotonic 1 2 1 LSB Data 000g Fli2 3 mV Data FFFy 2 039 2 0475 2 056 Volts Notes 3 4 16 ppm C Data 800g AVoutr 5 LSB Data 800g AVourT 5 LSB Ri 200 Q to Data 800g Data 000g No Oscillat
Download Pdf Manuals
Related Search
ANALOG DEVICES 3 Volt Serial Input Complete 12 Bit DAC AD8300 handbook