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MITSUBISHI ELECTRIC M5M51008DFP VP RV KV KR -55H -70H Manual

1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algorithms or circuit application examples contained in these materials All information contained in these materials including product data diagrams charts programs and algorithms represents information on products at the time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Mitsubishi Electric Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Mitsubishi Electri
2. Vvo 0 Vcc Active supply current AC MOS level S1 lt 0 2V S2 gt VCC 0 2V other inputs lt 0 2V or gt VCC 0 2V Output open duty 100 Active supply current AC TTL level S1 VIL S2 VIH other inputs VIH or VIL Output open duty 100 Stand by current 1 S2 lt 0 2V other inputs 0 Vcc 2 Si gt Vcc 0 2V S2 gt Vcc 0 2V other inputs 0 Vcc Stand by current 3 0V in case of AC Pulse width lt 50ns S1 VIH or S2 VIL other inputs 0 Vcc CAPACITANCE Ta 0 70 C Vcc 5V 10 unless otherwise noted Limits Parameter Test conditions FP VP RV KV Vi GND Vi 25mVrms f 1MHz FP VP RV KV Vo GND Vo 25mVrms f 1MHz Typ Input capacitance Output capacitance Note 1 Direction for current flowing into an IC is positive no mark 2 Typical value is Vcc 5V Ta 25 C MITSUBISHI ELECTRIC 3 Ver 1 1 MITSUBISHI LSis M5M51008DFP VP RV KV KR 55H 70H 1048576 BIT 131072 WORD BY 8 BIT CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS Ta 0 70 C 5V 10 unless otherwise noted 1 MEASUREMENT CONDITIONS voc Input pulse level ViH 2 4V ViIL 0 6V 70H Pye ViH 3 0V VIL 0 0V 55H Input rise and fall time 5ns 1 8kQ Reference level VoH VOL 1 5V Output ai Fig 1 CL 100pF 70H DQ CL 80pF 55H 9902 ZZ CL Including scope CL 5pF for ten tdis and JIG Transition is measured 5
3. S2 tcw tdis S2 tdis OE 3 DATA VALID TO gt Note 3 Note 3 Ao 16 X X Si Note 3 S2 Note 3 OE Ww DQ1 8 tsu S1 tsu S2 tsu A WH MITSUBISHI ELECTRIC Note 3 Ver 1 1 MITSUBISHI LSis M5M51008DFP VP RV KV KR 55H 70H 1048576 BIT 131072 WORD BY 8 BIT CMOS STATIC RAM Write cycle 51 control mode tcw Ao 16 Si S2 Note 3 Note 3 Note 5 WwW Note 4 Note 3 Note 3 tsu D th D DATAIN DQ1 8 STABLE Write cycle S2 control mode tcw Ao 16 X X S Note 3 Note 3 tsu A tsu S2 trec W lt Pid rid gt S2 Note 5 w Note 4 Note 3 Note 3 DATA IN DQi 8 STABLE Note 3 Hatching indicates the state is don t care _ Pe 4 Writing is executed while S2 high overlaps S and W low 5 When the falling edge of W is simultaneously or prior to the falling edge of S1 or rising edge of S2 the outputs are maintained in the high impedance state 6 Don t apply inverted phase signal externally when DQ pin is output mode MITSUBISHI ELECTRIC 6 Ver 1 1 MITSUBISHI LSis M5M51008DFP VP RV KV KR 55H 70H 1048576 BIT 131072 WORD BY 8 BIT CMOS STATIC RAM POWER DOWN CHARACTERISTICS 1 ELECTRICAL CHARACTERISTICS Ta 0 70 C unless otherwise noted Parameter Test conditions Power down supply voltage 2 2V lt Vcc PD 2V
4. 00mV from steady state voltage for ten tdis 777 Fig 1 Output load 2 READ CYCLE Limits Symbol Parameter 55H 70H Min Max Min tcR Read cycle time 55 70 ta A Address access time 55 ta S1 Chip select 1 access time 55 ta S2 Chip select 2 access time 55 ta OE Output enable access time 30 tdis S1 Output disable time after S1 high 20 tdis S2 Output disable time after S2 low 20 tdis OE Output disable time after OE high 20 ten S1 Output enable time after S1 low ten S2 Output enable time after S2 high ten OE Output enable time after OE low tv A Data valid time after address 3 WRITE CYCLE Limits Parameter 70H Max Write cycle time Write pulse width Address setup time Address setup time with respect to W Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low MITSUBISHI ELECTRIC 4 4 TIMING DIAGRAMS Read cycle Ao 16 Note 3 S2 Note 3 OE Note 3 DQ1 8 W H level Write cycle W control mode la Ver 1 1 MITSUBISHI LSis M5M51008DFP VP RV KV KR 55H 70H 1048576 BIT 131072 WORD BY 8 BIT CMOS STATIC RAM tcR ta S2 lt p ta OE ten OE ten S1 ten
5. 2 WORDS X 8 BITS 512 ROWS X128 COLUMNS X 16BLOCKS BUFFER ROW DECODER ADDRESS INPUTS A13 28 AE pag BUFFER COLUMN DECODER C ADDRESS INPUT A0 12 A10 23 X BUFFER BLOCK DECODER GENERATOR Me TNT SE Sh Gn 13 DQ1 r ep 23 15 J DQ3 TH esos 17 baa DATA INPUTS TT Eoo eurs DREGE ie 29 21 Das SENSE AMP OUTPUT BUFFER WRITE W CONTROL INPUT CHIP SELECT INPUTS OUTPUT OE ENABLE INPUT Pin numbers inside dotted line show those of TSOP MITSUBISHI ELECTRIC 2 ABSOLUTE MAXIMUM RATINGS Parameter Ver 1 1 MITSUBISHI LSis M5M51008DFP VP RV KV KR 55H 70H 1048576 BIT 131072 WORD BY 8 BIT CMOS STATIC RAM Conditions Ratings Supply voltage Input voltage With respect to GND Output voltage 0 3 7 0 3 Vecc 0 3 0 Vcc Power dissipation Ta 25 C 700 Operating temperature 0 70 Storage temperature 3 0V in case of AC Pulse width lt 50ns DC ELECTRICAL CHARACTERISTICS Ta 0 70 C Vcc 5V 10 unless otherwise noted Parameter Test conditions 65 150 Limits Typ Max High level input voltage Vcc 0 3 Low level input voltage 0 8 High level output voltage loH 1 0mA loH 0 1MA Low level output voltage loL 2mA Input current Vi 0 Vcc Output current in off state S1 Vin or S2 Vit or OE VIH
6. 2576 M 5M 51008D FPEM A Ver 1 1 MITSUBISHI LSis M5M51008DFP VP RV KV KR 55H 70H 1048576 BIT 131072 WORD BY 8 BIT CMOS STATIC RAM DESCRIPTION PIN NFIGUR The M5M51008DP FP VP RV KV are a 1048576 bit CMOS static CONFIGURATION TOP VIEW RAM organized as 131072 word by 8 bit which are fabricated using NC ff wy 32 V high performance quadruple polysilicon and double metal CMOS CO ADRESS technology The use of thin film transistor TFT load cells and A16 2 31 A15 INPUT CMOS periphery result in a high density and low power static Ata 3 30 CHIP SELECT RAM INPUT They are low standby current and low operation current and ideal A12 4 29 INPUT CONTROL for the battery back up application A7 5 28 The M5M51008DVP RV KV are packaged in a 32 pin thin small A outline package which is a high reliability and high density surface 6 neS z 27 ADDRESS mount device SMD Two types of devices are available ADDRESS 2 A5 7 2 26 INPUTS M5M51008DVP normal lead bend type package INPUTS 44 8 a bs M5M51008DRV reverse lead bend type package Using both types o ATOA SEYA of devices it becomes v
7. c Corporation by various means including the Mitsubishi Semiconductor home page http www mitsubishichips com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products Mitsubishi Electric Corporation assumes no responsibility for any damage liability or other loss resulting from the information contained herein Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must b xported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to th
8. e export control laws and regulations of Japan and or the country of destination is prohibited Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein afte MITSUBISHI ELECTRIC
9. ery easy to design a printed circuit board A3 9 8 24 OE input A2 0 iw 0 ADDRESS Tl INPUT Ai 1 Uv GHR SELECT Ao f2 DATA DQ1 13 FEATURES INPUTS DQ2 f4 ELAS OUTPUTS DQs fis OUTPUTS Power supply current Type name MMe stand by GND Ya max Outline 32P2M A FP M5M51008DFP VP RV KV 55H teak 20A M5M51008DFP VP RV KV 70H 1MHz Vcc 5 5V g 3 4 Directly TTL compatible All inputs and outputs Easy memory expansion and power down by S1 S2 9 Data hold on 2V power supply 6 Three state outputs OR tie capability 7 SA EE contention in the I O bus z M5M51008DVP KV Package gt M5M51008DFP seese 32pin 525mil SOP LO M5M51008DVP RV 32pin 8K 20 mnf _ TSOP M5M51008DKV seres 32pin 8X 13 4mn TSOP APPLICATION Small capacity memory units M5M51008DRV N Jl AIA oaj Ni ollo Outline 32P3H F RV NC NO CONNECTION MITSUBISHI ELECTRIC l Ver 1 1 MITSUBISHI LSis M5M51008DFP VP RV KV KR 55H 70H 1048576 BIT 131072 WORD BY 8 BIT CMOS STATIC RAM FUNCTION The operation mode of the M5M51008D series are determined by a combination of the device control inputs S1 S2 W and OE Each mode is summarized in the function table __ A
10. lt Vcc PD lt 2 2V 4 5V lt Vcc PD Vec PD lt 4 5V Vcc 3V 1 S2 lt 0 2V other inputs 0 3V Power down supply current 2 St gt Vec 0 2V S2 gt Vcc 0 2V other inputs 0 3V Chip select input Si Chip select input S2 2 TIMING REQUIREMENTS Ta 0 70 C unless otherwise noted Limits Typ Symbol Parameter Test conditions tsu PD Power down set up time trec PD Power down recovery time 3 POWER DOWN CHARACTERISTICS Si control mode Vcc trec PD 2 2V 2 2V Si gt Voc 0 2V Note 7 On the power down mode by controlling S1 the input level of S2 must be S2 gt Vcc 0 2V or S2 lt 0 2V The other pins Address 1 O WE OE can be in high impedance state S2 control mode Vcc S2 trec PD S2 lt 0 2V MITSUBISHI ELECTRIC i Keep safety first in your circuit designs Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials
11. write cycle is executed whenever the low level W overlaps with the low level S1 and the high level S2 The address must be set up before the write cycle and must be stable during the entire cycle The data is latched into a cell on the trailing edge of W S1 or S2 whichever occurs first requiring the set up and hold time relative to these edge to be maintained The output enable input OE directly controls the output stage Setting the OE at a high level the output stage is in a high impedance state and the data bus contention problem in the write cycle is eliminated ad A read cycle is executed by setting W at a high level and OE ata low level while S1 and S2 are in an active state S1 L S2 H FUNCTION TABLE Mode DQ Icc Non selection High impedance Stand by Non selection High impedance Stand by Write Din Active Read Dout Active High impedance Active BLOCK DIAGRAM When setting S1 at a high level or S2 at a low level the chip are in a non selectable mode in which both reading and writing are disabled In this mode the output stage is in a high impedance state allowing OR tie with other chips and memory expansion by Si and S2 The power supply current is reduced as low as the stand by current which is specified as Icc3 or Icc4 and the memory data can be held at 2V power supply enabling battery back up operation during power failure or power down operation in the non selected mode 13107

MITSUBISHI ELECTRIC M5M51008DFP VP RV KV KR -55H -70H Manual

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