ST M29F040 Manual
Contents
1. Low Supply Voltage Erase and Program lock out Read Block Protection RBP instruction The use of Read Electronic Signature RSIG command also allows access to the Block Protection status verify After giving the RSIG command AO and are set to with A1 at Vin while A16 A17 and A18 define the block of the block to be verified A read in these conditions will output a 01h if block is protected and a 00h if block is not protected This Read Block Protection is the only valid way to check the protection status of a block Neverthe less it must notbe used during the Block Protection phase as a method to verify the block protection Please refer to Block Protection paragraph Chip Erase CE instruction This instruction uses six write cycles The Erase Set up command 80h is written to address 5555h on third cycle after the two coded cycles The Chip Erase Confirm com 10 31 mand 10h is written at address 5555h on sixth cycle after another two coded cycles If the second com mand given is not an erase confirm or if the coded cycles are wrong the instruction aborts and the device is reset to Read Array It is not necessary to program the array with OOh first as the P E C will automatically do this before erasing to FFh Read operations after the sixth rising edge of W or E output the status register bits During the execu tion of the erase by the P E C the memory accepts only the Reset RST comman2. AOT AOAVI 840018 NIH LIM SS3HQQV 31A8 dA LNd LNO Viva P 22 31 M29F040 Figure 10 Data Polling Flowchart Figure 11 Data Toggle Flowchart READ DQ5 amp DQ7 READ at VALID ADDRESS DOB amp DQ6 DQ6 TOGGLE NO YES READ DQ7 READ DQ6 Table 16 Program Erase Times and Program Erase Endurance Cycles Ta 0 to 70 C Voc 5V 10 or 5V 5 wn w otic nomena H 2 amp s ome SS H se Lo Parameter mates ewe s m amp km e mem 9 o o mwamtmeOgepwRo wmm 3 29 91 M29F040 Figure 12 Data Toggle DQ6 AC Waveforms 049 ewou e se 816 sBuluun 10 y 91ON E Z9CL0IY 319A9 QV3H 9 3 dO 319A9 QV3H 31SSO1 INVHOOHd dO lt JIAO dyd MH 39901 Viva lt VIVA lt 319A9 1SV1 oq 3HONOI soq ooq 316901 dOLS s 900 I4 24 31 Figure 13 Block Protection Flowchart BLOCK ADDRESS on A16 A17 A18 i DNE s E E lt T G Vin E READ DQ0 at PROTECTION ADDRESS A0 A6 Vj A1 Vj and A16 A17 A18 DEFINING BLOCK o lt Al01368D 31 M29F040 25 31 M29F040 Figure 14 Block Unprotecting Flowchart PROTECT ALL BLOCKS A12 A16 VIH E G A9 Vip m gt e l z I lt lt um E G Vin gt
3. as 3 T iw metere mutans o o ow jmeemeenmnowemeneng o 9 we onpenabieHontocnpcnabietow 20 2 0 as owamaennoweaeo o so o s ES lEHQV1 Chip Enable High to Output Valid Program t Chip Enable High to Output Valid ee Erase tEHGL Chip Enable High to Output Enable Low Enable High to Output Enable Low tvcHwL wow Ex Note 1 Time is measured to Data Polling or Toggle Bit twHav twHazv tozvov 2 The temperature range 40 to 125 C is guaranteed at 70ns with High Speed Interface test condition and Vcc 5V 5 3 17 31 M29F040 Table 14B Write AC Characteristics Chip Enable Controlled Ta 0 to 70 C 20 to 85 C 40 to 85 C or 40 to 125 C se Farameter 5V 10 Voc 5V 10 E Interface Symbol Min Mex min Max wc eas vano eren wa m 5 ws ete Erato Low Grin natiouow o so so elegan gep ng o so T ton onp Erene Hono mutans o 0 ow jmeemeenenowmemeneng o 9 fh 20 2 o o so so Jomwtmpempometmpeum o Dus esmeweemes s wp aoe ee L lEHQV1 Chip Enable High to Output Valid Program t Chip Enable Hig
4. M295V040 120K RI SZA M29F040 4 Mbit 512Kb x8 Uniform Block Single Supply Flash Memory NOT FOR NEW DESIGN M29F040 is replaced by the M29F040B m 5V 10 SUPPLY VOLTAGE for PROGRAM ERASE and READ OPERATIONS FAST ACCESS TIME 70ns BYTE PROGRAMMING TIME 10us typical ERASE TIME Block 1 0 sec typical Chip 2 5 sec typical s PROGRAM ERASE CONTROLLER P E C Program Byte by Byte Data Polling and Toggle bits Protocol for P E C Status a MEMORY ERASE in BLOCKS 8 Uniform Blocks of 64 KBytes each Block Protection Multiblock Erase ERASE SUSPEND and RESUME MODES a LOW POWER CONSUMPTION Read mode 8mA typical at 12MHz Stand by mode 25 typical Automatic Stand by mode 100 000 PROGRAM ERASE CYCLES per BLOCK m 20 YEARS DATA RETENTION Defectivity below 1ppm year ELECTRONIC SIGNATURE Manufacturer Code 20h Device Code E2h Table 1 Signal Names Write Enable Supply Voltage Ground November 1999 PLCC32 K TSOP32 N 8x 20mm Figure 1 Logic Diagram K 1 gt DQ0 DQ7 M29F040 Al01372 1 31 This is information on a product still in production but not recommended for new designs M29F040 Figure 2A LCC Pin Connections Figure 2B TSOP Pin Connections M29F040 Normal Al01378 Al01379 Figure 2C TSOP Reverse Pin Connections DESCRIPTION The M29F040 is a non volatile memory that may be erased elect
5. Read Array Reset Read Electronic Signature Read Block Protection 3 Data aan ssn sm Addr 5555h 2AAAh 5555h Program Program a Address Read Data Polling or Toggle Bit until Program completes Program Data 8 7 Block Additional 5555h 2AAAh 5555h 5555h 2AAAh be s AAh 80h AAh 55h 3 3 be we sm s m om m A X Read until Toggle stops then read all the data needed from any uniform block s not being erased then Resume Erase Block Erase Chip Erase Erase Suspend Erase Resume Read Data Polling or Toggle Bit until Erase completes or Erase is suspended another time Notes 1 Command not interpreted in this table will default to read array mode 2 While writing any command or during RSG and RSP execution the P E C can be reset by writing the command 00h to the C I 3 X Don t Care 4 The first cycle of the RST RBP or RSIG instruction is followed by read operations to read memory array Status Register or Electronic Signature codes Any number of read cycles can occur after one command cycle 5 Signature Address bits AO A1 at Vit will output Manufacturer code 20h Address bits AO at Vin and A1 at Vi will output Device code 6 Protection Address AO at A1 at Vin and A16 A17 A18 within the uniform block to be checked will output the Block Protection status 7 Address bits A15 A18 are don t care for coded address inputs 8 Optional additional
6. Drawing is not to scale 30 31 Ti M29F040 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics All Rights Reserved All other names are the property of their respective owners STMicroelectronics GROUP OF COMPANIES Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U S A http www st com 31 31 3
7. ory will not accept any instruction Read operations output the status bits after the programming has started The status bits DQ5 DQ6 and DQ7 allow acheck of the status of the programming operation Memory programming is made only by writing O in place of 1 in a Byte Erase Suspend ES instruction The Block Erase operation may be suspended by this instruc tion which consists of writing the command OBOh without any specific address code No coded cycles are required It allows reading of data from another 12 31 block while erase is in progress Erase suspend is accepted only during the Block Erase instruction execution and defaults to read array mode Writing this command during Erase timeout will in addition to suspending the erase terminate the timeout The Toggle Bit DQ6 stops toggling when the P E C is suspended Toggle Bit status must be monitored at an address out of the block being erased Toggle Bit will stop toggling between 0 1us and 15us after the Erase Suspend ES command has been writ ten The M29F040 will then automatically set to Read Memory Array mode When erase is suspended Read from blocks being erased will output invalid data Read from block not being erased is valid During the suspension the memory will respond only to Erase Resume ER and Reset RST in structions RST command will definitively abort erasure and result in the invalid data in the blocks being erased M29F040 Figure 6 Read Mod
8. 5 Read Read operations are used to output the contents of the Memory Array the Status Register or the Electronic Signature Both Chip Enable E and Output Enable G must be low in order to read the output of the memory The Chip Enable input also provides power control and should be used for device selection Output Enable should be used to gate data onto the output independent of the device selection The data read depends on the previous command written to the memory see instructions RST and RSIG and Status Bits Write Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed A write operation is initiated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High Addresses are latched on the falling edge of W or E whichever occurs last Commands and Input Data are latched on the rising edge of W or E whichever occurs first Output Disable The data outputs are high imped ance when the Output Enable G is High with Write Enable W High Standby The memory is in standby when Chip Enable E is High and Program Erase Controller P E C is Idle The power consumption is reduced to the standby level and the outputs are high im pedance independent of the Output Enable G or Write Enable W inputs Automatic Standby After 150ns of inactivity and when CMOS levels are driving the addresses the chip automatically enters a pseudo standby mode 6 31 where consumpt
9. Data Polling is valid only effective during P E C operation that is after the fourth W pulse for programming or after the sixth W pulse for Erase It must be performed at the address being programmed or at an address within the block being erased If the byte to be programmed belongs to a protected block the com mand is ignored If all the blocks selected for era sure are protected DQ7 will set to 0 for about 100us and then return to previous addressed memory data See Figure 9 for the Data Polling flowchart and Figure 10 for the Data Polling wave forms Toggle bit DQ6 When Programming operations are in progress successive attempts to read DQ6 will output complementary data DQ6 will toggle following toggling of either G or E when G is low 8 31 The operation is completed when two successive reads yield the same output data The next read will output the bit last programmed or a 1 after erasing The toggle bit is valid only effective during P E C operations that is after the fourth W pulse for programming or after the sixth W pulse for Erase If the byte to be programmed belongs to a protected block the command will be ignored If the blocks selected for erasure are protected DQ6 will toggle for about 100us and then return back to Read See Figure 11 for Toggle Bit flowchart and Figure 12 for Toggle Bit waveforms Error bit DQ5 This bit is set to 1 by the P E C when there is a failure of byte programming block e
10. READ at UNPROTECTION ADDRESS VIH AO Vj and A16 A17 A18 DEFINING BLOCK INCREMENT see Note 1 BLOCK Al01371E Note 1 A6 is kept at Vin during unprotection algorithm in order to secure best unprotection verification During all other protection status reads must be kept at 26 31 Ti M29F040 ORDERING INFORMATION SCHEME Example M29F040 70 X N 1 TR Operating Voltage R Reverse Pinout TR Tape amp Reel Packing Power Supplies Temp Range 70 70ns blank Voc 10 K PLCC32 1 0to70 C 90 90ns X Voc t 59 N TSOP32 3 4010125 C 120 120ns EEUU 5 201085 C 15 150ns 6 40to85 C M29F040 is replaced by the new version M29F040B Device are shipped from the factory with the memory content erased to FFh For a list of available options Speed Package etc or for further information on any aspect of this device please contact the STMicroelectronics Sales Office nearest to you Lyr 27 31 M29F040 PLCC32 32 lead Plastic Leaded Chip Carrier rectangular F D2 E2 0 51 020 vt 920 K 4 44 045 A O CP Bi Drawing is not to scale 28 31 Ti M29F040 TSOP32 Normal Pinout 32 lead Plastic Thin Small Outline 8 x 20mm Drawing is not to scale Ti 29 31 M29F040 TSOP32 Reverse Pinout 32 lead Plastic Thin Small Outline 8 x 20mm
11. The Block Erase Confirm command 30h is written on sixth cycle after another two coded cycles During the input of the second command an address within the block to be erased is given and latched into the memory Additional Block Erase confirm com mands and block addresses can be written sub sequently to erase other blocks in parallel without further coded cycles The erase will start after an Erase timeout period of about 100us Thus addi tional Block Erase commands must be given within this delay The input of a new Block Erase com mand will restart the timeout period The status of the internal timer can be monitored through the level of DQ3 if DQ3 is 0 the Block Erase Com mand has been given and the timeout is running if DQ3 is 1 the timeout has expired and the P E C is erasing the block s Before and during Erase timeout any command different from 30h will abort the instruction and reset the device to read array mode It is not necessary to program the block with 00h as the P E C will do this automatically before erasing to FFh Read operations after the sixth rising edge of W or E output the status register bits During the execution of the erase by the P E C the memory accepts only the ES Erase Suspend and RST Reset instructions Data Polling bit DQ7 returns 0 while the erasure is in progress and 1 when it has completed The Toggle Bit DQ6 toggles during the erase operation It stops when erase is com
12. during the second cycle Addresses are latched on the falling edge of W or E while data is latched on the rising edge of W or E The coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles ky Read Array Reset RST instruction The Reset instruction consists of one write operation giving the command FOh It can be optionally preceded by the two coded cycles A wait state of 5us before read operations is necessary if the Reset command is applied during an Erase operation Read Electronic Signature RSIG instruction This instruction uses the two coded cycles followed by one write cycle giving the command 90h to address 5555h for command setup Asubsequent read will output the manufacturer code the device code or the Block Protection status depending on the levels of AO A1 A6 A16 A17 and A18 The manufacturer code 20h is output when the ad dresses lines AO A1 and A6 are Low the device code E2h is output when AO is High with A1 and A6 Low 9 31 M29F040 Table 11 DC Characteristics Ta 0 to 70 C 20 to 85 C 40 to 85 C or 40 to 125 C Vcc 5V 10 ae 7 mama wama cee es o em Evo i Supply Current Standby TTL Supply Current Standby CMOS Supply Current Chip Erase in progress Input Low Voltage Input High Voltage s os V Los Dessy V V Output High Voltage TTL loH 2 5mA Ps L High Voltage CMOS weca
13. test condition and Vcc 5V 5 3 20 31 M29F040 Table 15B Data Polling and Toggle Bit AC Characteristics 1 TA 0 to 70 C 20 to 85 C 40 to 85 C or 40 to 125 C M29F040 120 150 Parameter Vec 5V 10 Vcc 5V 10 Standard Standard Interface Interface Write Enable High to DQ7 Valid Program W Controlled Write Enable High to DQ7 Valid Block Erase W Controlled Chip Enable High to DQ7 Valid Program E Controlled Chip Enable High to DQ7 Valid Block Erase E Controlled Q7 Valid to Output Valid Data Polling Write Enable High to Output Valid Program Write Enable High to Output Valid Block Erase Chip Enable High to Output Valid Program Chip Enable High to Output Valid Block Erase Notes 1 All other timings are defined in Read AC Characteristics table 2 twHazv is the Program or Erase time 3 21 31 Figure 9 Data Polling DQ7 AC Waveforms M29F040 peseae Bulag 908 utuiiM eq snw Ssauppe a Ag uorejedo Huise Bung euin ese13 10 WeIKOlg eui S AZOHM ponad ple nd no eyep eui amp uunp 1urod Aue 18 pijen 0 lluusue1 ueo 900 000 pu Oq Z 9 9 81101 e se 818 SHUIWI 19410 IV S910N Sv9E LOIV 3SVu3 YO 319A9 QV3H S319049 QV3H INVHOOHd JO AdIH3A VLVQ 394 319A9 LSV1 ONITIOd Ka 9NITIOd VLIVA 319A9 1SV1 gt NOMO anya g9oq 0oq AZOHM AO191 MOHA
14. 4 are reserved for future use and should be masked 7 31 M29F040 Table 8 Status Register Erase Complete Indicates the P E C status check during Data Polling Erase on Goin Program or Erase and on completion al i duy Program Complete Erase Success Program on Going Erase Time Bit Reserved Going Program or Erase Error Program or Erase on Going Erase Timeout Period Expired Erase Timeout Period on 1 0 1 0 1 0 1 Erase or Program on Going Successive read output complementary P 0 on DQ6 data on DQ6 while Programming or Erase 0 0 0 0 0 0 0 rogram 0 on Toggle Bit 0 0 0 0 0 0 0 Complete D or Program nmm 1 on DQ6 Complete operations are going on DQ6 remain at constant level when P E C operations are completed or Erase Suspend is acknowledged This bit is set to 1 if P E C has exceded the specified time limits P E C Erase operation has started Only E command entry is Erase Suspend An additional block to be erased in buie can be entered to the P E C Note Logic level 1 is High 0 is Low 0 1 0 0 0 1 1 1 0 represent bit value in successive Read operations Data Polling bit DQ7 When Programming op erations are in progress this bit outputs the com plement of the bit being programmed on DQ7 During Erase operation it outputs a 0 After com pletion of the operation DQ7 will output the bit last programmed or a 1 after erasing
15. ata Polling Toggle and Status data to indicate completion of Program and Erase Operations Instructions are composed of up to six cycles The first two cycles input a code sequence to the Com mand Interface which is common to all P E C instructions see Table 7 for Command Descrip tions The third cycle inputs the instruction set up command instruction to the Command Interface Subsequent cycles output Signature Block Protec tion or the addressed data for Read operations For added data protection the instructions for pro gram and block or chip erase require further com mand inputs For a Program instruction the fourth command cycle inputs the address and data to be programmed For an Erase instruction block or chip the fourth and fifth cycles input a further code sequence before the Erase confirm command on the sixth cycle Byte programming takes typically 10us while erase is performed in typically 1 0 sec ond Erasure of a memory block may be suspended in order to read data from another block and then resumed Data Polling Toggle and Error data may be read at any time including during the program ming or erase cycles to monitor the progress of the operation When power is first applied or if Vcc falls below Vi the command interface is reset to Read Array 3 31 M29F040 Table 3 Operations Note X Vit or Vin Table 4 Electronic Signature Other Manufact Manufact Code Don t Don tCa
16. blocks addresses must be entered within a 80us delay after last write entry timeout status can be verified through DQ3 value When full command is entered read Data Polling or Toggle bit until Erase is completed or suspended 9 Read Data Polling or Toggle bit until Erase completes 10 A wait time of 5us is necessary after a Reset command if the memory is in a Block Erase status before starting any operation 3 5 31 M29F040 Memory Blocks The memory blocks of the M29F040 are shown in Figure 3 The memory array is divided in 8 uniform blocks of 64 Kbytes Each block can be erased separately or any combination of blocks can be erased simultaneously The Block Erase operation is managed automatically by the P E C The opera tion can be suspended in order to read from any other block and then resumed Block Protection provides additional data security Each uniform block can be separately protected or unprotected against Program or Erase Bringing A9 and G to Vip initiates protection while bringing A9 G and E to Vip cancels the protection The block affected during protection is addressed by the in puts on A16 A17 and A18 Unprotect operation affects all blocks Operations Operations are defined as specific bus cycles and signals which allow Memory Read Command Write Output Disable Standby Read Status Bits Block Protect Unprotect Block Protection Check and Electronic Signature Read They are shown in Tables 3 4
17. d Read of Data Polling bit DQ7 returns 0 then 1 on completion The Toggle Bit DQ6 toggles during erase operation and stops when erase is completed After comple tion the Status Register bit DQ5 returns 1 if there has been an Erase Failure because the erasure has not been verified even after the maximum number of erase cycles have been executed Table 12A Read AC Characteristics M29F040 TA 0 to 70 C 20 to 85 C 40 to 85 C or 40 to 125 C 9 iliis M29F040 D ec o Test Condition Voc 5V 5 5V 1096 Standard Standard EC RETE aS Address Valid to Output Valid ET NR EC Chip Enable Low to Output Transition NC Pj T Chip Enable Low to Output Valid as im sona Output Enable Low to Output F E is Output Enable Low to Output Valid L Chip Enable High to Output EI JEN Chip Enable High to Output Hi Z t Output Enable High to Output m GHOX Transition Output Enable High to Output Hi Z ERR RT Notes 1 Sampled only not 10096 tested 2 G may be delayed by up to terav tetov after the falling edge of E without increasing terav 3 The temperature range 40 to 125 C is guaranteed at 70ns with High Speed Interface test condition and Vcc 5V 5 Block Erase BE instruction This instruction uses a minimum of six write cycles The Erase Set up command 80h is written to address 5555h on third cycle after the two coded cycles
18. e AC Waveforms E9ELOIV l 318VN3 dIHO ANY QHIVA VIVO e 318VN3 LNdLNO 9 QGIIVASS3uQQ0v uBiH M 914813 AUM 910 Z0d 00d 13 31 M29F040 Table 13A Write AC Characteristics Write Enable Controlled Ta 0 to 70 C 20 to 85 C 40 to 85 C or 40 to 125 C t t WC tcs WP tps ipH 1 Write Enable High to Output Valid og E Write Enable High to Output Enable Low Note 1 Time is measured to Data Polling or Toggle Bit twHav twHa7v 7 2 The temperature range 40 to 125 C is guaranteed at 70ns with High Speed Interface test condition and Vcc 5V 5 Erase Resume ER instruction If an Erase Sus pend instruction was previously executed the erase operation may be resumed by giving the command 30h at any address and without any coded cycles Power Up The memory Command Interface is reset on power up to Read Array Either E or W must be tied to Viu during Power up to allow maximum security and the possibility to write a command on the first rising 14 81 adge of E or W Any write cycle initiation is blocked when Vcc is below Vi ko Supply Rails Normal precautions must be taken for supply volt age decoupling each device in a system should have the Vcc rail decoupled with a 1 0uF capacitor close to the Vcc and Vss pins The PCB trace widths should be sufficient to carry the Vcc pro gram and erase cu
19. h to Output Valid Block Erase tEHGL Chip Enable High to Output Enable Low Enable High to Output Enable Low tvcHwL wow EX Note 1 Time is measured to Data Polling or Toggle Bit twHav twHazv tazvav 3 18 91 M29F040 Figure 8 Write AC Waveforms E Controlled WRITE CYCLE VALID tEHEL DQ0 DQ7 VALID tEHDX Voc tVCHWL Al01366B Note Address are latched on the falling edge of E Data is latched on the rising edge of E 3 M29F040 Table 15A Data Polling and Toggle Bit AC Characteristics 1 Ta 0 to 70 C 20 to 85 C 40 to 85 C or 40 to 125 C 9 M29F040 70 Parameter Vcc 5V 10 Voc 5V 10 Standard Standard Interface Interface Write Enable High to DQ7 Valid Program W Controlled Write Enable High to DQ7 Valid Block Erase W Controlled Chip Enable High to DQ7 Valid Program E Controlled Chip Enable High to DQ7 Valid Block Erase E Controlled Q7 Valid to Output Valid Data Polling Write Enable High to Output Valid Program Write Enable High to Output Valid Block Erase Chip Enable High to Output Valid Program Chip Enable High to Output Valid Block Erase Notes 1 All other timings are defined in Read AC Characteristics table 2 twHazv is the Program or Erase time 3 The temperature range 40 to 125 C is guaranteed at 70ns with High Speed Interface
20. ion is reduced to the CMOS standby value while outputs are still driving the bus Electronic Signature Two codes identifying the manufacturer and the device can be read from the memory the manufacturer s code for STMicroelec tronics is 20h and the device code is E2h for the M29F040 These codes allow programming equip ment or applications to automatically match their interface to the characteristics of the particular manufacturer s product The Electronic Signature is output by a Read operation when the voltage applied to A9 is at Vip and address inputs A1 and A6 are at Low The manufacturer code is output when the Address input AO is Low and the device code when this input is High Other Address inputs are ignored The codes are output on DQ0 DQ7 This is shown in Table 4 The Electronic Signature can also be read without raising A9 to Vip by giving the memory the instruc tion RSIG see below Block Protection Each uniform block can be separately protected against Program or Erase Block Protection provides additional data security as it disables all program or erase operations This mode is activated when both A9 and G are set to Vip and the block address is applied on A16 A18 Block Protection is programmed using a Presto F program like algorithm Protection is initiated on the edge of W falling to Vii Then after a delay of 100us the edge of W rising to Vin ends the protection operation Protection verify is achieved by bri
21. nging G E and to while W is at Viu and A9 at Vip Under these conditions reading the data output will yield O1h if the block defined by the inputs on A16 A18 is protected Any attempt to program or erase a protected block will be ignored by the device Any protected block can be unprotected to allow updating of bit contents All blocks must be pro tected before an unprotect operation Block Un protect is activated when A9 G and E are at Vip The addresses inputs A6 A12 A16 must be main tained at Vin Block Unprotect is performed through a Presto F Erase like algorithm Unprotect is initi ated by the edge of W falling to Vit After a delay of 10ms the edge of W rising to ViH will end the unprotection operation Unprotect verify is achieved by bringing G and E to Vit while A6 and W are at Viu and A9 at Vip In these conditions reading the output data will yield OOh if the block defined by the inputs on A16 A18 has been suc cessfully unprotected All combinations of A16 A18 must be addressed in order to ensure that all of the 8 uniform blocks have been unprotected Block Protection Status is shown in Table 5 ky Figure 3 Memory Map and Block Address Table 64K Bytes Block 64K Bytes Block 64K Bytes Block 64K Bytes Block 64K Bytes Block Al01362B Instructions and Commands The Command Interface C I latches commands written to the memory Instructions are made up from one or more commands to perform Read A
22. ns for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality documents 2 Minimum Voltage may undershoot to 2V during transition and for less than 20ns 3 Depends on range tected against program and erase Block erasure may be suspended while data is read from other blocks of the memory and then resumed Bus Operations Seven operations can be performed by the appro priate bus cycles Read Array Read Electronic Signature Output Disable Standby Protect Block Unprotect Block and Write the Command of an Instruction Command Interface Command Bytes can be written to a Command Interface C I latch to perform Reading from the Array or Electronic Signature Erasure or Pro gramming For added data protection command execution starts after 4 or 6 command cycles The first second fourth and fifth cycles are used to input a code sequence to the Command Interface 6 This sequence is equal for all P E C instruc tions Command itself and its confirmation if it applies are given on the third and fourth or sixth cycles Instructions Seven instructions are defined to perform Reset Read Electronic Signature Auto Program Block Auto Erase Chip Auto Erase Block Erase Suspend and Block Erase Resume The internal Pro gram Erase Controller P E C handles all timing and verification of the Program and Erase instruc tions and provides D
23. pleted After completion the Status Register bit DOS returns 1 if there has been an Erase Failure because erasure has not completed even after the maximum number of erase cycles have been executed In this case it will be necessary to input a Reset RST to the command interface in order to reset the P E C 11 81 M29F040 Table 12B Read AC Characteristics TA 0 to 70 C 20 to 85 C 40 to 85 C or 40 to 125 C Symbol Parameter Test Condition Interface Interface Min Max Min Max uw we asians H Eu Reve wo wo a RN E Output Enable Low to Output LM Output Enable Low to Output Valid Chip Enable High to Output Ei RN tenor Chip Enable High to Output Hi Z Enable High to Output Hi Z t Output Enable High to Output SHOX Transition Output Enable High to Output Hi Z Address Transition to Output Notes X Sampled only not 100 tested 2 G may be delayed by up to terav tetov after the falling edge of E without increasing terav Program PG instruction The memory can be programmed Byte by Byte This instruction uses four write cycles The Program command AQ0h is written on the third cycle after two coded cycles A fourth write operation latches the Address on the falling edge of W or E and the Data to be written on its rising edge and starts the P E C During the execution of the program by the P E C the mem
24. put buffers decoders and sense amplifiers E High deselects the memory and reduces the power consumption to the standby level E can also be used to control writing to the command register and to the memory array while W remains at a low level Addresses are then latched on the falling edge of E while data is latched on the rising edge of E The Chip Enable must be forced to Vip during Block Unprotect operations Output Enable G The Output Enable gates the outputs through the data buffers during a read operation G must be forced to Vip level during Block Protect and Block Unprotect operations Write Enable W This input controls writing to the Command Register and Address and Data latches Addresses are latched on the falling edge of W and Data Inputs are latched on the rising edge of W Vcc Supply Voltage The power supply for all operations Read Program and Erase Vss Ground Vss is the reference for all voltage measurements ky M29F040 Table 6 Instructions 1 2 ast eye 2nd Cyc 3rd Cyc 4th Cyc 5th Cyc 6th Cyc 7th Cyc Read Memory Array until a new write cycle is initiated Daa Fon Addr 57 5555h 2AAAh 5555h Read Memory Array until a new write cycle is initiated be mm rm 3 7 39990 RANAN Spool Read Electronic Signature until a new write cycle is initiated See Note 5 AAh 55h 90h 5555h 2AAAh 5555h Read Block Protection until a new write cycle is initiated See Note 6
25. rase or chip erase that results in invalid data being programmed in the memory block In case of error in block erase or byte program the block in which the error occured or to which the pro grammed byte belongs must be discarded Other blocks may still be used Error bit resets after Reset RST instruction In case of success the error bit will set to 0 during Program or Erase and to valid data after write operation is completed ky M29F040 Table 9 AC Measurement Conditions Input Pulse Voltages 0 to 3V 0 45V to 2 4V 1 5V 0 8V and 2V Input and Output Timing Ref Voltages Figure 4 AC Testing Input Output Waveform High Speed Standard Al01275B Figure 5 AC Testing Load Circuit 1 3V 1N914 3 3kQ DEVICE UNDER TEST CL C 30pF for High Speed C 100pF for Standard C includes JIG capacitance Al01276B Table 10 Capacitance Ta 25 C f 1 MHz Note 1 Sampled only not 100 tested Erase Timer bit DQ3 This bit is set to 0 by the P E C when the last Block Erase command has been entered to the Command Interface and it is awaiting the Erase start When the wait period is finished after 80 to 120us DQ3 returns back to 1 Coded Cycles The two coded cycles unlock the Command Interface They are followed by a com mand input or a comand confirmation The coded cycles consist of writing the data AAh at address 5555h during the first cycle and data 55h at address 2AAAh
26. re Table 5 Block Protection Status Other oth h Protected Block Block Em va Vua va Vu Em Don t DontCare Note SA Address of block being checked DEVICE OPERATION Signal Descriptions Address Inputs A0 A18 The address inputs for the memory array are latched during a write opera tion The A9 address input is used also for the Electronic Signature read and Block Protect veri fication When A9 is raised to Vip either a Read Manufacturer Code Read Device Code or Verify Block Protection is enabled depending on the com bination of levels on AO A1 and When A1 and A6 are Low the Electronic Signature Manufac turer code is read when is High and A1 and are Low the Device code is read and when A1 is High and AO and A6 are low the Block Protection Status is read for the block addressed by A16 A17 A18 Data Input Outputs DQ0 DQ7 The data input is a byte to be programmed or a command written to the C I Both are latched when Chip Enable E and Write Enable W are active The data output is from the memory Array the Electronic Signature the Data Polling bit DQ7 the Toggle Bit DQ6 the Error bit DQ5 or the Erase Timer bit DQ3 Ou puts are valid when Chip Enable E and Output Enable G are active The output is high impedance 4 31 when the chip is deselected or the outputs are disabled Chip Enable E The Chip Enable activates the memory control logic in
27. rically at the block level and pro grammed Byte by Byte The interface is directly compatible with most mi croprocessors PLCC32 and TSOP32 8 x 20mm packages are available Both normal and reverse pin outs are available for the TSOP32 package Organisation The Flash Memory organisation is 512K x8 bits with Address lines AO A18 and Data Inputs Outputs DQO DQ7 Memory control is provided by Chip M29F040 Enable Output Enable and Write Enable Inputs Erase and Program are performed through the internal Program Erase Controller P E C Data Outputs bits DQ7 and DQ6 provide polling or toggle signals during Automatic Program or Erase to indicate the Ready Busy state of the internal Program Erase Controller Memory Blocks Erasure of the memory is in blocks There are 8 11748 uniform blocks of 64 Kbytes each in the memory address space Each block can be programmed and erased over 100 000 cycles Each uniform block may separately be protected and unpro Reverse 2 31 ky Table 2 Absolute Maximum Ratings 1 M29F040 Value Notes 1 Except for the rating Operating Temperature Range stresses above those listed in the Table Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied Exposure to Absolute Maximum Rating conditio
28. rray Reset Read Electronic Signature Block Erase Chip Erase Program Block Erase Suspend and Erase Resume Commands are made of ad dress and data sequences Addresses are latched on the falling edge of W or E and data is latched onthe rising of W or E The instructions require from 1 to 6 cycles the first or first three of which are always write operations used to initiate the com mand They are followed by either further write cycles to confirm the first command or execute the command immediately Command sequencing must be followed exactly Any invalid combination of commands will reset the device to Read Array The increased number of cycles has been chosen to assure maximum data security Commands are initialised by two preceding coded cycles which unlock the Command Interface In addition for Erase command confirmation is again preceeded by the two coded cycles P E C status is indicated during command execu tion by Data Polling on DQ7 detection of Toggle on M29F040 TOP BOTTOM ADDRESS ADDRESS 7FFFFh 70000h 6FFFFh 60000h 5FFFFh 50000h 4FFFFh 40000h 3FFFFh 30000h 2FFFFh 20000h 1FFFFh 10000h OFFFFh 00000h Table 7 Commands Erase Suspend Block Protection Status DQ6 or Error on DQ5 and Erase Timer DQ3 bits Any read attempt during Program or Erase com mand execution will automatically output those four bits The P E C automatically sets bits DQ3 DQ5 DOG and DQ7 Other bits DQ0 DQ1 DQ2 and DQ
29. rrents required 3 M29F040 Table 13B Write AC Characteristics Write Enable Controlled Ta 0 to 70 C 20 to 85 C 40 to 85 C or 40 to AES MO Interface Interface Cun we wm ma inn ie RE o Le e wr we Wit pms senn eo o ew te rouvan owe eroen 9 o wo te wit nabs tighoinpt tension 9 S mm Lec w wne ere in H won wr Wit seene enaner m a ww wm tas ess we er wt rable owt ates arson m vs ww onto Eat onto wae cramer o o e wee ws engo won T fire Enae tigro ouwpa vaa eega tw 1 woe a Note 1 Time is measured to Data Polling or Toggle Bit twHav twHa7v 7 3 15 91 M29F040 Figure 7 Write AC Waveforms W Controlled DQ0 DQ7 Voc WRITE CYCLE VALID tVCHEL Note Address are latched on the falling edge of W Data is latched on the rising edge of W 16 31 AI01365B 3 M29F040 Table 14A Write AC Characteristics Chip Enable controled Ta 0 to 70 C 20 to 85 C 40 to 85 C or 40 to 125 C 2 2 Farameter 5V 10 Voc 5V 10 ee Standard ee Interface Symbol Min Mex min Max we assess vaiswonencaacessvans m w ws ete Erato Low Grin natiouow o 0
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ST M29F040 Manual