Samsung K6T0808C1D Family handbook
Contents
1. November 19972. Memory array Row 256 rows select 128x8 columns I O Circuit Column select MY YY ARAYA A BG BN By A AW AN 6 6 6 6 A10 A3 AO Al A2 A9 At zi cs Control WE Logic OE SAMSUNG ELECTRONICS CO LTD reserves the right to change products and specifications without notice Revision 1 0 November 1997 K6T0808C1D Family PRODUCT LIST Commercial Temperature Products 0 70 C CMOS SRAM Industrial Temperature Products 40 85 C Part Name Function Part Name Function K6T0808C1D DL55 K6T0808C1D DB55 K6T0808C1D DL70 K6T0808C1D DB70 K6T0808C1D GL55 K6T0808C1D GB55 K6T0808C1D GL70 K6T0808C1D GB70 K6T0808C1D TL55 K6T0808C1D TB55 K6T0808C1D TL70 K6T0808C1D TB70 K6T0808C1D RL55 K6T0808C1D RB55 K6T0808C1D RL70 K6T0808C1D RB70 28 DIP 55ns L pwr 28 DIP 55ns LL pwr 28 DIP 70ns L pwr 28 DIP 70ns LL pwr 28 SOP 55ns L pwr 28 SOP 55ns LL pwr 28 SOP 70ns L pwr 28 SOP 70ns LL pwr 28 TSOP1 F 55ns L pwr 28 TSOP1 F 55ns LL pwr 28 TSOP1 F 70ns L pwr 28 TSOP1 F 70ns LL pwr 28 TSOP1 R 55ns L pwr 28 TSOP1 R 55ns LL pwr 28 TSOP1 R 70ns L pwr 28 TSOP1 R 70ns LL pwr FUNCTIONAL DESCRIPTION K6T0808C1D GP70 K
3. 32Kx8 e Power Supply Voltage 4 5 5 5V e Low Data Retention Voltage 2V Min e Three state output and TTL Compatible e Package Type 28 DIP 600B 28 SOP 450 28 TSOP1 0813 4 F R PRODUCT FAMILV Product Familv Operating Temperature Vcc Range GENERAL DESCRIPTION The K6T0808C1D families are fabricated by SAMSUNG s advanced CMOS process technology The families support various operating temperature ranges and have various package types for user flexibility of system design The fami lies also support low data retention voltage for battery back up operation with low data retention current Power Dissipation Standby Operating IsB1 Max lcc2 Max Speed PKG Type K6T0808C1D L K6T0808C1D B K6T0808C1D P K6T0808C1D F Commercial 0 70 C 4 5 to 5 5V Industrial 40 85 C 1 The parameter is tested with 50pF test load PIN DESCRIPTION A14 A12 WE 28 TSOP A7 Type1 Forward A6 A5 A4 A3 A2 A1 AO 1 01 28 TSOP 102 Type1 Reverse 1 03 VSS Function Pin Name Function 30uA 28 DIP 28 SOP 55 70ns 5LA 28 TSOP1 F R Chip Select Input 1 01 1 03 Data Inputs Outputs Output Enable Input Vcc Power Write Enable Input Vss Ground Address Inputs NC No connect 30uA 28 SOP 70ns 5UA 28 TSOP1 F R FUNCTIONAL BLOCK DIAGRAM Clk gen Precharge circuit
4. 40 to 85 C otherwise specified 2 Overshoot Vcc 3 0V in case of pulse width lt 30ns 3 Undershoot 3 0V in case of pulse width lt 30ns 4 Overshoot and undershoot are sampled not 100 tested CAPACITANCE f 1MHz TA 25 C Item Test Condition Input capacitance Vin 0V Input Output capacitance Vio 0V 1 Capacitance is sampled not 100 tested DC AND OPERATING CHARACTERISTICS Item Test Conditions Input leakage current Vin Vss to Vcc Output leakage current CS VIH or OE VIH or WE VIL Vio Vss to Vcc Operating power supply current llo 0mA CS VIL VIN VH or VIL Read Cycle time 1us 100 duty lio OmA Read Average operating current CS lt 0 2V Vin lt 0 2V Vin gt Vcc 0 2V Write Cycle time Min 100 duty llo 0mA CS VIL VIN VIH or VIL Output low voltage loL 2 1mA Output high voltage loH 1 0mA Standby Current TTL CS VIH Other inputs VIH or VIL Low Power Standby Current CMOS CS Vcc 0 2V Other inputs 0 Vcc Low Low Power F Revision 1 0 L November 1997 K6T0808C1D Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS Test Load and Test Input Output Reference O e O Input pulse level 0 8 to 2 4V Input rising and falling time 5ns CL Input and output reference voltage 1 5V Output load See right CL 100pF 1TTL V CL 50pF 1 TTL 1 Including scope and jig capacitance AC CHARACTERISTICS
5. vcc 4 5 5 5V K6T0808C1D L Family TA 0 to 70 C K6TO808C1D P Family TA 40 to 85 C Speed Bins Parameter List 70ns Min Read cycle time 70 Address access time Chip select to output Output enable to valid output Chip select to low Z output Output enable to low Z output Chip disable to high Z output Output disable to high Z output Output hold from address change Write cycle time Chip select to end of write Address set up time Address valid to end of write Write pulse width Write recovery time Write to output high Z Data to write time overlap Data hold from write time End write to output low Z 1 The parameter is tested with 50pF test load DATA RETENTION CHARACTERISTICS Item Test Condition Vcc for data retention CS gt Vcc 0 2V Data retention current Vcc 3 0V CS gt Vcc 0 2V Data retention set up time See data retention waveform Recovery time F Revision 1 0 gt November 1997 ELECTRONICS K6T0808C1D Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE 1 Address Controlled CS OE Vit WE ViH RC Address TAA tOH gt Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE 2 wE Vm RC Address Data out Data Valid NOTES READ CYCLE 1 tHZ and tOHZ are def
6. 035 0 016 0 004 Q amp Z MIN Revision 1 0 November 1997 CMOS SRAM Units millimeter inch K6T0808C1D Family PACKAGE DIMENSIONS 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 0813 4F xix lt g aia 13 40 0 20 gS 0 20 216 0 5284 0 008 sis 0 00800 M 9900 002 H EH 28 Q EM EA JF PEA Hp Rx y CU BH H HS A RZ IE a l 1 H 0 425 E pH i 0 017 y cy E 2 1 1 ca E 0 55 y Hp Vio 3 0217 14 ES 15 0 25 11 80 0 10 l 0 010 ap 0 465 0 004 gt 0 15 008 y ZEN 0 006 1 00 0 10 0 05 MIN 0 80 f L 0 039 0 004 AP 0 002 A Ti a 1 20 nna7MAX 0 047 0 45 0 75 0 50 0 018 0 030 e 0 020 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 0813 4R x lt g2 ce SS Slo 0 20 70 10 _13 40 0 20 _ Es 0 528 0 008 gt 0 0085 902 414 F E 15 TE A E Y oo MAI E 0 017 oc lt 1 Hp ol j 4 CO m foo o 14 H co lt E i 0 55 217 1 mo 428 4 v Hin 1 00 0 10 0 05 MIN i 80 0 10 7 0 039 0 004 0 002 0 010 TYP q 0 465 0 004 gt 0 15 005 a ers 0 006938 120 aa 0 047 0 89 CJ 0 45 0 75 0 018 0 030 gt Revision 1 0 lt gt
7. 2576 K6T O808C 1D 117 EJ K6T0808C1D Family CMOS SRAM Document Title 32Kx8 bit Low Power CMOS Static RAM Revision History Revision No History Draft Data 0 0 Initial draft May 18 1997 0 1 First revision April 1 1997 KM62256DL DLI IsB1 100 gt 50uA KM62256DL L IsB1 20 gt 10uA KM62256DLI L IsB1 50 gt 15uA CIN 6 gt 8pF Clo 8 gt 10pF KM62256D 4 5 7 Family tOH 5 gt 10ns KM62256DL DLI IDR 50 gt 30uA KM62256DL L DLI L IDR 30 gt 15uA 1 0 Finalize November 11 1997 Remove Icc write value Improved operating current Icc2 70 gt 60mA Improved standby current KM62256DL DLI IsB1 50 gt 30uA KM62256DL L IsB1 10 gt 5uA KM62256DLI L IsB1 15 gt 5uA Improved data retention current KM62256DL DLI IDR 30 gt 5uA KM62256DL L DLI L IDR 15 gt 3uA Remove 45ns part from commercial product and 100ns part from industrial product Replace test load 100pF to 50pF for 55ns part Remark Design target Preliminily Final The attached datasheets are provided by SAMSUNG Electronics SAMSUNG Electronics CO LTD reserves the right to change the specifications and products SAMSUNG Electronics will answer to your questions about device If you have any questions please contact the SAMSUNG branch offices GT Revision 1 0 November 1997 K6T0808C1D Family CMOS SRAM 32Kx8 bit Low Power CMOS Static RAM FEATURES e Process Technology TFT e Organization
8. 6T0808C1D GF70 K6T0808C1D TP70 K6T0808C1D TF70 K6T0808C1D RP70 K6T0808C1D RF70 28 SOP 70ns L pwr 28 SOP 70ns LL pwr 28 TSOP1 F 70ns L pwr 28 TSOP1 F 70ns LL pwr 28 TSOP1 R 70ns L pwr 28 TSOP1 R 70ns LL pwr Mode Power Deselected Standby Output Disabled Active Read Active 1 X means don t care Must be in high or ABSOLUTE MAXIMUM RATINGS Item Symbol Ratings Write Active Voltage on any pin relative to Vss VIN VOUT 0 5 to 7 0 Voltage on Vcc supply relative to Vss Voc 0 5 to 7 0 Power Dissipation PD 1 0 Storage temperature TSTG 65 to 150 Operating Temperature TA 0 to 70 K6T0808C1D L 40 to 85 K6T0808C1D P Soldering temperature and time TSOLDER 260 C 10sec Lead Only 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device Functional operation should be restricted to recommended operating condition Exposure to absolute maximum rating conditions for extended periods may affect reliability Revision 1 0 November 1997 K6T0808C1D Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS Item i Max Supply voltage E i 5 5 Ground 0 Input high voltage Vec 0 5V Input low voltage 0 8 Note 1 Commercial Product Ta 0 to 70 C otherwise specified Industrial Product Ta
9. NE PACKAGE 600mil Units millimeter inch 0 25 202 0 01 Ooo 28 15 A A Z 7 13 60 0 20 ale 0 535 0 008 Se o O v y 14 0 154 36 72 _3 81 0 20 _ 1 446 MAX 0 150 0 008 5 08 96 924 020 0 200 MAX i 0 le 0 008 gt y ll A A H y I y Y UNUT I y 3 30 0 30 CLERO 0 130 0 012 1 65 1 52 0 10 0 38 MIN 0 065 A 0 060 0 004 0 015 28 PIN PLASTIC SMALL OUTLINE PACKAGE 450mil pees 28 15 A A gt lo 11 81 0 30 8 38 0 20 nd 0 465 0 012 0 330 0 008 Elo y 1 y U 1 14 0 15 010 eos o 19 0 05 040 o i gwax AiE oooga SAGE a 3 00 18 29 0 20 0 118MAX lq 0 720 0 008 gt I ial 0 10 MAX y 6 004 MAX 1 A 0 89 0 41 0 10 1 27 0
10. ined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels 2 At any given temperature and voltage condition tHZ Max is less than tLZ Min both for a given device and from device to device interconnection F Revision 1 0 November 1997 ELECTRONICS K6T0808C1D Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE 1 WE Controlled Address Data in Data Valid tWHZ gt NIEJ Data out Data Undefined TIMING WAVEFORM OF WRITE CYCLE 2 CS Controlled two Address Data in Data Valid Data out Highz High Z NOTES WRITE CYCLE 1 A write occurs during the overlap of a low CS and a low WE A write begins at the latest transition among CS going Low and WE going low A write end at the earliest transition among CS going high and WE going high twr is measured from the begining of write to the end of write 2 tcw is measured from the CS going low to end of write 3 tAS is measured from the address valid to the beginning of write z 4 twa is measured from the end of write to the address change twR applied in case a write ends as CS or WE going high DATA RETENTION WAVE FORM CS controlled l Data Retention Mode tRDR tSDR Vcc e E O ay a eae Se CS2Vcc 0 2V F Revision 1 0 November 1997 K6T0808C1D Family CMOS SRAM PACKAGE DIMENSIONS 28 PIN DUAL INLI
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Samsung K6T0808C1D Family handbook