IDT IDT70V3599/89S Manual
Contents
1. 0b 1b Oc tc Od 1d FI PIPEL Qa 1a a b c d CE ry CEoL ie et CEIL HED 10 OEL ai FT PIPEL o 1 OoL VO35L CLK Ateli Counter REPEATL Address ADSL CNTENL 1 A16 is a NC for IDT70V3589 128K x MEI 36 MORY AY FT PIPER Le 4 Thy OS Cie Ce 1 0 T OER R R R R n je FT PIPER gt I OoR I O35R r CLKr A16R Counter R Address REPEATR ADSR CNTENR 5617 tbl 01 2003 Integrated Device Technology Inc DSC 5617 6 IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Description The IDT70V3599 89 is a high speed 128 64K x 362. gt jp tCH2 tCL2 gt CLK A NX NA NZZ NAA OPN SA tHA 4 ADDRESS An An 1 an 2 3 NEE P MIERDA Ax LAST ADS LOAD LAST ADS 1 An An 1 a R W l i ADS Yep Ltuaph CNTEN Yhsoy len tSCN tHCN tSRPT lt gt lt gt SD HD DATAN LK Do A DATAouT QLAST QLAST 1 Qn EXECUTE One WRITE _ gt READ READ gt READ gt i lt READ gt REPEAT LAST ADS LAST ADS LAST ADS ADDRESS n ADDRESS n 1 ADDRESS ADDRESS ADDRESS 1 5617 drw 19 NOTES _ 1 CEo BEn and R W Vit CE1 and REPEAT Vin 2 CEo BEn Vi CE1 Vin 3 The Internal Address is equal to the External Address when ADS Vit and equals the counter output when ADS Vin 4 Addresses do not have to be accessed sequentially since ADS Vit constantly loads the address on the rising edge of the CLK numbers are for reference use only Output state High Low or High impedance is determined by the previous cycle control signals No dead cycle exists during REPEAT operation A READ or WRITE cycle may be coincidental with the counter REPEAT cycle Address loaded by last valid ADS load will be accessed Extra cycles are shown here simply for clarification For more information on REPEAT function refer to Truth Table Il 7 CNTEN Vil advances Internal Address from An to An 1 The transition shown indicates the time required for the counter t
3. vaa fio soy oer fas aa a v Vss Ground jos fo fo oY VH Input High Voltage 2 0 Vopa 150mV Address amp Control ia er VIH input High Voltage V09 High Voltage 0 20 Vona 150mV v v rouo forf o S 5617 tbl 05b NOTES 1 Undershoot of Vit gt 1 5V for pulse width less than 10ns is allowed 2 VTERM must not exceed Voda 150mV 3 To select operation at 3 3V levels on the I Os and controls of a given port the OPT pin for that port must be set to VIH 3 3V and Vopax for that port must be supplied as indicated above IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Capacitance Ta 25 C F 1 0MHz PQFP ONLY Symb Paneer Conditons mar uit Input Capacitance Vin 3dV a oF Output Capacitance Vout 3dV 5617 tbl 07 NOTES 1 These parameters are determined by device characterization but are not production tested 2 3dV references the interpolated capacitance when the input and output switch from OV to 3V or from 3V to OV 3 Cout also references Cio DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Vpp 3 3V 150mvV 70V3599 89S Symbol Parameter Test Conditions Mn Max u Taa ae ILo CEo Vi or CE1 Vil VouT OV to Vopa o ua raean omais seam vine vr 2a omanan oes ana vey PT 5617 tbl 08 NOTE 1 At
4. 141 1 014R E14 E15 E16 E17 Voa is on 1 0121 1 O13R Vss 1 013 F1 F2 F3 F4 F14 F15 F16 F17 Vopat O23r 1 O24L Vss Vss 1 012R 1 0111 VDDAR G1 G2 G3 G4 G14 G15 G16 G17 O26 Vss 1 0251 1 024R 1 O9L VopaL 1 0101 1 011R H1 H2 H3 H4 H14 H5 Hi6 H17 BF 208 Ji J2 J3 J4 J14 J15 J16 J17 i 208 Pin foBGA K1 K2 K3 K4 f 7 K14 K15 K16 K17 VOzsr Vss ozz Vss Top View VO7R Vooa Osr vss i L2 L3 L4 L14 415 jue L17 1 O29R 1 0281 VoDar 1 027L Oer O7L Vss 1 OsL M1 M2 M3 M4 Mi4 m5 Mme M17 VopaL l O291 1 O30R Vss Vss 1 OeL I O5R VDDAR ni4 i5 Nie N17 1 O31L Vss 1 O31r OsoL V O3R Vopat 1 04R 1 O5L P1 P2 P3 P4 P5 P6 P7 P8 P9 pio P14 P12 P13 pi4 P15 Pie fP17 1 O32R 1 0321 Vopar 1 O35r TRST Aier A12R Asr BEiR Voo CLKRICNTENA Agr 1O21 1 OsL Vss 1 04 Rt R2 R3 R4 R5 R6 R7 R8 R9 Ro RI R12 R3 R4 Iris Rie R17 Vss I O33L 1 O34R TCK NC AisR A9 BE2R CEoR Vss ADSR Asr AiR Vss Vopat I 01R VDDaR Ti T2 T3 T4 T5 T6 T7 Teo fT T10 T11 T12 T13 T14 T5 me T17 O33R O34L VopaL TMS NC Aian Aion BEsR CE1R Vss RAWR Aer Agr Vss I Oor Vss 1 O2R K u3 u5 U6 U7 u8 ug u10 11 u12 u13 ui4 fuis fuie u17 feet PL FTRI We AisR A11R A7R BEoR Voo OER JREPEATR Asr Aor Voo OPTR Ool 1 O1L 5617 drw 02c NOTES 1 A16 is a NC for IDT70V3589 2 All VoD pins must be connected to 3 3V power supply 3 A
5. 2578 D T70V 3584 hy A IDT HIGH SPEED 3 3V 128 64K x 36 SYNCHRONOUS DUAL PORT STATIC RAM IDT70V3599 89S WITH 3 3V OR 2 5V INTERFACE Features True Dual Port memory cells which allow simultaneous access of the same memory location High speed data access Commercial 3 6ns 166MHz 4 2ns 133MHz max Industrial 4 2ns 133MHz max Selectable Pipelined or Flow Through output mode Counter enable and repeat features Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports 6nscycle time 166MHz operation 12Gbps bandwidth Fast 3 6ns clock to data out 1 7ns setup to clock and 0 5ns hold on all control data and address inputs 166MHz Data input address byte enable and control registers Self timed write allows fast cycle time Functional Block Diagram Est 4 gt Separate byte controls for multiplexed bus and bus matching compatibility Dual Cycle Deselect DCD for Pipelined Output mode LVTTL compatible 3 3V 150mV power supply for core LVTTL compatible selectable 3 3V 150mV or 2 5V 100mV power supply for I Os and control signals on each port Industrial temperature range 40 C to 85 C is available at 133MHz Available in a 208 pin Plastic Quad Flatpack PQFP 208 pin fine pitch Ball Grid Array fpBGA and 256 pin Ball Grid Array BGA Supports JTAG features compliant with IEEE 1149 1
6. A AA j tSA p TH ADDRESS XK an An 1 an 2 XX KKK anes tcD1 gt 4 toc gt Cc tCKHZ gt DATAout Qn KXKKX an 1 Qn 20 He tcKLz tOHz i iz a DC _ be OE NOTES tOE gt 5617 drw 07 1 OE is asynchronously controlled all other inputs are synchronous to the rising clock edge 2 ADS Vit CNTEN and REPEAT Vin 3 The output is disabled High Impedance state by CEo Vi CE1 Vit BEn Vin following the next rising edge of the clock Refer to Truth Table 1 4 Addresses do not have to be accessed sequentially since ADS Vi constantly loads the address on the rising edge of the CLK numbers are for reference use only 5 If BEn was HIGH then the appropriate Byte of DATAout for Qn 2 would be disabled High Impedance state 6 x denotes Left or Right port The diagram is with respect to that port 12 IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of a Multi Device Pipelined Read1 2 j tcyc2 gt tCH2 gt a tCL2 CLK SA JHA ADDRESS B1 Ao XXX At xx A2 Poe A3 XXX A4 xX A5 X Xm eem EPO LA AY NRA X omaron IILI IK XX KO oc atO tCKLZ CKHZ ADDRESS 82 A SOK at XOX a XXX As Xm XXX as eet DATAOUT B2 Q2 Q4 CKLZ CKLZ 5617 drw 08 Timing Waveform of a Multi
7. DOYTANUMNTNORDDOCOCCS Soe ge OK LOSs SER RT ESSER HT ETERS BES HERSEESSSSESSSSEgEgg NNN 88 SE 25e Beeece ct BRB BM gt gt gt gt slept lt lt lt e lt lt gt gt gt 5 Soa Ole NOTES A16 is a NC for IDT70V3589 All Voo pins must be connected to 3 3V power supply All Vopa pins must be connected to appropriate power supply 3 3V if OPT pin for that port is set to Vi 3 3V and 2 5V if OPT pin for that port is set to ViL OV All Vss pins must be connected to ground supply Package body is approximately 28mm x 28mm x 3 5mm This package code is used to reference the package diagram This text does not indicate orientation of the actual part marking SLO eo IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Names a Ta BEoL BEsL BEor BEsr Byte Enables 9 bit bytes VDAL Vppar Power I O Bus 3 3V or 2 5V NOTES OPTL OPTR Option for selecting Vonax 1 A16 is a NC for IDT70V3589 2 VoD OPTx and Vopax must be set to appropriate operating levels prior to VoD Power 3 3V applying inputs on the I Os and controls for that port Vss Ground 0V 3 OPTx selects the operating voltage levels for the I Os and controls on that port If OPTx is set to VIH 3 3V then that port s I Os and controls will operate at 3 3V TDI Test Data Input levels and Vopax must be supplied at 3 3V If OPTx is set to VIL OV then that po
8. Device Flow Through Read tcyc1 gt t tCHi gt tCL1 gt GLK E aN Ne NL Nee n SA JHA ADDRESS B1 Ao A1 KX A2 A3 A4 A5 A6 en donde CE0 B1 so IPN T T e t001 tens Leto __tcp1 p tcD1 DATAOUT B1 LXX Do Di Ds X Ds joc tD tcxz tex tekiz Ay tH ADDRESSe2 Oe k Al A2 A3 A4 A5 As l j HC otea Ye lant SEX DATAoutT B2 5617 drw 09 NOTES 1 B1 Represents Device 1 B2 Represents Device 2 Each Device consists of one IDT70V3599 89 for this waveform _and are setup for depth expansion in this example ADDRESS 1 ADDRESS e2 in this situation 2 BEn OE and ADS ViL CE1 B1 CE1 82 RAV CNTEN and REPEAT Vin IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Left Port Write to Pipelined Right Port Read 1 2 4 CLK a ao A NS A NRSC A N tsw _ tHWw rae RWa SA tHA ugn NO APRESS MATCH v CCC CCC COTOONS X tsD _ tHD CLK B Z N tcb2 gt a NO ADDRESS Karon gt oD 046 646 6064 DATAouT B VALID x NOTES Eg De 5617 drw 10 1 CEo BEn and ADS Vi CE1 CNTEN and REPEAT Vin 2 OE Vit for Port B which is being read from OE ViH for Port A which is being written to 3 If tco lt minimum specified then data fr
9. E1 WA xX lt x xx 438 H3 BEn AX AX AX syy ADDRESS gt lt gt lt An XOXA 1 X An 2 lt an 3 xx Xan 4 an DOCX sana 4s0 juo a 0 er ois 2K pn 3X tCKLZ tcp2 DATAOuT DOORKXX x READ gt WRITE gii READ NOTES 5617 diw 13 1 Output state High Low or High impedance is determined by the previous cycle control signals 2 CEo BEn and ADS Vit CE1 CNTEN and REPEAT ViH _ 3 Addresses do not have to be accessed sequentially since ADS ViL constantly loads the address on the rising edge of the CLK numbers are for reference use only 4 This timing does not meet requirements for fastest speed grade This waveform indicates how logically it could be done if timing so allows IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow Through Read to Write to Read OE Vil j icver rm tCH1 tCLi gt CLK A SF NH w FHF KH CEo ISG tHG CE1 SB LtH BEn SW tHW R W xs jsw tHw ADDRESS An An 1 Xan 2 An aX An 3 Kan 4 x dSA JHA isp EHD DATAIN Dn 2X 1 tcD1 E a ICD a CDI p DATAouT Qn Nan 1 K Qn 3 G gt ee tCKLZ pg READ gt lt NOP gt WRITE 1 READ 6517 diw 14 Timing Waveform of Flow Through Read to Write to Read OE Co
10. G4 Gio Jan 12 Giz jai4 e15 ate 1 O24R 1 0241 1 0251 VDDaR pa ve ea es ne Vss Vss Vss Vppa_ I O10L 1 O11L 1 011R H H5 H6 H7 mo H1 H12 H13 Hi4 j H15 jHi6 O26L ion ae ppar Vss Vss Vss ke lS Vss Vss Vss VppaL I OgR IOgL 1 O10R J1 J5 J10 J11 J12 J13 J4 yt5 J16 1 027L om losak DDaL Vss am he i ee Vss Vss Vss VppaR I OsR I O7R I Os Ki K3 Kio ki K12 K3 Kia K5 jki6 O29R fom ical VDDQL p A iM Vss Vss Vss VpparR I Oer l OeL I O7L L1 L5 p L11 L12 L13 14 L15 J6 1 O30L fon oe on VDD i nye Ass es Vss VoD VbDDQL 1 Os 1 O4R I OsR M1 M2 M3 M4 M5 M6 Mo fmn M12 M14 Mi5 Mmi6 1 O2R 1 0321 O3iL VpparR VoD VDD ne Ee Vss VoD VoD VpbaL I O3R 1 03 O4L N1 N2 N3 N4 N5 N6 N7 Nio N N12 N13 N14 Nis Nie 1 033L 1 034R I O33R JPIPE FTR VDDaRI VDDAR aah VDDQL on DDAR VDDaL VDDAL Voo 1 021 I O1R 1 02R P1 P2 P3 P4 P5 P6 P7 P10 P11 P12 p13 P14 P15 P16 O35R 1 O34L TMS A16R A13R Aton A7R Ein Eon CLKR ADSR Aor Asr I OoL 1 Oor 1 O1L Ri R2 R3 R4 R5 R6 R7 R8 R9 RIO Ri R12 R13 Ri4 Ri5 R16 VO3L NC TRST NC AisR A12R A9 BE3R CEoR R WR REPEATR A4sR Air OPTR NC NC Ti T2 T3 T4 T5 T6 T7 Te T9 mo fmu T12 T13 T14 T15 T16 NC TCK NC NC AiR Air Asr BE2R CE1R OER CNIENR Asr Agr Aon NC NC 5617 drw 02d NOTES 1 Ate is a NC for IDT70V3589 2 All VoD pins must be connected to 3 3V p
11. H ADDRESS COUNTER 5617 drw 16 Timing Waveform of Flow Through Read with Address Counter Advance j tcvei_ 4 CH1 tCLi gt CLK Hi A a ee Ny tSA_ tHA ADDRESS f a KX LISAQ tpapi tSCN tHCN lt a DATAout Qx Qn lt Xan X Qn 2 Qn 3 Qn 4 _ ide READ gt READ WITH COUNTER _ COUNTER READ EXTERNAL HOLD WITH ADDRESS COUNTER 5617 drw 17 NOTES 1 CEo OE BEn Vit CE1 RW and REPEAT Vin 2 If there is no address change via ADS Vit loading a new address or CNTEN Vit advancing the address i e ADS Vin and CNTEN Vin then the data output remains constant for subsequent clocks IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance Flow through or Pipelined Inputs lt tcyc2 gt He tcH2 eHe tcL2 gt CLK NA A NAA N NG SA Van ADDRESS Lan gt INTERNAL XXX X An An 1 An 2 An 3 An 4 ADDRESS tSCN tHCN lt gt lt gt tsD tHD lt _ DATAN KX Dn KX bn 1 XX Xon 2 Dn DOCX Dn 4X WRITE om lat WRITE gt a WRITE gt a a EXTERNAL WITH COUNTER cou R EoD WRITE WITH COUNTER Timing Waveform of Counter Repeat ya
12. TIN Junction Temperature lout DC Output Current BERA TsTG Temperature Under Bias 55 to 125 lt NOTES 5617 tbl 06 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 VTERM must not exceed Voo 150mV for more than 25 of the cycle time or 4ns maximum and is limited to lt 20mA for the period of VTERM gt VoD 150mV 3 Ambient Temperature Under Bias No AC Conditions Chip Deselected Recommended DC Operating Conditions with Vppa at 2 5V srmo poom in m m ot hosoro 2a asf 26 S eem CCE VH Input High Voltage 1 7 Voa 100mVv Address amp Control Inputs VH input High Voltage VO Voltage input High Voltage VO ari Vopa 100mV Lv v rooe ase or 5617 tbl 05a NOTES 1 Undershoot of Vit gt 1 5V for pulse width less than 10ns is allowed 2 VTERM must not exceed Voda 100mV 3 To select operation at 2 5V levels on the I Os and controls of a given port the OPT pin for that port must be set to VIL OV and Vopax for that port must be supplied as indicated above Recommended DC Operating Conditions with Vppa at 3 3V TE
13. V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range Read and Write Cycle Timing von 3 3v 150mv Ta 0 C to 70 C all i me 5 n n n n n n n 70V3599 89S166 70V3599 89S133 Com Only om amp Ind Symbol Parameter te 3 i Or Ea S E FPTeofes elfTerslT Telrerl1 elrl1elrIT ets afna Nlofwfaypnfpofrnfoalwfoapfnpaypa tcyct Clock Cycle Time Flow Through 20 25 tcyc2 Clock Cycle Time Pipelined tcH2 Clock High Time Pipelined tcL2 Clock Low Time Pipelined tsa Address Setup Time tHA Address Hold Time tsc Chip Enable Setup Time tHe Chip Enable Hold Time tSB Byte Enable Setup Time n tHB Byte Enable Hold Time tsw R W Setup Time n tHw R W Hold Time tsb Input Data Setup Time tHD Input Data Hold Time n n ADS Setup Time tHAD ADS Hold Time 0 5 n tscn CNTEN Setup Time ten CNTEN Hold Time tSRPT REPEAT Setup Time tHRPT REPEAT Hold Time A N toE Output Enable to Data Valid tolz Output Enable to Output Low Z toHz Output Enable to Output High Z 1 tcp1 Clock to Data Valid Flow Through ao gt s i n tcp2 Clock to Data Valid Pipelined ns Data Output Hold After Clock High 1 1 Port to Port Delay 5617 tbl 11 NOTES 1 The Pipelined output parameters tcyc2 tcp2 apply to either o
14. Voo lt 2 0V leakages are undefined 2 Vppa is selectable 3 3V 2 5V via OPT pins Refer to p 5 for details IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range voo 3 3V 150mv 70V3599 89S166 70V3599 89S133 Symbol Parameter Test Condition Version i S Dynamic Operating CEL and CER VL Current Both Outputs Disabled Ports Active f Max a lt GS 2 gt 3 gt Standby Current CEL CER VH Both Ports TTL Outputs Disabled Level Inputs f fax 3 gt Standby Current CE Vit and CE s VH One Port TTL Active Port Outputs Disabled Level Inputs f fmax Full Standby Current Both Ports Outputs Disabled Both Ports CMOS CEL and CER gt VDD 0 2V Level Inputs VN gt VDD 0 2V or VN lt 0 2V f 0 3 gt oa w oO oa wo 3 gt Full Standby Current CE a lt 0 2V and CE B gt VDD 0 2V One Port CMOS VIN gt VDD 0 2V or VIN lt 0 2V Level Inputs Active Port Outputs Disabled f fax N oa NOTES 5617 tbl 09 1 Atf fmax address and control lines except Output Enable are cycling at the maximum frequency clock cycle of 1 tcyc using AC TEST CONDITIONS at input levels of GND to 3V 2 f 0 means no address clock or control lines change Appl
15. ated earlier in this document 4 JTAG operations occur at one speed 10MHz The base device may run at any speed specified in this datasheet IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Identification Register Definitions Revision Number 31 28 Reserved for version number IDT Device ID 27 12 0x0312 Defines IDT part number IDT JEDEC ID 11 1 Allows unique identification of device vendor as IDT ID Register Indicator Bit Bit 0 Indicates the presence of an ID register NOTE 5617 tbl 13 1 Device ID for IDT70V3589 is 0x0313 Scan Register Sizes Register Name Instruction IR Bypass BYR Identification IDR Boundary Scan BSR 5617 tbl 14 System Interface Parameters EXTEST 0000 Forces contents of the boundary scan cells onto the device outputs Places the boundary scan register BSR between TDI and TDO BYPASS 1111 Places the bypass register BYR between TDI and TDO IDCODE 0010 Loads the ID register IDR with the vendor ID code and places the register between TDI and TDO HIGHZ 0011 Places the bypass register BYR between TDI and TDO Forces all device output drivers to a High Z state SAMPLE PRELOAD 0001 Places the boundary scan register BSR between TDI and TDO SAMPLE allows data from device inputs to be captured in the boundary scan cells and shifted serially through TDO PRELOAD allows data to be input
16. bitsynchronous or bidirectional data flow in bursts An automatic power down feature Dual Port RAM The memory array utilizes Dual Port memory cells to controlled by CEoand CE1 permits the on chip circuitry of each port to allow simultaneous access of any address from both ports Registerson enter a very low standby power mode control data and address inputs provide minimal setup and hold The 70V3599 89 can support an operating voltage of either 3 3V or times The timing latitude provided by this approach allows systems 2 5V ononeorbothports controllable bythe OPT pins The powersupply tobedesignedwith very shortcycle times With aninputdataregister the for the core of the device VDD remains at 3 3V IDT70V3599 89 has been optimized for applications having unidirectional Pin Configuration 23 45 06 28 02 A1 A2 A3 A4 A5 A6 A7 A8 A9 Aio fati A12 A3 jais jas faie JA17 lO1oL lOisL Vss TDO NC AieL Aiz As BEiL Voo CLKL CNTENL AsL Ao OPTL 1 0171 Vss B1 B2 B3 B4 B5 B6 B7 B8 B9 Bio B11 B12 B13 f Bi4 B15 Bie B17 VOz R Vss O1sr TDI NC Ais Ao BE2L CEo Vss ADSL Ast AiL Vss Vopar 1 O1eL 1 015R C1 c2 c3 C4 c5 c6 C7 c8 c9 cio c c12 fca fca fcis jcie C17 VoDa O19R Vopar PL FTL NC A14t Aio BEaL CEIL Vss RAWL AeL A2L Voo 1 O1er 1 Oi5L Vss D1 D2 D3 D5 D6 D9 Dio D11 D12 f D13 D4 pbi5 foie D17 VOz2L Vss 1 O2iL Oa Ais A11L ee RA Voo OEL REPEATL AsL Voo 1 O17R VopaL 1 0
17. ies only to input at CMOS level standby 3 Port A may be either left or right port Port B is the opposite from port A 4 VoD 3 3V Ta 25 C for Typ and are not production tested IDD pc f 0 120mA Typ 5 CEx Vit means CEox Vit and CE1x VIH CEx Vin means CEox Vik or CE1x VIL CEx lt 0 2V means CEox lt 0 2V and CE1x gt Vcc 0 2V CEx gt Vcc 0 2V means CEox gt Vcc 0 2V or CE1x 0 2V X represents L for left port or R for right port IDT70V3599 89S Industrial and Commercial Temperature Ranges High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM AC Test Conditions Vona 3 3V 2 5V 2 5V Input Pulse Levels Address amp Controls GND to 3 0V GND to 2 4V Input Pulse Levels I Os GND to 3 0V GND to 2 4V 8330 Input Rise Fall Times 2ns Input Timing Reference Levels 1 5V 1 25V DATAOUT Output Reference Levels 1 5V 1 25V 7700 5pF Output Load Figures 1 and 2 5617 tbl 10 3 3V 590Q 50Q 50Q DATAoUT E Dw 1 5V 1 25 DATAouT e 10pF 5pF I Tester me p a 5617 drw 03 Figure 1 AC Output Test load 2 5617 drw 04 Figure 2 Output Test Load For tckLz tcKHz tolz and touz Including scope and jig 10 5pF is the I O capacitance of this device and 10pF is the AC Test Load Capacitance AtCD Typical ns po woof O ODN T t T T T 20 5 30 50 80 100 200 Capacitance pF 5617 drw 05 Figure 3 Typical Output Derating Lumped Capacitive Load IDT70
18. ing is the same for both left and right ports Port A may be either left or right port Port B is the opposite of Port A 14 IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read to Write to Read OE Vin 2 tcyc2 gt K tcHo toL CLK 7 E Ss ee RK Re o K o lt x X y SW fH RW ZN sw gy OO ADDRESS gt lt An An 1 An 2 An 2 An 3 Xan 4 SAn HA s9 Hn DATAIN Dn 2 1 ce gt i tCKHZ tCKLZ C2 DATAout COX X Qn Non 3 READ gt lt Nop wriTE gt lt READ 5617 drw 12 NOTES 1 Output state High Low or High impedance is determined by the previous cycle control signals 2 CEo BEn and ADS ViL CE1 CNTEN and REPEAT Vi NOP is No Operation 3 Addresses do not have to be accessed sequentially since ADS Vit constantly loads the address on the rising edge of the CLK numbers are for reference use only 4 NOP is No Operation Data in memory at the selected address may be corrupted and should be re written to guarantee data integrity Timing Waveform of Pipelined Read to Write to Read OE Controlled 2 tcyc2 gt K tCH2 tCL2 7 W a ANA CLK TE gt KXA LAXA AX isc IHG C
19. l Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History 6 2 00 Initial Public Offering 7 12 00 Added muxto functional block diagram 7 30 01 Page 20 Changed maximum value for JTAG AC Electrical Characteristics for tico from 20ns to 25ns Page 9 Added Industrial Temperature DC Parameters 11 20 01 Page 2 3 amp 4 Added date revision for pin configurations Page 11 Changed toe value in AC Electrical Characteristics please refer to Errata SMEN 01 05 Page 1 amp 22 Replaced Tm logo with logo Page 10 Changed AC Test Conditions Input Rise Fall Times 7 1102 Consolidated multiple devices into one datasheet Page 1 amp 5 Added DCD capability for Pipelined Outputs Page 7 Clarified Taias and added Tun Page 9 Changed DC Electrical Parameters Page 11 Removed Clock Rise amp Fall Time from AC Electrical Characteristics Table Removed Preliminary status 05 19 03 Page 11 Added Byte Enable SetupTime amp Byte Enable Hold Time to AC Elecctrical Characteristics Table Page 22 Added IDT Clock Solution Table CORPORATE HEADQUARTERS for SALES for Tech Support l DT 2975 Stender Way 800 345 7015 or 408 727 5166 831 754 4613 Santa Clara CA 95054 fax 408 492 8674 DualPortHelp idt com www idt com The IDT logo is a registered trademark of Integrated Device Technology Inc
20. lications requiring expanded width asindicatedin Figure 4 Through combining the control signals the devices can be grouped as necessary to accommodate applications needing 72 bits or wider Ai7 At6 1 IDT70V3599 89 Control Inputs IDT70V3599 89 Control Inputs IDT70V3599 89 Control Inputs IDT70V3599 89 Control Inputs Figure 4 Depth and Width Expansion with IDT70V3599 89 NOTE 1 A17 is for IDT70V3599 A16 is for IDT70V3589 5617 drw 20 REPEAT CNTEN IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges JTAG Timing Specifications tJCYC t F O TCK pra tS Device Inputs TDI TMS tJDC Sey J oo Device Outputs gam ERX TDO pel aur tURSR T TRST 5617 drw 21 Figure 5 Standard JTAG Timing NOTES 1 Device inputs All device inputs except TDI TMS and TRST 2 Device outputs All device outputs except TDO JTAG AC Electrical Characteristics 34 70V3599 89 Symbol Parameter Min Max units uoe mmecoo marora o e w mecan 0 e w meow e m moone e u snccoarartne a w mere fe uen amo ReetRecoey o f w memon w m menomare o is mem _ w mew s e 5617 tbl 12 NOTES Guaranteed by design 2 30pF loading on external output signals 3 Refer to AC Electrical Test Conditions st
21. ll Vopa pins must be connected to appropriate power supply 3 3V if OPT pin for that port is set to VIH 3 3V and 2 5V if OPT pin for that port is set to Vit OV All Vss pins must be connected to ground supply Package body is approximately 15mm x 15mm x 1 4mm with 0 8mm ball pitch This package code is used to reference the package diagram This text does not indicate orientation of the actual part marking Soc IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Configuration 2 5 con t 70V3599 89BC BC 256 256 Pin BGA 06 28 02 Top View A A2 A3 A4 A5 A6 A7 A8 Ag Aio JA11 A12 A13 At4 jais fate NC TDI NC NC A Atte AsL BE2L CEiL OEL JCNTENL AsL Az Ao NC NC B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 VOisL NC TDO NC Asl AizL Ao BEsL CEoL RAWL REPEATL AsL AiL Voo I O17L NC C1 C4 c5 C8 cio fon c12 fcis fcis c15 cie 1 O18R M ne Ate A13L ae eo BEL SEa CLKL ADSL AeL AsL OPTL I O17R 1 O16L D8 Dio pi D12 D13 D14 D15 D16 o io ae PIPET Rai Vppar ae Vppa_ VDDaR Vopar Voo 1 O15R 1 0151 O16R E1 E2 E3 E9 E10 E11 E12 E13 E14 E15 E16 V O21R 1 0211 1 O22L a Vie e p ras Vss Vss VoD VoD VppDaR 1 013L 1 0141 O14R F5 F6 F7 F10 F11 F12 F13 F14 F15 F16 Toul fer cel Vppa_ Voo Vss Vss ae i Vss Vss Voo Vppar I O12R 1 O13R 1 012L G1 G2 G3
22. ntrolled teye e tCH1 gt tCLi gt CLK A Nee Ne a O CEo LdSC HG CE A 7y SB_ tHB BEn N a Yaa xx ADDRESS ADOK an XOX An 4 An 2 An 3 ing OK A x LISA JHA isp HD DATAIN Dn K Dn 3 D tcb1 jog tepr tcD1 DATAouT Qn I Kan 4 READ WRITE gis READ 5617 drw 15 NOTES 1 Output state High Low or High impedance is determined by the previous cycle control signals 2 CEo BEn and ADS Vil CE1 CNTEN and REPEAT Vin 3 Addresses do not have to be accessed sequentially since ADS Vi constantly loads the address on the rising edge of the CLK numbers are for reference use only 4 NOP is No Operation Data in memory at the selected address may be corrupted and should be re written to guarantee data integrity 16 IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance tevc2 gt je tCH2 tCL2 CLK WH XH NO ao tsA_ tHA ADDRESS LKX S tSAD tHAD ADS tSAD tHAD e a CNTEN XXX tSCN tHCN e a tep2 DATAour Qx 1 xX Qx X 7 Qn Qn 1 Qn 22 Qn 3 toc READ gt lt gt COUNTER gt READ EXTERNAL READ WITHICOUNTER HOLD WIT
23. o advance The An 1 Address is written to during this cycle on S IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Functional Description The IDT70V3599 89 provides a true synchronous Dual Port Static RAM interface Registered inputs provide minimal set up and holdtimes onaddress data and all critical control inputs All internal registers are clocked on the rising edge of the clock signal however the self timed internal write pulse is independentofthe LOW to HIGH transition ofthe clock signal An asynchronous output enable is provided to ease asyn chronous businterfacing Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications AHIGH on CEoor a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption Multiple chip enables allow easier banking of multiple IDT70V3599 89s for depth expansion configurations Two cycles are required with CEo LOW and CE1HIGH to re activate the outputs Industrial and Commercial Temperature Ranges Depth and Width Expansion The IDT70V3599 89 features dual chip enables refer to Truth Table I in order to facilitate rapid and simple depth expansion with no requirements for external logic Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth The IDT70V3599 89 can also be used in app
24. om Port B read is not valid until following Port B clock cycle ie time from write to valid read on opposite port will be tco 2 tcyc2 tcD2 If tco gt minimum then data from Port B read is available on first Port B clock cycle ie time from write to valid read on opposite port will be tco tcyc2 tcp2 4 All timing is the same for Left and Right ports Port A may be either Left or Right port Port B is the opposite of Port A Timing Waveform with Port to Port Flow Through Read 1 2 4 CLK a tsw_ tHw lt _ _ gt lt gt PRW a tsa tHA ADDRESS w COOK maton XO OOOO ih OOQO OOO OOK tsD jtHD DATAN a VALID tco CLK B 7 NL o tcD1 T en R W B tsw thW SA l ADDRESS s MATCH MATCH le tcp1 DATAOUT B VALID VALID tbc a tDC NOTES 5617 drw 11 1 CEo BEn and ADS Vit CE1 CNTEN and REPEAT Vin 2 OE Vit for the Right Port which is being read from OE Vin for the Left Port which is being written to 3 If tco lt minimum specified then data from Port B read is not valid until following Port B clock cycle i e time from write to valid read on opposite port will be tco tcyc tcp If tco gt minimum then data from Port B read is available on first Port B clock cycle i e time from write to valid read on opposite port will be tco tcp1 4 All tim
25. ower supply 3 All Vopa pins must be connected to appropriate power supply 3 3V if OPT pin for that port is set to ViH 3 3V and 2 5V if OPT pin for that port is set to Vit OV All Vss pins must be connected to ground supply Package body is approximately 17mm x 17mm x 1 4mm with 1 0mm ball pitch This package code is used to reference the package diagram This text does not indicate orientation of the actual part marking So aS IDT70V3599 89S h Speed 3 3V 128 64K x 36 hronous Static RAM and Commercial Temperature Ranges Pin Configuration 23 con t FEM 06 28 02 S Q Q a HUE sssss VO 1 NNNNA V O1eL 1 019 L 2 1 016R 1O21 LY 3 1 015L 1 020 L_ 4 1 015R Vova C 5 Vss vss C 6 VDDAL voz LY 7 1 014L VOzin C 8 1 014R 1 022L 1 013L 1 0227 C 1 013R Vopar L Vss vss C VDDOR 1 0231 L 1 012L 1 O23R C 1 012R voz C Onl 1 024R VO1R Vopa L Vss Vss CJ VpbaL VO25L VO10L VOzr C 1 010R VOze L 1 O9L VOzer C 1 O9R Vopar L Vss Vss C 70V3599 89DR Vppar voo CY VDD VoD DR 208 6 VoD vss 4 Vss vss C Vss VppaL Vss vss J 208 Pin PQFP Vppat VOz7R CL a V Osr voz C Top View VOsL VOzsr C VO7R VOzs C VO7L Vopar L Vss Vss VDDOR 1 029 C 1 O6R 1 029 L 1 O6L 1 030R VOsR 1 030 C 1 O5L Vopa L Vss Vss CJ VDDAL VOsir C Oar vosi CJ VO4aL VOser L 1 O3R 1 032L VO3L Vopar L Vss vss CJ VppaR 1 O33r CL 1 02R Osa L Oa 1 034 LY 1 01R vosa L PETEN VOIL MOTNOnNRDDOrAMY OWwOnDRDOrnn MOOR DDOrTAMNMTNONRDDM
26. r both left and right ports when FT PIPEx Vin Flow through parameters tcyc1 tcp1 apply when FT PIPE Vi for that port 2 All input signals are synchronous with respect to the clock except for the asynchronous Output Enable OE and FT PIPE FT PIPE should be treated as a DC signal i e steady state during operation 3 These values are valid for either level of Vopa 3 3V 2 5V See page 5 for details on selecting the desired operating voltage levels for each port vjje alNI OTS OTS Sle Pel Se ere Pele le Te se ye E ad awe Ei o aol loaftofyjn yo lans aos ataosyjjnfjolsyoa lo lalslo y oo oo uo Aaja A NIAJN g fo 11 IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Pipelined Operation FT PIPE x Vin he tcyc2 gt le tCH2 tcL2 val CLK TE KXXXOA OOOO tsc tsc 8 WSZ CH ZN tsB tsB BE DOS 3 N tsw thw SA A ADDRESS An An 1 An 2 An 3 1 Latency DATAout tekLz O he 1 OE 5617 drw 06 Timing Waveform of Read Cycle for Flow through Output FT PIPE x V L 2 e tcyc1 gt a CHi tcL1 gt CLK 7 f Eo AXXXL tsc _ tHC tsc He 3 CE1 OOOO tsB _ tHB BEn l tSB tHB RW ZISA tswa n
27. rt s I Os and address controls will operate at 2 5V levels and Vopax must be TDO Test Data Output supplied at 2 5V The OPT pins are independent of one another both ports can R operate at 3 3V levels both can operate at 2 5V levels or either can operate TK TBst Logi Glock OM at 3 3V with the other at 2 5V TMS Test Mode Select 4 When REPEATXx is asserted the counter will reset to the last valid address loaded via ADSx TRST Reset Initialize TAP Controller 5 Chip Enables and Byte Enables are double buffered when PL FT Vin i e the 5617 bl 01 signals take two cycles to deselect IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Truth Table I Read Write and Enable Control 1 2 3 4 fo mm fof e e e CLK CEo CE1 BE BEo 1027 35 1 018 26 1 0917 1100 8 EJ x E B E 2 uone on fow Chore z om noz owes roy on rz ronz wom 20H a m on Swee erzo Con f on fow HighZ High Z Dn rane High Z High Z i To ECE orz mz NOTES 5617 tbl02 1 H Vik L Vit X Don t Care 2 ADS CNTEN REPEAT Vin 3 OE is an asynchronous input signal 4 It is possible to read or write any combination of bytes during a given access A few representative samples have been illustrated here Truth Table II Address Counter Control Previous Internal External Internal Address Address Addres
28. s Used CNTEN REPEAT 110 x 0 Dvo p External Address Blocked Counter disabled Ap reused H NOTES 5617 tbl 03 1 H Vin L Vit X Don t Care 2 Read and write operations are controlled by the appropriate setting of R W CEo CE1 BEn and OE 3 Outputs configured in flow through output mode if outputs are in pipelined mode the date out will be delayed by one cycle 4 ADS and REPEAT are independent of all other memory control signals including CEo CE1 and BEn 5 6 The address counter advances if CNTEN Vit on the rising edge of CLK regardless of all other memory control signals including CEo CE1 BEn When REPEAT is asserted the counter will reset to the last valid address loaded via ADS This value is not set at power up a known location should be loaded via ADS during initialization if desired Any subsequent ADS access during operations will update the REPEAT address location IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage Ambient Temperature Industrial 40 C to 85 C NOTES 1 This is the parameter TA This is the instant on case temperature 5617 tbl 04 Absolute Maximum Ratings Commercial Symbol amp Industrial Terminal Voltage 0 5 to 4 6 with Respect to GND Vterm Teas Storage Temperature 65 to 150
29. serially into the boundary scan cells via the TDI RESERVED All other codes Several combinations are reserved Do not use codes other than those identified above 5617 tbl 15 NOTES 1 Device outputs All device outputs except TDO 2 Device inputs All device inputs except TDI TMS and TRST 3 The Boundary Scan Descriptive Language BSDL file for this device is available on the IDT website www idt com or by contacting your local IDT sales representative IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dual Port Synchronous Static RAM Ordering Information IDT _XXXXX A 999 A A Device Power Speed Package Process Type Temperature Range Industrial and Commercial Temperature Ranges Blank Commercial 0 C to 70 C Industrial 40 C to 85 C BF 208 ai gt BGA BF 208 DR 208 pin POFP R 208 BC 256 Bin BGA BC 256 166 Commercial Only j 133 Commercial amp industrial Speed in Megahertz S Standard Power 70V3599 4Mbit 128K x 36 Bit Synchronous Dual Port RAM 70V3589 2Mbit 64K x 36 Bit Synchronous Dual Port RAM 5617 drw 22 IDT Clock Solution for IDT70V3599 89 Dual Port Dual Port I O Specitications Port I O Dual Port I O Specitications IDT Dual Port Part Number Input Clock Specifications IDT PLL Clock Device Input Duty Maximum Frequency Tolerance Cycle Requirement 5617 tbl16a IDT70V3599 89S High Speed 3 3V 128 64K x 36 Dua
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