HOLT HI-8783 HI-8784 HI-8785 handbook
Contents
1. HOLT INTEGRATED CIRCUITS 4 8783 8784 8785 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Voltages referenced to Ground Supply Voltages Supply voltages Temperature Range Industrial Screening 409 to 85 Hi Temp Screening 55 to 125 Power dissipation at 25 Military Screening 55 C to 125 C plastic DIL 1 0W derate 10mW C ceramic DIL 0 5W 7mW C NOTE Stresses above absolute maximum ratings or outside recommended operating Solder Temperature 275 C for 10 sec conditions may cause permanent damage 1o the device These are stress ratings only Operation at Storage Temperature 65 C to 150 C the limits is not recommended DC ELECTRICAL CHARACTERISTICS HI 8783 HI 8784 and HI 8785 5 0 Vss OV Ta Operating Temperature Range unless otherwise specified PARAMETER conomon Me ss E29 2 1 uo Cmn p owes LE d o wow E Output Votage 10 w erem 9 v opmmgCuemban temm os ma ELECTRICAL CHARACTERISTICS 8784 and 8785 only 5 0V Vss 10V2. INTEGRATED CIRCUITS HI 8783 8784 HI 8785 ARINC INTERFACE DEVICE January 2001 8 bit parallel data converted to 429 amp 561 serial data out DESCRIPTION The 8783 HI 8784 and 8785 are system compo nents for interfacing 8 bit parallel data to an ARINC 429 bus The HI 8783 is alogic device only and requires a sep arate line driver circuit such as the HI 8382 8585 The 8784 and HI 8785 combine logic and line driver on one chip The HI 8784 has an output resistance of 37 5 ohms and the 8785 has an output resistance of 10 ohms to facilitate external lightning protection cicuitry The technology is analog digital CMOS The 8783 is available in a 22 pin DIP format as a second source replacement for the Micrel California Devices DLS 111BV The products offer high speed data bus data transactions to a buffer register After loading 4 bytes data is automati cally transferred and transmitted The data rate is equal to the clock rate Parity can be enabled in the 32nd bit Reset is used to initialize the logic upon startup Word gaps are transmitted automatically 8784 and HI 8785 require 10 volt supplies ad ditionto the5 voltsupply FEATURES Automatically converts 8 bit parallel data to ARINC 429 or 561 data High speed data bus interface e On chip line driver option e SOIC packages available Military processing options PIN CONFIGURATIONS
3. 561 DATA DATA ZERO DATA ONE ani cuin PARITY ENB HI 8783PST XMT READY XMIT CLK 20 Pin Plastic SOIC WB package HI 8784PSI HI 8784PST HI 8785PSI amp HI 8785PST 24 Pin Plastic SOIC WB package See page 7 for additional pin configurations HOLT INTEGRATED CIRCUITS DS8783 Rev B 01 01 8783 8784 8785 PIN DESCRIPTIONS PIN 8783 20 8783 22 8784 8785 SYMBOL FUNCTION VCC power supply DESCRIPTION 5 volt rail 561 SYNC digital output ARINC 561 Sync signal digital inputs Parallel 8 bit Data Input power supply Ground digital input Byte address 0 1 for 1st byte 0 0 for 2nd 3rd amp 4th bytes SLP1 5 digital input Selects the slope of the line driver High 1 5us WRITE digital input Write strobe loads data on rising edge RESET digital input Registers and sequencing logic initialized when low XMIT CLK digital input Clock input for the transmitter XMT RDY digital output Goes high if the buffer register is empty PARITY digital input When high the 32nd bit output is odd parity power supply 10 volt rail DATA ONE digital output Goes high for each ARINC bit output that is DATA ZERO digital output Goes high for each ARINC bit output that is a zero TXAOUT analog
4. 10 Operating Temperature Range unless otherwise specified conomon UNIS Femme Line Driver Output Levels Ref GND ONE no load VCC 5 0V NULL ZERO Line Driver Output Levels Differential ONE no load 5 0V NULL ZERO Minimum Short Circuit Sink or Source Current HOLT INTEGRATED CIRCUITS 5 8783 8784 8785 ELECTRICAL CHARACTERISTICS 8783 8784 and 8785 5 0V Vss Operating Temperature Range unless otherwise specified PARAMETER Te Max DATA BUS TIMING y Hold WAITE to DataBus Hodao WRITE m Pulse width WEITE m Pulse width AQ m Delay last WRITE to XMT PDY tt tts AC ELECTRICAL CHARACTERISTICS HI 8784 and HI 8785 only V 10V V 10V Ta Operating Temperature Range unless otherwise stated for HI 8784 only PARAMETERS SYMBOL TEST CONDITIONS MN UNITS Line Driver propagation delay Output high to low Output low to high Line Driver transition times Output high to low SLP1 5 logic 1 Output low to high SLP1 5 logic 1 Output high to low SLP1 5 logic 0 Output low
5. 01 838 432 22 PIN PLASTIC 1 105 015 28 067 381 350 010 8 89 254 135 4 015 3 429 381 i cae 1375 0125 3 4925 3175 025 5010 635 254 iL 0 100 TYP 4 019 004 483 102 053 013 1 346 330 HOLT INTEGRATED CIRCUITS 8 8783 8784 8785 PACKAGE DIMENSIONS inches millimeters Package Type 20HW 0105 0015 2667 0381 1 SEE DETAIL 2 090 010 2 286 254 UA 254 ors 0035 0035 089 7 2 Package 22 400 gt 010 10 160 254 E gt a 435 4 035 11 049 889 HI 8783 8784 8785 PACKAGE DIMENSIONS INTEGRATED CIRCUITS inches millimeters 24 PIN PLASTIC SMALL OUTLINE SOIC WB Wide Body Package Type 24HW 606 004 15 392 102 gt j 10105 2 0015 2667 0381 4065 0125 2955 0035 10 325 318 7 506 089 NG SEE DETAIL 095 005 2 413 127 0 osi 1005 2055 191 089 E 838 432 AIL HOLT INTEGRATED CIRCUITS 9
6. in the low state Each 8 bit byte is loaded into the input buffer register by a low pulse on the WHITE input See figure 1 After the fourth byte is loaded the XMT RDY output goes low The contents of the input buffer register are transferred to the output register during the fourth bit period of the gap If the fourth gap bit period of the previous word has already been transmitted the contents of the input buffer register will be transferred to the output shift register during the first bit pe riod after the loading of the fourth byte and the XMT RDY output goes high After the output shift register is loaded the data is shifted outto the output logic in the order shown in figure 2 The 561 SYNC output pulses low when the XMT CLK is low during the 8th bit of the ARINC transmission The XMIT CLK is the same as the data rate HOLT INTEGRATED CIRCUITS 2 8783 8784 8785 XMIT CLK status amp control logic O XMT RDY driver o TXBOUT 8 to 32 bit 32 bit mux buffer register 32 bit shift register word gap 1 counter HI 8784 HIB785 1 Figure 1 FUNCTIONAL DESCRIPTION Con 8784 and 8785 have the same digital logic func tion as the HI 8783 but include an on chip line driver de signed to d
7. irectly drive the ARINC 429 bus The two ARINC outputs TXAOUT and TXBOUT provide a differential volt age to produce a 10 volt One a 10 volt Zero and a 0 volt Null The slope of the ARINC outputs is controlled by the SLP1 5 pin If SLP1 5 is high the output rise and fall time is nominally 1 5us If SLP1 5 is set low the rise and fall times are 10us DATA ONE and DATA ZERO outputs are not pro videdfor the 8784 and 8785 The HI 8784 has 37 5 ohms in series with each line driver output The 8785 has 10 0 ohms in series The 8785 is for applications where external series resistance is needed typically for lightning protection devices 1 10 DATA ONE 1 1 DATA ZERO bit 1 HI 8783 O 561 SYNC 2O 561 DATA PARITY O Block Diagram t Data Bus ARINC Bits ARINC 1 ARINC 8 ARINC 9 ARINC 16 ARINC 17 ARINC 24 ARINC 25 ARINC 32 Figure 2 Order of transmitted bytes HOLT INTEGRATED CIRCUITS 3 8783 8784 8785 TIMING DIAGRAMS DATA TRANSMISSION EXAMPLE PATTERN GAP gt 36 XMIT CLK DATA ONE DATA ZERO 561 DATA 561 SYNC LOW DURING CLK 8 TRANSMITTER OPERATION DATA BUS BYTE1VALID X lt BYTE 2 VALID BYTE 4 VALID WRITE XMT RDY LINE DRIVER OUTPUTS XMT CLK DATA ONE d OV DIFFERENTIAL VOLTAGE TXAOUT TXBOUT
8. output Line driver ouptut A side TXBOUT analog output Line driver output B side 561 DATA digital output Serial output for ARINC 561 data FUNCTIONAL DESCRIPTION The 8783 is a parallel to serial converter which when loaded with four eight bit parallel bytes outputs the data as 32 serial word Timing circuitry inserts a 4 bit gap atthe end of each 32 bit word An input buffer register allows load operations to take place while the previously loaded word is being transmitted If the PARITY ENB pin is high the 32nd bit will be a parity bit inserted so as to make the 32 bit word have odd parity If the PARITY ENB pin is low the 32nd bit will be the D7 bit of the 4th byte Outputs are provided for both ARINC 429 575 DATA ONE and DATA ZERO pins and ARINC 561 561 DATA and 561 SYNC pins type data low signal applied to the RESET pin resets the HI 8783 s internal logic so that spurious transmission does not take place during power up The registers are cleared so that a continuous gap will be transmitted until the first word is loaded into the transmitter 10 volt rail Input data can be loaded when the XMT RDY signal is high which indicates the input buffer register is empty The first 8 bit byte is the label byte and is loaded with the AO in put high which initializes the internal byte counter The re maining three bytes are loaded with AO
9. to high SLP1 5 logic 0 HOLT INTEGRATED CIRCUITS 6 8783 8784 8785 ADDITIONAL 8783 PIN CONFIGURATION 561 SYNC e VCC 561 DATA D1 DATA ZERO D2 DATA ONE D3 L5 8783 8 PARITY ENB D4 e XMT READY D5 XMIT CLK D6 8 RESET NC 9 WRITE D7 NC GND 0 22 Pin Plastic DIP package See page 1 for additional pin configurations ORDERING INFORMATION PART NUMBER HI 8783PDI OUTPUT RESISTOR PACKAGE DESCRIPTION 22 Pin Plastic DIP INCLUDES LINE DRIVER HI 8783PDT 22 Pin Plastic DIP TEMPERATURE RANGE 40 85 55 125 PROCESS FLOW LEAD FINISH SOLDER SOLDER HI 8783PSI NO 20 Pin Plastic SOIC WB 40 C TO 85 C SOLDER HI 8783PST NO 20 Pin Plastic SOIC WB HI 8784PSI 37 5 ohm 24 Pin Plastic SOIC WB HI 8784PST 37 5 ohm 24 Pin Plastic SOIC WB HI 8785PSI 10 0 ohm 24 Pin Plastic SOIC WB HI 8785PST 10 0 ohm 24 Pin Plastic SOIC WB Legend WB Wide HOLT INTEGRATED CIRCUITS 7 55 TO 125 40 85 55 125 40 85 55 125 SOLDER SOLDER SOLDER SOLDER SOLDER HOLT INTEGRATED CIRCUITS 20 PIN PLASTIC SMALL OUTLINE SOIC WB Wide Body 5035 4 0075 12 789 191 4065 4 0125 10 325 318 296 003 7 518 076 018 455 TY 0 to 8 bons
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