MICREL SY10E151 SY100E151 FINAL handbook
Contents
1. Device Skew Rise Fall Time 20 to 80 NOTE 1 Within device skew is defined as identical transitions on similar paths through a device 2 Specification for packaged product only PRODUCT ORDERING CODE Ordering Package Operating Code Type Range SY10E151JITR J28 1 SY100E151JITR J28 1 Tape and Reel SY10E151 Micrel SY100E151 28 LEAD PLCC J28 1 TOP VIEW SIDE VIEW 4 2048 1 22 aw ies 0 042 1 07 ERES 0 048 1 22 BOTTOM VIEW 0 042 1 07 PER GC ams n mumn 4 E L Mal LST VA D DS UUU i 5 M l O H 1 ee c o g Ne ale P t3 4 g B cong feu J E rI L ul E ia o g p 457 0 452 888 O O Se 1 487898 O m T o g urs E Eq Ko CJ 4 C ILTLILELELILTI I COI TEE Ey zi Li oi Lia 0 452 7203 AA 0 172 088 11 487885 4 37 8 8 0 4907800 e 0 004 0 10 12 452813 z ae 1 DIMENSIONS ARE IN INCHES MM 2 CONTROLLING DIMENSION INCHES 0 0125 0 32 A DIMENSION DOES NOT INCLUDE MOLD FLASH 0 0075 0 19 OR PROTRUSIONS EITHER OF WHICH SHALL NOT i EXCEED 0 008 0 203 n l AN LEAD DIMENSION DOES NOT INCLUDE DAMBAR 0 020L0 51 i PROTRUSION MIN 0 101 8989 5 MAXIMUM AND MINIMUM SPECIFICATIONS AR IHI J 2 561223 INDICATED AS FOLLOWS MAX MIN YA i JA PACKAGE TOP DIMENSION MAY BE SLIGHTLY SMAL2. 3L 1Q2 Do 4 12 Q2 5 6 7 8 9101 J YUTTU z 90000 9 gt gt m Fun OS CLK1 CLK2 Clock Inputs M Master Reset True Outputs Inverting Outputs Vcc to Output Rev E Issue Date November 2002 Amendment 0 SY10E151 Micrel SY100E151 TRUTH TABLES Asynchronous Operation Synchronous Operation hipus Output D cik CL Mh aten a a a mmm o on ae ce w es NOTE 1 H HIGH Voltage Level L LOW Voltage Level X Don t Care t Time before positive CLK transition t 1 Time after positive CLK transition u LOW to HIGH transition DC ELECTRICAL CHARACTERISTICS VEE VEE Min to VEE Max Vcc Vcco GND Ta 25 C Ta 85 C Parameter Min Typ Max Min Typ Max Min Typ Max Condition Input HIGH Current 150 150 65 78 65 78 p ABE 75 NOTE 1 Specification for packaged product only SY10E151 Micrel SY100E151 AC ELECTRICAL CHARACTERISTICS VEE VEE Min to VEE Max Vcc Vcco GND TA 25 C symbol Parameter Tvp Max min Typ Mex min Typ max Max Toggle Frequency 1100 1400 1100 1400 1100 summo o sp 0 175 7 i Fle Ke E CLK MR E 300 Propagation Delay to Output 475 650 800 475 650 800 475 650 MR 475 650 850 475 650 850 475 650 Hume o s 175 Within
3. LER THAN BOTTOM DIMENSION sa MUT sos 0 050 1 27 0 467513 BSC 0 032 0 81 0 026 0 66 xim Rev 03 DETAIL A MICREL INC 1849 FORTUNE DRIVE SAN JOSE CA 95131 USA TEL 1 408 944 0800 rax 1 408 944 0970 wes http www micrel com This information is believed to be accurate and reliable however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use No license is granted by implication or otherwise under any patent or patent right of Micrel Inc 2002 Micrel Incorporated 4 WWW ALLDATASHEET COM Copyright O Each Manufacturing Company All Datasheets cannot be modified without permission T his datasheet has been download from www AllDataSheet com 10096 Free DataSheet Search Site Free Download No Register Fast Search Sy stem www AllDataSheet com
4. MICHEL The Infinite Bandwidth Company FEATURES E 1100MHz toggle frequency E Extended 100E VEE range of 4 2V to 5 46V B Differential outputs E Asynchronous Master Reset E Dual clocks B Fully compatible with industry standard 10KH 100K ECL levels E Internal 75KQ input pulldown resistors B Fully compatible with Motorola MC10E 100E151 B Available in 28 pin PLCC package BLOCK DIAGRAM Do Di D2 D4 T J a w D3 Q3 d eel 6 BIT D REGISTER SY10E151 SY100E151 FINAL DESCRIPTION The SY10 100E151 offer 6 edge triggered high speed master slave D type flip flops with differential outputs designed for use in new high performance ECL systems The two external clock signals CLK1 CLK2 are gated through a logical OR operation before use as clocking control for the flip flops Data is clocked into the flip flops on the rising edge of either CLK1 or CLK2 or both When both CLK1 and CLk2 are at a logic LOW data enters the master and is transferred to the slave when either CLK1 or CLK2 or both go HIGH The MR Master Reset signal operates asynchronously to make all Q outputs go to a logic LOW PIN CONFIGURATION Nos O lt lt Oo ao Soo 866 25 24 23 22 21 20 19 N D5 26 18 Q4 D4 27 17 Q4 2 16 Da L 28 PLCC Vcc VEC IO TOP VIEW 15 Qs D2 2 J28 1 147 1Q3 D1 3 1
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MICREL SY10E151 SY100E151 FINAL handbook