MAXIM MX7543 Data Sheet
Contents
1. 0 00 000 c eee eee 450mW derate 6mW C above 70 C Operating Temperature Range Commercial MX7543J K GK 0 C to 70 C Industrial MX7543A B GB 25 C to 85 C Military MX7543S T GT 55 C to 125 C Storage Temperature 65 C to 150 C Lead Temperature Soldering 10 sec 300 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum ratings conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS Ts Tun to Tumax Vop t5V Veer 10V Vouri Vout GND unless otherwise specified PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 12 Bits MX7543J A S 1 Non Linearity MX7543K B T 0 5 LSB MX7543GK GB GT 0 5 MX7543J A S Note 1 2 Differential Non Linearity MX7543K B T Note 2 1 LSB MX7543GK GB GT Note 2 1 MX7543J K A B S T Ty 25 C 12 3 MX7543J K A B Tun tO Trax 413 5 MX7543S T Tyn to T 14 5 Gain Error JMN MAX LSB MX7543GK GB GT T 25 C 10 MX7543GK GB Twin tO Tmax L1 MX7543GT Tun tO Tmax 2 Gain Temperature Coefficient 2 5 mec AGa2. C Plastic DIP 1 LSB MX7543JCWE 0 C to 70 C Small Outline 1 LSB MX7543KCWE 0 C to 70 C Small Outline t LSB MX7543GKCWE 0 C to 70 C Small Outline LSB MX7543u D 0 C to 70 C Dice 1 LSB MX7543AD 25 C to 85 C Ceramic t1 LSB MX7543BD 25 C to 85 C Ceramic LSB MX7543GBD 25 C to 85 C Ceramic LSB MX7543AQ 25 C to 85 C CERDIP 1 LSB MX7543BQ 25 C to 85 C CERDIP 5 LSB MX7543GBQ 25 C to 85 C CERDIP 1 s LSB MX7543SD 55 C to 125 C Ceramic 1 LSB MX7543TD 55 C to 125 C Ceramic H LSB MX7543GTD 55 C to 125 C Ceramic t s LSB MX7543SQ 55 C to 125 C CERDIP 1LSB MX7543TQ 55 C to 125 C CERDIP LSB MX7543GTQ 55 C to 125 C CERDIP gt LSB All devices 16 pin packages Maxim reserves the right to ship Ceramic packages in heu of CERDIP packages Pin Configuration Top View OUTI QUT AGND STB tor NC SRI STB2 Maxim Integrated Products 1 Call toll free 1 800 998 8800 for free samples or literature ErslXN MX7543 CMOS Serial Input 12 Bit DAC ABSOLUTE MAXIMUM RATINGS Von tO AGND 0 cece eee 0 3V 7V Vpo tO DAND oo cence 0 3V 7V AGND to DGND cence Voo DGND to AGND 1 eens DD Digital Input Voltage to DGND 0 3V Vbp 0 3V Pins 4 11 13 Vane Vping tO AGND woe eee 0 3V Vop 0 3V Vaer t0 AGND oo ect nen ene 25V Vprg tO AGND 20 2 cece een ees 25V Power Dissipation
3. negative output is obtained If gain and offset trims are not required R1 and R2 in Figure 5 can be omitted EvrSLXN MX7543 CMOS Serial Input 12 Bit DAC Interface Logic Serial data is first loaded into the 12 bit Shift Register A shown in the MX7543 functional diagram Each bit of serial data appearing at pin SRI is clocked into Register A MSB first by any one of the four strobe inputs STB1 STB2 and STB4 all clock data into Shift Register A on the rising edge of the strobe pulse STB3 clocks data into Register A on its falling edge Table 3 illustrates the logic states for the control inputs Figure 6 shows the timing diagram for the Data is then transferred from Shift Register_A into Register B by momentarily moving both LD1 and LD2 low Bringing CLR input low asynchronously resets Regis ter B to 0000 0000 0000 This initializes the DAC output voltage to a known condition With the unipolar circuit of Figure 4 a CLR results in a DAC output voltage of 0 volts Using the bipolar circuit of Figure 5 momentarily bringing CLR low sets the DAC output voltage to its lowest value of Vper loading sequence m 1 t Ha tsRi tm U l BIT 1 tos1 tos tosa gt toHt toH2 toHa STROBE INPUT hy TOR 1 STB1 STB2 STB4 gt NOTE tera l tsTB2 l tetas Wp lt __ LOADING REGISTER A tasB tto2 LD1 AND LD2 O Z r LOADING REGISTER B WITH CONTENTS OF REGISTER A NOTE ST
4. 1 MSB BIT2 BIT3 BIT N LSB L Figure 1 MX7543 Functional Diagram Circuit Configurations Unipolar Operation The most common configuration for the MX7543 is shown in Figure 4 The circuit is used for unipolar binary operation and or 2 quadrant multiplication The code table is given in Table 1 Note that the polarity of the output is the inverse of the reference input in many applications gain adjustment of the MX7543 will not be necessary In those cases and also when gain is trimmed but only at the reference source resistors R1 and R2 in Figure 4 can be omitted However if the trims are desired and the DAC is to operate over a wide temperature range then low tempco lt 300ppm C resistors should be used at R1 and R2 RFB OUT1 75pF VREF mv t OUT2 IREF IREF ILEAKAGE 260pF 4096 RFB R 15K R VREF OUTI T 260pF IREF A I IREF 4096 LEAKAGE iS ILEAKAGE we OUT2 TSpF HH 4 Figure 2 MX7543 DAC Equivalent Circuit Ali Digital Inputs LOW Figure 3 MX7543 DAC Equivalent Circuit All Digital Inputs HIGH MAXLM CMOS Serial Input 12 Bit DAC VIN To VREF MAXIM 10pF 33pF MAXIZVI Vout Table 1 Code Table Unipolar Binary MX7543 0uT2 DGND_ AGND 2 MAX400 TRIM J K A GK GB RESISTOR B S T GT R1 1209 100 R2 600 52 Figure 4 Unipolar Binary Operatio
5. 2 78 M X 7543 tH AY FS 19 0240 Rev 2 7 95 MAA ALSVI CMOS Serial Input 12 Bit DAC __ _ _ General Description The MX7543 is a high precision 12 bit digital to analog converter DAC which uses a serial rather than parallel input scheme for loading data Included are a serial to parallel shift register a separate DAC register and a multiplying DAC Serial data is clocked in at the SRI pin on the rising or falling edge user selected of the strobe input When the input register is full the contents are transferred to the DAC register using the load input A clear input is provided to initialize the part asynchronously The MxX7543 features excellent gain stability Sppm C max and operates from a single 5V power supply while dissipating about 10mW MESSE Applications Remote Analog Systems Robotics Programmable Attenuators Automatic Test Equipment Auto Calibration Systems _ _ sFunctional Diagram REGISTER A 12 BIT SHIFT REGISTER MAXIM Features Serial Interface and 1 LSB Linearity CLEAR input For Initialization Single 5V Supply Operation Sppm C Gain Stability 1 LSB Max Feedthrough At 10kHz Small Size 16 Lead DIP Ordering Information PART TEMP RANGE PACKAGE ERROR MX7543UN 0 C to 70 C Plastic DIP 1 LSB MX7543KN 0 C to 70 C Plastic DIP LSB MX7543GKN O C to 70
6. Cin 8 pF SWITCHING CHARACTERISTICS see Figure 6 Note 5 t Ta 26 C 50 0S1 Tun tO Trax 100 t T 25 C 20 Serial Input ps2 Tmn tO Tmax 40 ns to Strobe Setup Time t T 25 C 0 ps3 Twin t0 Tmax 0 t Ta 25 C oj ps4 Twin tO Tmax 0 t Ty 25 C 30 DHI Tun tO Trax 60 t Ta 25 C 60 Serial Input DH Twin tO Tmax 120 ns to Strobe Hold Time T 25 C 80 tos Thn tO Tmax 160 t Ta 25 C 80 L DHA Twin tO Tmax 160 Ta 25 C 80 SRI data pulse width top Thn to Tax 160 T Ta 25 C 80 STB1 pulse width totpy Tun tO Tmax 160 Ta 25 C 80 STB2 pulse width tstB2 Tan t0 Tmax 160 TF Ta 25 C 100 STB3 pulse width t A P 89 Tun t0 Tax 200 Ta 26 C 100 STB4 pulse width tstB4 Thn t0 Tmax 200 ns t T 25 C 150 Load 1 pulse width tepi Tun tO Tmax 300 Ta 26 C 150 Load 2 pulse width tioe Twain tO Tmax 300 Time between strobing ORO LSB into Register A and tasg T 5 e o loading Register B MIN MAX Ta 25 C 200 Clear pulse width terr Ton tO Tapax 400 POWER SUPPLY Supply Voltage Voo 5V 5 4 75 5 25 V Supply Current T lop 25 mA MAXI AVI 3 EpSZXWN MX7543 CMOS Serial Input 12 Bit DAC Detailed Description The basic MX7543 DAC circuit consists of a laser trimmed thin film R 2R resistor array with NMOS current switches as shown in Figure 1 Binarily weighted currents are switched to either OUT1 or OUT2 depending on the status of each input bit Although the current at OUT1 or OUT2 will depen
7. ROBE WAVEFORM IS INVERTED IF STB3 IS USED TO STROBE SERIAL DATA BITS INTO REGISTER A Figure 6 Timing Diagram Table 3 MX7543 Truth Table MX7543 Logic inputs Register A Register B Control Inputs Control Inputs MX7543 Operation Notes STB4 STB3 STB2 STB1 CLR LD2 LDI Q 1 0 X x x Data Appearing At SRI Strobed Into Register A 2 3 l 0 1 0 X X X Data Appearing At SRI Strobed Into Register A 2 3 0 L Q 0 X xX X Data Appearing At SRI Strobed Into Register A 2 3 f 1 0 0 X X X Data Appearing At SRI Strobed Into Register A 2 3 1 x X X X 0 X x No Operation Register A 3 x X 1 x X x X 1 0 x X Clear Register B To Code 0000 0000 0000 13 Asynchronous Operation gt 1 1 x No Operation Register B 3 1 X 1 1 0 0 Load Register B With The Contents Of Register A 3 Notes 1 CLR Q Asynchronously resets Register B to 0000 0000 0000 but has no effect on Register A 2 Serial data is loaded into Register A MSB first on edges shown F is positive edge ES is negative edge 3 0 Logic LOW 1 Logic HIGH X Don t Care s MAXIM CMOS Serial Input 12 Bit DAC _ Ss Application Information Output Amplifier Offset For best linearity OUT1 and OUT2 should be termi nated exactly at OV In most applications OUT1 is connected to the summing junction of an inverting op amp The amplifier s input offset voltage can de grade the linearity of the DAC by causing OUT1 to be te
8. d on the digital input code the sum of the two output currents is always equal to the input current at Vper minus the termination resistor current Rr Either current output can be converted into a voltage externally by adding an output amplifier Figure 4 The Vper input accepts a wide range of signals in cluding fixed and time varying voltage or current inputs If a current source is used for the reference input then a low temperature coefficient external resistor should be used for Reg to minimize gain variation with temperature Equivalent Circuit Analysis Figures 2 and 3 show the equivalent circuits for the R 2R ladder when all digital inputs are LOW and HIGH respectively The input resistance at Var is nominally 15kQ and does not change with digital input code The Ipe 4096 current source which is actually the ladder termination resistor Ry Figure 1 results in an intentional 1 bit current loss to GND The leakage Current sources represent junction and surface leakage currents Capacitors Cour and Courto represent the switches ON and OFF capacitances respectively When all inputs are switched from LOW to HIGH the capaci tance at OUT1 changes from approximately 75pF to 260pF This capacitance is code dependent and is a function of the number of ON switches that are con nected to a specific output 15K 15K 15K VREF Ar 30K 30K 30K 3 SN i if vy OuUT2 l OUTI Pkg y La di Are T BIT
9. in ATemperature Note 4 ppm _ Ta 25 C 0 005 Power Supply Rejection PSRR Vpop 4 75V to 5 25V Tuin tO Trrax 0 01 V pp Ta 25 C 1 Output Leakage Current MX7543J K GK Twin tO Trax 10 nA louti lourz Note 3 MX7543A B GB Tun tO Tmax 10 MX7543S T GT Tun to Trax 200 DYNAMIC PERFORMANCE Note 4 Output Current Settling Time To 1 2 LSB Outi Load 100Q 2 us Feedthrough Error Veer 10V 10kHz sine wave 2 5 mVpp REFERENCE INPUT Input Resistance pin 15 RREF 8 15 25 kQ ANALOG OUTPUT Note 4 Cours DAC Register 0000 0000 0000 75 DAC Register 1111 1111 1111 260 OUT Output Capacitance jure DAC Register 1111 1111 1111 75 pF out2 DAC Register 0000 0000 0000 260 Note 1 Monotonic to 11 bits from Tain to Tmax Note 2 Monotonic to 12 bits from Tmin tO Tmax Note 3 laj tested with DAC register loaded to all O s louz tested with DAC register loaded to all 1 s Note 4 Guaranteed by design but not tested Note 5 Sample tested at 25 C to ensure compliance 2 MAXIM CMOS Serial Input 12 Bit DAC ELECTRICAL CHARACTERISTICS Continued Ta Twin tO Tmax Ypo 5V Veee 10V Vouti Vout GND unless otherwise specified PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS Logic HIGH Voltage INH 3 0 v Logic LOW Voltage INL 0 8 Logic Input Current lin Vin OV or Vpop 1 LA Input Capacitance Note 4
10. must quickly settie to a new programmed value the AC parameters of the output op amp must be considered Another error source in dynamic applications is para sitic coupling of signal from the Vper terminal to OUT1 or OUT2 This is normally a function of board layout and package lead to lead capacitance Signals can also be injected into the DAC outputs when the digital inputs are switched This digital feedthrough is usually dependent on circuit board layout and on chip capacitive coupling Layout induced feedthrough can be minimized with guard traces between digital inputs Vag and the DAC outputs Compensation A compensation capacitor C1 may be needed when the DAC is used with a high speed output amplifier The purpose of the capacitor is to cancel the pole formed by the DAC s output capacitance and internal feedback resistance Its value depends on the type of Op amp used but typical values range from 10 to 33pF Too small a value causes output ringing while excess capacitance overdamps the output The size of C1 can be minimized and output settling perform ance improved by keeping the PC board trace and stray capacitance at OUT1 as small as possible Grounding and Bypassing Since OUT1 OUT2 and the output amp s noninverting inputs are sensitive to offset voltages nodes that are to be grounded should be connected directly to single point ground through a separate very low resistance less than 0 29 path The cur
11. n DIGITAL INPUT MSB LSB ANALOG OUTPUT 1111 1111 1111 vee ope 1000 0000 0000 wer aos aer 0000 0000 0001 Maer sa 0000 0000 0000 ov Table 2 Code Table Bipolar Offset Binary Operation DIGITAL INPUT MSB LSB ANALOG OUTPUT T 2047 20k0 1413 1131 1444 Veer oo Fan Yrer 9048 v 1 T 14000 00000001 Veer aaka AN 5kQ 10 1000 0000 0000 ov TRIM J K A GK GB RESISTOR B S T GT R1 1209 109 0111 1111 1111 vaer zal R2 600 59 2048 48 P 0000 0000 0000 Veer aoao Figure 5 Bipolar Operation 4 Quadrant Multiplication 2048 Bipolar Operation With the circuit configuration in Figure 5 the MX7543 operates in the bipolar or 4 quadrant multiplying mode A second amplifier and three matched resistors are required Matching to 0 01 is recommended for 12 bit performance The code table for the output which is offset binary is listed in Table 2 In multi plying applications the MSB determines output po larity while the other 11 bits control amplitude MAK To adjust the circuit load the DAC with a code of 1000 0000 0000 and trim R1 for a OV output With R1 and R2 omitted an alternative zero trim is to adjust the ratio of R3 and R4 for OV out Full scale can be trimmed by loading the DAC with all zeros or all ones and adjusting the amplitude of Vper or varying RS until the desired positive or
12. rent at OUT1 and OUT2 varies with input code creating a code dependent error if these terminals are connected to ground or a virtual ground through a resistive path A iuF bypass capacitor in parallel with a 0 01yF ceramic capacitor should be connected as close to the DAC s Vpp and GND pins as possible The MxX7543 has high impedance digital inputs To minimize noise pick up they should be tied to either Voo or GND when not us d It is also good practice to connect active inputs to Vpop or GND through high valued resistors 1MQ to prevent static charge accumulation if these pins are left floating such as when a circuit card is left unconnected Chip Topography 4 8 12 1 Voo CLR DGND STB4 A VREF 10 155 STB3 Rre A 0 100 F 9 2 54mm z LD2 OUT om L N 1 TIT hae 8 OUT2 Ace a TE STB2 2 ioy 7 TE 7 AGND LA EE TOL SRI 4 5 STB1 LD1 a 0409 gt l 277mm MAXIM EPGZLXW
13. rminated to a non zero voltage The resulting error iS Error Voltage Vos 1 Reg Ro where Vos is the op amp s offset voltage and Ro is the output resistance of the DAC Ro is a function of the digital input code and varies from approximately 15kQ to 45kQ The error voltage range is then typically 4 3V og to 2Vos a change of 2 3Vog An amplifier with 3mV of offset will therefore degrade the linearity by 2mV almost a full LSB with a 10V reference voltage For best linearity a low offset amplifier such as the MAX400 should be used or the amplifier offset must be trimmed to zero A good rule of thumb is that Vog should be no more than 1 10 of an LSB s value The output amplifier input bias current lg can also limit performance since Ig x Reg generates an offset error lg should therefore be much less than the DAC output current for 1 LSB typically 250nA with Vper 10V One tenth of this value 25nA is recommended Offset and linearity can also be impaired if the output amplifiers noninverting input is grounded through a bias current compensation resistor This resistor adds to offset at this pin and should not be used Best performance is obtained when the noninverting input is directly connected to ground Dynamic Considerations In static or DC applications the AC characteristics of the output amplifier are not critical In higher speed applications where either the reference input is an AC signal or the DAC output
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MAXIM MX7543 Data Sheet mx7333-1