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MOTOTOLA MC68HC908AP64/MC68HC908AP32/MC68HC908AP16/MC68HC908AP8 handbook

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1. Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read COCO ADC Status and Control ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCHO 0057 Register Write ADSCR Reset 0 0 0 1 1 1 1 1 Read 0 0 ADC Clock Control apiv2 ADIVi ADIVO ADICLK MODE MODEO 0058 Register Write R ADICLK Reset 0 0 0 0 0 1 0 0 Read ADx ADx ADx ADx ADx ADx ADx ADC Data Register HighO 0059 ADRHO Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 Read ADx ADx ADx ADx ADx ADx ADx ADC Data Register Low 0 005A ADRLO Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 Read AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data RegisterLow1 005B ADRL1 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 Read AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data RegisterLow2 005C ADRL3 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 Read AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data RegisterLow3 005D ADRL3 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 ADC Auto scan Control Read 0 9 AUTO1 AUTOO ASCAN 005E Register Write ADASCR Reset o 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 17 1 ADC Register Summary Data Sheet MC68HC908AP Family Rev 2 5 346 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC Fun
2. Data Sheet MC68HC908AP Family Rev 2 5 306 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Resetting the SPI The following sources in the SPI status and control register can generate CPU interrupt requests SPI receiver full bit SPRF The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register If the SPI receiver interrupt enable bit SPRIE is also set SPRF generates an SPI receiver error CPU interrupt request e SPltransmitter empty SPTE The SPTE bit becomes set every time a byte transfers from the transmit data register to the shift register If the SPI transmit interrupt enable bit SPTIE is also set SPTE generates an SPTE CPU interrupt request 15 9 Resetting the SPI Any system reset completely resets the SPI Partial resets occur whenever the SPI enable bit SPE is low Whenever SPE is low the following occurs The SPTE flag is set e Any transmission currently in progress is aborted The shift register is cleared The SPI state counter is cleared making it ready for a new complete transmission e All the SPI port logic is defaulted back to being general purpose These items are reset only by a system reset All control bits in the SPCR register e
3. Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 ADC Data Register Low 0 Read ADx ADx ADx ADx ADx ADx ADx ADx 005A ADRLO write R R R R R R R R Reset 0 0 0 0 0 0 0 0 005B ADRL1 write R R R R R R R R Reset 0 0 0 0 0 0 0 0 ADRL2 write R R R R R R R R Reset 0 0 0 0 0 0 0 0 005D ADRL3 write R R R R R R R R Reset 0 0 0 0 0 0 0 0 ADC Auto scan Control AUTO1 AUTOO ASCAN 005E Register Write ADASCR Reset 0 0 0 0 0 0 0 0 Read 005F Unimplemented Write Reset Read 4 b SBSW 5 SIM Break Status Register FE00 SBSR Write Note Reset 0 Note Writing a logic 0 clears SBSW Read POR PIN COP ILOP MODRST LVI 0 SIM Reset Status Register FEO01 SRSR Write Reset 1 0 0 0 0 0 0 0 Read R R R R R R R R FE02 Reserved Write Reset U Unaffected X Indeterminate Unimplemented R Reserved Figure 2 2 Control Status and Data Registers Sheet 10 of 12 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 47 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 SIM Break Flag Control Read BCFE R R R R R R R FE03 Reg
4. D W gt 9 M RWU E 5 9 WARE SCRF Q2 WAKEUP zb PARITY gt CHECKING EZB IDLE UE DMARE SCRF SCRIE Sea DMARE SCRF SCRIE DMARE SRE OR ke ORIE ORE NF NE FE EET lige FEIE s PEIE Figure 14 8 SCI Receiver Block Diagram MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 261 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications 714 6 3 2 Character Reception During an SCI reception the receive shift register shifts characters in from the RxD pin The SCI data register IRSCDR is the read only buffer between the internal data bus and the receive shift register After a complete character shifts into the receive shift register the data portion of the character transfers to the IRSCDR The SCI receiver full bit SCRF in IRSCI status register 1 IRSCS1 becomes set indicating that the received byte can be read If the SCI receive interrupt enable bit SCRIE in IRSCC2 is also set the SCRF bit generates a receiver CPU interrupt request 714 6 3 3 Data Sampling The receiver samples the RxD pin at the RT clock rate The RT clock is an internal signal with a frequency 16 times the baud rate To adjust for baud rate mismatch the RT clock is resynchronized at the following times see Fi
5. INTERNAL TSTOP Ps2 PS1 PSO TRST TI LOGIC TOVO CHANNEL 0 ELSOB ELSOA CHOMAX TI1 2 CHO d 16 BIT LATCH INTERRUPT MSOA CHOIE iiid mso gt 69 TOV1 CHANNEL 1 ELS1B ELS1A CH1MAX T 1 2 CH1 3 4 E 16 BIT LATCH INTERRUPT z LOGIC MS1A CH1IE Figure 11 1 Block Diagram Figure 11 2 summarizes the timer registers NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number For example TSC may generically refer to both T1SC and T2SC MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 183 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read TOF 0 0 Timer 1 Status and Control TOIE TSTOP PS2 PS1 PSO 0020 Register Write 0 TRST T1SC Reset 0 0 1 0 0 0 0 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Timer 1 Counter 0021 Register High Write 1 Reset 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 Timer 1 Counter 0022 Register Low Write TICNTL Reset 0 0 0 0 0 0 0 0 Read Timer 1 Counter Modulo Bit 15 14 13 12 11 10 9 Bit 8 0023 Register High Write T1MODH eset 1 1
6. Priority Flag Interrupt Source y bn Reserved IF21 is Timebase IF20 Ee Infrared SCI Transmit IF19 Infrared SCI Receive IF18 SEEDS Infrared SCI Error IF17 SPI Transmit IF16 SPI Receive IF15 diis ADC Conversion Complete IF14 SEES Keyboard IF13 iis SCI Transmit IF12 SCI Receive IF11 iux SCI Error IF10 ide MMIIC IF9 dica TIM2 Overflow IF8 Miis TIM2 Channel 1 IF7 TIM2 Channel 0 IF6 eiiis TIM1 Overflow IF5 MALES TIM1 Channel 1 IF4 uuu TIM1 Channel 0 IF3 ii PLL REESE Reset Highest FFFF MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 143 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM 9 5 1 5 Interrupt Status Register 2 Address FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read F14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 9 13 Interrupt Status Register 2 INT2 IF14 IF7 Interrupt Flags 14 7 These flags indicate the presence of interrupt requests from the sources shown in Table 9 3 1 Interrupt request present 0 No interrupt request present 95 1 6 Interrupt Status Register 3 Address FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 IF21 IF20 IF19 IF18 IF17 IF16 IF15 Write R
7. PS 2 0 bits Table 11 2 Prescaler Selection PS2 PS1 PSO TIM Clock Source 0 0 Internal bus clock 1 0 1 Internal bus clock 2 0 1 0 Internal bus clock 4 0 1 1 Internal bus clock 8 1 0 0 Internal bus clock 16 1 0 1 Internal bus clock 32 1 1 0 Internal bus clock 64 1 1 1 Not available Data Sheet MC68HC908AP Family Rev 2 5 196 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM Registers 11 9 2 TIM Counter Registers The two read only TIM counter registers contain the high and low bytes of the value in the TIM counter Reading the high byte TCNTH latches the contents of the low byte TCNTL into a buffer Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read Reset clears the TIM counter registers Setting the TIM reset bit TRST also clears the TIM counter registers NOTE If you read TCNTH during a break interrupt be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt Otherwise TCNTL retains the value latched during the break Address T1CNTH 0021 and T2CNTH 002C Bit 7 6 5 4 3 2 1 Bit 0 Read Bit15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 5 TIM Counter Registers High TCNTH Address T1CNTL 0022 and T2CNTL 002D
8. 259 14 6 2 5 Transmitter Interrupts iiis snae xa xa en 260 1463 MOC uia ace awe eee iiss de ue acd SP SR T ei do 260 14 6 3 1 Character USI eae sd 260 14 6 3 2 Character Reception 262 14633 Dua Sampling e 6 262 14 6 3 4 UR Ee dec 264 14 6 3 5 Baud Rate 264 14 6 3 6 Receiver 267 14 6 3 7 Receiver 268 14 6 3 8 Eror Ioa aeo odes 268 14 7 Low Power Modes 269 14 7 1 269 DUE Stop Do PRENNE 269 14 8 SCI During Break Module 269 149 VO Signals Tr 270 1481 PTC6 SCTxD Transmit 270 14 9 2 PTC7 SCRxD Receive Data 270 1410 FO Regie ienai a a 271 14 10 1 Control Register 1 272 1440 2 IRSCI Control 2 274 1410 3 IRSCI Control 3 277 14 10 4 IRSCI Status Register 1 279 M4105 IRSCI Status 2 283 14 10 6 IRSCI Data 284 14 10 7 IRSCI Baud Rate
9. 101 8 2 ao aie en NI 101 8 3 Functional Description 102 8 3 1 Oscillator Module ax ERE RA EXE XR GE xA 105 8 3 2 Phase Locked Loop Circuit PLL 105 8 3 3 PLL Circuits LL uice de ee aah p eck ok dh 105 8 3 4 Acquisition and Tracking Modes 107 8 3 5 Manual and Automatic PLL Bandwidth Modes 107 8 3 6 Programming the PLL 524 2333 secede RC RO 109 8 3 7 Special Programming Exceptions 113 8 3 8 Base Clock Selector 113 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 9 For More Information On This Product Go to www freescale com Data Sheet Freescale Semiconductor Inc Table of Contents 8 3 9 8 4 8 4 1 8 4 2 8 4 3 8 4 4 8 4 5 8 4 6 8 4 7 8 4 8 8 5 8 5 1 8 5 2 8 5 3 8 5 4 8 5 5 8 6 8 7 8 7 1 8 7 2 8 7 3 8 8 8 8 1 8 8 2 8 8 3 9 1 9 2 9 2 1 Jaa 9 2 3 9 3 9 3 1 CGM External Connections 114 E IHRE 114 External Filter Capacitor Pin CGMXFC 115 PLL Analog Power Pin 115 PLL Analog Ground Pin 115 Oscillator Output Frequency Signal CGMXCLK 115 CGM Reference Clock 115 CGM VCO Cl
10. 285 14 10 8 IRSCI Infrared Control 288 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Data Sheet Section 15 Serial Peripheral Interface Module SPI 15 1 5 ob eee ds dE 289 15 2 dd Rm RR 289 15 3 Pin Name Conventions and I O Register Addresses 290 15 4 Functional Description 291 15 4 1 Master Mode 292 1542 E 4 293 15 5 Transmission uda ce cece cee xo eo Jor CR Ro 294 15 5 1 Clock Phase and Polarity Controls 294 15 5 2 Transmission Format When 0 295 15 5 8 Transmission Format When 1 297 15 5 4 Transmission Initiation Latency 298 15 6 Queuing Transmission 300 15 7 301 15741 MOM EHI 301 303 Dt 23545 re 305 15 9 Resetingihe uo duy d ded oce ER olo 307 15 10 Low Power Modes 308 15 101 WSR MOGUS ha ae Rn m d ae 308 154102 SOD OG ccu 3 48 eke bees 308 15 11 SPI
11. 325 16 58 Handshaking us Eb da qa d s oC i oda 325 16 5 9 Packet Error Code cisco cece end ERR nun eds 326 16 6 MMIIC 326 16 6 1 MMIIC Address Register 326 16 6 2 MMIIC Control Register 1 MMCR1 328 16 6 3 MMIIC Control Register 2 MMCR2 330 16 6 4 Status Register 332 16 6 5 MMIIC Data Transmit Register 334 16 6 6 MMIIC Data Receive Register MMDRR 335 16 6 7 MMIIC CRC Data Register MMCRCDR 336 16 6 8 MMIIC Frequency Divider Register MMFDR 337 16 7 Program Lodo eese o de ael doi P ede 338 16 7 1 Data 339 16 8 SMBus Protocols with PEC and without PEC 340 16 8 1 Quick 340 Iss And BU 340 OSEE 340 16 8 4 Write BEVIN os cues quede dure E RR ER EE E dns 341 16 8 5 Read Ld scade CIR Ee d EORR aus 341 16 8 6 Process Gall ssc ipi dle de dO dodo r tkt REESE RR E ears 342 16 8 7 Block 342 16 9 SMBus Protocol Implementation 343 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 17 For More Information On This Product Go to www freescale com
12. Bit 7 6 5 4 3 2 1 Bit 0 Read SCTE TC SCRF IDLE OR NF FE PE Write Reset 1 1 0 0 0 0 0 0 Unimplemented Figure 13 12 SCI Status Register 1 SCS1 SCTE SCI Transmitter Empty Bit This clearable read only bit is set when the SCDR transfers a character to the transmit shift register SCTE can generate an SCI transmitter CPU interrupt request When the SCTIE bit in SCC2 is set SCTE generates an SCI transmitter CPU interrupt request In normal Data Sheet MC68HC908AP Family Rev 2 5 240 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Registers operation clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR Reset sets the SCTE bit 1 SCDR data transferred to transmit shift register 0 SCDR data not transferred to transmit shift register TC Transmission Complete Bit This read only bit is set when the SCTE bit is set and no data preamble or break character is being transmitted TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set TC is automatically cleared when data preamble or break is queued and ready to be sent There may be up to 1 5 transmitter clocks of latency between queueing data preamble and break and the transmission actually starting Reset sets the TC bit 1 No transmission in progre
13. A START Repeated STOP signal START signal signal Figure 16 2 Multi Master Bus Transmission Signal Diagram Data Sheet MC68HC908AP Family Rev 2 5 322 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC Multi Master IIC Bus Protocol 16 5 1 START Signal When the bus is free i e no master device is engaging the bus both SCL and SDA lines are at logic high a master may initiate communication by sending a START signal As shown in Figure 16 2 a START signal is defined as a high to low transition of SDA while SCL is high This signal denotes the beginning of a new data transfer each data transfer may contain several bytes of data and wakes up all slaves 16 5 2 Slave Address Transmission The first byte transferred immediately after the START signal is the slave address transmitted by the master This is a 7 bit calling address followed by a R W bit The R W bit dictates to the slave the desired direction of the data transfer A logic indicates that the master wishes to transmit data to the slave a logic 1 indicates that the master wishes to receive data from the slave Only the slave with a matched address will respond by sending back an acknowledge bit by pulling SDA low on the 9th clock cycle See Figure 16 2 16 5 3 Data Transfer Once a successful slave addressing is achieved the dat
14. Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 6 TIM Counter Registers Low TCNTL MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 197 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module 11 9 3 TIM Counter Modulo Registers The read write TIM modulo registers contain the modulo value for the TIM counter When the TIM counter reaches the modulo value the overflow flag TOF becomes set and the TIM counter resumes counting from 0000 at the next timer clock Writing to the high byte TMODH inhibits the TOF bit and overflow interrupts until the low byte TMODL is written Reset sets the TIM counter modulo registers Address T1MODH 0023 and T2MODH 002E Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 Figure 11 7 TIM Counter Modulo Register High TMODH Address T1MODL 0024 and T2MODL 002F Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 Figure 11 8 TIM Counter Modulo Register Low TMODL NOTE Reset the TIM counter before writing to the TIM counter modulo registers Data Sheet MC68HC908AP Family Rev 2 5 198 MOTOROLA For More Information On This Product Go to www freescale com Freescal
15. MMIIC Baud Rates for Bus Clocks MMBR2 MMBR1 MMBRO Divider 8MHz 4MHz 2MHz 1MHz 0 0 0 20 400kHz 200kHz 100kHz 50kHz 0 0 1 40 200kHz 100kHz 50kHz 25kHz 0 1 0 80 100kHz 50kHz 25kHz 12 5kHz 0 1 1 160 50kHz 25kHz 12 5kHz 6 25kHz 1 0 0 320 25kHz 12 5kHz 6 25kHz 3 125kHz 1 0 1 640 12 5kHz 6 25kHz 3 125kHz 1 5625kHz 1 1 0 1280 6 25kHz 3 125kHz 1 5625kHz 0 78125kHz 1 1 1 2560 3 125kHz 1 5625kHz 0 78125kHz 0 3906kHz NOTE frequency of the MMIIC baud rate is only guaranteed for 100kHz to 10kHz The divider is available for the flexibility on bus frequency selection MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA For More Information On This Product Go to www freescale com 337 Freescale Semiconductor Inc Multi Master IIC Interface MMIIC 16 7 Program Algorithm When the MMIIC module detects an arbitration loss in master mode it releases both SDA and SCL lines immediately But if there are no further STOP conditions detected the module will hang up Therefore it is recommended to have time out software to recover from this condition The software can start the time out counter by looking at the MMBB bus busy flag and reset the counter on the completion of one byte transmission If a time out has occurred software can clear the MMEN bit disable MMIIC module to release the bus and hence clear the MMBB flag This is the only way to clear the MMBB flag by software if the m
16. T Samples Verification Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 If start bit verification is not successful the RT clock is reset and a new search for a start bit begins To determine the value of a data bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 14 3 summarizes the results of the data bit samples Table 14 3 Data Bit Recovery Ts ames t pate canton Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 263 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications NOTE The RT8 RT9 and RT10 samples do not affect start bit verification If any or all of the RT8 RT9 and RT10 start bit samples are logic 1s following a successful start bit verification the noise flag NF is set and the receiver assumes that the bit is a start bit To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and 10 Table 14 4 summarizes the results of the stop bit samples Table 14 4 Stop Bit Recovery RT8 RIS RT10 Error Fig Noise Flag 000 1 001 1 1 010 1 011 0 l 100 1 101 0 110 0 111 0 p 14 6 3 4 Framing Errors If the data recovery logi
17. RESET KEYBOARD INTERRUPT FF hes Keyboard Interrupt Request TO PULLUP ENABLE Figure 20 2 Keyboard Interrupt Block Diagram Writing to the KBIE7 KBIEO bits in the keyboard interrupt enable register independently enables or disables each port D pin as a keyboard interrupt pin Enabling a keyboard interrupt pin in port D also enables its internal pull up device A logic O applied to an enabled keyboard interrupt pin latches a keyboard interrupt request A keyboard interrupt is latched when one or more keyboard pins goes low after all were high The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt Data Sheet MC68HC908AP Family Rev 2 5 388 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt Module KBI Functional Description e Ifthe keyboard interrupt is edge sensitive only a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low To prevent losing an interrupt request on one pin because another pin is still low software can disable the latter pin while it is low e If the keyboard interrupt is falling edge and low level sensitive an interrupt request is present as long as any keyboard pin is low If the MODEK bit is set the keyboard interrupt pins are both falling edge and
18. 1 397 21 3 6 Reset 397 21 3 7 COPD COP Disable RR Rae 397 21 38 COPRS COP Rate 398 21 4 COP Control 5 398 215 co au hc esp ae la E ER 399 216 Montor MOB SEER e Ca dedo ow dax b 399 21 7 Low Power 399 21 7 1 PUR 399 mt 399 21 8 COP Module During Break 400 Section 22 Low Voltage Inhibit LVI 22 1 s he Pm 401 p LLL dcr a 401 22 3 Functional Description 402 22 31 Low Eoo CR PCT 403 2202 LOW Vpgg enhn erpii 403 22 3 3 Polled LVI Operation 404 MC68HC908AP Family Rev 2 5 20 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 22 34 Forced Reset 404 22 3 5 Voltage Hysteresis Protection 404 22 4 LVI Status 404 22 5 LUMINE 405 22 6 Low Power MO0GS dbp ed ae 405 Wat BUE Lubeke add abet el 4d nde acd dci 405
19. Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 16 10 MMIIC CRC Data Register MMCRCDR When the MMIIC module is enabled MMEN 1 and the CRC buffer full flag is set MMCRCBF 1 data in this read only register contains the generated CRC byte for the last byte of received or transmitted data A CRC byte is generated for each received and transmitted data byte and loaded to the CRC data register The MMCRCBF bit will be set to indicate the CRC byte is ready in the CRC data register Reading the CRC data register clears the MMCRCBFE bit If the CRC data register is not read the MMCRCBF bit will be cleared by hardware before the next CRC byte is loaded MC68HC908AP Family Rev 2 5 336 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 16 6 8 MMIIC Frequency Divider Register MMFDR Multi Master IIC Interface MMIIC MMIIC I O Registers Address 004F Bit 7 5 4 2 1 Bit 0 Read 0 0 0 MMBR2 MMBR1 MMBRO Write Reset 0 0 0 1 0 0 Unimplemented Figure 16 11 MMIIC Frequency Divider Register MMFDR The three bits in the frequency divider register MMFDR selects the divider to divide the bus clock to the desired baud rate for the MMIIC data transfer Table 16 2 shows the divider values for MMBR 2 0 Table 16 2 MMIIC Baud Rate Selection
20. TNP 1 0 IREN i TRANSMIT 0 SCI_TxD ENGODES gt SCTxD p SCI_R32XCLK SCI R16XCLK 4 YY IR_RxD RECEIVE DECODER 7 x SCI_RxD Figure 14 3 Infrared Sub Module Diagram The infrared sub module provides the capability of transmitting narrow pulses to an infrared LED and receiving narrow pulses and transforming them to serial bits which are sent to the SCI module The infrared sub module receives two clocks from the SCI One of these two clocks is selected as the base clock to generate the 3 16 1 16 or 1 32 bit width narrow pulses during transmission MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 253 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications The sub module consists of two main blocks the transmit encoder and the receive decoder When transmitting data the SCI data stream is encoded by the infrared sub module For every 0 bit a narrow low pulse is transmitted no pulse is transmitted for 1 bits When receiving data the infrared pulses should be detected using an infrared photo diode for conversion to CMOS voltage levels before connecting to the RxD pin for the infrared decoder The SCI data stream is reconstructed by stretching the 0 pulses 14 5 1 Infrared Transmit Encoder The infrared transmit encoder converts the O bits in the serial data stream from the SCI module to narrow low p
21. 219 13 4 2 4 Idle 219 13 4 2 5 Inversion of Transmitted Output 220 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 13 For More Information On This Product Go to www freescale com Data Sheet Freescale Semiconductor Inc Table of Contents 13 4 2 6 Transmitter 220 134 3 0 cetacean sede irdd ed aeen ees 221 13 4 3 1 Character 221 13 4 3 2 Character Reception 221 134 3 3 Data Sampling Lea dap qe Rad 223 13 4 3 4 Framing Ls aoa ak ER EEG CV RERO CR RA 225 13 4 3 5 Baud Rate 225 13 4 3 6 Receiver 228 13 4 3 7 Receiver 229 13 4 3 8 Error 229 13 5 230 Tom Fe gt 230 feme MoJa S Lor dad Eb lcd bb bebe ie den 230 13 6 SCI During Break Module Interrupts 230 jac RO DIDI Rota goa do ddr RR 231 13 71 TxD Transmit Data qaaa eur HER 231 13 7 2 RxD Receive 231 13 8 VO Registers TET 232 13 8 1 SCI Control Register 1
22. DDRAx RESET INTERNAL DATA BUS READ PTA 0000 Figure 18 4 Port A I O Circuit When DDRAx is a logic 1 reading address 0000 reads the PTAx data latch When DDRAx is a logic 0 reading address 0000 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 18 2 summarizes the operation of the port A pins Table 18 2 Port A Pin Functions DDR A PT A Accesses to Accesses to diu Read Write Read Write 0 x Input Hi Z DDRA 7 0 Pin PTA 7 0 9 1 X Output DDRA 7 0 PTA 7 0 PTA 7 0 Notes 1 X don t care 2 Hi Z high impedance 3 Writing affects data register but does not affect input MC68HC908AP Family Rev 2 5 368 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Input Output I O Ports Port A 18 2 3 Port A LED Control Register LEDA The port A LED control register LEDA controls the direct LED drive capability on PTA7 PTAO pins Each bit is individually configurable and requires that the data direction register DDRA bit be configured as an output Address 000 Bit 7 6 5 4 3 2 1 Bit 0 Read LEDA7 LEDA6 LEDA5 LEDA4 LEDA3 LEDA2 LEDA1 LEDAO Write Reset 0 0 0 0 0 0 0 0 Figure 18 5 Port A LED Control Register LEDA LEDA 7 0 Port A L
23. Unimplemented Figure 8 6 PLL Multiplier Select Register High PMSH Address 0039 Bit 7 6 5 4 3 2 1 Bit 0 Read MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MULO Write Reset 0 1 0 0 0 0 0 0 Figure 8 7 PLL Multiplier Select Register Low PMSL MULJ 1 1 0 Multiplier Select Bits These read write bits control the modulo feedback divider that selects the VCO frequency multiplier N See 8 3 3 PLL Circuits and 8 3 6 Programming the PLL A value of 0000 in the multiplier select registers configure the modulo feedback divider the same as a value of 0001 Reset initializes the registers to 0040 for a default multiply value of 64 NOTE multiplier select bits have built in protection such that they cannot be written when the PLL is on PLLON 1 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 121 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM 8 5 4 PLL VCO Range Select Register NOTE Data Sheet The PLL VCO range select register PMRS contains the programming information required for the hardware configuration of the VCO Address 003A Bit 7 6 5 4 3 2 1 Bit 0 Read VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRSO Write Reset 0 1 0 0 0 0 0 0 Figure 8 8 PLL VCO Range Select Register PMRS VRS 7 0 VCO Range Select Bits These read wri
24. Revision Date Level Description Number s Added MC68HC908AP106 AP8 information throughout Section 10 Monitor ROM MON Corrected RAM address to 167 October 2003 2 5 60 Section 24 Electrical Specifications Added run and wait 421 data for 8MHz at 3V August 2003 2 4 Section 24 Electrical Specifications Updated stop Ipp data 417 421 Removed MC68HC908AP16 references throughout Table 1 2 Pin Functions Added footnote for 30 5 3 Configuration Register 1 CONFIG1 Clarified LVIPWRD 67 and LVIREGD bits Section 8 Clock Generator Module CGM 8 7 2 Stop Mode 125 July 2003 2 3 Updated BSC bit behavior 10 5 ROM Resident Routines Corrected data size limits and 168 193 control byte size for EE READ and EE WRITE Figure 12 2 Timebase Control Register TBCR Corrected 207 register address Section 24 Electrical Specifications Updated 415 Updated for 125kHz and filter components 101 May 2003 22 in CGM section Updated electricals 415 Data Sheet MC68HC908AP Family Rev 2 5 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Data Sheet MC68HC908AP Family List of Sections For Mo Section 1 General Description 23 Section 2 Memory 35 Section 3 Random Access Memory RAM 53 Section 4
25. 0 1 pF Vpp 0 1 uF 1 V 1 REG 4 9152 MHz 9 8304MHz 50 DUTY T 5 1 1 gt _ 001 MUST BE USED IF SW2 IS AT POSITION ilk E CONNECT TO OSC1 WITH OSC2 UNCONNECTED 0 033 uF Tcp 4 eo EXT OSC ee E 32 768 kHz Ld 6 30 MAX232 T 80k DD l L 2 6 30 pF du boann SS ei SSeS XTAL CIRCUIT Vist C SEE NOTE 1 Voo 1 1 pF aS 85V D ABE E k DB9 2 2 d 5 3 Vpp 5 1 10k 5 10 SW1 SEE NOTE 2 o l NOTES pe 1 Monitor mode entry method SW2 Position C High voltage entry must use external OSC 10k 10k 2 Bus clock depends on SW1 note 2 mM SW2 Position D Reset vector must be blank SFFFE FFFF FF Bus clock 2 4576MHz 2 Affects high voltage entry to monitor mode only SW2 at position C SW1 Position A Bus clock OSC1 4 SW1 Position Bus clock OSC1 2 5 See Table 24 4 for voltage level requirements Figure 10 1 Monitor Mode Circuit MC68HC908AP Family Rev 2 5 RST HC908AP VREFH VREG VREFL Vss Vssa CGMXFC OSC1 OSC2 PTAO PTA1 PTBO PTA2 Data Sheet MOTOROLA For More Information On This Product Go to www freescale com 155 Freescale Semiconductor Inc Monitor 10 3 1 Entering Monitor Mode Data Sheet Table
26. C68HC 908A P1E H IVF reescale Semiconductor Inc oye Q MOTORA digital dna intelligence everywhere MC68HC908AP64 MC68HC908AP32 MC68HC908AP16 MC68HC908AP8 Data Sheet 68 08 Microcontrollers MC68HC908AP64 D Rev 2 5 10 2003 MOTOROLA COM SEMICONDUCTORS For More Information On This Product o to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC908AP64 MC68HC908AP32 MC68HC908AP16 MC68HC908AP8 Data Sheet To provide the most up to date information the revision of our documents on the World Wide Web will be the most current Your printed copy may be an earlier revision To verify you have the latest information available refer to http motorola com semiconductors The following revision history table summarizes changes contained in this document For your convenience the page number designators have been linked to the appropriate location Motorola and the Stylized M Logo are registered trademarks of Motorola Inc DigitalDNA is a trademark of Motorola Inc This product incorporates SuperFlash technology licensed from SST Motorola Inc 2003 MC68HC908AP Family Rev 2 5 Data Sheet 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Revision History Revision History
27. Figure 15 4 Transmission Format CPHA 0 MISO MOSI 1 y BYTE 2 BYTE 3 y MASTERSS S BARS Y A A z SLAVE SS Ja CPHA 1 Figure 15 5 CPHA SS Timing When CPHA 0 for a slave the falling edge of SS indicates the beginning of the transmission This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data Once the transmission begins no new data is allowed into the shift register from the transmit data register Therefore the SPI data register of the slave must be loaded with transmit data before the falling edge of SS Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission Data Sheet MC68HC908AP Family Rev 2 5 296 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Transmission Formats 15 5 3 Transmission Format When CPHA 1 Figure 15 6 shows an SPI transmission in which CPHA is logic 1 The figure should not be used as a replacement for data sheet parametric information Two waveforms are shown for SPSCK one for CPOL 0 and another for CPOL 1 The diagram may be interpreted as a master or slave timing diagram since the serial clock SPSCK master in slave out MISO and master out slave in MOSI pins are directly connected between the master and the slave Th
28. 2 rel result 0 INH 5B 3 DBNZ opr X rel PC lt 3 rel result 0 IX1 6B 5 DBNZ X rel PC lt PC 2 rel result 0 IX 7B 4 DBNZ SPrel PC lt 4 rel result 0 SP1 frr 6 DEC opr M M 1 DIR 4 DECA A lt A 1 INH 4A 1 DECX X lt X 1 NM _ INH 5A 1 DEC Decrement M lt M 1 T 1 7 Iq 6A f 4 DEC X M M 1 IX 7A 3 DEC opr SP M lt M 1 SP1 5 DIV Divide Ae EANO t t INH 52 7 lt Remainder EOR opr IMM A8 2 EOR DIR dd 3 EOR opr EXT C8 hhll 4 EOR opr X IX2 08 4 EOR oprX Exclusive OR M with A A lt M 0 712 Es ff 3 EOR X IX F8 2 EOR opr SP SP1 9EE8 4 EOR opr SP SP2 9 08 5 Data Sheet MC68HC908AP Family Rev 2 5 84 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Opcode Map Table 6 1 Instruction Set Summary Sheet 5 of 8 Effect on Source Operation Description CCR g S 9 3 3 9 2 1 2 6 6 6 INC opr M lt M 1 DIR 3C dd 4 INCA lt 1 INH 4C 1 INCX X lt X 1 21110101 INH 5C 1 INC M lt M 1 1 1 6 4 INC X M lt
29. Converter ADC Data Sheet MC68HC908AP Family Rev 2 5 362 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 18 Input Output I O Ports 18 1 Introduction Thirty two 32 bidirectional input output pins form four parallel ports All I O pins are programmable as inputs or outputs NOTE Connect any unused I O pins to an appropriate logic level either V5 or Vas Although the ports do not require termination for proper operation termination reduces excess current consumption and the possibility of electrostatic damage MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 363 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read PTA7 5 PTA4 2 1 PTAO 0000 Port A Data Register Write PTA Reset Unaffected by reset Read PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTBO 0001 Port B Data Register Write PTB Reset Unaffected by reset Read PTC7 PTC6 5 PTC4 PTC3 PTC2 PTC1 PTCO 0002 Port C Data Register Write PTC Reset Unaffected by reset Read PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PT
30. NOTES DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 CONTROLLING DIMENSION INCH DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH MAXIMUM MOLD FLASH 0 25 0 010 A INCHES MILLIMETERS MIN MAX MIN MAX 1485 1 465 36 45 37 21 0 540 0 560 13 72 14 22 0 155 0 200 3 94 5 08 0 014 0 022 0 36 0 56 D 0 032 0 046 0 81 117 G 0 070 BSC 1778 BSC i 0 300 7 62 BSC T h J 0 008 0 015 0 20 038 SEATING 4 K 0 115 0 135 2 92 3 43 PLANE NE L 0 600 BSC 15 24 BSC M 0 15 o 15 J 42 PL 0 020 0 040 051 1 02 e 025 001 T 4 0 5 0 010 B Figure 25 3 42 Pin SDIP Case 858 Data Sheet MC68HC908AP Family Rev 2 5 436 MOTOROLA For More Information On This Product Go to www freescale com Data Sheet MC68HC908AP Family Freescale Semiconductor Inc 26 1 Introduction 26 2 MC Order Numbers This section contains device ordering numbers Table 26 1 MC Order Numbers Section 26 Ordering Information MC Order Number postca Package MC68HC908AP64CB 2 048 62 368 42 pin SDIP 40 to 85 C MC68HC908AP64CFB 2 048 62
31. 174 10 5 5 MON _ 175 10 5 60 EE pies ck dede on eL A048 he CORR AGRAR ED 176 EE READ EROR RR E 179 Section 11 Timer Interface Module TIM 1 ed RO ER eae dur do opi Pre rd E de DRM 181 Tus PRENDE 181 113 PinName 182 11 4 Functional Description 182 11 4 1 186 11 42 186 11 4 3 187 11 4 3 1 Unbuffered Output Compare 187 11 4 3 2 Buffered Output Compare 188 11 4 4 Pulse Width Modulation 188 11 4 4 1 Unbuffered PWM Signal Generation 189 11 4 4 2 Buffered PWM Signal Generation 190 11 4 4 3 P 191 22 do ER ET ree ood 192 11 6 Low Power Modes 192 1161 Wat MOQG iode Xx abd dac Rd roaa na cde rd Rd 193 11 5 2 GOD MOOS 193 MC68HC908AP Family Rev 2 5 12 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 11 7 TIM During Break 193 M SEI a de cach ud RE
32. CGMPCLK PHASE Loop DETECTOR FILTER OSCILLATOR 1 LOCK 2 INTERRUPT ME DETECTOR CONTROL CONTROL To SIM 1 1 LOCK AUTO ACQ PLLIE PLLF MUL 11 0 PRE 1 0 CGMVDV FREQUENCY FREQUENCY CGMVCLK DIVIDER DIVIDER Figure 8 1 CGM Block Diagram MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 103 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read PLLF Sod PLL Control Register iis PLLIE PLLON BCS PRE1 PREO VPR1 VPRO PTCL Reset 0 0 1 0 0 0 0 0 Read LOCK Pen 0 0 0 0 PLL Bandwidth Control AUTO ACQ R 0037 Register Write PBWC Reset 0 0 0 0 0 0 0 E Read 0 0 0 0 PLL Multiplier Select MUL11 MUL10 MUL9 MUL8 0038 Register High Write PMSH Reset 0 0 0 0 0 0 0 0 Read PLL Multiplier Select MUL7 MUL6 MUL5 MUL2 MULO 0039 Register Low Write PMSL Reset 0 1 0 0 0 0 0 0 Read PLL VCO Range Select vRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRSO 003A Register Write PMRS Reset 0 1 0 0 0 0 0 0 Read 0 0 0 0 PLL Reference Divider RDS3 RDS2 RDS1 RDSO 003B Select Register Write PMDS Reset 0 0 0 0 0 0 0 1 Unimplemented R Reserved NOTES 1 When AUTO 0 PLLIE is forced clear and is read only 2 When
33. is disabled if the RST pin or the IRQ1 is held at Vst During the break state on the RST disables the COP Place COP clearing instructions in the main program and not in an interrupt subroutine Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly The following paragraphs describe the signals shown in Figure 21 1 ICLK is the internal oscillator output signal See Section 24 Electrical Specifications for ICLK frequency specification 21 3 2 STOP Instruction Data Sheet The STOP instruction clears the COP prescaler MC68HC908AP Family Rev 2 5 396 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Computer Operating Properly COP Signals 21 3 3 COPCTL Write Writing any value to the COP control register COPCTL see 21 4 COP Control Register clears the COP counter and clears bits 12 through 5 of the prescaler Reading the COP control register returns the low byte of the reset vector 21 3 4 Power On Reset The power on reset POR circuit clears the COP prescaler 4096 ICLK cycles after power up 21 3 5 Internal Reset An internal reset clears the COP prescaler and the COP counter 21 3 6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus A reset vector fetch clears the COP prescaler 21 3 7 COPD COP Dis
34. AGE ee oe bed 405 Section 23 Break Module BRK WONG PP 407 FEES PPP TCI 407 23 3 Functional Description 408 23 3 1 Flag Protection During Break Interrupts 409 23 3 2 CPU During Break 409 23 33 TIMI and TIM2 During Break Interrupts 410 23 3 4 During Break Interrupts 410 29 4 Low Power Modes aided da 410 WARIO KS PURI 410 2942 BIOP Mod 410 23 5 Break Module 5 lt 410 23 5 1 Break Status and Control Register 411 23 5 2 Break Address Registers 412 23 5 3 SIM Break Status 412 23 5 4 SIM Break Flag Control 414 Section 24 Electrical Specifications WCCO La soa dedic Vb dca ee i aee E 415 24 2 Absolute Maximum Ratings 415 243 Functional Operating 416 24 4 Thermal 5 416 24 5 5V DC Electrical Characteristics 417 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 21 For More Information On This Product Go to www freescale com Data Sheet Freescale Semicon
35. MOTOROLA 431 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 24 17 FLASH Memory Characteristics Table 24 15 FLASH Memory Electrical Characteristics Characteristic Symbol Min Max Unit Data retention voltage VRDR 1 3 V Number of rows per page 8 Rows Number of bytes per page 512 Bytes Read bus clock frequency fread 32k 8M Hz Page erase time MC 20 ms Mass erase time tme 200 ms PGM ERASE to HVEN setup time tnvs 5 High voltage hold time 5 High voltage hold time mass erase thvh1 100 HS Program hold time togs 10 us Program time torog 20 40 us Address data setup time tads 20 ns Address data hold time tadh 30 ns Recovery time trav 1 us Cumulative HV period thy 8 ms Row erase endurance 10k Cycles Row program endurance 10k ES Cycles Data retention time 10 E Years Notes 1 freag is defined as the frequency range for which the FLASH memory be read 2 If the page erase time is longer than terase Min there is no erase disturb but it reduces the endurance of the FLASH memory 3 If the mass erase time is longer than tme Min there is no erase disturb but is reduces the endurance of the FLASH memory 4 It is defined as the time it needs before the FLASH can be read after turning off
36. N 199 5 N eor tu SUE pr gE fo ro TOS SFOs Gays SOI Gals Sols Daly 29199 7 a On 1 pepuex3 1X3 paid uid WNI juejeuu HNI a a S a S a S a S a a S a S a S a S 4 6 6 2 9 9 Su T10ug S13SH8 S 4 62 6 vlasuad u Toug d 13SHH8 S 6 cud Toug 6 9 6 S ua 6 L13Sug S 6 Ou 10Hg S 6 0139H8 S L d d L u d u L d u d L d MC68HC908AP Family Rev 2 5 89 Data Sheet Central Processor Unit CPU For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Data Sheet MC68HC908AP Family Rev 2 5 90 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family 7 1 Introduction Section 7 Oscillator OSC The oscillator module consist of three types of oscillator circuits e Internal oscillator RC oscillator e 32 768kHz crystal x tal oscillator The reference clock for the CGM
37. Reset Indeterminate after reset Timer 1 Channel 0 Read Bit 7 6 5 4 3 2 1 Bit 0 0027 Register Low Write ee Reset Indeterminate after reset U Unaffected X Indeterminate Unimplemented R Reserved Figure 2 2 Control Status and Data Registers Sheet 4 of 12 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 41 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0 Timer 1 Channel 1 Status MS1A ELS1B ELS1A TOV1 CH1MAX 0028 and Control Register Write 0 118 1 Reset 0 0 0 0 0 0 0 0 Timer 1 Channel 1 8829 imer 1 Channe Bit 15 14 13 12 11 10 9 Bit 8 0029 Register High Write Reset Indeterminate after reset Timer 1 Channel 1 Read Bit 7 6 5 4 3 2 1 Bit 0 002A Register Low Write Reset Indeterminate after reset Read TOF 0 0 Timer2Statusand TOIE TSTOP Ps2 PSt PSO 002B Control Register Write 0 TRST 7250 Reset 0 0 1 0 0 0 0 0 Timer 2 Counter Read Bit15 14 13 12 11 10 9 Bit 8 002C Register High Write 2 Reset 0 0 0 0 0 0 0 0 Timer 2 Counter Read Bit 7 6 5 4 3 2 1 Bit 0 002D Register Low Write TECNTL Reset o 0 0 0 0 0 0 0 Read Timer 2 Counter Modulo Bi
38. Data Sheet MC68HC908AP Family Rev 2 5 416 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 5V DC Electrical Characteristics 24 5 5V DC Electrical Characteristics Table 24 4 DC Electrical Characteristics 5 V Characteristic Symbol Min Typ Max Unit Output high voltage lj 12 Von Vpp 0 8 V PTA 0 7 PTB 4 7 PTC 0 5 PTD 0 7 Output low voltage 1 8mA 0 7 PTB 4 7 PTC 0 5 PTD O 7 VoL LI 0 4 V ILOAD 15mA PTB 0 3 PTC 6 7 VoL 0 4 V ILOAD 15mA as TxD RxD SCTxD SCRxD Voisci 0 4 V 1 see Table 24 12 as SDA SCL 0 4 V LED sink current Vo 3V 9 15 25 PTA 0 7 E 5 Input high voltage PTA 0 7 PTB 0 7 PTC 0 7 PTD 0 7 RST IRQ1 Vin 0 7 x Vpp Vpp V OSC1 0 7 x VnEG VREG V Input low voltage PTA 0 7 PTB 0 7 PTC 0 7 PTD 0 7 RST 1 Vi Vss 03xVpp V OSC1 Vss 0 3 x VnEG V Vpp supply current fop 8 MHz Run 10 20 mA Wait 2 5 10 mA Stop 25 C with OSC TBM and LVI modules 0 8 1 8 with OSC and TBM modules on ne 22 150 all modules off 9 20 125 Stop 0 to 85 with OSC TBM and LVI modules 1 2 5 mA with OSC and TBM modules on 45 300 all modules off 9 42 250 Digital ports
39. 0 100 POR rise time ramp rate 0 02 V ms Monitor mode entry voltage Vui 1 4 x Vpp 8 5 V Pullup resistors PTD 0 7 21 27 39 kQ RST IRQ1 IRQ2 Rpu2 21 27 39 Low voltage inhibit trip falling 1 11 VrRIPF1 2 25 2 45 2 65 V Low voltage inhibit trip rising 1 17 VrRIPR1 2 35 2 55 2 75 V Low voltage inhibit trip voltage2 VrRIPF2 2 25 2 45 2 65 V 12 VnEG 2 25 2 50 2 75 V Notes 1 2 7 to 3 3 Vss 0 T to Ty unless otherwise noted 2 Typical values reflect average measurements at midpoint of voltage range 25 C only 3 At Vpp on chip charge pump is activated for the Vpgg regulator therefore some lpp values will appear higher than the Ipp values at Vpp 5V 4 Run operating Ipp measured using external 16 MHz 32MHz clock to OSC1 all inputs 0 2 V from rail no dc loads less than 100 pF on all outputs C 20 pF on 2 all ports configured as inputs OSC2 capacitance linearly affects run Ipp measured with all modules enabled Wait Ipp measured using external 16 MHz 32 MHz clock to OSC1 all inputs 0 2 V from rail no dc loads less than 100 pF on all outputs 20 pF on OSC2 all ports configured as inputs OSC2 capacitance linearly affects wait Ipp STOP Ipp measured with external 32 768kHz clock to OSC1 no port pins sourcing current STOP Ipp measured with OSC1 grounded no port pins sourcing
40. 232 13 8 2 SCI Control 5 2 235 13 8 3 SCI Control Register 3 238 13 8 4 SCI Status Register 1 240 13 8 5 Status 2 244 13 8 6 SCI Data Register 245 13 8 7 SCI Baud Rate 5 246 Section 14 Infrared Serial Communications Interface Module IRSCI os carve P RARERRC R e QR dE RR E D oc 249 TLE died ERE Ea a RS RR d 250 143 Pin Name 252 14 4 IRSCI Module 252 14 5 Infrared Functional Description 253 MC68HC908AP Family Rev 2 5 14 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 14 5 1 Infrared Transmit 254 14 5 2 Infrared Receive Decoder 254 146 SCI Functional 255 1461 Data ias dod deo oie ad o C ek ede oo 256 cae ee ees Sacer eee 257 14 6 2 1 Character 258 14 6 2 2 Character 5 510 258 14 6 2 3 Break Las as dre 259 14 6 2 4 Idle
41. 5 0 0 1 1 0 ADC6 0 0 1 1 1 7 PTA7 0 1 0 0 0 ADC8 i i 4 4 Reserved 1 1 1 0 0 ADC28 1 1 1 0 1 ADC29 see Note 2 1 1 1 1 0 ADC30 Vngr see Note 2 1 1 1 1 1 ADC powered off NOTES 1 If any unused channels are selected the resulting ADC conversion will be unknown 2 The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA For More Information On This Product Go to www freescale com 355 Freescale Semiconductor Inc Converter ADC 17 7 2 ADC Clock Control Register The ADC clock control register ADICLK selects the clock frequency for the ADC Address 0058 Read 0 0 ADIV2 ADIV1 ADIVO ADICLK MODE1 MODEO Write R Reset 0 0 0 0 0 1 0 0 Unimplemented R Reserved Figure 17 4 ADC Clock Control Register ADICLK ADIV 2 0 ADC Clock Prescaler Bits ADIV2 ADIV1 and ADIVO form a 3 bit field which selects the divide ratio used by the ADC to generate the internal ADC clock Table 17 2 shows the available clock configurations The ADC clock should be set to between 500kHz and 2MHz Table 17 2 ADC Clock Divide Ratio ADIV2 ADIV1 ADIVO ADC Clock Rate 0 0 0 ADC input clock 1 0
42. Buisseuppy seiAg Jo jequunN epoodo ui epoodo jo YIH 145 Y 145 ady 145 VHO v 145 Y 145 Y 145 VLS v 145 val v 145_ v 145 145 145 295 Y 145 v 145 ans v 2 IX XLS IX X qi gt N N rep x x 2 5 x vaql 2 EP x x OS Xo e e 295 IXI Z d IXI c ans ady S dS Y VHO S v 645 v 6 dS Y uoa S dS VLS S 64 val S dS 9 64 9 645 v 9 645 v 085 8 64 S 64 Y ans S EN m Sep z o ans v 51 6 0135 9 9 9 n S JeuoepexeH epoodo Jo eig N HNI VXL cj H d ON Su aS 19 ds 19 e lt us um gt gt a a lt 2 2 HNI 2 HNI 9 HNI XYL XSL 2 HNI SXL 2 2 TH 2 158 2 Ig z uu 2 ans 398 2 6 z age o z z HNI LIVM HNI dOLs
43. IMASK1 IRQ1 Interrupt Mask Bit Writing a logic 1 to this read write bit disables IRQ1 interrupt requests Reset clears IMASK1 1 IRQ1 interrupt requests disabled 0 IRQ1 interrupt requests enabled MODE1 IRQ1 Edge Level Select Bit This read write bit controls the triggering sensitivity of the IRQ1 pin Reset clears MODE1 1 IRQ1 interrupt requests on falling edges and low levels 0 IRQ1 interrupt requests on falling edges only Data Sheet MC68HC908AP Family Rev 2 5 384 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ IRQ Registers 19 6 2 IRQ2 Status and Control Register The IRQ2 status and control register INTSCR2 controls and monitors operation of IRQ2 The INTSCR2 has the following functions e Enables disables the internal pullup device on IRQ2 pin e Shows the state of the IRQ2 flag e Clears the IRQ2 latch Masks IRQ2 interrupt request e Controls triggering sensitivity of the IRQ2 interrupt pin Address 001C Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 IRQ2F 0 PUCOENB IMASK2 MODE2 Write ACK2 Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 19 5 IRQ2 Status and Control Register INTSCR2 PUCOENB IRQ2 Pin Pullup Enable Bit Setting this bit to logic 1 disables the pullup on PTCO IRQ2 pin Reset clears this bit 1 IRQ2 pin internal pullup is disabled
44. Multi Master IIC Interface MMIIC 16 5 9 Packet Error Code The packet error code PEC for the MMIIC interface is in the form a cyclic redundancy code CRC The PEC is generated by hardware for every transmitted and received byte of data The transmission of the generated PEC is controlled by user software The CRC data register MMCRCDR contains the generated PEC byte with three other bits in the MMIIC control registers and status register monitoring and controlling the PEC byte 16 6 MMIIC I O Registers These I O registers control and monitor MMIIC operation e MMIIC address register MMADR 0048 e MMIIC control register 1 MMCR1 0049 e MMIIC control register 2 MMCR2 004A e MMIIC status register MMSR 004B e MMIIC data transmit register MMDTR 004C MMIIC data receive register MMDRR 0040 e MMIIC CRC data register MMCRCDR 004E e MMIIC frequency divide register MMFDR 004F 16 6 1 MMIIC Address Register MMADR Address 0048 Bit 7 6 5 4 3 2 1 Bit 0 Read MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD Write Reset 1 0 1 0 0 0 0 0 Figure 16 4 MMIIC Address Register MMADR Data Sheet MC68HC908AP Family Rev 2 5 326 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC MMIIC Registers MMAD 7 1 Multi Maste
45. 1 25 3 BEQ rel Branch if Equal PC lt PC 2 rel 7 1 REL 27 3 Branch if Greater Than or Equal To 5 BGE opr Signed Operands lt PC 2 rel N V 0 REL 90 3 BGT opr Signed lt 2 rel ZI Ne V 0 REL 92 m 3 Operands BHCC rel Branch if Half Carry Bit Clear lt PC 2 rel 0 28 3 BHCS rel Branch if Half Carry Bit Set PC lt PC 2 rel 1 REL 29 3 BHI Branch if Higher lt 2 rel 1 2 0 JREL 22 3 Branch if Higher or Same 2 _ 21212121010 BHS rel Same as BCC lt 2 rel 20 REL 24 jrr 3 BIH rel Branch if IRQ Pin High PC lt 2 rel IRQ 1 REL 2F mr 3 BIL rel Branch if IRQ Pin Low lt 2 rel IRQ 0 REL 2E 3 IMM 5 2 DIR B5 dd 3 BIT opr EXT C5 4 IX2 05 jeeff 4 BIT opr X Biles amp 21 7 pq E5 3 BIT X IX F5 2 BIT opr SP SP1 9EE5 4 BIT opr SP SP2 9ED5 5 Branch if Less Than or Equal To er E e BLE opr Signed Operands PC lt PC 2 rel Z NG V 1 REL 93 3 BLO rel Branch if Lower Same as BCS PC lt PC 2 rel C 1 25 3 BLS rel Branch if Lower or Same lt 2 rel 1 2 1 REL 23 3 BLT opr Branch if Less Than S
46. Analog to Digital Converter ADC Signals 17 6 1 ADC Voltage In Vapin VapiN iS the input voltage signal from one of the eight ADC channels to the ADC module 17 6 2 ADC Analog Power Pin VppA The ADC analog portion uses VppA as its power pin Connect the pin to the same voltage potential as Vpp External filtering may be necessary to ensure clean Vppa for good results NOTE Route VppA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package 17 6 3 ADC Analog Ground Pin VssA The ADC analog portion uses as its ground pin Connect the pin to the same voltage potential as Vgc 17 6 4 ADC Voltage Reference High Pin Vpery Vngry is the power supply for setting the reference voltage Varry Connect the pin to the same voltage potential as There will be a finite current associated with Vprry see Section 24 Electrical Specifications NOTE Route carefully for maximum noise immunity and place bypass capacitors as close as possible to the package 17 6 5 ADC Voltage Reference Low Pin is the lower reference supply for the ADC Connect the Vref pin to the same voltage potential as Vssa There will be a finite current associated with Vprr see Section 24 Electrical Specifications MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 353 For More Information On This Product Go to ww
47. Bit 7 6 5 4 3 2 1 Bit 0 Read COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD Write Reset 0 0 0 0 0 0 0 0 Figure 5 2 Configuration Register 1 CONFIG1 COPRS COP Rate Select Bit COPRS selects the COP time out period Reset clears COPRS See Section 21 Computer Operating Properly COP 1 COP time out period 213 2 ICLK cycles 0 COP time out period 218 2 cycles LVISTOP LVI Enable in Stop Mode Bit When the LVIPWRD or LVIREGD bit is clear setting the LVISTOP bit enables the LVI to operate during stop mode Reset clears LVISTOP See Section 22 Low Voltage Inhibit LVI 1 LVI enabled during stop mode 0 LVI disabled during stop mode NOTE IfLVISTOP O set LVIRSTD 1 before entering stop mode LVIRSTD LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module See Section 22 Low Voltage Inhibit LVI 1 LVI module resets disabled LVI module resets enabled MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 67 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Configuration amp Mask Option Registers LVIPWRD Vpp LVI Circuit Disable Bit LVIPWRD disables the Vpp LVI circuit See Section 22 Low Voltage Inhibit LVI 1 Vpp LVI circuit disabled 0 Vpp LVI circuit enabled LVIREGD LVI Circuit Disable Bit LVIREGD disables the LVI circuit See
48. SERIAL SCI R32XCLK COMMUNICATIONS INFRARED INTERFACE MODULE SCI_R16XCLK SUB MODULE BUS CLOCK SCI SCI_RxD SCRxD Figure 14 2 IRSCI Block Diagram The SCI module provides serial data transmission and reception with a programmable baud rate clock based on the bus clock or the CGMXCLK Data Sheet MC68HC908AP Family Rev 2 5 252 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI Infrared Functional Description The infrared sub module receives two clock sources from the SCI module SCI_R16XCLK and 5 R32XCLK Both reference clocks are used to generate the narrow pulses during data transmission The SCI R16XCLK and R32XCLK are internal clocks with frequencies that are 16 and 32 times the baud rate respectively Both SCI_R16XCLK and 5 R32XCLK clocks are used for transmitting data The SCI_R16XCLK clock is used only for receiving data NOTE For proper SCI function transmit or receive the bus clock MUST be programmed to at least 32 times that of the selected baud rate When the infrared sub module is disabled signals on the TxD and RxD pins pass through unchanged to the SCI module 14 5 Infrared Functional Description Figure 14 3 shows the structure of the infrared sub module
49. Serial Communications Interface To verify the start bit and to detect noise data recovery logic takes samples at RT3 RT5 and RT7 Table 13 2 summarizes the results of the start bit verification samples Table 13 2 Start Bit Verification iis Semis id Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 Start bit verification is not successful if any two of the three verification samples are logic 1s If start bit verification is not successful the RT clock is reset and a new search for a start bit begins To determine the value of a data bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 13 3 summarizes the results of the data bit samples Table 13 3 Data Bit Recovery uu NM ET 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 Data Sheet MC68HC908AP Family Rev 2 5 224 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Functional Description NOTE 8 RT9 and RT10 samples do not affect start bit verification If any or all of the RT8 RT9 and RT10 start bit samples are logic 1s following a successful start bit verification the noise flag NF is set and the receiver assumes that the bit is a start bit To verify a stop b
50. Write any data to any FLASH address within the row address range desired y Wait for a time thy Y i Set HVEN bit Y 5 Wait for a time tog n gt Y Write data to the FLASH address to be programmed Y j Wait for a time torog Completed programming this row Y NOTE z Clear PGM bit The time between each FLASH address change step 6 to step 6 or Y the time between the last FLASH address programmed 10 to clearing PGM bit step 6 to step 9 Wait for a time tnv must not exceed the maximum programming time tppoc max Y Clear HVEN bit This row program algorithm assumes the row s to be programmed are initially erased Y Wait for a time Y End of Programming Figure 4 3 FLASH Programming Flowchart MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 61 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FLASH Memory 4 7 FLASH Protection NOTE Due to the ability of the on board charge pump to erase and program the FLASH memory in the target application provision is made to protect pages of memory from unintentional erase or program operations due to system malfunction This protection is done by use of a FLASH block protect register FLBPR The FLBPR determines the range of the FLASH memory which is to be protected The range of the protected area starts from a location defined by FLBPR and ends to the botto
51. 1 for a slave the first edge of the SPSCK indicates the beginning of the transmission This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data Once the transmission begins no new data is allowed into the shift register from the transmit data register Therefore the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK Any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission 15 5 4 Transmission Initiation Latency When the SPI is configured as a master SPMSTR 1 writing to the SPDR starts a transmission CPHA has no effect on the delay to the start of the transmission but it does affect the initial state of the SPSCK signal When CPHA 0 the SPSCK signal remains inactive for the first half of the first SPSCK cycle When CPHA 1 the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level The SPI clock rate selected by SPR1 SPRO0O affects the delay from the write to SPDR and the start of the SPI transmission See Figure 15 7 The internal SPI clock in the master is a free running derivative of the internal MCU clock To conserve power it is enabled only when both the SPE and SPMSTR bits are set SPSCK edges occur halfway through the low time of the internal MCU clock Since the SPI clock is free running it is uncertain w
52. Figure 17 2 ADC Block Diagram Data Sheet MC68HC908AP Family Rev 2 5 348 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC Functional Description 17 3 3 Conversion Time Conversion starts after a write to the ADSCR One conversion will take between 16 and 17 ADC clock cycles therefore 16 to17 ADC cycles ADC frequency Conversion time Number of bus cycles conversion time x bus frequency The ADC conversion time is determined by the clock source chosen and the divide ratio selected The clock source is either the bus clock or CGMXCLK and is selectable by the ADICLK bit located in the ADC clock register The divide ratio is selected by the ADIV 2 0 bits For example if a 4MHz CGMXCLK is selected as the ADC input clock source with a divide by four prescale and the bus speed is set at 2MHz 16 to17 ADC cycles 4MHz 4 Conversion time 16 to 17 us Number of bus cycles 16 us x 2MHz 32 to 34 cycles NOTE ADC frequency must be between minimum and fApjc maximum to meet A D specifications See 24 5 5V DC Electrical Characteristics Since an ADC cycle may be comprised of several bus cycles four in the previous example and the start of a conversion is initiated by a bus cycle write to the ADSCR from zero to four additional bus cycles may occur before the start of the initial ADC cycle This re
53. Figure 20 3 Keyboard Status and Control Register KBSCR KEYF Keyboard Flag Bit This read only bit is set when a keyboard interrupt is pending Reset clears the KEYF bit 1 Keyboard interrupt pending 0 No keyboard interrupt pending ACKK Keyboard Acknowledge Bit Writing a logic 1 to this write only bit clears the keyboard interrupt request ACKK always reads as logic 0 Reset clears ACKK MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 391 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt Module KBI IMASKK Keyboard Interrupt Mask Bit Writing a logic 1 to this read write bit prevents the output of the keyboard interrupt mask from generating interrupt requests Reset clears the IMASKK bit 1 Keyboard interrupt requests masked 0 Keyboard interrupt requests not masked MODEK Keyboard Triggering Sensitivity Bit This read write bit controls the triggering sensitivity of the keyboard interrupt pins Reset clears MODEK 1 Keyboard interrupt requests on falling edges and low levels 0 Keyboard interrupt requests on falling edges only 20 5 2 Keyboard Interrupt Enable Register The port D keyboard interrupt enable register enables or disables each port D pin to operate as a keyboard interrupt pin Address 001B Bit 7 6 5 4 3 2 1 Bit 0 Read KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1
54. HNI L HHSd 2 HNI 2 XHSd 2 2 VHSd 2 vnd 2 L HNI dVL 2 HNI IMS 6 HNI S1H v HNI L dew epoodo 2 9 14 1 Xl 419 Ax 2 ot ac MZ 7 lt X gt lt Xx tr o i E lt lt H lt lt xl Gx SAN 2 1ueuJeJ9u 1504 eig L pexepu LXI 1ueuJeJ9u 1504 J8SHO ON XI OSHO 19 91 JOIUIOd YIS 245 JOSHO 19 8 JIS 45 HNI x419 ER c AOW Y HNI XLSL I 2 2 a 2 vo v XO3N VO3N L HNI I z 911 M lpoj peeu 1 oejs 10 1 y 1 XIG J SHO 19 91 pexepul 1G 8 pexepul 1 5 ON 9 2 O3N v ANI LXI XI dH c 5 uia aa a y um tr Qent zcezc a a or EN a 199 199 5 199 Sod 199 2 N N N N 579
55. IDLE enabled to generate CPU interrupt requests 0 IDLE not enabled to generate CPU interrupt requests TE Transmitter Enable Bit Setting this read write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the TxD pin If software clears the TE bit the transmitter completes any transmission in progress before the TxD returns to the idle condition MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 275 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications logic 1 Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted Reset clears the TE bit 1 Transmitter enabled 0 Transmitter disabled NOTE Writing to the TE bit is not allowed when the enable SCI bit ENSCI is clear ENSCI is in SCI control register 1 RE Receiver Enable Bit Setting this read write bit enables the receiver Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits Reset clears the RE bit 1 Receiver enabled 0 Receiver disabled NOTE Writing to the RE bit is not allowed when the enable SCI bit ENSCI is clear ENSCI is in SCI control register 1 RWU Receiver Wakeup Bit This read write bit puts the receiver in a standby state during which receiver interrupts are disabled The WAKE b
56. IRQ1 Vector High FFFB IRQ1 Vector Low FFFC SWI Vector High i FFFD SWI Vector Low Y FFFE Reset Vector High Highest i FFFF Reset Vector Low MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 51 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Data Sheet MC68HC908AP Family Rev 2 5 52 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 3 Random Access Memory RAM 3 1 Introduction This section describes the 2 048 or 1 024 bytes of RAM 3 2 Functional Description Addresses 0060 through 085F or 045F are RAM locations The location of the stack RAM is programmable The 16 bit stack pointer allows the stack to be anywhere in the 64k byte memory space NOTE For correct operation the stack pointer must point only to RAM locations Within page zero are 160 bytes of RAM Because the location of the stack RAM is programmable all page zero RAM locations can be used for I O control and user data or code When the stack pointer is moved from its reset location at 00FF direct addressing mode instructions can access efficiently all page zero RAM locations Page zero RAM therefore provides ideal locations for frequently accessed global variables Before processing an interrupt the CPU uses five bytes of
57. M 1 IX 7C 3 INC opr SP M lt M 1 SP1 9 6 5 JMP opr DIR BC dd 2 JMP opr EXT CC jhhil 3 JMP opr X Jump PC lt Jump Address 1 2 DC 4 JMP opr X 1 1 EC 3 JMP X IX FC 2 JSR opr PC lt PC n n 1 2 or 3 DIR BD dd 4 JSR opr CD 5 Push PCL SP lt SP 1 JSR opr X Jump to Subroutine IX2 DD 6 Push PCH SP lt SP 1 JUOD PC lt Unconditional Address ee 5 JSR 2 4 LDA opr IMM A6 jii 2 LDA opr DIR B6 dd 3 LDA opr EXT C6 4 LDA opr X IX2 06 jeeff 4 LDA oprX Load A from M lt M 0 1 21 2 xi Ee ff 3 LDA X IX F6 2 LDA opr SP SP1 9EE6 4 LDA opr SP SP2 9ED6 jee ff 5 LDHX stopr 2 _ 45 1 3 LDHX opr Load H X from M H X M M 1 0 DIR 55 ldd 4 LDX opr IMM AE 2 LDX opr DIR dd 3 LDX opr EXT hhll 4 LDX opr X IX2 DE 4 LDX opr X Load X from M X lt M 0 712 xi EE 3 LDX 4 2 LDX opr SP SP1 9EEE 4 LDX opr SP SP2 9EDE eeff 5 LSL opr DIR 38 dd 4 LSLA 4 INH 48 1 LSLX Logical Shift Left 0 SE BB PS ee INH 58 1 LSL opr X Same as ASL b7 bO IX1 68 4 LSL X IX 78 3 LSL opr SP SP1 9E68 ff 5 LSR opr DIR 34 jdd 4 LSRA INH 44 1 LSRX 0 54 1 LSR Logical Shift Right t 0 t xi 64 f 4 LSR X IX 74 3 LSR opr SP SP1 9E64 ff 5 MC68HC908AP Family Rev 2 5 Data Sheet MOT
58. e RSCI infrared control register IRSCIRCR MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 271 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications 14 10 1 IRSCI Control Register 1 SCI control register 1 Enables loop mode operation e Enables the SCI e Controls output polarity e Controls character length e Controls SCI wakeup method e Controls idle character detection e Enables parity function e Controls parity type Address 0040 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 LOOPS ENSCI M WAKE ILTY PEN PTY Write Reset 0 0 0 0 0 0 0 0 Figure 14 12 IRSCI Control Register 1 IRSCC1 LOOPS Loop Mode Select Bit This read write bit enables loop mode operation for the SCI only In loop mode the RxD pin is disconnected from the SCI and the transmitter output goes into the receiver input Both the transmitter and the receiver must be enabled to use loop mode The infrared encoder decoder is not in the loop Reset clears the LOOPS bit 1 Loop mode enabled 0 Normal operation enabled ENSCI Enable SCI Bit This read write bit enables the SCI and the SCI baud rate generator Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts Reset clears the ENSCI bit 1 SCI enabled 0 SCI disabled Data Sheet MC68HC908AP Family Rev 2 5 272
59. 0 OR 0 READ IRSCDR READ IRSCDR READ IRSCDR BYTE 1 BYTE 2 BYTES DELAYED FLAG CLEARING SEQUENCE T T Eu ku 9 BO BO 95 BO 1 2 BYTE 3 4 READ IRSCS1 E READ IRSCS1 E SCRF 1 SCRF 1 OR 0 OR 1 READ IRSCDR READ IRSCDR BYTE 1 BYTE 3 Figure 14 16 Flag Clearing Sequence PE Receiver Parity Error Bit This clearable read only bit is set when the SCI detects a parity error in incoming data PE generates an SCI error CPU interrupt request if the PEIE bit in IRSCC3 is also set Clear the PE bit by reading IRSCS1 with PE set and then reading the IRSCDR Reset clears the PE bit 1 Parity error detected 0 No parity error detected Data Sheet MC68HC908AP Family Rev 2 5 282 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI Registers 14 10 5 IRSCI Status Register 2 IRSCI status register 2 contains flags to signal the following conditions Break character detected Incoming data Address 0044 Bit 7 6 5 4 3 2 1 Bit 0 Read BKF RPF Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 14 17 IRSCI Status Register 2 IRSCS2 BKF Break Flag Bit This clearable read only bit is set when the SCI detects a break character on the RxD pin In IRSCS1 the FE and bits are also set I
60. 01 3 10 4 11 13 SCR2 SCRO0 SCI Baud Rate Select Bits These read write bits select the SCI baud rate divisor as shown in Table 14 8 Reset clears SCR2 SCRO MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 285 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Table 14 8 IRSCI Baud Rate Selection SCR2 SCR1 and SCRO Baud Rate Divisor BD 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Use this formula to calculate the SCI baud rate baud rate where SCI clock source 16 x PD x BD SCI clock source fgus or CGMXCLK selected by CKS bit PD prescaler divisor BD baud rate divisor Table 14 9 shows the SCI baud rates that can be generated with a 4 9152 MHz bus clock when fpys is selected as SCI clock source Data Sheet MC68HC908AP Family Rev 2 5 286 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI I O Registers Table 14 9 IRSCI Baud Rate Selection Examples SCP1 and Prescaler SCR2 SCR1 Baud Rate Baud Rate SCPO Divisor PD and SCRO Divisor BD fgus 4 9152 MHz 00 1 000 1 00 1 001 2 00 1 010 4
61. 413 2 r START TXINV PEN PARITY PTY GENERATION T8 DMATE DMATE LOAD FROM SCDR SCTE SCTE DMATE P SCTE SCTIE SCTIE TC TC TCIE SHIFT ENABLE PREAMBLE ALL 1s BREAK ALL 0s TRANSMITTER CONTROL LOGIC SBK LOOPS ENSCI Figure 13 4 SCI Transmitter MC68HC908AP Family Rev 2 5 TE TxD Data Sheet MOTOROLA For More Information On This Product Go to www freescale com 217 Freescale Semiconductor Inc Serial Communications Interface 13 42 1 Character Length The transmitter can accommodate either 8 bit or 9 bit data The state of the M bit in SCI control register 1 SCC1 determines character length When transmitting 9 bit data bit T8 SCI control register SCC3 is the ninth bit bit 8 13422 Character Transmission Data Sheet During an SCI transmission the transmit shift register shifts a character out to the TxD pin The SCI data register SCDR is the write only buffer between the internal data bus and the transmit shift register To initiate an SCI transmission 1 Enable the SCI by writing a logic 1 to the enable SCI bit ENSCI in SCI control register 1 SCC1 2 Enable the transmitter by writing a logic 1 to the transmitter enable bit TE in SCI control r
62. A mode fault in a master SPI causes the following events to occur e f ERRIE 1 the SPI generates an SPI receiver error CPU interrupt request SPE bit is cleared e The SPTE bit is set e SPI state counter is cleared e The data direction register of the shared I O port regains control of port drivers To prevent bus contention with another master SPI after a mode fault error clear all SPI bits of the data direction register of the shared I O port before enabling the SPI When configured as a slave SPMSTR 0 the MODF flag is set if SS goes high during a transmission When CPHA 0 a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of the eighth data bit When CPHA 1 the transmission begins when the SPSCK leaves its idle level and SS is already low The transmission continues until the SPSCK returns to its idle level following the shift of the last data bit See 15 5 Transmission Formats Setting the MODF flag does not clear the SPMSTR bit The SPMSTR bit has no function when SPE 0 Reading SPMSTR when MODF 1 shows the difference between a MODF occurring when the SPI is a master and when it is a slave When CPHA 0 a MODF occurs if a slave is selected SS is at logic 0 and later unselected SS is at logic 1 even if no SPSCK is sent to that MC68HC908AP Family Rev 2 5 304 MOTOROLA For More Information On This Pr
63. ELS1A TOVI 0033 and Control Register Write 0 T2SC1 Reset 0 0 0 0 0 0 0 0 Read Timer 2 Channel 1 Bit 15 14 13 12 11 10 9 Bit 8 0034 Register High Write T2CH1H Reset Indeterminate after reset Read Timer 2 Channel 1 Bit 7 6 5 4 3 2 1 Bit 0 0035 Register Low Write T2CH1L Reset Indeterminate after reset 11 4 1 TIM Counter Prescaler 11 4 2 Input Capture Data Sheet Unimplemented Figure 11 2 TIM I O Register Summary Sheet 3 of 3 The TIM clock source can be one of the seven prescaler outputs The prescaler generates seven clock rates from the internal bus clock The prescaler select bits PS 2 0 in the TIM status and control register select the TIM clock source With the input capture function the TIM can capture the time at which an external event occurs When an active edge occurs on the pin of an input capture channel the TIM latches the contents of the TIM counter into the TIM channel registers TCHxH TCHXxL The polarity of the active edge is programmable Input captures can generate TIM CPU interrupt requests MC68HC908AP Family Rev 2 5 186 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Timer Interface Module TIM Functional Description 11 4 3 Output Compare With the output compare function the TIM can generate a periodic pulse with a programmable polarity duration and freq
64. IONS S AND V LANE DIMENSIONS A AND DO NOT INCLUDE MOLD O BE DETERMINED AT O BE DETERMINED A PROTRUSION ALLOWABLE PROTRUSION IS 0 25 0 010 PER SIDE DIMENSIONS A AND B DO NCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08 0 003 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9 90 10 10 0 390 0 398 B 9 90 10 10 0 390 0 398 2 10 2 45 0 083 0 096 D 0 30 0 45 0 012 0 018 E 2 00 2 10 0 079 0 083 F 0 30 0 40 0 012 0 016 G 0 80 BSC 0 031 BSC H 0 25 0 010 J 0 13 0 23 0 005 0 009 K 0 65 0 95 0 026 0 037 L 8 00 REF 0 315 REF M 5 10 5 10 N 0 18 0 17 0 005 0 007 Q 0 0 a R 0 13 0 30 0 005 0 012 S 12 95 1345 0 510 0 530 T 0 18 0 005 U 0 0 V 1295 13 45 0 510 0 530 0 40 0 016 X 1 6 REF 0 063 REF Figure 25 2 44 Pin QFP Case 824A MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mechanical Specifications 25 4 42 Pin Shrink Dual In Line Package SDIP
65. SPI SPMSTR SPI Master Bit This read write bit selects master mode operation or slave mode operation Reset sets the SPMSTR bit 1 Master mode 0 Slave mode CPOL Clock Polarity Bit This read write bit determines the logic state of the SPSCK pin between transmissions See Figure 15 4 and Figure 15 6 To transmit data between SPI modules the SPI modules must have identical CPOL values Reset clears the CPOL bit CPHA Clock Phase Bit This read write bit controls the timing relationship between the serial clock and SPI data See Figure 15 4 and Figure 15 6 To transmit data between SPI modules the SPI modules must have identical CPHA values When CPHA 0 the SS pin of the slave SPI module must be set to logic 1 between bytes See Figure 15 12 Reset sets the CPHA bit SPWOM SPI Wired OR Mode Bit This read write bit disables the pullup devices on pins SPSCK MOSI and MISO so that those pins become open drain outputs 1 Wired OR SPSCK MOSI and MISO pins 0 Normal push pull SPSCK MOSI and MISO pins SPE SPI Enable This read write bit enables the SPI module Clearing SPE causes a partial reset of the SPI See 15 9 Resetting the SPI Reset clears the SPE bit 1 SPI module enabled 0 SPI module disabled SPTIE SPI Transmit Interrupt Enable This read write bit enables CPU interrupt requests generated by the SPTE bit SPTE is set when a byte transfers from the transmit data regi
66. The port A data register contains a data latch for each of the eight port A pins Address 0000 Bit 7 6 5 4 3 2 1 Bit 0 Read PTA7 5 PTA4 PTA2 PTA1 PTAO Write Reset Unaffected by reset Alternative Function A ADC7 ADC6 ADC5 ADCA ADC3 ADC2 ADC1 ADCO Additional Function LED drive LED drive LED drive LED drive LED drive LED drive LED drive LED drive Figure 18 2 Port A Data Register PTA PTA 7 0 Port A Data Bits These read write bits are software programmable Data direction of each port A pin is under the control of the corresponding bit in data direction register A Reset has no effect on port A data ADC7 ADCO ADC Channels 7 to 0 ADC7 ADCO are pins used for the input channels to the analog to digital converter module The channel select bits ADCH 4 0 in the ADC status and control register define which port pin will be used as an ADC input and overrides any control from the port I O logic NOTE must be taken when reading port A while applying analog voltages to ADC7 ADCO pins If the appropriate ADC channel is not enabled excessive current drain may occur if analog voltages are applied to the PTAx ADCx pin while PTA is read as a digital input Those ports not selected as analog input channels are considered digital I O ports Data Sheet MC68HC908AP Family Rev 2 5 366 MOTOROLA For More Information On This Pro
67. WRITE DDRD 0007 71 e DDRDx 2 RESET lt Ec 5 WRITE 0003 5 PTDx PTDx READ PTD 0003 rat PTD7 PTDO have schmitt trigger inputs Figure 18 14 Port D I O Circuit MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 377 For More Information On This Product Go to www freescale com Data Sheet Freescale Semiconductor Inc Input Output Ports When bit DDRDx is a logic 1 reading address 0003 reads the PTDx data latch When bit DDRDx is a logic 0 reading address 0003 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 18 5 summarizes the operation of the port D pins Table 18 5 Port D Pin Functions Accesses to DDRD Accesses to PTD DDRD FTD 1 0 Pin Mode Read Write Read Write 0 X Input Hi Z DDRDI7 0 Pin FEM 1 X Output DDRD 7 0 PTD 7 0 PTD 7 0 Notes 1 X don t care 2 Hi Z high impedance 3 Writing affects data register but does not affect input MC68HC908AP Family Rev 2 5 378 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 19 External Interrupt IRQ 19 1 Introduction The external interrupt IRQ module provides two maskable interrupt inputs IRQ1 and IRQ2 19 2 Features Features of the IRQ module inclu
68. ah ia PTB7 T2CHI PTB6 T2CHO MONITOR ROM 959 BYTES PTBS T1CH1 2 CHANNEL TIMER INTERFACE Ke em PTB4 T1CHO ea a T t USERFLASHVECTORSPACE 48BYTES MODULE Z aje diis X PTB1 SCL t OSCILLATORS AND SERIAL COMMUNICATIONS PTBO SDA f CLOCK GENERATOR MODULE INTERFACE MODULE 1 INTERNAL OSCILLATOR E X RC OSCILLATOR MULTI MASTER IIC SMBUS PTC6 SCTxD 1 OSC1 INTERFACE MODULE K PTC5 SPSCK OSC2 X TAL OSCILLATOR e PTCA SS PHASE LOCKED LOOP PTC3 MOSI CGMXFC SERIAL COMMUNICATIONS PTC2MISO INTERFACE MODULE 2 WITH INFRARED oer SYSTEM INTEGRATION MODULATOR DEMODULATOR PTCO IRQ2 RST MODULE SERIAL PERIPHERAL SEN TROT eae INTERFACE MODULE des ce ok a ee e E PTD4 KBI4 n COMPUTER OPERATING KEYBOARD INTERRUPT dub ale PTD3 KBI3 PROPERLY MODULE MODULE PTD2 KBI2 PTD1 KBI PTDO KBIO S LOW VOLTAGE INHIBIT MODULE VDD VDDA Pin contains integrated pullup device VSS Pin contains configurable pullup device VSSA Pin contains integrated pullup device when configured as KBI VREG t Pin is open drain when configured as output LED direct sink pin ADC REFERENCE Pin not bonded on 42 pin SDIP USER RAM USER FLASH DEVICE bytes bytes MC68HC908AP64 2 048 62 368 MC68HC908AP32 2 048 32 768 MC68HC908AP 16 1 024 16 384 MC68HC908AP8 1 024 8 192 Figure 1 1 MC68HC908AP64 Block Diagram Data Sheet MC68HC908AP Family Rev 2 5 26 MOTOROLA For More Information On This Produ
69. slave MCU the SPSCK pin is the clock input In full duplex operation the master and slave MCUs exchange a byte of data in eight serial clock cycles When enabled the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I O port 15 12 4 SS Slave Select The SS pin has various functions depending on the current state of the SPI For an SPI configured as a slave the SS is used to select a slave For CPHA 0 the SS is used to define the start of a transmission See 15 5 Transmission Formats Since it is used to indicate the start of a transmission the SS must be toggled high and low between each byte transmitted for the CPHA 0 format However it can remain low between transmissions for the CPHA 1 format See Figure 15 12 MISO MOSI y BYTE 1 2 i BYTE 3 MASTERSS _ BASE SLAVE SS CPHA 1 Figure 15 12 CPHA SS Timing When an SPI is configured as a slave the SS pin is always configured as an input It cannot be used as a general purpose I O regardless of the state of the MODFEN control bit However the MODFEN bit can still prevent the state of the SS from creating a MODF error See 15 13 2 SPI Status and Control Register NOTE Alogic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state The slave SPI ignores all incoming SPSCK clocks even if it was already in the middle of a transmissi
70. www freescale com Freescale Semiconductor Inc Memory Map Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0050 Reserved Write Reset Timebase Control Read TBIF 0 Register m TBR2 TBR1 TBRO TACK TBIE TBON R TBCR Reset 0 0 0 0 0 0 0 0 Read 0052 Unimplemented Write Reset Read 0053 Unimplemented Write Reset Read 0054 Unimplemented Write Reset Read 0055 Unimplemented Write Reset Read 0056 Unimplemented Write Reset ADC Status and Control 8640 COCO Aen anco ADCH3 ADCH2 ADCHO 0057 Register Write ADSCR Reset 0 0 0 1 1 1 1 1 ADC Clock Control P anvi ApicLK MODE moneo _ i 0058 Register Write R ADICLK Reset 0 0 0 0 0 0 0 0 Read ADx ADx ADx ADx ADx ADx ADx Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 U Unaffected X Indeterminate Unimplemented R Reserved 0051 ADC Data Register High 0 ADRHO 0059 Figure 2 2 Control Status and Data Registers Sheet 9 of 12 Data Sheet MC68HC908AP Family Rev 2 5 46 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Input Output I O Section
71. 0 05 2 gt mm BA FFE 2 o O aa Figure 1 3 44 QFP Pin Assignments Data Sheet MC68HC908AP Family Rev 2 5 28 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description Pin Assignment PTD2 KBI2 1 VDDA PTD1 KBI1 2 VSSA PTDO KBIO 3 PTD3 KBI3 PTB7 T2CH1 4 PTD4 KBI4 CGMXFC 5 PTD5 KBI5 PTB6 T2CHO 6 PTD6 KBI6 VREG 7 PTD7 KBI7 PTB5 T1CH1 8 VREFH VDD 9 VREFL OSC1 10 PTAO ADCO OSC2 11 PTA1 ADC1 vss 12 PTA2 ADC2 PTB4 T1CHO 13 PTA3 ADC3 IRQI 14 PTA4 ADC4 PTB3 RxD 15 PTA5 ADC5 RST 16 PTA6 ADC6 PTB2 TxD 17 PTA7 ADC7 PTB1 SCL 18 PTC2 MISO PTBO SDA 19 PTC3 MOSI PTC7 SCRxD 20 4 65 PTC6 SCTxD 21 PTC5 SPSCK Pins not available on 42 pin package Internal connection PTCO IRQ2 Unconnected PTC1 Unconnected Figure 1 4 42 Pin SDIP Pin Assignment MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description 1 5 Pin Functions Description of the pin functions are provided in Table 1 2 Table 1 2 Pin Functions VOLTAGE PIN NAME PIN DESCRIPTION IN OUT LEVEL 4 5 to 5 5 Vpp Power supply In or 2 7 to 3 3 Vss Power supply ground Out OV VppA Powe
72. 0 IRQ2 pin internal pullup is enabled IRQ2F IRQ2 Flag Bit This read only status bit is high when the IRQ2 interrupt is pending 1 IRQ2 interrupt pending 0 IRQ2 interrupt not pending ACK2 IRQ2 Interrupt Request Acknowledge Bit Writing a logic 1 to this write only bit clears the IRQ2 latch ACK2 always reads as logic 0 Reset clears ACK2 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 385 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ IMASK2 IRQ2 Interrupt Mask Bit Writing a logic 1 to this read write bit disables IRQ2 interrupt requests Reset clears IMASK2 1 IRQ2 interrupt requests disabled 0 IRQ2 interrupt requests enabled MODE2 IRQ2 Edge Level Select Bit This read write bit controls the triggering sensitivity of the IRQ2 pin Reset clears MODE2 1 IRQ2 interrupt requests on falling edges and low levels 0 IRQ2 interrupt requests on falling edges only Data Sheet MC68HC908AP Family Rev 2 5 386 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 20 Keyboard Interrupt Module KBI 20 1 Introduction The keyboard interrupt module KBI provides eight independently maskable external interrupts which are accessible via PTDO PTD7 When a port pin is enabled for keyboard interrupt function an i
73. 0 2 V from rail no dc loads less than 100 pF on all outputs C 20 pF on 2 all ports configured as inputs OSC2 capacitance linearly affects wait Ipp STOP Ipp measured using external 32 768kHz clock to OSC1 no port pins sourcing current STOP Ipp measured with OSC1 grounded no port pins sourcing current Maximum is highest voltage that POR is guaranteed The rearm voltage is triggered by VREG If minimum Vpp is not reached before the internal POR reset is released RST must be driven low externally until minimum Vpp is reached Rpu4 and are measured at Vpp 5 0V 10 Values are not affected by operating Vpp they are the same for 3V and 5V 11 Measured from Vpp Min to 5 5 V Data Sheet MC68HC908AP Family Rev 2 5 418 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 24 6 5V Control Timing Table 24 5 Control Timing 5V Electrical Specifications 5V Control Timing Characteristic Symbol Min Max Unit Internal operating frequency fop 8 MHz RST input pulse width low tin 750 ns Notes 1 4 5 to 5 5 Vdc Vss 0 timing shown with respect to 20 Vpp 70 Vpp unless otherwise noted 2 Some modules may require a minimum frequency greater than dc for proper operation see appropriate table for this information 3 Minimum pulse width reset is guaranteed to
74. 13 5 Low Power Modes 13 5 1 Wait Mode 13 5 2 Stop Mode The WAIT and STOP instructions put the MCU in low power consumption standby modes The SCI module remains active after the execution of a WAIT instruction In wait mode the SCI module registers are not accessible by the CPU Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode If SCI module functions are not required during wait mode reduce power consumption by disabling the module before executing the WAIT instruction Refer to 9 6 Low Power Modes for information on exiting wait mode The SCI module is inactive after the execution of a STOP instruction The STOP instruction does not affect SCI register states SCI module operation resumes after an external interrupt Because the internal clock is inactive during stop mode entering stop mode during an SCI transmission or reception results in invalid data Refer to 9 6 Low Power Modes for information on exiting stop mode 13 6 SCI During Break Module Interrupts Data Sheet The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state To allow software to clear status bits during a break interrupt write a logic 1 to the BCFE bit If a status bit is cleared during the break state it remains cleared when
75. 16 6 2 MMIIC Control Register 1 MMCR1 Address 0049 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 MMEN MMIEN MMTXAK REPSEN MMCRCBYTE Write MMCLRBB Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 16 5 MMIIC Control Register 1 MMCR1 MMEN MMIIC Enable This bit is set to enable the Multi master IIC module When MMEN 0 module is disabled and all flags will restore to its power on default states Reset clears this bit 1 MMIIC module enabled 0 MMIIC module disabled MMIEN MMIIC Interrupt Enable When this bit is set the MMTXIF MMRXIF MMALIF and MMNAKIF flags are enabled to generate an interrupt request to the CPU When MMIEN is cleared the these flags are prevented from generating an interrupt request Reset clears this bit 1 MMTXIF MMRXIF MMALIF and or MMNAKIF bit set will generate interrupt request to CPU MMTXIF MMRXIF MMALIF and or MMNAKIF bit set will not generate interrupt request to CPU MMCLRBB MMIIC Clear Busy Flag Writing a logic 1 to this write only bit clears the MMBB flag MMCLRBB always reads as a logic 0 Reset clears this bit 1 Clear MMBB flag 0 No affect on MMBB flag Data Sheet MC68HC908AP Family Rev 2 5 328 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC MMIIC Registers MMTXAK MMIIC Transmit Acknowledge Enable Th
76. 2 SCC2 SCTIE SCI Transmit Interrupt Enable Bit This read write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests Reset clears the SCTIE bit 1 SCTE enabled to generate CPU interrupt 0 SCTE not enabled to generate CPU interrupt TCIE Transmission Complete Interrupt Enable Bit This read write bit enables the TC bit to generate SCI transmitter CPU interrupt requests Reset clears the TCIE bit 1 TC enabled to generate CPU interrupt requests 0 TC not enabled to generate CPU interrupt requests SCRIE SCI Receive Interrupt Enable Bit This read write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests Reset clears the SCRIE bit 1 SCRF enabled to generate CPU interrupt 0 SCRF not enabled to generate CPU interrupt ILIE Idle Line Interrupt Enable Bit This read write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests Reset clears the ILIE bit 1 IDLE enabled to generate CPU interrupt requests 0 IDLE not enabled to generate CPU interrupt requests TE Transmitter Enable Bit Setting this read write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the TxD pin If software clears the TE bit the transmitter completes any transmission in progress before the TxD returns to the idle condition Data Sheet MC68HC908AP Family Rev 2 5 236 MOTOROLA For More Informatio
77. 2 1 Bit 0 0035 Register Low Write T2CH1L Reset Indeterminate after reset Brad PLLIE peer PLLON BCS PRE1 PREO VPR1 VPRO PLL Control Register 0036 PCTL Write Reset 0 0 1 0 0 0 0 0 PLL Bandwidth Control Read AUTO LOCK ACO 0 0 0 0 R 0037 Register Write PBWC Reset 0 0 0 0 0 0 0 0 Read 0 0 0 0 PLL Multiplier Select MUL11 MUL10 MUL9 MUL8 0038 Register High Write PMSH Reset 0 0 0 0 0 0 0 0 PLL Multiplier Select 1980 MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MULO 0039 Register Low Write PMSD poset 0 0 0 0 0 0 0 PLL VCO Range Select 1930 Sngde oelec VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRSO 003A Register Write PMRS Reset 0 0 0 0 0 0 0 PLL Reference Divider Read 0 0 0 0 RDS3 RDS2 RDS1 RDSO 003B Select Register Write PMDS Reset 0 0 0 0 0 0 0 1 U Unaffected X Indeterminate Unimplemented R Reserved Figure 2 2 Control Status and Data Registers Sheet 6 of 12 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 43 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 003C Unimplemented Write Reset Read 003D Unimplemented Write Reset Read 003E Unimplemented Write Reset
78. 76800 00 1 011 8 38400 00 1 100 16 19200 00 1 101 32 9600 00 1 110 64 4800 00 1 111 128 2400 01 3 000 1 01 3 001 2 51200 01 3 010 4 25600 01 3 011 8 12800 01 3 100 16 6400 01 3 101 32 3200 01 3 110 64 1600 01 3 111 128 800 10 4 000 1 76800 10 4 001 2 38400 10 4 010 4 19200 10 4 011 8 9600 10 4 100 16 4800 10 4 101 32 2400 10 4 110 64 1200 10 4 111 128 600 11 13 000 1 23632 11 13 001 2 11816 11 13 010 4 5908 11 13 011 8 2954 11 13 100 16 1477 11 13 101 32 739 11 13 110 64 369 11 13 111 128 185 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 287 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications 14 10 8 IRSCI Infrared Control Register The infrared control register contains the control bits for the infrared sub module e Enables the infrared sub module e Selects the infrared transmitter narrow pulse width Address 0047 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 R R TNP1 TNPO IREN Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 14 20 IRSCI Infrared Control Register IRSCIRCR TNP1 and TNPO Transmitter Narrow Pulse Bits These read write bits select the infrared transmitter narrow pulse width as shown in Table 14 10 Reset clears TNP1 and TNPO Table 14 10 Infrared Narrow Pulse Selection TNP1 and TNPO Prescaler Divisor PD 00 SCI t
79. AUTO 0 PLLF and LOCK read as clear 3 When AUTO 1 ACQ is read only 4 When PLLON 0 or VRS7 VRSO 0 BCS is forced clear and is read only 5 When PLLON 1 the PLL programming register is read only 6 When BCS 1 PLLON is forced set and is read only Figure 8 2 CGM I O Register Summary Data Sheet MC68HC908AP Family Rev 2 5 104 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Functional Description 8 3 1 Oscillator Module The oscillator module provides two clock outputs CGMXCLK and CGMRCLK to the CGM module CGMXCLK when selected is driven to SIM module to generate the system bus clock CGMRCLK is used by the phase lock loop to provide a higher frequency system bus clock The oscillator module also provides the reference clock for the timebase module TBM See Section 7 Oscillator OSC for detailed oscillator circuit description See Section 12 Timebase Module TBM for detailed description on TBM 8 3 2 Phase Locked Loop Circuit PLL 8 3 3 PLL Circuits The PLL is a frequency generator that can operate in either acquisition mode or tracking mode depending on the accuracy of the output frequency The PLL can change between acquisition and tracking modes either automatically or manually The PLL consists of these circuits Voltage controlled oscillator VCO e Reference divider e Frequency pre
80. All control bits in the SPSCR register MODFEN ERRIE SPR1 and SPRO e The status flags SPRF OVRF and MODF By not resetting the control bits when SPE is low the user can clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 307 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI By not resetting the SPRF OVRF and MODF flags the user can still service these interrupts after the SPI has been disabled The user can disable the SPI by writing O to the SPE bit The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set 15 10 Low Power Modes 15 10 1 Wait Mode 15 10 2 Stop Mode Data Sheet The WAIT and STOP instructions put the MCU in low power consumption standby modes The SPI module remains active after the execution of a WAIT instruction In wait mode the SPI module registers are not accessible by the CPU Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode If SPI module functions are not required during wait mode reduce power consumption by disabling the SPI module before executing the WAIT instruction To exit wait mode when an overflow condition occurs enable the OVRF bit to generate CPU inter
81. Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 SCP1 SCPO R SCR2 SCR1 SCRO Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 13 16 SCI Baud Rate Register SCBR SCP1 and SCPO SCI Baud Rate Prescaler Bits These read write bits select the baud rate prescaler divisor as shown in Table 13 6 Reset clears SCP1 and SCPO Table 13 6 SCI Baud Rate Prescaling SCP1 and SCPO Prescaler Divisor PD 00 1 01 3 10 4 11 13 SCR2 SCRO0 SCI Baud Rate Select Bits These read write bits select the SCI baud rate divisor as shown in Table 13 7 Reset clears SCR2 SCRO Data Sheet MC68HC908AP Family Rev 2 5 246 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Registers Table 13 7 SCI Baud Rate Selection SCR2 SCR1 and SCRO Baud Rate Divisor BD 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Use this formula to calculate the SCI baud rate SCI clock source baud rate 54x PD BD where SCI clock source fgys or CGMXCLK selected by SCIBDSRC bit in CONFIG2 register PD prescaler divisor BD baud rate divisor Table 13 8 shows the SCI baud rates that can be generated with a 4 9152 MHz bus clock when fpys is selected as SCI clock source MC68HC908AP Family Rev 2 5 Data Sheet 247 For More I
82. Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset Figure 11 13 TIM Channel 0 Register Low TCHOL Address T1CH1H 0029 and T2CH1H 0034 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset Figure 11 14 TIM Channel 1 Register High TCH1H Address T1CH1L 002A and T2CH1L 0035 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset Figure 11 15 TIM Channel 1 Register Low TCH1L MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 203 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module Data Sheet MC68HC908AP Family Rev 2 5 204 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 12 Timebase Module TBM 12 1 Introduction This section describes the timebase module TBM The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the selected OSCCLK clock from the oscillator module This TBM version uses 18 divider stages eight of which are user selectable 12 2 Features Features of the TBM module include Software programmable 8s 45 2s 1s 2ms 1ms 0 5ms and 0 25ms periodic interrupt using 32 768 kHz OSCCLK clock e Use
83. COP will be disabled In the latter situation after VrsT is applied to the RST can be removed from the IRQ1 pin in the interest of freeing the IRQ1 for normal functionality in monitor mode Figure 10 2 shows a simplified diagram of the monitor mode entry when the reset vector is blank and just Vpp voltage is applied to the IRQ1 pin An external oscillator of 9 8304 MHz is required for a baud rate of 9600 as the internal bus frequency is automatically set to the external frequency divided by four Enter monitor mode with pin configuration shown in Figure 10 1 by pulling RST low and then high The rising edge of RST latches monitor mode Once monitor mode is latched the values on the specified pins can change Once out of reset the MCU waits for the host to send eight security bytes See 10 4 Security After the security bytes the MCU sends a break signal 10 consecutive logic O s to the host indicating that it is ready to receive a command MC68HC908AP Family Rev 2 5 158 MOTOROLA For More Information On This Product Go to www freescale com NOTE Freescale Semiconductor Inc POR RESET IS VECTOR BLANK YES MONITOR MODE EXECUTE MONITOR Monitor ROM MON Functional Description NORMAL USER MODE Figure 10 2 Low Voltage Monitor Mode Entry Flowchart In monitor mode the MCU uses different vectors for r
84. During Break Interrupts 309 FO SIIAS rrr 309 15 12 1 MISO Master In Slave 310 15 12 2 MOSI Master Out Slave 1 310 1512 39 BPSOK Senal CICK os iin tees dees eR cade ewan 311 1512 4 311 1512 5 COND Clock 312 1513 a E ae ke sey 313 1539 31 SPI Control 5 313 15 13 2 SPI Status and Control Register 315 15133 SPI chee edie 318 MC68HC908AP Family Rev 2 5 16 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Section 16 Multi Master Interface MMIIC 5 319 IRE DERNIER 44522225535 dw bar og ae ios 320 mE S esa dn b 320 16 4 Multi Master System Configuration 322 16 5 Multi Master Bus 322 1851 START SONA 323 16 5 2 Slave Address Transmission 323 16 5 3 Data Transfer 323 16 5 4 Repeated START 510 324 1655 262430 ee PDIeY4 22 hose dicte 324 16 5 6 Arbitration 324 16 5 7 Clock
85. Family Rev 2 5 10 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 9 3 2 Active Resets from Internal Sources 134 9 3 2 1 Power On Reset 135 9 3 2 2 Computer Operating Properly COP 136 9 3 2 3 Illegal Opcode 137 9 3 2 4 legal Address 137 9 3 2 5 Low Voltage Inhibit LVI 137 9 3 2 6 Monitor Mode Entry Module Reset 137 BA V UG ee Re Fd p Rok aco d ee dica 138 9 4 1 SIM Counter During Power On Reset 138 9 4 2 SIM Counter During Stop Mode Recovery 138 9 4 3 SIM Counter and Reset 138 9 5 Exception 139 9 5 1 P a EA ere E SAEN T E T 139 9 5 1 1 Hardware 1 141 9 5 1 2 SWI Instruction naana aana 142 9 5 1 3 Interrupt Status Registers 142 9 5 1 4 Interrupt Status 1 142 9 5 1 5 Interrupt Status 2 144 9 5 1 8 Interrupt Status Register 3 144 9 5 2 DESEE eee ee EX EROR eee ee GU HERREN AER ER 145 9 5 3 Break Interrupts 145
86. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI SCI Functional Description 14 6 23 Break Characters Writing a logic 1 to the send break bit SBK in IRSCC2 loads the transmit shift register with a break character A break character contains all logic Os and has no start stop or parity bit Break character length depends on the M bit in IRSCC1 As long as SBK is at logic 1 transmitter logic continuously loads break characters into the transmit shift register After software clears the SBK bit the shift register finishes transmitting the last break character and then transmits at least one logic 1 The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic O where the stop bit should be Receiving a break character has the following effects on SCI registers e Sets the framing error bit FE in IRSCS1 e Sets the SCI receiver full bit SCRF in IRSCS1 e Clears the SCI data register IRSCDR e Clears the R8 bit in IRSCC3 e Sets the break flag bit BKF in IRSCS2 May set the overrun OR noise flag NF parity error PE or reception in progress flag RPF bits 14 6 2 4 ldle Characters An idle character contains all logic 1s and has no start stop or
87. Freescale Semiconductor Inc Table of Contents Data Sheet Section 17 Analog to Digital Converter ADC Seb bote od dci doi det AARRE E 345 exl PTT 345 17 3 Functional Description 347 17 8 1 ADG Pont VO PINS conser doi dod d gd E EUR OR ID CI dea 347 17 3 2 Voltage Conversion 347 17 3 3 Conversion Time 349 17 3 4 Continuous Conversion 349 17 3 5 5 MOOR coe oe 350 17 3 6 Result 350 17 3 7 Data Register Interlocking 351 173 8 MONDIODIDIN cad de 351 IP s 0U 352 172 Low Power NOSE 352 17 5 1 Wait Mode Ln uas aud aco det diede esca ne eee e dett 352 17 5 2 Slop D rrrReRR 352 hom FO SNAS Lied ies apatite N 352 17 6 1 ADC Voltage In Vari 353 17 5 8 ADC Analog Power Pin 353 17 6 3 Analog Ground Pin 353 17 6 4 ADC Voltage Reference High Pin 353 17 6 5 ADC Voltage Reference Low Pin 353 17 7 VO Register 2 ceideoscevcuceeestiesddarccecss 354 17 7 1 ADC Status and Control Register 354 17 7 2 ADC Clock Control Register 356 17 7 3 ADC D
88. Module SCI 13 1 Introduction The MC68HC908AP64 has two SCI modules e is a standard SCI module and e SCI2isan infrared SCI module This section describes 5 1 the serial communications interface SCI module which allows high speed asynchronous communications with peripheral devices and other MCUs NOTE When the SCI is enabled the TxD is an open drain output and requires a pullup resistor to be connected for proper SCI operation NOTE References to DMA direct memory access and associated functions are only valid if the MCU has a DMA module This MCU does not have the DMA function Any DMA related register bits should be left in their reset state for normal MCU operation MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 211 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface 13 2 Features Features of the SCI module include the following Data Sheet Full duplex operation Standard mark space non return to zero NRZ format 32 programmable baud rates Programmable 8 bit or 9 bit character length Separately enabled transmitter and receiver Separate receiver and transmitter CPU interrupt requests Programmable transmitter output polarity Two receiver wakeup methods Idle line wakeup Address mark wakeup Interrupt driven operation with eight interrupt flags Transmitter empty Transmission compl
89. More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Special Modes 8 7 2 Stop Mode The STOP instruction disables the PLL analog circuits and no clock will be driven out of the VCO When entering stop mode with the VCO clock CGMPCLK selected before executing the STOP instruction 1 Setthe oscillator stop mode enable bit STOP XCLKEN in CONFIG2 if continuos clock is required in stop mode 2 Clear the BCS bit to select CGMXCLK as CGMOUT On exit from stop mode 1 Setthe PLLON bit if cleared before entering stop mode 2 Waitfor PLL to lock by checking the LOCK bit 3 Set BCS bit to select CGMPCLK as CGMOUT 8 7 3 CGM During Break Interrupts The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state See 9 7 3 SIM Break Flag Control Register To allow software to clear status bits during a break interrupt write a logic 1 to the BCFE bit If a status bit is cleared during the break state it remains cleared when the MCU exits the break state To protect the PLLF bit during the break state write a logic O to the BCFE bit With BCFE at logic O its default state software can read and write the PLL control register during the break state without affecting the PLLF bit M
90. PTA4 ADC4 5 DDRAS5 PTA5 ADC5 6 DDRA6 PTA6 ADC6 7 DDRA7 PTA7 ADC7 0 DDRBO PTBO SDAU MBUS 1 0049 MMEN 1 DDRB1 PTB1 SCLU 2 DDRB2 PTB2 TxD SCI SCC1 0013 ENSCI 3 DDRB3 PTB3 RxD 4 DDRB4 EM T1SCO 0025 ELSOB ELSOA 4 1 0 2 5 DDRB5 T1SC1 0028 ELS1B ELS1A PTB5 T1CH10 6 DDRB6 S 25 0 0030 ELSOB ELSOA PTBe T2CHO0 2 7 DDRB7 T2SC1 0033 ELS1B ELS1A PTB7 T2CH10 0 DDRCO IRQ2 INTSCR2 001C IMASK2 2 2 1 DDRC1 PTC1 2 DDRC2 PTC2 MISO 3 DDRC3 PTC3 MOSI C SPI SPCR 0010 SPE 4 DDRC4 PTC4 SS 5 DDRC5 PTC5 SPSCK 6 DDRC6 PTC6 SCTxD IRSCI IRSCC1 0040 ENSCI 7 DDRC7 PTC7 SCRxD 0 DDRDO KBIEO PTDO KBIO 1 DDRD1 KBIE1 PTD1 KBI1 2 2 DDRD2 KBIE2 2 2 2 3 DDRD3 KBIE3 PTD3 KBI3 2 D KBI KBIER 001B 5 4 DDRD4 KBIE4 PTD4 KBl4 5 DDRD5 5 PTD5 KBI5 6 DDRD6 KBIE6 PTD6 KBI6 7 DDRD7 KBIE7 PTD7 KBI7 Notes 1 Pin is open drain when configured as output Pullup resistor must be connected when configured as output 2 Pin has schmitt trigger when configured as input MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 365 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports 18 2 PortA Port A is an 8 bit special function port that shares all of its pins with the analog to digital converter ADC module Port A pins also have LED direct drive capability 18 2 1 Port A Data Register PTA
91. Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI NOTE When the master SPI starts a transmission the data in the slave shift register begins shifting out on the MISO pin The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission Otherwise the byte already in the slave shift register shifts out on the MISO pin Data written to the slave shift register during a transmission remains in a buffer until the end of the transmission When the clock phase bit CPHA is set the first edge of SPSCK starts a transmission When CPHA is clear the falling edge of SS starts a transmission See 15 5 Transmission Formats SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge 15 5 Transmission Formats During an SPI transmission data is simultaneously transmitted shifted out serially and received shifted in serially A serial clock synchronizes shifting and sampling on the two serial data lines A slave select line allows selection of an individual slave SPI device slave devices that are not selected do not interfere with SPI bus activities On a master SPI device the slave select line can optionally be used to indicate multiple master bus co
92. REGISTER PRE BAUD SCALER DIVIDER SCP1 m SCPO NSMIT 5 SHIFT REGISTER SCR1 SCR 615432 L SCI_TxD SCRO d 2 2 B g 5 6 5 P PARITY oc 2 L GENERATIO a y 5 o lt 5 e a E 7 4 cr bs xd aa lt lt T8 Q 5 gt 7 wn lt lt TRANSMITTER DMATE CONTROL LOGIC SCTIE SCTE DMATE SCTE LOOPS SCTIE SCTIE ENSCI us TC TE Figure 14 7 SCI Transmitter MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 257 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications 14621 Character Length The transmitter can accommodate either 8 bit or 9 bit data The state of the M bit in IRSCI control register 1 IRSCC1 determines character length When transmitting 9 bit data bit T8 in IRSCI control register 3 IRSCC3 is the ninth bit bit 8 46 22 Character Transmission Data Sheet During an SCI transmission the transmit shift register shifts a character out to the TxD pin The IRSCI data register IRSCDR is the write only buffer between the internal data bus and the transmit shift register To initiate an SCI transmission 1 Enab
93. RT10 MSB STOP RECEIVER RT CLOCK RT RT2 RT3 RT4 RT5 RT6 RT7 RT8 T RT10 RT11 RT12 RT13 RT14 RT15 RT16 DATA SAMPLES Figure 14 10 Slow Data For an 8 bit character data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles 10 RT cycles 154 RT cycles With the misaligned character shown in Figure 14 10 the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times x 16 RT cycles 3 RT cycles 147 RT cycles The maximum percent difference between the receiver count and the transmitter count of a slow 8 bit character with no errors is 54 47 154 100 4 54 For 9 bit character data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles 10 RT cycles 170 RT cycles With the misaligned character shown in Figure 14 10 the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles 3 RT cycles 163 RT cycles MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 265 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Data Sheet The maximum percent difference between the receiver count and the transmitter count of a slow 9 bit character with no errors is mz 163 17
94. Read Unimplemented Write Reset Port A LED Control 1984 nol Lepa7 LEDA6 LEDAS LEDA4 LEDA3 LEDA2 LEDA1 LEDAO Register Write LEDA 0 0 0 0 0 0 0 0 Read Unimplemented Write Reset Read Unimplemented Write Reset Read Unimplemented Write Reset Read SPI Control SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE Write SPCR Reset 0 0 1 0 1 0 0 0 Read SPRF OVRF MODF SPTE SPI Status and Control ERRIE MODFEN SPR1 SPRO Register Write SPSCR Reset 0 0 0 0 1 0 0 0 Read R7 R6 R5 R4 R3 R2 R1 RO Write T7 T6 T5 T4 T3 T2 T1 TO Reset Unaffected by reset Read SCI Control Register 1 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY Write SCC1 Reset 0 0 0 0 0 0 0 0 U Unaffected X Indeterminate Unimplemented R Reserved SPI Data Register SPDR Figure 2 2 Control Status and Data Registers Sheet 2 of 12 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 39 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 ii SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCI Contr
95. Read Write Reset R7 RO T7 TO Receive Transmit Data Bits Bit 7 6 5 4 3 2 1 Bit 0 R7 R6 R5 R4 R3 R2 R1 RO T7 T6 T5 T4 T3 T2 TO Unaffected by reset Figure 15 15 SPI Data Register SPDR Do not use read modify write instructions on the SPI data register since the register read is not the same as the register written MC68HC908AP Family Rev 2 5 318 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 16 Multi Master IIC Interface MMIIC 16 1 Introduction The multi master IIC MMIIC interface is a two wire bidirectional serial bus which provides a simple efficient way for data exchange between devices The interface is designed for internal serial communication between the MCU and other IIC devices It has hardware generated START and STOP signals and byte by byte interrupt driven software algorithm This bus is suitable for applications which need frequent communications over a short distance between a number of devices It also provides a flexibility that allows additional devices to be connected to the bus The maximum data rate is 100k bps and the maximum communication distance and number of devices that can be connected is limited by a maximum bus capacitance of 400pF This MMIIC interface is also SMBus System Management Bus version 1 0 and 1 1 com
96. SIM reset status register by reading it A power on reset sets the POR bit and clears all other bits in the register Address FE01 Bit 7 6 5 4 3 2 1 Bit 0 Read POR PIN COP ILOP ILAD MODRST LVI 0 Write Reset 1 0 0 0 0 0 0 0 Unimplemented Figure 9 21 SIM Reset Status Register SRSR POR Power On Reset Bit 1 Last reset caused by POR circuit 0 Read of SRSR PIN External Reset Bit 1 Last reset caused by external reset pin RST 0 POR or read of SRSR COP Computer Operating Properly Reset Bit 1 Last reset caused by COP counter 0 POR or read of SRSR ILOP Illegal Opcode Reset Bit 1 Last reset caused by an illegal opcode 0 POR or read of SRSR ILAD Illegal Address Reset Bit opcode fetches only 1 Last reset caused by an opcode fetch from an illegal address 0 POR or read of SRSR MODRST Monitor Mode Entry Module Reset Bit 1 Last reset caused by monitor mode entry when vector locations FFFE and FFFF are FF after POR while IRQ1 Vpp 0 POR or read of SRSR MC68HC908AP Family Rev 2 5 150 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM SIM Registers LVI Low Voltage Inhibit Reset Bit 1 Last reset caused by the LVI circuit 0 POR or read of SRSR 9 7 3 SIM Break Flag Control Register The SIM break control register con
97. See 8 5 2 PLL Bandwidth Control Register e PLL multiplier select registers PMSH and PMSL See 8 5 3 PLL Multiplier Select Registers e PLL VCO range select register PMRS See 8 5 4 PLL VCO Range Select Register e PLL reference divider select register PMDS See 8 5 5 PLL Reference Divider Select Register Data Sheet MC68HC908AP Family Rev 2 5 116 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM CGM Registers 8 5 1 PLL Control Register The PLL control register PCTL contains the interrupt enable and flag bits the on off switch the base clock selector bit the prescaler bits and the VCO power of two range selector bits Address 0036 Bit 7 6 5 4 3 2 1 Bit 0 Read PLLF PLLIE PLLON BCS PRE1 PREO VPR1 VPRO Write Reset 0 0 1 0 0 0 0 0 Unimplemented Figure 8 4 PLL Control Register PCTL PLLIE PLL Interrupt Enable Bit This read write bit enables the PLL to generate an interrupt request when the LOCK bit toggles setting the PLL flag PLLF When the AUTO bit in the PLL bandwidth control register PBWC is clear PLLIE cannot be written and reads as logic 0 Reset clears the PLLIE bit 1 PLL interrupts enabled 0 PLL interrupts disabled PLLF PLL Interrupt Flag Bit This read only bit is set whenever the LOCK bit toggles PLLF generates an interrupt request
98. Table 14 6 When enabled the parity function inserts a parity bit in the most significant bit position See Figure 14 6 Reset clears the PEN bit 1 Parity function enabled 0 Parity function disabled MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 273 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications PTY Parity Bit This read write bit determines whether the SCI generates and checks for odd parity or even parity See Table 14 6 Reset clears the PTY bit 1 Odd parity 0 Even parity NOTE Changing the PTY bit in the middle of a transmission or reception can generate a parity error Table 14 6 Character Format Selection Control Bits Character Format M Start Data parity Stop a 0 Ox 1 8 None 1 10 bits 1 1 9 1 11 bits 0 10 1 7 1 10 bits 0 11 1 7 Odd 1 10 bits 1 10 1 8 Even 1 11 bits 1 11 1 8 Odd 1 11 bits 14 10 2 IRSCI Control Register 2 IRSCI control register 2 e Enables the following CPU interrupt requests Enables the SCTE bit to generate transmitter CPU interrupt requests Enables the TC bit to generate transmitter CPU interrupt requests Enables the SCRF bit to generate receiver CPU interrupt requests Enables the IDLE bit to generate receiver CPU interrupt requests Enables the transmitter Enabl
99. Timer 2 Status and Control TOIE TSTOP PS2 PS1 PSO 002B Register Write 0 TRST T2SC Reset 0 0 1 0 0 0 0 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Timer 2 Counter 002C Register High Write T2CNTH Reset 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 Timer 2 Counter 002D Register Low Write T2CNTL Reset 0 0 0 0 0 0 0 0 Read Timer 2 Counter Modulo Bit 15 14 13 12 11 10 9 Bit 8 002E Register High Write T2MODH Reset 1 1 1 1 1 1 1 1 Read Timer 2 Counter Modulo Bit 7 6 5 4 3 2 1 Bit 0 002F Register Low Write T2MODL Reset 1 1 1 1 1 1 1 1 Read CHOF Timer 2 Channel 0 Status CHOIE MSOB MSOA ELSOB ELSOA TOVO CHOMAX 0030 and Control Register Write 0 25 0 Reset 0 0 0 0 0 0 0 0 Read Timer 2 Channel 0 Bit 15 14 13 12 11 10 9 Bit 8 0031 Register High Write T2CHOH Reset Indeterminate after reset Unimplemented Figure 11 2 TIM I O Register Summary Sheet 2 of 3 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 185 For More Information On This Product Go to www freescale com Timer Interface Module Freescale Semiconductor Inc Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read Timer 2 Channel 0 Bit 7 6 5 4 3 2 1 Bit 0 0032 Register Low Write T2CHOL Reset Indeterminate after reset Read 0 Timer 2 Channel 1 Status CHIIE ELS1B
100. Unaffected Figure 13 2 SCI Register Summary MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 215 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface 13 4 1 Data Format 13 4 2 Transmitter Data Sheet The SCI uses the standard non return to zero mark space data format illustrated in Figure 13 3 8 BIT DATA FORMAT PARITY BIT M IN SCC1 CLEAR BIT NEXT erro Y er Y er Y ers Y era Y ers are stop Br 9 BIT DATA FORMAT BIT MIN SCC1 SET p NEXT START START f Y 1 X Brr2 J Bra 4 X 7 STOP BIT Figure 13 3 SCI Data Formats Figure 13 4 shows the structure of the SCI transmitter The baud rate clock source for the SCI can be selected via the configuration bit SCIBDSRC Source selection values are shown in Figure 13 4 MC68HC908AP Family Rev 2 5 216 MOTOROLA For More Information On This Product Go to www freescale com SCIBDSRC FROM CONFIG2 SL 0 gt X A SL 1 gt X B TRANSMITTER CPU INTERRUPT REQUEST Freescale Semiconductor Inc Serial Communications Interface Module SCI INTERNAL BUS Functional Description PRE BAUD SCALER DIVIDER TRANSMITTER DMA SERVICE REQUEST TRANSMIT 11 BIT SCI DATA REGISTER SHIFT REGISTER 6 5
101. an dedicated pin and Supply voltage VDDA 4 5 5 5 V should be tied to Vpp on the PCB with proper decoupling Input range VADIN 0 VpDA V Vanin VppA Resolution BAD 10 10 bits Includes quantization Absolute accuracy AAD 1 5 LSB 20 5 LSB 1 ADC step ADC internal clock fADIC 500k 1 048M Hz tanic 1 fapic Conversion range Rap VREFL VREFH V ADC voltage reference high VREFH Vppa 0 1 M ADC voltage reference low VREFL 0 1 V S t t 16 17 Conversion time ADC cycles t Sample time ADS 5 cycles Monotonicity Map Guaranteed Zero input reading ZADI 000 001 HEX VapiN VREFL Full scale reading FADI 3FD 3FF HEX VapiN VnEFH Input capacitance CADI 20 pF Not tested Input impedance Rapi 20M Q VREFH V REFL lvnEF 1 6 mA Not tested Notes 1 Vpp 4 5 to 5 5 Vdc Vss 0 TA T to Ty unless otherwise noted Data Sheet MC68HC908AP Family Rev 2 5 420 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 24 9 3V DC Electrical Characteristics Table 24 8 DC Electrical Characteristics 3V Electrical Specifications 3V DC Electrical Characteristics Characteristic Symbol Min Typ Max Unit Output high voltage 1 4mA Von Vpp 04 _ _ V 0 7 PTB 4 7 PTC 0 5 PTD 0 7 Output low voltage 4mA 0 7 PTB 4 7 PTC 0 5 PTD O
102. and master out slave in MOSI pins are directly connected between the master and the slave The MISO signal is the output from the slave and the MOSI signal is the output from the master The SS line is the slave select input to the slave The slave SPI drives its MISO output only when its slave select input SS is at logic 0 so that only the selected slave drives to the master The SS pin of the master is not shown but is assumed to be inactive The SS pin of the master must be high or must be reconfigured as general purpose not affecting the SPI See 15 7 2 Mode Fault Error When CPHA 0 the first SPSCK edge is the MSB capture strobe Therefore the slave must begin driving its data before the first SPSCK edge and a falling edge on the SS pin is used to start the slave data transmission The slave s SS pin must be toggled back to high and then low again between each byte transmitted as shown in Figure 15 5 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 295 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI SPSCK CYCLE FOR REFERENCE SPSCK 0 SPSCK CPOL 1 MOSI FROMMASTER y erre y erra y erra y 2 y err MISO FROM SLAVE MSB BIT 6 BIT 5 BIT 4 4 BIT2 X BIT 1 LSB JM SS TO SLAVE CAPTURE STROBE A A A A A A A A
103. as shown in Table 15 1 MC68HC908AP Family Rev 2 5 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Registers 15 13 Registers Three registers control and monitor SPI operation e SPI control register SPCR e SPI status and control register SPSCR SPI data register SPDR 15 13 1 SPI Control Register The SPI control register Enables SPI module interrupt requests e Configures the SPI module as master or slave e Selects serial clock polarity and phase e Configures the SPSCK MOSI and MISO pins as open drain outputs e Enables the SPI module Address 0010 Bit 7 6 5 4 3 2 1 Bit 0 Read SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE Write Reset 0 0 1 0 1 0 0 0 Unimplemented R Reserved Figure 15 13 SPI Control Register SPCR SPRIE SPI Receiver Interrupt Enable Bit This read write bit enables CPU interrupt requests generated by the SPRF bit The SPRF bit is set when a byte transfers from the shift register to the receive data register Reset clears the SPRIE bit 1 SPRF CPU interrupt requests enabled 0 SPRF CPU interrupt requests disabled MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 313 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module
104. be programmed START ADDR DS W 1 FLASH starting address DATAARRAY DS B 15 Reserved data array EE WRITE EQU SFF36 FLASH START EQU SEEOO ORG FLASH INITIALISATION MOV 20 BUS SPD MOV 15 DATASIZE LDHX FLASH START STHX START ADDR RTS MAIN BSR INITIALISATION LHDX FILE PTR JSR EE WRITE NOTE WRITE routine is unable to check for incorrect data blocks such as the FLASH page boundary address and data size It is the responsibility of the user to ensure the starting address indicated in the data block is at the FLASH page boundary and the data size is 7 to 15 If the FLASH page is already programmed with a data array with a different size the EE_WRITE call will be ignored Data Sheet MC68HC908AP Family Rev 2 5 178 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON ROM Resident Routines 10 5 7 EE READ EE READ is used to load the data array in RAM with a set of data from FLASH Table 10 17 EE READ Routine Routine Name EE READ Emulated EEPROM read Data size ranges from 7 to 15 bytes at a time Calling Address FD5B Routine Description Stack Used 18 bytes Data Block Format Bus speed BUS SPD Data size DATASIZE Starting address ADDRH Starting address ADDRL Data 1 Data N Notes 1 The start address must be a page boundary start address The EE READ routine reads
105. bit in MMCR is also set This bit is cleared by writing O to it or by reset or when the MMEN O 1 New data in data receive register MMDRR 0 No data received MMTXIF MMIIC Transmit Interrupt Flag This flag is set when data in the data transmit register MMDTR is downloaded to the output circuit and that new data can be written to the MMDTR MMTXIF generates an interrupt request to CPU if the MMIEN bit in MMCR is also set This bit is cleared by writing O to it or when the MMEN O 1 Data transfer completed 0 Data transfer in progress MMATCH MMIIC Address Match Flag This flag is set when the received data in the data receive register MMDRR is a calling address which matches with the address or its extended addresses MMEXTAD 1 specified in the address register MMADR The MMATCH flag is set at the 9th clock of the calling address and will be cleared on the 9th clock of the next receiving data Note slave transmits do not clear MMATCH MC68HC908AP Family Rev 2 5 332 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC MMIIC Registers 1 Received address matches MMADR Received address does not match MMSRW MMIIC Slave Read Write Select This bit indicates the data direction when the module is in slave mode It is updated after the calling address is received from a master device
106. by the parity error bit PE See 14 10 4 IRSCI Status Register 1 Reset clears PEIE 1 SCI error CPU interrupt requests from PE bit enabled 0 SCI error CPU interrupt requests from PE bit disabled 14 10 4 IRSCI Status Register 1 SCI status register 1 contains flags to signal these conditions e Transfer of IRSCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to IRSCDR complete e Receiver input idle Receiver overrun Noisy data Framing error e Parity error Address 0043 Bit 7 6 5 4 3 2 1 Bit 0 Read SCTE TC SCRF IDLE OR NF FE PE Write Reset 1 1 0 0 0 0 0 0 Unimplemented Figure 14 15 IRSCI Status Register 1 IRSCS1 SCTE SCI Transmitter Empty Bit This clearable read only bit is set when the IRSCDR transfers a character to the transmit shift register SCTE can generate an SCI transmitter CPU interrupt request When the SCTIE bit in IRSCC2 is set SCTE generates an SCI transmitter CPU interrupt request In MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 279 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Data Sheet normal operation clear the SCTE bit by reading IRSCS1 with SCTE set and then writing to IRSCDR Reset sets the SCTE bit 1 IRSCDR data transferred to transmit shift register 0 IRSCDR d
107. cannot change during the break state as long as BCFE is at logic O After the break doing the second step clears the status bit Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register Therefore a write to the SPDR in break mode with the BCFE bit cleared has no effect 15 12 1 O Signals The SPI module has five I O pins and shares four of them with a parallel I O port They are MISO Data received e MOSI Data transmitted e SPSCK Serial clock e SS Slave select CGND Clock ground internally connected to Vss MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 309 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI The SPI has limited inter integrated circuit 2 capability requiring software support as a master in a single master environment To communicate with I2C peripherals MOSI becomes an open drain output when the SPWOM bit in the SPI control register is set In 2 communication the MOSI and MISO pins are connected bidirectional pin from the 2 peripheral and through pullup resistor to Vpp 15 12 1 MISO Master In Slave Out MISO is one of the two SPI module pins that transmits serial data In full duplex operation the M
108. current Maximum is highest voltage that POR is guaranteed The rearm voltage is triggered by If minimum Vpp is not reached before the internal POR reset is released RST must be driven low externally until minimum Vpp is reached 10 Rpy and are measured at Vpp 5 0V 11 Values are not affected by operating Vpp they are the same for 3V and 5V 12 Measured from Vpp Min to 5 5 V ONO 24 10 Control Timing Table 24 9 Control Timing 3V Characteristic Symbol Min Max Unit Internal operating frequency fop 8 MHz RST input pulse width low tin 1 5 us Notes 1 2 7 to 3 3 Vdc Vss 0 Vdc timing shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 Some modules may require a minimum frequency greater than dc for proper operation see appropriate table for this information 3 Minimum pulse width reset is guaranteed to be recognized It is possible for a smaller pulse width to cause a reset Data Sheet MC68HC908AP Family Rev 2 5 422 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 24 11 3V Oscillator Characteristics Table 24 10 Oscillator Specifications 3V Electrical Specifications 3V Oscillator Characteristics Characteristic Symbol Min Typ Max Unit Internal oscillator clock freq
109. data stored by the EE WHITE routine An EE READ call will retrieve the last data written to a FLASH page and loaded into the data array in RAM Same as EE WRITE the data size indicated by DATASIZE is 7 to 15 and the start address ADDRH ADDRL must the FLASH page boundary address The coding example below uses the data stored by the EE WRITE coding example see 10 5 6 EE WRITE It loads the 15 byte data set stored in the EEOO EFFF page to the data array in RAM The initialization subroutine is the same as the coding example for EE WRITE see 10 5 6 EE WRITE EE READ EQU SFD5B MAIN BSR INITIALIZATION LDHX FILE PTR JSR EE READ MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 179 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON NOTE TheEE READ routine is unable to check for incorrect data blocks such as the FLASH page boundary address and data size It is the responsibility of the user to ensure the starting address indicated in the data block is at the FLASH page boundary and the data size is 7 to 15 If the FLASH page is programmed with a data array with a different size the EE READ call will be ignored Data Sheet MC68HC908AP Family Rev 2 5 MOTOROLA 180 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 11 Timer Interface Module T
110. determines whether the SCI generates and checks for odd parity or even parity See Table 13 5 Reset clears the PTY bit 1 Odd parity 0 Even parity NOTE Changing the PTY bit in the middle of a transmission or reception can generate a parity error Table 13 5 Character Format Selection Control Bits Character Format M Start Data parity Stop a 0 Ox 1 8 None 1 10 bits 1 1 9 1 11 bits 0 10 1 7 Even 1 10 bits 0 11 1 7 Odd 1 10 bits 1 10 1 8 Even 1 11 bits 1 11 1 8 Odd 1 11 bits 13 8 2 SCI Control Register 2 SCI control register 2 e Enables the following CPU interrupt requests Enables the SCTE bit to generate transmitter CPU interrupt requests Enables the TC bit to generate transmitter CPU interrupt requests Enables the SCRF bit to generate receiver CPU interrupt requests Enables the IDLE bit to generate receiver CPU interrupt requests Enables the transmitter e Enables the receiver e Enables SCI wakeup e Transmits SCI break characters MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 235 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Address 0014 Bit 7 6 5 4 3 2 1 Bit 0 Read SCTIE TCIE SCRIE ILIE TE RE RWU SBK Write Reset 0 0 0 0 0 0 0 0 Figure 13 10 SCI Control Register
111. disables the COP module See Section 21 Computer Operating Properly COP 1 COP module disabled 0 COP module enabled 5 4 Configuration Register 2 CONFIG2 Address 001D Reat srop STOP STOP 0 0 Write RCLKEN XCLKEN OSCCLK1 OSCCLKO SCIBDSRC Reset 0 0 0 0 0 0 7 5 Figure 5 3 Configuration Register 2 CONFIG2 STOP ICLKDIS Internal Oscillator Stop Mode Disable STOP ICLKDIS disables the internal oscillator during stop mode Setting the STOP ICLKDIS bit disables the oscillator during stop mode See Section 7 Oscillator OSC Reset clears this bit 1 Internal oscillator disabled during stop mode 0 Internal oscillator enabled to operate during stop mode STOP RCLKEN RC Oscillator Stop Mode Enable Bit STOP RCLKEN enables the RC oscillator to continue operating during stop mode Setting the STOP RCLKEN bit allows the oscillator to operate continuously even during stop mode This is useful for driving the timebase module to allow it to generate periodic wake up while in stop mode See Section 7 Oscillator OSC Reset clears this bit 1 RC oscillator enabled to operate during stop mode 0 RC oscillator disabled during stop mode MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 69 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Configuration amp Mask Option Registers STOP XCLKEN X
112. for the duration of two bits and then echoes back the break signal MISSING STOP BIT 4 5 2 STOP BIT DELAY BEFORE ZERO ECHO 3 ek 9 1 2 3 4 5 6 7 Figure 10 4 Break Transaction The communication baud rate is controlled by the crystal frequency and the state of the PTBO pin when IRQ1 is set to upon entry into monitor mode When PTBO is high the divide by ratio is 1024 If the PTBO pin is at logic O upon entry into monitor mode the divide by ratio is 512 If monitor mode was entered with Vpp on IRQ1 then the divide by ratio is set at 1024 regardless of PTBO If monitor mode was entered with Vss on IRQ1 then the internal PLL steps up the external frequency presumed to be 32 768 kHz to 2 4576 MHz These latter two conditions for monitor mode entry require that the reset vector is blank MC68HC908AP Family Rev 2 5 160 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Functional Description Table 10 3 lists external frequencies required to achieve a standard baud rate of 9600 BPS Other standard baud rates can be accomplished using proportionally higher or lower frequency generators If using a crystal as the clock source be aware of the upper frequency limit that the internal clock module can handle Table 10 3 Monitor Baud Rate Selection Er Quen
113. greoa Mer Sis S NIE Wite R R R R R R R Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 2 SIM Register Summary 9 2 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU The system clocks are generated from an incoming clock as shown in Figure 9 3 This clock can come from either an external oscillator or from the on chip PLL See Section 8 Clock Generator Module CGM MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 131 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM were OSCCLK TOTBM OSCILLATOR OSC MODULE e CGMXCEK TO TIM ADC PT SIM COUNTER IMOSCEN STOP MODE CLOCK SIMOSC ENABLE SIGNALS Cnr scu er e Va eR es 2 FROM CONFIG2 COMBELE SYSTEM INTEGRATION MODULE TO REST r OF MCU Bs REST PHASE LOCKED LOOP PLL SE MCU PTBO SIMDIV2 MONITOR MODE L USER MODE CGMVCLK m Figure 9 3 CGM Clock Signals 9 2 1 Bus Timing In user mode the internal bus frequency is either the oscillator output CGMXCLK divided by four or the divided PLL output CGMPCLK divided by four 9 2 2 Clock Start up from POR or LVI Reset When the power on reset module or the low voltage inhibit module ge
114. has reached modulo value 0 TIM counter has not reached modulo value TOIE TIM Overflow Interrupt Enable Bit This read write bit enables TIM overflow interrupts when the TOF bit becomes set Reset clears the TOIE bit 1 TIM overflow interrupts enabled 0 TIM overflow interrupts disabled MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 195 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TSTOP TIM Stop Bit This read write bit stops the TIM counter Counting resumes when TSTOP is cleared Reset sets the TSTOP bit stopping the TIM counter until software clears the TSTOP bit 1 TIM counter stopped 0 TIM counter active NOTE Donotsetthe TSTOP bit before entering wait mode if the TIM is required to exit wait mode TRST TIM Reset Bit Setting this write only bit resets the TIM counter and the TIM prescaler Setting TRST has no effect on any other registers Counting resumes from 0000 TRST is cleared automatically after the TIM counter is reset and always reads as logic 0 Reset clears the TRST bit 1 Prescaler TIM counter cleared No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of 0000 PS 2 0 Prescaler Select Bits These read write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 11 2 shows Reset clears the
115. if the PLLIE bit also is set PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register PBWC is clear Clear the PLLF bit by reading the PLL control register Reset clears the PLLF bit 1 Change in lock condition 0 No change in lock condition NOTE not inadvertently clear the bit Any read or read modify write operation on the PLL control register clears the PLLF bit MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 117 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Data Sheet NOTE PLLON PLL On Bit This read write bit activates the PLL and enables the VCO clock CGMVCLK PLLON cannot be cleared if the VCO clock is driving the base clock CGMOUT BCS 1 See 8 3 8 Base Clock Selector Circuit Reset sets this bit so that the loop can stabilize as the MCU is powering up 1 2 on 0 PLL off BCS Base Clock Select Bit This read write bit selects either the oscillator output CGMXCLK or the divided VCO clock CGMPCLK as the source of the CGM output CGMOUT CGMOUT frequency is one half the frequency of the selected clock BCS cannot be set while the PLLON bit is clear After toggling BCS it may take up to three CGMXCLK and three CGMPCLK cycles to complete the transition from one source clock to the other During the transition CGMOUT is held in stasis See 8 3 8 Base Clock Sel
116. ii 2 AND opr DIR dd 3 AND opr EXT C4 hhil 4 AND opr X IX2 04 4 AND opr X Logical AND lt A amp M 0 1 21 2 E4 f 3 AND X IX F4 2 AND opr SP SP1 4 4 AND opr SP SP2 9EDA 5 ASL opr DIR 38 4 ASLA INH 48 1 ASLX Arithmetic Shift Left s I Lega INH 58 1 ASL Same as LSL E 1 1 68 ff 4 ASL X b7 bo IX 78 3 ASL opr SP SP1 9E68 ff 5 ASR opr DIR 37 jdd 4 ASRA INH 47 1 ASRX SO EN LC INH 57 1 ASR opr X Arithmetic Shift Right m xi 67 m 4 ASR IX 77 3 ASR opr SP SP1 9E67 ff 5 BCC rel Branch if Carry Bit Clear lt 2 rel 0 REL 24 3 DIR bO 11 dd 4 DIR b1 13 dd 4 DIR b2 15 dd 4 7 DIR 63 17 4 BCLR n Clear Bit n in M Mn 0 1 1 5 7 19 4 DIR b5 1B dd 4 DIR b6 1D dd 4 DIR 67 1F 4 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 81 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Table 6 1 Instruction Set Summary Sheet 2 of 8 Effect on Source Operation Description CCR 9 g S 9 Form 3 3 9 2 1 2 zs 6 6 18 BCS rel Branch if Carry Bit Set Same as BLO PC lt PC 2 rel
117. is used by the power on reset module POR and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus IBUS clocks The SIM counter also serves as a prescaler for the computer operating properly module COP The SIM counter overflow supplies the clock for the COP module The SIM counter is 13 bits long and is clocked by the falling edge of CGMXCLK 9 4 1 SIM Counter During Power On Reset The power on reset module POR detects power applied to the MCU At power on the POR circuit asserts the signal PORRST Once the SIM is initialized it enables the clock generation module CGM to drive the bus clock state machine 9 4 2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery The STOP instruction clears the SIM counter After an interrupt break or reset the SIM senses the state of the short stop recovery bit SSREC in the mask option register If the SSREC bit is a logic 1 then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles This is ideal for applications using canned oscillators that do not require long start up times from stop mode External crystal applications should use the full stop recovery time that is with SSREC cleared 9 4 3 SIM Counter and Reset States Data Sheet External reset has no effect on the SIM counter See 9 6 2 Stop Mode for details The SIM counter is free running after all
118. larger output compare value enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine The TIM overflow interrupt occurs at the end of the current counter overflow period Writing a larger value in an output compare interrupt routine at the end of the current pulse could cause two output compares to occur in the same counter overflow period MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 187 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module 71 43 2 Buffered Output Compare NOTE Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCHO pin The TIM channel registers of the linked pair alternately control the output Setting the MSOB bit in TIM channel 0 status and control register TSCO links channel O and channel 1 The output compare value in the TIM channel 0 registers initially controls the output on the TCHO pin Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows At each subsequent overflow the TIM channel registers 0 or 1 that control the output are the ones written to last TSCO controls and monitors the buffered output compare function and TIM channel 1 status and control register TSC1 is unused While the MSOB bit is set the channel 1 pin 1 is available as a g
119. latching of address and data for programming 2 Write any data to any FLASH location within the address range of the row to be programmed Wait for a time tnvs 5 us Set the HVEN bit Wait for a time tpgs 10 us Write data to the FLASH location to be programmed Wait for time tprog 20 us to 40 us gt Repeat steps 6 and 7 until all bytes within the row are programmed 9 Clear the PGM bit 10 Wait for time tayn 5 us 11 Clear the HVEN bit 12 After time 1 uis the memory can be accessed in read mode again This program sequence is repeated throughout the memory until all data is programmed The time between each FLASH adaress change step 6 to step 6 or the time between the last FLASH addressed programmed to clearing the PGM bit step 6 to step 9 must not exceed the maximum programming time torog max Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory While these operations must be performed in the order shown other unrelated operations may occur between the steps MC68HC908AP Family Rev 2 5 60 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FLASH Memory FLASH Program Operation Set PGM bit Algorithm for programming a row 64 bytes of FLASH memory
120. level of the SS pin does not affect the operation of an enabled SPI configured as a master For an enabled SPI configured as a slave having MODFEN low only prevents the MODF flag from being set It does not affect any other part of SPI operation See 15 7 2 Mode Fault Error SPR1 and SPRO SPI Baud Rate Select Bits In master mode these read write bits select one of four baud rates as shown in Table 15 4 SPR1 and SPRO have no effect in slave mode Reset clears SPR1 and SPRO Table 15 4 SPI Master Baud Rate Selection SPR1 and SPRO Baud Rate Divisor BD 00 2 01 8 10 32 11 128 Use this formula to calculate the SPI baud rate CGMOUT Baud rate 2x BD where CGMOUT base clock output of the clock generator module CGM BD baud rate divisor MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 317 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI 15 13 3 SPI Data Register Data Sheet NOTE The SPI data register consists of the read only receive data register and the write only transmit data register Writing to the SPI data register writes data into the transmit data register Reading the SPI data register reads data from the receive data register The transmit data and receive data registers are separate registers that can contain different values See Figure 15 2 Address 0012
121. low level sensitive and both of the following actions must occur to clear a keyboard interrupt request e Vector fetch or software clear A vector fetch generates interrupt acknowledge signal to clear the interrupt request Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register KBSCR The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins A falling edge that occurs after writing to the ACKK bit latches another interrupt request If the keyboard interrupt mask bit IMASKK is clear the CPU loads the program counter with the vector address at locations FFEO and FFE1 Return of all enabled keyboard interrupt pins to logic 1 As long as any enabled keyboard interrupt pin is at logic 0 the keyboard interrupt remains set The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order If the MODEK bit is clear the keyboard interrupt pin is falling edge sensitive only With MODEK clear a vector fetch or software clear immediately clears the keyboard interrupt request Reset clears the keyboard interrupt
122. misalignments between transmitter bit times and receiver bit times Slow Data Tolerance Figure 13 7 shows how much a slow received character can be misaligned without causing a noise error or a framing error The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8 RT9 and RT10 MSB STOP RECEIVER t t t CEU ER ROBES c c cr cr cr mr c cr c cc k DATA SAMPLES Figure 13 7 Slow Data For an 8 bit character data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles 10 RT cycles 154 RT cycles With the misaligned character shown in Figure 13 7 the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times x 16 RT cycles 3 RT cycles 147 RT cycles The maximum percent difference between the receiver count and the transmitter count of a slow 8 bit character with no errors is 54 47 154 100 4 54 For 9 bit character data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles 10 RT cycles 170 RT cycles With the misaligned character shown in Figure 13 7 the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles 3 RT cycles 163 RT cycles MC68HC908AP Family Rev 2 5 226 MOTO
123. of a certain tolerance See 8 8 Acquisition Lock Time Specifications for more information CPU interrupts can occur if enabled PLLIE 1 when the PLL s lock condition changes toggling the LOCK bit See 8 5 1 PLL Control Register The PLL also may operate in manual mode AUTO 0 Manual mode is used by systems that do not require an indicator of the lock condition for proper operation Such systems typically operate well below BUSMAX Data Sheet MC68HC908AP Family Rev 2 5 108 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Functional Description The following conditions apply when in manual mode 8 3 6 Programming the PLL ACQ is a writable control bit that controls the mode of the filter Before turning on the PLL in manual mode the ACQ bit must be clear Before entering tracking mode ACQ 1 software must wait a given time taco See 8 8 Acquisition Lock Time Specifications after turning on the PLL by setting PLLON in the PLL control register PCTL Software must wait a given time t after entering tracking mode before selecting the PLL as the clock source to CGMOUT BCS 1 The LOCK bit is disabled CPU interrupts from the CGM are disabled The following procedure shows how to program the PLL NOTE round function in the following equations means that the real number should be rou
124. priority logic unless the IMASK bit is clear MC68HC908AP Family Rev 2 5 380 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ Functional Description NOTE Theinterrupt mask 1 in the condition code register CCR masks all interrupt requests including external interrupt requests 4 2 m VECTOR e FOR DECODER INSTRUCTIONS a a lt ad lt INTERNAL Vpp PULLUP IRQIF DEVICE SYNCHRO IRQ1 TROT NIZER INTERRUPT Tel D gt REQUEST N7 IMASK1 HIGH TO MODE VOLTAGE SELECT DETECT LOGIC Figure 19 2 IRQ1 Block Diagram 4 VECTOR FETCH DECODER 5 a lt E lt INTERNAL t PULLUP uj DEVICE z L Yoo IRQ2F p PUCOENB SYNCHRO IRQ2 NIZER INTERRUPT OZ e REQUEST IMASK2 Figure 19 3 IRQ2 Block Diagram MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 381 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ 19 4 IRQ1 and 2 Pins Data Sheet NOTE A logic 0 on the IRQ pin can latch a
125. pue s uswasinbey jeus 2 LL JeuJo1x3 eal S9 oN yuelg ION 9533 X sl i X X d n L FS n Nu i E 0914 0 14 JONUOW 1 01 1 1 ikk bo kek ki Data Sheet MC68HC908AP Family Rev 2 5 Monitor ROM MON 157 For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Monitor Data Sheet NOTE If the reset vector is blank and monitor mode is entered the chip will see an additional reset cycle after the initial POR reset Once the part has been programmed the traditional method of applying a voltage to IRQ1 must be used to enter monitor mode The COP module is disabled in monitor mode based on these conditions e f monitor mode was entered as a result of the reset vector being blank above condition set 2 or 3 the COP is always disabled regardless of the state of IRQ1 or RST e f monitor mode was entered with on IRQ1 condition set 1 then the COP is disabled as long as is applied to either IRQ1 or RST The second condition states that as long as is maintained on the IRQ1 pin after entering monitor mode or if is applied to RST after the initial reset to get into monitor mode when was applied to IRQ1 then the
126. reads as logic O Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry into lock or an exit from lock When the PLL enters lock the divided VCO clock CGMPCLK divided by two can be selected as the CGMOUT source by setting BCS in the PCTL When the PLL exits lock the VCO clock frequency is corrupt and appropriate precautions should be taken If the application is not frequency sensitive interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations Software can select the CGMPCLK divided by two as the CGMOUT source even if the PLL is not locked LOCK 0 Therefore software should make sure the PLL is locked before setting the BCS bit 8 7 Special Modes 8 7 1 Wait Mode Data Sheet The WAIT instruction puts the MCU in low power consumption standby modes The WAIT instruction does not affect the CGM Before entering wait mode software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register PCTL to save power Less power sensitive applications can disengage the PLL without turning it off so that the PLL clock is immediately available at WAIT exit This would be the case also when the PLL is to wake the MCU from wait mode such as when the PLL is first enabled and waiting for LOCK or LOCK is lost MC68HC908AP Family Rev 2 5 124 MOTOROLA For
127. scaler Modulo VCO frequency divider Phase detector Loop filter Lock detector MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 105 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Data Sheet The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise including supply and CGMXFC noise The VCO frequency is bound to a range from roughly one half to twice the center of range frequency fyns Modulating the voltage on the CGMXFC pin changes the frequency within this range By design fyrs is equal to the nominal center of range frequency 125 kHz times a linear factor L and a power of two factor E or L x CGMRCLK is the PLL reference clock a buffered version of CGMXCLK CGMRCLK runs at a frequency fac and is fed to the PLL through a programmable modulo reference divider which divides by a factor R The divider s output is the final reference clock CGMRDV running at a frequency fapy With an external crystal 2 100 2 always set R 1 for specified performance With an external high frequency clock source use H to divide the external frequency to between 30kHz and 100kHz The VCO s output clock CGMVCLK running at a frequency fyc k is fed back through a programmable pre scaler divider and a programmable modu
128. software to clear the keyboard interrupt latch during a break interrupt write a logic 1 to the BCFE bit If a latch is cleared during the break state it remains cleared when the MCU exits the break state To protect the latch during the break state write a logic O to the BCFE bit With BCFE at logic O its default state writing to the keyboard acknowledge bit ACKK in the keyboard status and control register during the break state has no effect MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 393 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt Module KBI Data Sheet MC68HC908AP Family Rev 2 5 394 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 21 Computer Operating Properly COP 21 1 Introduction The computer operating properly COP module contains a free running counter that generates a reset if allowed to overflow The COP module helps software recover from runaway code Prevent a COP reset by clearing the COP counter periodically The COP module can be disabled through the COPD bit in the configuration register 1 CONFIG1 21 2 Functional Description Figure 21 1 shows the structure of the COP module RESET CIRCUIT RESET STATUS REGISTER gt 12 BIT COP PRESCALER ICLK LEAR ALL STAGES i STOP IN
129. the MCU exits the break state MC68HC908AP Family Rev 2 5 230 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Signals To protect status bits during the break state write a logic O to the BCFE bit With BCFE at logic O its default state software can read and write I O registers during the break state without affecting status bits Some status bits have a 2 step read write clearing procedure If software does the first step on such a bit before the break the bit cannot change during the break state as long as BCFE is at logic O After the break doing the second step clears the status bit 13 7 1 O Signals Port B shares two of its pins with the SCI module The two SCI I O pins are PTB2 TxD Transmit data e PTB3 RxD Receive data 13 7 1 TxD Transmit Data When the SCI is enabled ENSCI 1 the PTB2 TxD pin becomes the serial data output TxD from the SCI transmitter regardless of the state of the DDRB2 bit in data direction register B DDRB The TxD pin is an open drain output and requires a pullup resistor to be connected for proper SCI operation NOTE PTBZ TXD pin is an open drain pin when configured as an output Therefore when configured as a general purpose output pin PTB2 a pullup resistor must be connected to this pin 13 7 2 RxD Receive Data When the SCI is enabled ENS
130. the high voltage charge pump by clearing HVEN to logic O thy is the cumulative high voltage programming time to the same row before next erase and the same address can not be programmed twice before next erase The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase program cycles The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase program cycle The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified N Data Sheet MC68HC908AP Family Rev 2 5 432 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 25 Mechanical Specifications 25 1 Introduction This section gives the dimensions for e 48 pin plastic low profile quad flat pack case 932 e 44 pin plastic quad flat pack case 824A e 42 pin shrink dual in line package case 858 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 433 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mechanical Specifications 25 2 48 Pin Low Profile Quad Flat Pack LQFP NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 CONTROLLING DIMENSION MILLIMETER DATUM PLANE AB IS LOCA
131. when CHxIE 1 CHxF and are in the TIM channel x status and control register 11 6 Low Power Modes Data Sheet The WAIT and STOP instructions put the MCU in low power consumption standby modes MC68HC908AP Family Rev 2 5 192 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM TIM During Break Interrupts 11 6 1 Wait Mode The TIM remains active after the execution of a WAIT instruction In wait mode the TIM registers are not accessible by the CPU Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode If TIM functions are not required during wait mode reduce power consumption by stopping the TIM before executing the WAIT instruction 11 6 2 Stop Mode The TIM is inactive after the execution of a STOP instruction The STOP instruction does not affect register conditions or the state of the TIM counter TIM operation resumes when the MCU exits stop mode after an external interrupt 11 7 TIM During Break Interrupts A break interrupt stops the TIM counter The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state See 9 7 3 SIM Break Flag Control Register To allow software to clear status bits during a brea
132. 0 AC T U Z i SECTION AE AE LE E DETAIL AD K Figure 25 1 48 Pin LQFP Case 932 Data Sheet MC68HC908AP Family Rev 2 5 434 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 25 3 44 Pin Quad Flat Pack QFP a a lt lt T m o 957 9o Cv s ege 2 eoo ex oio n me Mechanical Specifications 44 Pin Quad Flat Pack QFP A B D DETAIL A F BASE METAL V TL 0 20 0 008 4 6 _ 0 05 0 002 S gt 0 20 0 008 4 SEATING PLANE DATUM PLANE DETAIL C H E DETAIL C Pd lt DATUM PLANE a 0 10 0 004 0 20 0 008 c DO SECTION B B VIEW ROTATED 90 NOTES 1 DIMENS Y14 5M JONING AND TOLERANCING PER ANS 1982 2 CON ROLLI NG D MENSION MILLIMETER 3 DATUM PLANE H IS LOCATED AT BOTTOM OF HE BOTT LEAD AND LEAD EXITS TOM Ol S F THE NCIDENT WITH THE LEAD WHERE HE PLASTIC BODY AT THE PARTING LINE 4 5 6 DATUM DIMENS SEATING PI DATUMS B AND D PLANE H
133. 0 x 100 4 12 Fast Data Tolerance Figure 14 11 shows how much a fast received character can be misaligned without causing a noise error or a framing error The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8 RT9 and RT10 STOP OR NEXT CHARACTER TES mb c cr c c ck FE EF EE k DATA SAMPLES Figure 14 11 Fast Data For an 8 bit character data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles 10 RT cycles 154 RT cycles With the misaligned character shown in Figure 14 11 the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles 160 RT cycles The maximum percent difference between the receiver count and the transmitter count of a fast 8 bit character with no errors is 5 160 154 100 3 90 For 9 bit character data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles 10 RT cycles 170 RT cycles With the misaligned character shown in Figure 14 11 the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles 176 RT cycles MC68HC908AP Family Rev 2 5 266 MOTOROLA For More Information On This Product Go to www freescale
134. 0 1 ADC input clock 2 0 1 0 ADC input clock 4 0 1 1 ADC input clock 8 1 X X ADC input clock 16 X 2 don t care ADICLK ADC Input Clock Select Bit ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC clock Reset selects CGMXCLK as the ADC clock source Data Sheet MC68HC908AP Family Rev 2 5 356 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC I O Registers If the external clock CGMXCLK is equal to or greater than 1 MHz CGMXCLK can be used as the clock source for the ADC If CGMXCLK is less than 1 MHz use the PLL generated bus clock as the clock source As long as the internal ADC clock is at fapic correct operation can be guaranteed 1 Internal bus clock 0 External clock CGMXCLK fADIC CGMXCLK or bus frequency ADIV 2 0 MODE1 and MODEO Modes of Result Justification MODE 1 and MODEO selects between four modes of operation The manner in which the ADC conversion results will be placed in the ADC data registers is controlled by these modes of operation Reset returns right justified mode Table 17 3 ADC Mode Select MODE1 MODEO Justification Mode 0 0 8 bit truncated mode 0 1 Right justified mode 1 0 Left justified mode Left justified sign data mode MC68HC908AP Family Rev 2 5 Dat
135. 045F MC68HC908AP64 2 048 Bytes Unimplemented Unimplemented 085F 085F 1 024 Bytes 1 024 Bytes 0860 0860 0860 FLASH Memory 0860 FLASH Memory 8 192 Bytes esr 16 384 Bytes 2860 FLASH Memory 485F 32 768 Bytes 4860 FLASH Memory ond Unimplemented MC68HC908AP64 i Unimplemented i 54 176 Bytes 45 984 Bytes Unimplemented 29 600 Bytes SFBFF Monitor ROM 2 FDFF 512 Bytes FEO00 SIM Break Status Register FEO1 SIM Reset Status Register FE02 Reserved FE03 SIM Break Flag Control Register FE04 Interrupt Status Register 1 FE05 Interrupt Status Register 2 FE06 Interrupt Status Register 3 FE07 Reserved FE08 FLASH Control Register 5 09 FLASH Block Protect Register FEOA Reserved FEOB Reserved FEOC Break Address Register High FEOD Break Address Register Low FEOE Break Status and Control Register FEOF LVI Status Register nde Monitor ROM 1 FFCE 447 Bytes FFCF Mask Option Register SFFDO FLASH Vectors FFFF 48 Bytes Figure 2 1 Memory Map MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 37 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 R PTA7 5 PTA4 PTA2 PTA1 PTAO 0000 Port A Data Register Wri
136. 1 1 1 1 1 1 Read Timer 1 Counter Modulo Bit 7 6 5 4 3 2 1 Bit 0 0024 Register Low Write TIMODL Reset 1 1 1 1 1 1 1 1 Read CHOF Timer 1 Channel 0 Status CHOIE MSOB MSOA ELSOB ELSOA TOVO CHOMAX 0025 and Control Register Write 0 115 0 Reset 0 0 0 0 0 0 0 0 Read Timer 1 Channel 0 Bit 15 14 13 12 11 10 9 Bit 8 0026 Register High Write 1 Reset Indeterminate after reset Read Timer 1 Channel 0 Bit 7 6 5 4 3 2 1 Bit 0 0027 Register Low Write T1CHOL Reset Indeterminate after reset Read 0 Timer 1 Channel 1 Status MS1A ELS1B ELS1A TOVI 0028 and Control Register Write 0 T1SC1 Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 2 TIM I O Register Summary Sheet 1 of 3 Data Sheet MC68HC908AP Family Rev 2 5 184 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM Functional Description Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read Timer 1 Channel 1 Bit 15 14 13 12 11 10 9 Bit 8 0029 Register High Write T1CH1H Reset Indeterminate after reset Read Timer 1 Channel 1 Bit 7 6 5 4 3 2 1 Bit 0 002A Register Low Write T1CH1L Reset Indeterminate after reset Read TOF 0 0
137. 10 1 shows the pin conditions for entering monitor mode As specified in the table monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met 1 If FFFE and FFFF do not contain FF programmed state The external clock is 4 9152 MHz with PTBO low or 9 8304 MHz with PTBO high IRQ1 PLL off 2 If FFFE and FFFF both contain FF erased state The external clock is 9 8304 MHz 1 Vpp this can be implemented through the internal IRQ1 pullup PLL off 3 If FFFE and FFFF both contain FF erased state The external clock is 32 768 kHz crystal RQt Vss this setting initiates the PLL to boost the external 32 768 kHz to an internal bus frequency of 2 4576 MHz If Vst is applied to IRQ1 and PTBO is low upon monitor mode entry above condition set 1 the bus frequency is a divide by two of the input clock If PTBO is high with Vrsr applied to IRQ1 upon monitor mode entry the bus frequency will be a divide by four of the input clock Holding the PTBO pin low when entering monitor mode causes a bypass of a divide by two stage at the oscillator only if is applied to IRQ1 In this event the CGMOUT frequency is equal to the CGMXCLK frequency and the OSC1 input directly generates internal bus clocks In this case the OSC1 signal must have 50 duty cycle at maximum bus frequency If entering m
138. 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 X X X X X X X X X Indeterminate Figure 6 3 Index Register H X 6 3 3 Stack Pointer The stack pointer is a 16 bit register that contains the address of the next location on the stack During a reset the stack pointer is preset to 00FF The reset stack pointer RSP instruction sets the least significant byte to FF and does not affect the most significant byte The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack In the stack pointer 8 bit offset and 16 bit offset addressing modes the stack pointer can function as an index register to access data on the stack The CPU uses the contents of the stack pointer to determine the conditional address of the operand Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 6 4 Stack Pointer SP MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 75 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU NOTE The location of the stack is arbitrary and may be relocated anywhere in RAM Moving the SP out of page 0 0000 to 00FF frees direct address page 0 space For correct operation the stack pointer must point only to RAM locations 6 3 4 Program Counter The program counte
139. 2 MMAD1 MMEXTAD 0048 MMADR write Reset 1 0 1 0 0 0 0 0 id MMEN MMIEN MMIIC Control Register 1 MMCROBYTE 0049 MMCRI Write MMCLRBB Reset 0 0 0 0 0 0 0 0 i Read MMALIF MMBB 0 0 MMIIC Control Register 2 MMAST MMRW MMCRCEF 004A MMCR2 write 0 Reset 0 0 0 0 0 0 0 Unaffected MMIIC Status Register Read MMRXIF MMTXIF MMATCH MMSRW MMCRCBF MMTXBE MMRXBF 004B MMSR write 0 0 Reset 0 0 0 0 1 0 1 0 Read MMIIC Data Transmit MMTD7 MMTD6 MMTD4 MMTD2 MMTD1 MMTDO 004C Register Write MMDTR Reset 0 0 0 0 0 0 0 0 Data Receive Pead MMRD7 6 MMRDS MMRD4 MMRD3 MMRD2 MMRD1 MMRDO 004D Register Write MMDRR 0 0 0 0 0 0 0 0 CRC Data Register Read MMCRCD7 MMCRCD6 MMCRCDS MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCDO 004E MMCRDR write Reset 0 0 0 0 0 0 0 0 MMIIC Frequency Divider Read MMBR2 1 MMBRO 004F Register Write MMFDR Reset o 0 0 0 0 1 0 0 U Unaffected X Indeterminate Unimplemented R Reserved Figure 2 2 Control Status and Data Registers Sheet 8 of 12 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 45 For More Information On This Product Go to
140. 368 44 pin QFP 40 to 85 C MC68HC908AP64CFA 2 048 62 368 48 pin LQFP 40 to 85 C MC68HC908AP32CB 2 048 32 768 42 pin SDIP 40 to 85 C MC68HC908AP32CFB 2 048 32 768 44 pin QFP 40 to 85 C MC68HC908AP32CFA 2 048 32 768 48 pin LQFP 40 to 85 C MC68HC908AP16CB 1 024 16 384 42 pin SDIP 40 to 85 C MC68HC908AP16CFB 1 024 16 384 44 pin QFP 40 to 85 C MC68HC908AP16CFA 1 024 16 384 48 pin LQFP 40 to 85 C MC68HC908AP8CB 1 024 8 192 42 pin SDIP 40 to 85 C MC68HC908AP8CFB 1 024 8 192 44 pin QFP 40 to 85 C MC68HC908AP8CFA 1 024 8 192 48 pin LQFP 40 to 85 C MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA For More Information On This Product Go to www freescale com 437 Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Rev 2 5 438 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOW TO REACH US USA EUROPE LOCATIONS NOT LISTED Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 800 521 6274 or 480 768 2130 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Ta
141. 68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 139 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Interrupts are latched and arbitration is performed in the SIM at the start of interrupt processing The arbitration result is a constant that the CPU uses to determine which vector to fetch Once an interrupt is latched by the SIM no other interrupt can take precedence regardless of priority until the latched interrupt is serviced or the bit is cleared See Figure 9 10 FROM RESET BREAK YES INTERRUPT gt YES IRQ1 YES INTERRUPT gt NO Y STACK CPU REGISTERS AS MANY INTERRUPTS LOAD PC Vm VECTOR AS EXIST ON CHIP lt Y FETCH NEXT INSTRUCTION UNSTACK CPU REGISTERS EXECUTE INSTRUCTION Figure 9 10 Interrupt Processing Data Sheet MC68HC908AP Family Rev 2 5 140 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Exception Control 95 1 1 Hardware Interrupts A hardware interrupt does not stop the current instruction Processing of a hardware interrupt begins after completion of the current instruction When the current instruction is complete the SIM checks all pending hardware interrupts If interr
142. 7 Voi z 0 4 V lLoap 10mA PTB 0 3 PTC 6 7 VoL 0 4 V ILOAD 10mA as TxD RxD SCTxD SCRxD Voisci 0 4 V 11 see Table 24 12 as SDA SCL 0 4 V LED sink current Vo 2V 7 1 PTA 0 7 OL 3 5 m Input high voltage 0 7 PTB 0 7 0 7 0 7 RST IRQ1 Vin 0 7 x Vpp Vpp V OSC1 0 7 x VnEG VnEG V Input low voltage 0 7 PTB 0 7 PTC 0 7 PTD 0 7 RST IRQI Vib Vss 03xVpp V OSC1 Vss 0 3 x VREG V Vpp supply current with fop 4 MHz 6 10 mA with fop 8 MHz 7 5 10 mA Wait with fop 4 MHz 2 5 mA with fop 8 MHz 29 5 mA Stop 25 C with OSC TBM and LVI modules on 9 12 1 6 mA with OSC and TBM modules Bp 7 60 uA all modules off 5 50 Stop 0 to 85 with OSC TBM and LVI modules 6 1 3 22 mA with OSC and TBM modules 6 35 220 uA all modules off m 30 200 Digital ports Hi Z leakage current liL 10 pA Input current lin t1 Capacitance Cour 12 pF Ports as input or output 8 pF MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 421 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications Table 24 8 DC Electrical Characteristics 3V Characteristic Symbol Min Typ Max Unit POR rearm voltage
143. 9 5 4 Status Flag Protection in Break Mode 145 Low Power Modes 146 9 6 1 i1 doo ee ee ra ere ae 146 9 6 2 BUDE RIDES dw RP Eb Ea 147 97 5 148 9 7 1 SIM Break Status 149 9 7 2 SIM Reset Status Register 150 9 7 3 SIM Break Flag Control Register 151 Section 10 Monitor ROM MON 101 OUCH uz ose eh RAE Ree Dede 153 153 10 3 Functional Description 154 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Data Sheet 10 3 1 Entering Monitor 156 10 3 2 Lata FOU 3 4 Xr CCo XCECRHACR a ekia 160 10 33 DEL kd tes E E DOUG bid PAR eR d 160 10 3 4 160 COMMAS Losada E adea oe ew asa 161 TOM Cx ponds wha ae OX RU OR cet bet en pP ee 166 10 5 ROM Resident 168 Te PRORNOE dard OS RSE E GU ded ee RR CER 170 10 5 2 EBMAMBOE casas ae RC ene eed 172 oe LDANGE ERE A rei e es x3 dos 173 12194 PRGRNGE ii ahha RO RA RA A
144. 908AP Family Rev 2 5 Data Sheet MOTOROLA 339 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC 16 8 SMBus Protocols with PEC and without PEC Following is a description of the various MMIIC bus protocols with and without a packet error code PEC 16 8 1 Quick Command 1 7 1 1 1 START Slave Address AW STOP Master to Slave L Start Condition L Stop Condition Bl Slave to Master Command Bit Acknowledge Figure 16 13 Quick Command 16 8 2 Send Byte START Slave Address cx Command Code ACK STOP 8 Send Byte Protocol START Slave Address ex Command Code ACK PEC ACK STOP b Send Byte Protocol with PEC Figure 16 14 Send Byte 16 8 3 Receive Byte START Slave Address R NAK STOP a Receive Byte Protocol START Slave Address Be ACK NAK STOP b Receive Byte Protocol with PEC Figure 16 15 Receive Byte Data Sheet MC68HC908AP Family Rev 2 5 340 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC SMBus Protocols with PEC and without PEC 16 8 4 Write Byte Word START Slave Address Wack Command Code ACK Data Byte STOP a Write Byte Protocol START Slave Address Command Code ACK Data Byte ACK PEC STOP b Write Byte Protocol with PEC START Slave Address Wack Command Code Data Byte Low D
145. A block diagram of the SIM is shown in Figure 9 1 Table 9 1 is a summary of the SIM input output I O registers The SIM is a system state controller that coordinates CPU and exception timing The SIM is responsible for Bus clock generation and control for CPU and peripherals Stop wait reset break entry and recovery Internal clock control Master reset control including power on reset POR and COP timeout Interrupt control Acknowledge timing Arbitration control timing Vector address generation CPU enable disable timing Modular architecture expandable to 128 interrupt sources Table 9 1 shows the internal signal names used in this section MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 129 For More Information On This Product Go to www freescale com RESET PIN LOGIC INTERNAL PULLUP DEVICE Freescale Semiconductor Inc System Integration Module SIM MODULE STOP MODULE WAIT CPU STOP FROM CPU CPU WAIT FROM CPU gt SIMOSCEN CGM OSC STOP WAIT CONTROL COP CLOCK ICLK FROM OSC CGMOUT FROM CGM COM EL CLOCK GENERATORS INTERNAL CLOCKS LVI FROM LVI MODULE ILLEGAL OPCODE FROM CPU ILLEGAL ADDRESS FROM ADDRESS MAP DECODERS COP FROM COP MODULE INTERRUPT CONTROL INTERRUPT SOURCES AND PRIORITY DECODE gt CPU INTERFACE Figure 9 1 SIM Block Diagram Table 9 1 S
146. ASH Control Register FE08 FLCR Write Reset 0 0 0 0 0 0 0 0 Read FLASH Block Protect BPR7 BPR6 BPR5 BPR4 BPR2 BPR1 BPRO 5 09 Register Write FLBPR Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 4 1 FLASH I O Register Summary MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 55 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FLASH Memory 4 2 Functional Description NOTE Data Sheet The FLASH memory consists of an array of 62 368 bytes for user memory plus a block of 48 bytes for user interrupt vectors and one byte for the mask option register An erased bit reads as logic 1 and a programmed bit reads as a logic 0 The FLASH memory page size is defined as 512 bytes and is the minimum size that can be erased in a page erase operation Program and erase operations are facilitated through control bits in FLASH control register FLCR The address ranges for the FLASH memory are e 0860 FBFF user memory 62 368 bytes e FFDO FFFF user interrupt vectors 48 bytes e FFCF mask option register Programming tools are available from Motorola Contact your local Motorola representative for more information A security feature prevents viewing of the FLASH contents 1 No security feature is absolutely secure However Motorola s strategy is to make reading or copying the FLASH difficult for unauthorized users MC68HC908AP F
147. B1 pullup resistors must be connected to these pins Data Sheet MC68HC908AP Family Rev 2 5 320 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC Table 16 1 Pin Name Conventions MMIIC Generic Pin Names Full MCU Pin Names Pin Selected for MMIIC Function By SDA PTBO SDA MMEN bit in MMCR1 0049 SCL PTB1 SCL Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read MMIIC Address Register MMAD7 MMAD6 MMADS MMAD4 MMADS MMAD2 MMAD1 MMEXTAD 0048 Write MMADR Reset 1 0 1 0 0 0 0 0 liis MMEN MMIEN 2 MMTXAK REPSEN j MMCRCBYTE 0049 MMIIC Control Register 1 Write MMCLRBB 1 Reset 0 0 0 0 0 0 0 0 Read MMALIF MMNAKIF MMBB Vitae 0 0 Control Register2 MMCRCEF 004A 2 Write 0 0 Reset 0 0 0 0 0 0 0 Unaffected Read MMRXIF MMTXIF MMATCH MMSRW MMRXAK MMCRCBF MMTXBE MMRXBF MMIIC Status Register 004B MMSR Write 0 0 Reset 0 0 0 0 1 0 1 0 MMIIC Data Transmit 1989 gia ranis MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTDO 004C Register Write MMDTR Reset 0 0 0 0 0 0 0 0 MMIIC Data Receive Read MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRDO 004D Register Writ
148. B1 as SCL of MMIIC In Out Vpp PTB3 RxD PTB2 as TxD of SCI open drain output Out Vpp PTB4 T1CHO PTB3 as RxD of SCI In Vpp PTBS TICH as T1CHO of TIMI In Out Vin PTB6 T2CHO PTB5 as T1CH1 of TIM1 In Out Vpp PTB7 T2CH1 PTB6 as T2CHO of TIM2 In Out VDD PTB7 as T2CH1 of TIM2 In Out Vpp 8 bit t PTC7 PTCO IRQ2 PTC1 PTCO is shared with IRQ2 and has schmitt trigger input In VDD PTC2 MISO PTC2 as MISO of SPI In Vpp PTCS MOSI PTC3 as MOSI of SPI Out 4 55 ZR PTC4 as SS of SPI In Vpp PTC5 SPSCK V PTC6 SCTxD PTC5 as SPSCK of SPI In Out DD PTC7 SCRxD PTC6 as SCTXD of IRSCI open drain output Out Vpp PTC7 as SCRxD of IRSCI In Vpp PTDO KBIO 8 bit general purpose port with schmitt trigger inputs In Out Vpp PTD7 KBI7 Pins as keyboard interrupts with pullup KBIO KBIT In Vpp Notes 1 See Section 24 Electrical Specifications for Vpeg tolerance MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 31 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description 1 6 Power Supply Bypassing VDD VDDA VSS VSSA Data Sheet Vpp and Vss are the power supply and ground pins the MCU operates from a single power supply together with an on chip voltage regulator Fast signal transitions on MCU pins place high short duration current demands on the power supply To prevent noise problems take special care to provide power supply bypassing
149. C68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 125 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM 8 8 Acquisition Lock Time Specifications The acquisition and lock times of the PLL are in many applications the most critical PLL design parameters Proper design and use of the PLL ensures the highest stability and lowest acquisition lock times 8 8 1 Acquisition Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time within specified tolerances of the system to a step input In a PLL the step input occurs when the PLL is turned on or when it suffers a noise hit The tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change Therefore the reaction time is constant in this definition regardless of the size of the step input For example consider a system with a 5 percent acquisition time tolerance If a command instructs the system to change from OHz to 1 MHz the acquisition time is the time taken for the frequency to reach 1MHz 50kHz 50kHz 5 of the 1MHz step input If the system is operating at 1 MHz and suffers a 100 kHz noise hit the acquisition time is the time taken to return from 900kHz to 1MHz 5kHz 5kHz 5 of the 100kHz step input Other systems refer to acquisition and lock tim
150. CI 1 the PTB3 RxD pin becomes the serial data input RxD to the SCI receiver regardless of the state of the DDRBS3 bit in data direction register DDRB NOTE The PTBS RxD pin is an open drain pin when configured as an output Therefore when configured as a general purpose output pin PTB3 a pullup resistor must be connected to this pin MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 231 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface 13 8 I O Registers These I O registers control and monitor SCI operation SCI control register 1 SCC1 SCI control register 2 SCC2 SCI control register 3 SCC3 SCI status register 1 SCS1 SCI status register 2 SCS2 SCI data register SCDR SCI baud rate register SCBR 13 8 1 SCI Control Register 1 SCI control register 1 Data Sheet Enables loop mode operation Enables the SCI Controls output polarity Controls character length Controls SCI wakeup method Controls idle character detection Enables parity function Controls parity type MC68HC908AP Family Rev 2 5 232 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Registers Address 0013 Bit 7 6 5 4 3 2 1 Bit 0 Read LOOPS ENSCI TXINV M WAKE ILTY PEN PTY Write Re
151. CU e OSCCLK Reference clock for timebase module TBM Data Sheet MC68HC908AP Family Rev 2 5 92 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Oscillator OSC Clock Selection 7 2 1 CGM Reference Clock Selection The clock generator module CGM reference clock CGMXCLK is the reference clock input to the MCU It is selected by programming two bits in a FLASH memory location the mask option register MOR at FFCF See 5 5 Mask Option Register MOR Address FFCF Bit 7 6 5 4 3 2 1 Bit 0 Read OSCSEL1 OSCSELO R R R R R R Write Reset Unaffected by reset Erased 1 1 1 1 1 1 1 1 R Reserved Figure 7 2 Mask Option Register MOR Table 7 1 CGMXCLK Clock Selection OSCSEL1 OSCSELO CGMXCLK OSC2 Pin Comments 0 0 Not used 0 1 ICLK fgus Internal oscillator generates the CGMXCLK RC oscillator generates the CGMXCLK 1 0 RCCLK fgus Internal oscillator is available after each POR or reset Inverting X tal oscillator generates the CGMXCLK 1 1 XCLK output of Internal oscillator is available after each POR X TAL or reset The internal oscillator is a free running oscillator and is available after each POR or reset It is turned off in stop mode by setting the STOP ICLKDIS bit in CONFIG2 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 93 For More Infor
152. Control Register Write SERER COPCTL Reset Memory Map Input Output I O Section Reset Reset MOR is a non volatile FLASH register write by programming U Unaffected Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRKE BRKA 0 0 0 0 0 0 0 0 LVIOUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCSEL1 OSCSELO R R R R R R 1 1 1 1 1 1 1 1 U U U U U U U U Low byte of reset vector Writing clears COP counter any value Unaffected by reset X Indeterminate Unimplemented R Reserved Figure 2 2 Control Status and Data Registers Sheet 12 of 12 Data Sheet MC68HC908AP Family Rev 2 5 MOTOROLA For More Information On This Product Go to www freescale com 49 Freescale Semiconductor Inc Memory Map Table 2 1 Vector Addresses Priority INT Flag Address Vector Lowest FFDO Reserved A B FFD1 Reserved FFD2 TBM Vector High v FFD3 TBM Vector Low FFD4 SCI2 IRSCI Transmit Vector High ne FFD5 SCI2 IRSCI Transmit Vector Low FFD6 SCI2 IRSCI Receive Vector High TE FFD7 SCI2 IRSCI Receive Vector Low FFD8 SCI2 IRSCI Error Vector High di FFD9 SCI2 IRSCI Error Vector Low FFDA SPI Transmit Vector H
153. DDRESS ADDRESS VADDRESS y Notes 1 Echo delay 2 bit times 2 Cancel command delay 11 bit times 3 Wait 1 bit time before sending next byte Figure 10 6 Write Transaction A brief description of each monitor mode command is given in Table 10 4 through Table 10 9 Table 10 4 READ Read Memory Command Description Read byte from memory Operand 2 byte address in high byte low byte order Data Returned Returns contents of specified address Opcode 4A Command Sequence SENT TO MONITOR ADDRESS ADDRESS VADDRESS V ADDRES n READ A HIGH yy HIGH LOW yy PATA RETURN MC68HC908AP Family Rev 2 5 162 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Functional Description Table 10 5 WRITE Write Memory Command Description Write byte to memory 2 byte address in high byte low byte order Operand iow byte followed by data byte Data Returned ong Opcode 49 Command Sequence oo peu ee ey NN ECHO Table 10 6 IREAD Indexed Read Command Description Read next 2 bytes in memory from last address accessed Operand 2 byte address in high byte low byte order Data Returned Returns contents
154. DDRH ADDRL and the number of bytes in the data array is specified by DATASIZE The minimum number of bytes that can be programmed in one routine call is 7 bytes the maximum is 15 bytes ADDRH ADDRL must always be the start of boundary address the page start address X000 X200 X400 X600 X800 XCOO or XE00 and DATASIZE must be the same size when accessing the same page In some applications the user may want to repeatedly store and read a set of data from an area of non volatile memory This is easily possible when using an EEPROM array As the write and erase operations can be executed on a byte basis For FLASH memory the minimum erase size is the page 512 bytes per page for MC68HC908AP84 If the data array size is less than the page size writing and erasing to the same page cannot fully utilize the page Unused locations in the page will be wasted The EE WHITE routine is designed to emulate the properties similar to the EEPROM Allowing a more efficient use of the FLASH page for data storage MC68HC908AP Family Rev 2 5 176 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON ROM Resident Routines When the user dedicates a page of FLASH for data storage and the size of the data array defined each call of the EE WHRTIE routine will automatically transfer the data in the data array in RAM to the next blank block of location
155. DM gt lt IDB 5 6 sae sae Y 22 RST ED seii uu Figure 9 17 Wait Recovery from Internal Reset 9 6 2 Stop Mode In stop mode the SIM counter is reset and the system clocks are disabled An interrupt request from a module can cause an exit from stop mode Stacking for interrupts begins after the selected stop recovery time has elapsed Reset or break also causes an exit from stop mode The SIM disables the clock generator module output CGMOUT in stop mode stopping the CPU and peripherals Stop recovery time is selectable using the SSREC bit in the configuration register 1 CONFIG1 If SSREC is set stop recovery is reduced from the normal delay of 4096 ICLK cycles down to 32 This is ideal for applications using canned oscillators that do not require long start up times from stop mode NOTE External crystal applications should use the full stop recovery time by clearing the SSREC bit MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 147 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM A break interrupt during stop mode sets the SIM break stop wait bit SBSW in the SIM break status register SBSR The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery It is then used to t
156. DO 0003 Port D Data Register Write PTD Reset Unaffected by reset Read Data Direction Register A DDRA7 DDRA6 DDRAS DDRA4 DDRA3 DDRA2 DDRA1 DDRAO 0004 Write DDRA Reset 0 0 0 0 0 0 0 0 Read Data Direction Register B DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRBO 0005 Write DDRB Reset 0 0 0 0 0 0 0 0 Read Data Direction Register C DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRCO 0006 Write DDRC Reset 0 0 0 0 0 0 0 0 Read Data Direction Register D DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRDO 0007 Write DDRD Reset 0 0 0 0 0 0 0 0 Read Port A LED Control LEDA7 LEDA6 LEDA5 LEDA4 LEDA3 LEDA2 LEDA1 LEDAO 000C Register Write LEDA Reset 0 0 0 0 0 0 0 0 Figure 18 1 I O Port Register Summary Data Sheet MC68HC908AP Family Rev 2 5 364 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output I O Ports Introduction Table 18 1 Port Control Register Bits Summary Module Control Port Bit DDR Pin Module Register Control Bit 0 DDRAO PTAO ADCO 1 DDRA1 PTA1 ADC1 2 DDRA2 PTA2 ADC2 3 DDRA3 PTA3 ADC3 A ADC ADSCR 0057 ADCH 4 0 4 DDRA4
157. Description The configuration registers and the mask option register are used in the initialization of various options These two types of registers are configured differently e Configuration registers Write once registers after reset e Mask option register FLASH register write by programming The configuration registers can be written once after each reset All of the configuration register bits are cleared during reset Since the various options affect the operation of the MCU it is recommended that these registers be written immediately after reset The configuration registers are located at 0010 and 001F The configuration registers may be read at anytime NOTE The CONFIG registers are not in the FLASH memory but are special registers containing one time writable latches after each reset Upon a reset the CONFIG registers default to predetermined settings as shown in Figure 5 2 and Figure 5 3 Data Sheet MC68HC908AP Family Rev 2 5 66 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Configuration amp Mask Option Registers CONFIG amp MOR Configuration Register 1 CONFIG1 The mask option register MOR is used for selecting one of the three clock options for the MCU The MOR is a byte located in FLASH memory and is written to by a FLASH programming routine 5 3 Configuration Register 1 CONFIG1 Address 001F
158. E9 0 1 40 19 6608 MHz 19 6608 MHz 4 9152 MHz 32 768 kHz 258 0 2 27 20 MHz 20 MHz 5 0MHz 32 768 kHz 263 0 2 28 29 4912 MHz 29 4912 MHz 7 3728 MHz 32 768 kHz 384 0 2 32 MHz 32 MHz 8 0MHz 32 768 kHz 3D1 0 2 40 32 MHz 16 MHz 4 0MHz 32 768 kHz 1E9 1 2 40 32 MHz 8 MHz 2 0MHz 32 768 kHz F5 2 2 0 32 MHz 4 MHz 1 0 MHz 32 768 kHz 7B 3 2 40 MC68HC908AP Family Rev 2 5 112 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Functional Description 8 3 7 Special Programming Exceptions The programming method described in 8 3 6 Programming the PLL does not account for three possible exceptions A value of for or Lis meaningless when used in the equations given To account for these exceptions e AOvalue for R or N is interpreted exactly the same as a value of 1 e AO value for L disables the PLL and prevents its selection as the source for the base clock See 8 3 8 Base Clock Selector Circuit 8 3 8 Base Clock Selector Circuit This circuit is used to select either the oscillator clock CGMXCLK or the divided VCO clock CGMPCLK as the source of the base clock CGMOUT The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMPCLK cycles to change from one clock source to the other Durin
159. ED Drive Enable Bits These read write bits are software programmable to enable the direct LED drive on an output port pin 1 Corresponding port A pin is configured for direct LED drive with 15mA current sinking capability 0 Corresponding port A pin is configured for standard drive MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 369 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports 18 3 Port B Port B is an 8 bit special function port that shares two of its pins with the multi master MMIIC module two of its pins with SCI module and four of its pins with two timer interface TIM1 and TIM2 modules NOTE PTBS3 PTBOare open drain pins when configured as outputs regardless whether the pins are used as general purpose I O pins MMIIC pins or SCI pins Therefore when configured as general purpose output pins MMIIC pins or SCI pins the TxD pin pullup resistors must be connected to these pins 18 3 1 Port B Data Register PTB The port B data register contains a data latch for each of the eight port B pins Address 0001 Bit 7 6 5 4 3 2 1 Bit 0 Read PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTBO Write Reset Unaffected by reset Alternative Function T2CH1 T2CHO T1CH1 T1CHO RxD TxD SCL SDA Figure 18 6 Port B Data Register PTB PTB 7 0 Port B Data Bits These read write bits are softwar
160. EG Rex M 31 I Figure 7 5 RC Oscillator 7 5 X tal Oscillator The crystal x tal oscillator circuit is designed for use with an external 32 768kHz crystal to provide an accurate clock source In its typical configuration the x tal oscillator is connected in a Pierce oscillator configuration as shown in Figure 7 6 This figure shows only the logical representation of the internal components and may not represent actual circuitry The oscillator configuration uses five components Crystal X4 32 768kHz Fixed capacitor e Tuning capacitor C can also be a fixed capacitor Feedback resistor e Series resistor Rg optional Data Sheet MC68HC908AP Family Rev 2 5 96 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Oscillator OSC Signals From SIM To Clock Selection MUX SIMOSCEN XCLK CONFIG2 STOP XCLKEN MCU OSC1 OSC2 e Rs Xi See Section 24 for component value requirements L 32 768kHz C4 DL Co I Figure 7 6 Crystal Oscillator The series resistor Rg is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation especially with high frequency crystals Refer to the crystal manufacturer s data for more information 7 6 O Signals The following paragraphs describe the oscillator I O
161. F set and then reading the SPI data register Reset clears the SPRF bit 1 Receive data register full 0 Receive data register not full MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 315 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI ERRIE Error Interrupt Enable Bit This read write bit enables the MODF and bits to generate CPU interrupt requests Reset clears the ERRIE bit 1 MODF and OVRF can generate CPU interrupt requests 0 MODF and OVRF cannot generate CPU interrupt requests OVRF Overflow Bit This clearable read only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register In an overflow condition the byte already in the receive data register is unaffected and the byte that shifted in last is lost Clear the bit by reading the SPI status and control register with OVRF set and then reading the receive data register Reset clears the bit 1 Overflow 0 No overflow MODF Mode Fault Bit This clearable read only flag is set in a slave SPI if the SS pin goes high during a transmission with the MODFEN bit set In a master SPI the MODF flag is set if the SS pin goes low at any time with the MODFEN bit set Clear the MODF bit by reading the SPI status and control register SPSCR with MODF set and then writin
162. FLASH 55 Section 5 Configuration amp Mask Option Registers CONFIG amp 65 Section 6 Central Processor Unit 73 Section 7 Oscillator 5 91 Section 8 Clock Generator Module CGM 101 Section 9 System Integration Module SIM 129 Section 10 Monitor ROM MON 153 Section 11 Timer Interface Module TIM 181 Section 12 Timebase Module 205 Section 13 Serial Communications Interface Module i 5 re 211 Section 14 Infrared Serial Communications Interface Module 5 1 249 Section 15 Serial Peripheral Interface Module SPI 289 Section 16 Multi Master IIC Interface MMIIC 319 Section 17 Analog to Digital Converter ADC 345 Section 18 Input Output I O Ports 363 Section 19 External Interrupt 379 Section 20 Keyboard Interrupt Module 387 Section 21 Computer Operating Properly COP 395 Section 22 Low Voltage Inhibit LVI 401 Section 23 Break Module BRK 407 Section 24 Electrical Specifications 415 Section 25 Mechanical Specifications 433 Section 26 Ordering Informa
163. G BYTE 3 AND CLEARING SPTE BIT 9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER SETTING SPRF BIT BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER SETTING SPTE BIT 11 CPU READS SPSCR WITH SPRF BIT SET 12 CPU READS SPDR CLEARING SPRF BIT Figure 15 8 SPRF SPTE CPU Interrupt Timing The transmit data buffer allows back to back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer Also if no new data is written to the data buffer the last value contained in the shift register is the next data word to be transmitted MC68HC908AP Family Rev 2 5 300 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Error Conditions For an idle master or idle slave that has no data loaded into its transmit buffer the SPTE is set again no more than two bus cycles after the transmit buffer empties into the shift register This allows the user to queue up a 16 bit value to send For an already active slave the load of the shift register cannot occur until the transmission is completed This implies that a back to back write to the transmit data register is not possible The SPTE indicates when the next write can occur 15 7 Error Conditions The following flags signal SPI error conditions Overflow OVRF Faili
164. HC908AP16 and MC68HC908AP8 Two 16 bit 2 channel timer interface modules TIM1 and TIM2 with selectable input capture output compare and PWM capability on each channel e Timebase module Serial communications interface module 1 SCI e Serial communications interface module 2 SCI with infrared IR encoder decoder e Serial peripheral interface module SPI e System management bus SMBus version 1 0 1 1 multi master bus e 8 channel 10 bit analog to digital converter ADC external interrupt pin with integrated pullup 2 external interrupt pin with programmable pullup e 8 bit keyboard wakeup port with integrated pullup 32 general purpose input output I O pins 31 shared function I O pins 8LED drivers sink 25mA open drain I O with pullup e Low power design fully static with stop and wait modes 1 No security feature is absolutely secure However Motorola s strategy is to make reading or copying the FLASH difficult for unauthorized users Data Sheet MC68HC908AP Family Rev 2 5 24 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description MCU Block Diagram Master reset pin with integrated pullup and power on reset System protection features Optional computer operating properly COP reset driven by internal RC oscillator Low voltage detection with optional reset or inte
165. Hi Z leakage current li 10 pA Input current lin 1 Capacitance m EE 12 pF Ports as input or output CiN 8 pF MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 417 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications Table 24 4 DC Electrical Characteristics 5V Characteristic Symbol Min Typ Max Unit POR rearm voltage Vpor 0 100 mV POR rise time ramp rate Rpor 0 035 V ms Monitor mode entry voltage 1 4 x Vpp 8 5 V Pullup resistors PTD O 7 Reus 21 27 39 kQ RST IRQ1 IRQ2 2 21 27 39 kQ Low voltage inhibit trip falling voltage1 9 VTRIPF1 2 25 2 45 2 65 V Low voltage inhibit trip rising voltage1 19 VTRIPR1 2 35 2 55 2 75 V Low voltage inhibit trip voltage2 VTRIPF2 2 25 2 45 2 65 V 9 CD VREG 2 25 2 50 2 75 V Notes 1 2 3 4 5 6 T 8 9 Vpp 4 5 to 5 5 Vss 0 Vdc T4 T to Ty unless otherwise noted Typical values reflect average measurements at midpoint of voltage range 25 C only Run operating Ipp measured using external 32 MHz clock to OSC1 all inputs 0 2 V from rail no dc loads less than 100pF on all outputs C 20 pF on OSC2 all ports configured as inputs OSC2 capacitance linearly affects run Ipp measured with all modules enabled Wait Ipp measured using external 32MHz to OSC1 all inputs
166. IM 11 1 Introduction This section describes the timer interface TIM module The TIM is a two channel timer that provides a timing reference with input capture output compare and pulse width modulation functions Figure 11 1 isa block diagram of the TIM This particular MCU has two timer interface modules which are denoted as TIM1 and 2 11 2 Features Features of the TIM include Two input capture output compare channels Rising edge falling edge or any edge input capture trigger Set clear or toggle output compare action e Buffered and unbuffered pulse width modulation PWM signal generation Programmable TIM clock input with 7 frequency internal bus clock prescaler selection e Free running or modulo up count operation Toggle any channel pin on overflow counter stop and reset bits MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 181 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module 11 3 Pin Name Conventions NOTE The text that follows describes both timers TIM1 and TIM2 The TIM input output I O pin names are T 1 2 CHO timer channel 0 and T 1 2 CH1 timer channel 1 where 1 is used to indicate TIM1 and 2 is used to indicate TIM2 The two TIMs share four I O pins with four I O port pins The full names of the TIM I O pins are listed in Table 11 1 The generic pin names appe
167. IRQ pin is falling edge sensitive only With MODE clear a vector fetch or software clear immediately clears the IRQ latch The IRQF bit in the INTSCR register can be used to check for pending interrupts The IRQF bit is not affected by the IMASK bit which makes it useful in applications where polling is preferred Use the BIH or BIL instruction to read the logic level on the IRQ1 pin The BIH BIL instructions do not read the logic level on the 2 pin MC68HC908AP Family Rev 2 5 382 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ IRQ Module During Break Interrupts NOTE When using the level sensitive interrupt trigger avoid false interrupts by masking interrupt requests in the interrupt routine The IRQ1 pin has a permanent internal pullup device connected while the IRQ2 pin has an optional pullup device that can be enabled or disabled by the PUCOENB bit in the INTSCR2 register 19 5 IRQ Module During Break Interrupts The BCFE bit in the SIM break flag control register SBFCR enables software to clear the latch during the break state See Section 23 Break Module BRK To allow software to clear the IRQ latch during a break interrupt write a logic 1 to the BCFE bit If a latch is cleared during the break state it remains cleared when the MCU exits the break state To protect CPU interrupt flags during the brea
168. IRQI PTBO BPS 4 9152 MHz Mgr 0 2 4576 MHz 9600 9 8304 MHz Vies 1 2 4576 MHz 9600 9 8304 MHz Vis x 2 4576 MHz 9600 32 768 kHz Waid x 2 4576 MHz 9600 10 3 5 Commands The monitor ROM firmware uses these commands READ read memory WRITE write memory e READ indexed read e WRITE indexed write READSP read stack pointer e RUN run user program The monitor ROM firmware echoes each received byte back to the PTAO pin for error checking An 11 bit delay at the end of each command allows the host to send a break character to cancel the command A delay of two bit times occurs before each echo and before READ IREAD or READSP data is returned The data returned by a read command appears after the echo of the last byte of the command NOTE Wait one bit time after each echo before sending the next byte MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 161 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor Data Sheet FROM HOST ADDRESS VADDRESS VADDRESS VADDRESS J READ yy READ y HIGH t HIGH A LOW yy LOW DEA 4 1 4 1 i 4 1 3 2 4 RETURN Notes 1 Echo delay 2 bit times 2 Data return delay 2 bit times 3 Cancel command delay 11 bit times 4 Wait 1 bit time before sending next byte Figure 10 5 Read Transaction FROM HOST ADDRESSV VA
169. ISO pin of the master SPI module is connected to the MISO pin of the slave SPI module The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin Slave output data on the MISO pin is enabled only when the SPI is configured as a slave The SPI is configured as a slave when its SPMSTR bit is logic O and its SS pin is at logic 0 To support a multiple slave system a logic 1 on the SS pin puts the MISO pin in a high impedance state When enabled the SPI controls data direction of the MISO pin regardless of the state of the data direction register of the shared port 15 12 2 MOSI Master Out Slave In MOSI is one of the two SPI module pins that transmits serial data In full duplex operation the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin When enabled the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I O port Data Sheet MC68HC908AP Family Rev 2 5 310 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Signals 15 12 3 SPSCK Serial Clock The serial clock synchronizes data transmission between master and slave devices In a master MCU the SPSCK pin is the clock output In a
170. Interrupts 80 Instruction Set Summary 80 Opcode 80 MC68HC908AP Family Rev 2 5 8 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Section 7 Oscillator OSC 7 1 Introduction anaana aaa 0000 cee ee hh 91 ech dort bbe 92 7 2 1 CGM Reference Clock 93 7 2 2 TBM Reference Clock Selection 94 7 3 Internal 94 7 4 RC 95 Jor lg DSi Ub Eo RR CR d 96 5 ESS 97 7 5 1 Crystal Amplifier Input Pin OSC1 97 752 Crystal Amplifier Output Pin 05 2 98 7 6 3 Oscillator Enable Signal SIMOSCEN 98 7 6 4 CGM Oscillator Clock 98 7 5 5 CGM Reference Clock 98 7 6 6 Oscillator Clock to Time Base Module OSCCLK 98 7 7 Low Power Modes 98 7 7 1 Wait Mode 99 I cred SUM CIT TP 99 7 8 Oscillator During Break 99 Section 8 Clock Generator Module CGM 8 1
171. KBIEO Write Reset 0 0 0 0 0 0 0 0 Figure 20 4 Keyboard Interrupt Enable Register KBIER KBIE7 KBIEO Keyboard Interrupt Enable Bits Each of these read write bits enables the corresponding keyboard interrupt pin to latch interrupt requests Reset clears the keyboard interrupt enable register 1 KBlx pin enabled as keyboard interrupt pin 0 KBIx pin not enabled as keyboard interrupt pin Data Sheet MC68HC908AP Family Rev 2 5 392 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt Module Low Power Modes 20 6 Low Power Modes 20 6 1 Wait Mode 20 6 2 Stop Mode The WAIT and STOP instructions put the MCU in low power consumption standby modes The keyboard interrupt module remains active in wait mode Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode The keyboard interrupt module remains active in stop mode Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode 20 7 Keyboard Module During Break Interrupts The system integration module SIM controls whether the keyboard interrupt latch can be cleared during the break state The BCFE bit in the SIM break flag control register BFCR enables software to clear status bits during the break state To allow
172. L MC68HC908AP Family Rev 2 5 94 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Oscillator OSC RC Oscillator The internal oscillator by default is always available and is free running after POR or reset It can be turned off in stop mode by setting the STOP ICLKDIS bit before executing the STOP instruction Figure 7 4 shows the logical representation of components of the internal oscillator circuitry From SIM To Clock Selection MUX From SIM and COP SIMOSCEN ICLK BUS CLOCK CONFIG2 STOP ICLKDIS EN INTERNAL OSCILLATOR OSC2 Figure 7 4 Internal Oscillator 7 4 RC Oscillator The RC oscillator circuit is designed for use with an external resistor and a capacitor In its typical configuration the RC oscillator requires two external components one R and one C Component values should have a tolerance of 1 or less to obtain a clock source with less than 10 tolerance The oscillator configuration uses two components Cext Rext MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 95 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc fo Ko M 01103 From SIM To Clock Selection MUX From SIM SIMOSCEN BUS CLOCK CONFIG2 STOP_RCLKEN EN RC OSCILLATOR MCU OSC1 OSC2 See Section 24 for component value requirements VR
173. LK cycles e Low voltage inhibit LVI on Vpp LVl on VREG e LVI module reset LVI module in stop mode e STOP instruction e Stop mode recovery time 32 or 4096 cycles e Oscillator internal RC and crystal during stop mode e Serial communications interface clock source CGMXCLK or fgys The mask option register selects one of the following oscillator options e Internal oscillator RC oscillator Crystal oscillator MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 65 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Configuration amp Mask Option Registers Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 quration Register PS _ sTOP STOP 0 SCIBD Configuration Register 2 N XCLKEN OSCCLK1 OSCCLKO SRC 001D CONFIG2 t Write CLKDIS RCLKE Reset 0 0 0 0 0 0 0 0 Read Configuration Register 1 COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD 001F Write CONFIG1 t 9 Reset 0 0 0 0 0 0 0 0 Read Mask Option Register OSCSEL1 OSCSELO R R R R R R FFCF Write Erased 1 1 1 1 1 1 1 1 t One time writable register after each reset MOR is a non volatile FLASH register write by programming Unimplemented R Reserved Figure 5 1 CONFIG and MOR Registers Summary 5 2 Functional
174. LL VCO Range Select Register controls the hardware center of range frequency fyas VPR1 VPRO cannot be written when the PLLON bit is set Reset clears these bits Table 8 3 VPR1 and VPRO Programming and VPRO E Range Multiplier 00 0 1 01 1 2 10 2 4 NOTE Do not program E to a value of 3 8 5 2 PLL Bandwidth Control Register The PLL bandwidth control register PBWC e Selects automatic or manual software controlled bandwidth control mode e Indicates when the PLL is locked e In automatic bandwidth control mode indicates when the PLL is acquisition or tracking mode n manual operation forces the PLL into acquisition or tracking mode MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 119 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Address 0037 Bit 7 6 5 4 3 2 1 Bit 0 Read LOCK 0 0 0 0 AUTO ACQ R Write Reset 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 8 5 PLL Bandwidth Control Register PBWCR AUTO Automatic Bandwidth Control Bit This read write bit selects automatic or manual bandwidth control When initializing the PLL for manual operation AUTO 0 clear the ACQ bit before turning on the PLL Reset clears the AUTO bit 1 Automatic bandwidth control 0 Manual bandwidth control LOCK Lock Indicator B
175. MDTR Load Data2 to MMDTR Load dummy FF to MMDTR Figure 16 20 SMBus Protocol Implementation MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA For More Information On This Product Go to www freescale com 343 Freescale Semiconductor Inc Multi Master IIC Interface MMIIC Data Sheet MC68HC908AP Family Rev 2 5 344 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 17 Analog to Digital Converter ADC 17 1 Introduction This section describes the analog to digital converter ADC The ADC is a 8 channel 10 bit linear successive approximation ADC 17 2 Features Features of the ADC module include Fourteen channels with multiplexed input High impedance buffered input Linear successive approximation with monotonicity 10 bit resolution Single or continuous conversion Auto scan conversion on four channels Conversion complete flag or conversion complete interrupt Selectable ADC clock Conversion result justification MC68HC908AP Family Rev 2 5 8 bit truncated mode Right justified mode Left justified mode Left justified sign mode Data Sheet MOTOROLA 345 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Converter ADC
176. MMAST bit to enter master mode The MMRW bit determines the transfer direction of the data bytes that follows When itis 1 the module is in master receive mode When it is 0 the module is in master transmit mode Reset clears this bit 1 Master mode receive 0 Master mode transmit MMCRCEF MMIIC CRC Error Flag This flag is set when a CRC error is detected and cleared when no CRC error is detected The MMCRCEF is only meaningful after receiving a PEC data This flag is unaffected by reset 1 CRC error detected on PEC byte 0 No CRC error detected on PEC byte MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 331 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC 16 6 4 MMIIC Status Register MMSR Data Sheet Address 004B Bit 7 6 5 4 3 2 1 Bit 0 Read MMRXIF MMTXIF MMATCH MMSRW MMCRCBF MMTXBE MMRXBF Write 0 0 Reset 0 0 0 0 1 0 1 0 Unimplemented Figure 16 7 MMIIC Status Register MMSR MMRXIF MMIIC Receive Interrupt Flag This flag is set after the data receive register MMDRR is loaded with a new received data Once the MMDRR is loaded with received data no more received data can be loaded to the MMDRR register until the CPU reads the data from the MMDRR to clear MMRXBF flag MMRXIF generates an interrupt request to CPU if the MMIEN
177. MMNAKIF generates an interrupt request to CPU if the MMIEN bit in MMCR1 is set This bit is cleared by writing O to it or by reset 1 No acknowledge bit detected 0 Acknowledge bit detected MMBB MMIIC Bus Busy Flag This flag is set after a start condition is detected bus busy and is cleared when a stop condition bus idle is detected or the MMIIC is disabled Reset clears this bit 1 Start condition detected 0 Stop condition detected or MMIIC is disabled Data Sheet MC68HC908AP Family Rev 2 5 330 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC MMIIC Registers MMAST MMIIC Master Control This bit is set to initiate a master mode transfer In master mode the module generates a start condition to the SDA and SCL lines followed by sending the calling address stored in MMADR When the MMAST bit is cleared by MMNAKIF set no acknowledge or by software the module generates the stop condition to the lines after the current byte is transmitted If an arbitration loss occurs MMALIF 1 the module reverts to slave mode by clearing MMAST and releasing SDA and SCL lines immediately This bit is cleared by writing O to it or by reset 1 Master mode operation 0 Slave mode operation MMRW MMIIC Master Read Write This bit is transmitted out as bit O of the calling address when the module sets the
178. MMSRW 1 when the calling master is reading data from the module slave transmit mode MMSRW 0 when the master is writing data to the module receive mode 1 Slave mode transmit 0 Slave mode receive MMRXAK MMIIC Receive Acknowledge When this bit is cleared it indicates an acknowledge signal has been received after the completion of eight data bits transmission on the bus When MMRXAK is set it indicates no acknowledge signal has been detected at the 9th clock the module will release the SDA line for the master to generate STOP or repeated START condition Reset sets this bit 1 No acknowledge signal received at 9th clock 0 Acknowledge signal received at 9th clock MMCRCBF CRC Data Buffer Full Flag This flag is set when the CRC data register MMCRCDR is loaded with a CRC byte for the current received or transmitted data In transmit mode after a byte of data has been sent MMTXIF 1 the MMCRCBF will be set when the CRC byte has been generated and ready in the MMCRCDR The content of the MMCRCDR should be copied to the MMDTR for transmission In receive mode the MMCRCBF is set when the CRC byte has been generated and ready in MMCRCDR for the current byte of received data The bit is cleared when the CRC data register is read Reset also clears this bit 1 Data ready in CRC data register MMCRCDR 0 Data not ready in CRC data register MMCRCDR MC68HC908AP Family Rev 2 5 Data
179. MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI I O Registers M Mode Character Length Bit This read write bit determines whether SCI characters are eight or nine bits long See Table 14 6 The ninth bit can serve as an extra stop bit as a receiver wakeup signal or as a parity bit Reset clears the M bit 1 9 bit SCI characters 0 8 bit SCI characters WAKE Wakeup Condition Bit This read write bit determines which condition wakes up the a logic 1 address mark in the most significant bit position of a received character or an idle condition on the RxD pin Reset clears the WAKE bit 1 Address mark wakeup 0 Idle line wakeup ILTY Idle Line Type Bit This read write bit determines when the SCI starts counting logic 1s as idle character bits The counting begins either after the start bit or after the stop bit If the count begins after the start bit then a string of logic 1s preceding the stop bit may cause false recognition of an idle character Beginning the count after the stop bit avoids false idle character recognition but requires properly synchronized transmissions Reset clears the ILTY bit 1 Idle character bit count begins after stop bit 0 Idle character bit count begins after start bit PEN Parity Enable Bit This read write bit enables the SCI parity function See
180. MSRW 1 or the previous data in the output circuit has be transmitted and the receiving master returns an acknowledge bit indicated by a received acknowledge bit MMRXAK 0 Data Sheet MC68HC908AP Family Rev 2 5 334 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC MMIIC Registers If the calling master does not return an acknowledge bit MMRXAK 1 the module will release the SDA line for master to generate a STOP or repeated START condition The data in the MMDTR will not be transferred to the output circuit until the next calling from a master The transmit buffer empty flag remains cleared MMTXBE 0 In master mode the data in MMDTR will be transferred to the output circuit when the module receives an acknowledge bit MMRXAK 0 after setting master transmit mode MMRW 0 and the calling address has been transmitted or the previous data in the output circuit has be transmitted and the receiving slave returns an acknowledge bit indicated by a received acknowledge bit MMRXAK 0 If the slave does not return an acknowledge bit MMRXAK 1 the master will generate a STOP or repeated START condition The data in the MMDTR will not be transferred to the output circuit The transmit buffer empty flag remains cleared MMTXBE 0 The sequence of events for slave transmit and master transmit are illust
181. Module BRK 23 1 Introduction This section describes the break module The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program 23 2 Features Features of the break module include e Accessible input output I O registers during the break interrupt e CPU generated break interrupts Software generated break interrupts e COP disabling during break interrupts MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 407 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK 23 3 Functional Description When the internal address bus matches the value written in the break address registers the break module issues a breakpoint signal to the CPU The CPU then loads the instruction register with a software interrupt instruction SWI after completion of the current CPU instruction The program counter vectors to FFFC and FFFD FEFC and FEFD in monitor mode The following events can cause a break interrupt to occur A CPU generated address the address in the program counter matches the contents of the break address registers e Software writes a logic 1 to the bit in the break status and control register When a CPU generated address matches the contents of the break address registers the break interrupt begins after the CPU completes its current instruction A return from
182. Module BRK 23 5 2 Break Address Registers The break address registers BRKH and BRKL contain the high and low bytes of the desired breakpoint address Reset clears the break address registers Address SFEOC Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 Figure 23 4 Break Address Register High BRKH Address SFEOD Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Figure 23 5 Break Address Register Low BRKL 23 5 3 SIM Break Status Register SIM break status register SBSR contains a flag to indicate that a break caused an exit from wait mode The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt Address Bit 7 6 5 4 3 2 1 Bit 0 Read SBSW R R R R R R R Write Note Reset 0 Note Writing a logic 0 clears SBSW R Reserved Figure 23 6 SIM Break Status Register SBSR Data Sheet MC68HC908AP Family Rev 2 5 412 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK Break Module Registers SBSW Break Wait Bit This status bit is set when a break interrupt causes an exit from wait mode or stop mode Clear SBSW by writing a logic O to it Reset clears SBSW 1
183. OROLA 85 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Table 6 1 Instruction Set Summary Sheet 6 of 8 Effect on one Operation Description CCR 9 2 3 S 8 5 o o vHilNzic 38 amp amp 5 MOV opropr DD 4E dddd 5 MOV Eden M pestination lt M scurce DIX 5E dd 4 Move 0 212 n MOV IMD 6E 4 MOV H X lt H X 1 IX D DIX DGD 7E Idd 4 MUL Unsigned multiply X A lt X x A 0 0 INH 42 5 NEGX INH 50 1 NEG oprX Negate Two s Complement X X 00 X 2 2 2 2 xi eo ff 4 NEG M 00 4M IX 70 3 NEG opr SP M 00 M SP1 9E60 lff 5 NOP No Operation None 9D 1 NSA Nibble Swap A lt 3 01 7 4 7 INH 62 3 ORA opr IMM AA iii 2 ORA opr DIR BA dd 3 ORA opr EXT CA hhll 4 ORA opr X 2 DA 4 ORA oprX Inclusive OR A and M A lt A M 0 712 EA f 3 ORA X IX FA 2 ORA opr SP SP1 9EEA 4 ORA opr SP SP2 9EDA ee ff 5 PSHA Push A onto Stack Push SP lt SP 1 87 2 5 Push H onto Stack Push SP lt SP 1 8 2 5 Push X onto
184. OTE Route Vss carefully for maximum noise immunity and place bypass capacitors as close as possible to the package 8 4 4 Oscillator Output Frequency Signal CGMXCLK CGMXCLK is the oscillator output signal It runs at the full speed of the oscillator and is generated directly from the crystal oscillator circuit the RC oscillator circuit or the internal oscillator circuit 8 4 5 CGM Reference Clock CGMRCLK CGMRCLK is a buffered version of CGMXCLK this clock is the reference clock for the phase locked loop circuit MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 115 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM 8 4 6 CGM VCO Clock Output CGMVCLK CGMVCLK is the clock output from the VCO 8 4 7 CGM Base Clock Output CGMOUT CGMOUT is the clock output of the CGM This signal goes to the SIM which generates the MCU clocks CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency CGMOUT is software programmable to be either the oscillator output CGMXCLK divided by two or the divided VCO clock CGMPCLK divided by two 8 4 8 CGM CPU Interrupt CGMINT CGMINT is the interrupt signal generated by the PLL lock detector 8 5 CGM Registers The following registers control and monitor operation of the CGM e PLL control register PCTL See 8 5 1 PLL Control Register e PLL bandwidth control register
185. OTOROLA For More Information On This Product Go to www freescale com 7 7 1 Wait Mode 7 7 2 Stop Mode Freescale Semiconductor Inc Oscillator OSC Oscillator During Break Mode The WAIT instruction has no effect on the oscillator module continues to drive to the clock generator module and OSCCLK continues to drive the timebase module The STOP instruction disables the x tal or the RC oscillator circuit and hence the CGMXCLK clock stops running For continuous x tal or RC oscillator operation in stop mode set the STOP XCLKEN for x tal or STOP RCLKEN for RC bit to logic 1 before entering stop mode The internal oscillator clock continues operation in stop mode It can be disabled by setting the STOP ICLKDIS bit to logic 1 before entering stop mode 7 8 Oscillator During Break Mode The oscillator continues to drive CGMXCLK when the device enters the break state MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 99 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc fo Ko M 6109 Data Sheet MC68HC908AP Family Rev 2 5 100 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family 8 1 Introduction 8 2 Features Section 8 Clock Generator Module CGM This section describes the clock generator module CGM The CGM generates the
186. OTOROLA 399 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Computer Operating Properly 21 8 COP Module During Break Mode The COP is disabled during a break interrupt when is present the RST pin Data Sheet MC68HC908AP Family Rev 2 5 400 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family 22 1 Introduction NOTE 22 2 Features Section 22 Low Voltage Inhibit LVI This section describes the low voltage inhibit LVI module The LVI module monitors the voltage on the Vpp pin and pin and can force a reset when Vpp voltage falls below or Vreg voltage falls below VTRIPF2 The Vpeg pin is the output of the internal voltage regulator and is guaranteed to meet operating specification as long as Vpp is within the MCU operating voltage The LVI feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application Vpp voltage collapsing completely to an unsafe level It is not intended that users operate the microcontroller at lower than the specified operating voltage VDD Features of the LVI module include e Independent voltage monitoring circuits for and VREG e Independent disable for Vpp and LVI circuits e Programmable LVI reset e Progra
187. PWM signals use the following initialization procedure 1 In the TIM status and control register TSC a Stop the TIM counter by setting the TIM stop bit TSTOP b Reset the TIM counter and prescaler by setting the TIM reset bit TRST 2 Inthe TIM counter modulo registers TMODH TMODL write the value for the required PWM period Inthe TIM channel x registers TCHxH TCHXL write the value for the required pulse width 4 channel x status and control register TSCx a Write 0 1 for unbuffered output compare or PWM signals or 1 0 for buffered output compare or PWM signals to the mode select bits MSxB MSxA See Table 11 3 b Write 1 to the toggle on overflow bit TOVx c Write 1 0 to clear output on compare or 1 1 to set output on compare to the edge level select bits ELSxB ELSxA The output action on compare must force the output to the complement of the pulse width level See Table 11 3 NOTE PWM signal generation do not program the PWM channel to toggle on output compare Toggling on output compare prevents reliable 0 duty cycle generation and removes the ability of the channel to self correct in the event of software error or noise Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new much larger value 5 Inthe TIM status control register TSC clear the TIM stop bit TSTOP MC68HC908AP Family Rev 2 5 Data Shee
188. R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 9 14 Interrupt Status Register 3 INT3 IF21 IF15 Interrupt Flags 21 15 These flags indicate the presence of an interrupt request from the source shown in Table 9 3 1 Interrupt request present 0 No interrupt request present Data Sheet MC68HC908AP Family Rev 2 5 144 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Exception Control 9 5 2 Reset All reset sources always have equal and highest priority and cannot be arbitrated 9 5 3 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break interrupt output See Section 23 Break Module BRK The SIM puts the CPU into the break state by forcing it to the SWI vector location Refer to the break interrupt subsection of each module to see how each module is affected by the break state 9 5 4 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit BCFE in the SIM break flag control register SBFCR Protecting flags in break mode ensures that set flags will not be cleared while in break mode This protection allows registers to be
189. R bit is at logic 1 the value in the port data latch is read 17 3 2 Voltage Conversion When the input voltage to the ADC equals the ADC converts the signal to 3FF full scale If the input voltage equals ADC converts it to 000 Input voltages between Vper a straight line linear conversion All other input voltages will result in 3FF if greater than and 000 if less than NOTE Input voltage should not exceed the analog supply voltages MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 347 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Converter ADC INTERNAL DATA BUS a READ DDRAx 4 WRITE DDRAx gt DISABLE RESET DDRAx e WRITE PTA 3 PTAx PTAx ADCx READ PTAx ra ADCO ADC7 8 CHANNELS ADC DATA REGISTERS DISABLE ADRHO ADRLO ADRL1 ADRL2 VREFH 2 ADRL3 VREFL ADC CONVERSION VOLTAGE IN INTERRUPT COMPLETE VapiN CHANNEL LOGIC t TOBIT ADOS SELECT AIEN COCO oon MUX 4 CGMXCLK 9 ciock BUS CLOCK GENERATOR ADCH 4 0 ADIV 2 0 ADICLK 2 BIT UP COUNTER 44 auToj1 0
190. ROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Functional Description The maximum percent difference between the receiver count and the transmitter count of a slow 9 bit character with no errors is 9 163 170 x 100 4 12 Fast Data Tolerance Figure 13 8 shows how much a fast received character can be misaligned without causing a noise error or a framing error The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8 RT9 and RT10 STOP OR NEXT CHARACTER RECEIVER RT CLOCK RT RT2 RT3 RT4 RT5 RT6 RT7 RT8 T RT10 RT11 RT12 RT13 RT14 RT15 RT16 DATA SAMPLES Figure 13 8 Fast Data For an 8 bit character data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles 10 RT cycles 154 RT cycles With the misaligned character shown in Figure 13 8 the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles 160 RT cycles The maximum percent difference between the receiver count and the transmitter count of a fast 8 bit character with no errors is 55 44 x 100 3 9096 154 For 9 bit character data sampling of the stop bit takes the receiver 10 bit times x 16
191. RT INITIALISATION MOV MOV LDHX STHX RTS MAIN BSR LDHX JSR MC68HC908AP Family Rev 2 5 Monitor ROM MON ROM Resident Routines ORG RAM DS B 1 Indicates 4x bus frequency DS B T Data size to be programmed DS W 1 FLASH start address DS B 64 Reserved data array EQU SFC34 EQU SEEOO ORG FLASH 20 BUS_SPD 64 DATASIZE FLASH START START ADDR INITIALISATION FILE PTR PRGRNGE Data Sheet MOTOROLA 171 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor 10 5 2 ERARNGE Data Sheet ERARNGE is used to erase a range of locations in FLASH Table 10 12 ERARNGE Routine Routine Name ERARNGE Routine Description Erase a page or the entire array Calling Address FCE4 Stack Used 9 bytes Data Block Format Bus speed BUS_SPD Data size DATASIZE Starting address ADDRH Starting address ADDRL There are two sizes of erase ranges a page or the entire array The ERARNGE will erase the page 512 consecutive bytes in FLASH specified by the address ADDRH ADDRL This address can be any address within the page Calling ERARNGE with ADDRH ADDRL equal to FFFF will erase the entire FLASH array mass erase Therefore care must be taken when calling this routine to prevent an accidental mass erase The ERARNGE routine do not use a data array The DATASIZE byte is a dummy byte
192. RT cycles 10 RT cycles 170 RT cycles With the misaligned character shown in Figure 13 8 the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles 176 RT cycles MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 227 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface The maximum percent difference between the receiver count and the transmitter count of a fast 9 bit character with no errors is 9 1 9 x 100 3 5396 13 4 3 6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple receiver systems the receiver can be put into a standby state Setting the receiver wakeup bit RWU in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled Depending on the state of the WAKE bit in SCC1 either of two conditions on the RxD pin can bring the receiver out of the standby state e Address mark An address mark is a logic 1 in the most significant bit position of a received character When the WAKE bit is set an address mark wakes the receiver from the standby state by clearing the RWU bit The address mark also sets the SCI receiver full bit SCRF Software can then compare the character containing the address mark to the user defined address of the receiver If they are the same the receiver remains aw
193. Read 003F Unimplemented Write Reset H LOOPS ENSCI WAKE ILTY PEN PTY IRSCI Control Register 1 0040 IRSCC1 Write Reset 0 0 0 0 0 0 0 0 bids SCTIE TCIE SCRIE ILIE TE RE RWU SBK IRSCI Control Register2 0041 IRSCC2 Write Reset 0 0 0 0 0 0 0 0 bs is T8 DMARE DMATE ORIE NEIE FEIE PEIE IRSCI Control Register 3 0042 IRSCC3 Write Reset U U 0 0 0 0 0 0 Read SCTE TC SCRF IDLE OR NF FE PE IRSCI Status Register 1 0043 IRSCS1 Write Reset 1 1 0 0 0 0 0 0 Read BKF RPF IRSCI Status Register 2 0044 IRSCS2 Write Reset 0 0 0 0 0 0 0 0 Read R7 R6 R5 R4 R3 R2 R1 RO IRSCI Data Register 0045 IRSCDR Write T7 T6 T5 T4 T3 T2 T1 TO Reset Unaffected by reset U Unaffected X Indeterminate Unimplemented R Reserved Figure 2 2 Control Status and Data Registers Sheet 7 of 12 Data Sheet MC68HC908AP Family Rev 2 5 44 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Input Output I O Section Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 dd CKS SCP1 SCPO R SCR2 SCR1 SCRO IRSCI Baud Rate Register 0046 IRSCBR Write Reset 0 0 0 0 0 0 0 0 IRSCI Infrared Control Poad R i 0 0 R TNP1 TNPO IREN 0047 Register Write RSCIRCR Reset 0 0 0 0 0 0 0 0 1 Read Address Register MMAD7 MMAD6 MMADS MMAD4 MMAD3 MMAD
194. Reset R7 T7 RO TO Receive Transmit Data Bits Unaffected by reset Figure 14 18 IRSCI Data Register IRSCDR Reading the IRSCDR accesses the read only received data bits R7 RO Writing to the IRSCDR writes the data to be transmitted T7 TO Reset has no effect on the IRSCDR NOTE not use read modify write instructions on the IRSCI data register MC68HC908AP Family Rev 2 5 284 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI I O Registers 14 10 7 IRSCI Baud Rate Register The baud rate register selects the baud rate for both the receiver and the transmitter Address 0046 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 CKS SCP1 SCPO R SCR2 SCR1 SCRO Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 14 19 IRSCI Baud Rate Register IRSCBR CKS Baud Clock Input Select This read write bit selects the source clock for the baud rate generator Reset clears the CKS bit selecting CGMXCLK 1 Bus clock drives the baud rate generator 0 CGMXCLK drives the baud rate generator SCP1 and SCPO SCI Baud Rate Prescaler Bits These read write bits select the baud rate prescaler divisor as shown in Table 14 7 Reset clears SCP1 and SCPO Table 14 7 SCI Baud Rate Prescaling SCP1 and SCPO Prescaler Divisor PD 00 1
195. Rev 2 5 290 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Functional Description 15 4 Functional Description Figure 15 2 shows the structure of the SPI module INTERNAL BUS TRANSMIT DATA REGISTER CGMOUT 2 SHIFT REGISTER FROM SIM 514 3 2 MISO RECEIVE DATA REGISTER T gt MOSI CLOCK DIVIDER SPSCK SELECT RESERVED TRANSMITTER CPU INTERRUPT REQUEST SPI lt RESERVED CONTROL ET RECEIVER ERROR CPU INTERRUPT REQUEST Figure 15 2 SPI Module Block Diagram The SPI module allows full duplex synchronous serial communication between the MCU and peripheral devices including other MCUs Software can poll the SPI status flags or SPI operation can be interrupt driven The following paragraphs describe the operation of the SPI module MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 291 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI 15 4 1 Master Mode Data Sheet NOTE The SPI operates in master mode when the SPI master bit SPMSTR is set Configure the SPI modules as master or slave before enabling them Enable the master SPI before enabling the slave SPI Disable the slave SPI befo
196. Routine Routine Name MON ERARNGE Routine Description Erase a page or the entire array in monitor mode Calling Address FF28 Stack Used 11 bytes Data Block Format Bus speed Data size Starting address high byte Starting address low byte The MON_ERARNGE routine is designed to be used in monitor mode It performs the same function as the ERARNGE routine see 10 5 2 ERARNGE except that MON_ERARNGE returns to the main program via an SWI instruction After a MON_ERARNGE call the SWI instruction will return the control back to the monitor code MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 175 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor 10 5 6 EE WRITE Data Sheet EE WRITE is used to write a set of data from the data array to FLASH Table 10 16 EE WRITE Routine Routine Name EE WRITE Emulated EEPROM write Data size ranges from 7 to 15 Routine Description bytes at a time Calling Address FF36 Stack Used 30 bytes Data Block Format Bus speed BUS_SPD Data size DATASIZE Starting address ADDRH Starting address ADDRL Data 1 Data N Notes 1 The minimum data size is 7 bytes The maximum data size is 15 bytes 2 The start address must be a page boundary start address The start location of the FLASH to be programmed is specified by the address A
197. S ENSCI PTY DATA SELECTION CONTROL RECEIVE FLAG TRANSMIT CONTROL CONTROL CONTROL Figure 13 1 SCI Module Block Diagram SCI DATA REGISTER TRANSMIT m SHIFT REGISTER MC68HC908AP Family Rev 2 5 214 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Serial Communications Interface Module SCI Functional Description Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read SCI Control Register 1 Weis LOOPS ENSCI TXINV M WAKE ILTY PEN PTY SCC1 Reset 0 0 0 0 0 0 0 0 Read T SCI Control Register 2 T SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCC2 Reset 0 0 0 0 0 0 0 0 Read R8 6 T8 DMARE DMATE RIE NEIE FEIE PEIE 0015 SCI Control Register 3 Write SCC3 Reset U U 0 0 0 0 0 0 Read SCTE TC SCRF IDLE OR NF FE PE SCI Status Register 1 0016 SCS1 Write Reset 1 1 0 0 0 0 0 0 Read BKF RPF SCI Status Register2 0017 552 Write Reset 0 0 0 0 0 0 0 0 Read R7 R6 R5 R4 R3 R2 R1 RO SCI Data Register 0018 SCDR Write 7 T6 T5 T4 T3 T2 T1 TO Reset Unaffected by reset Read 0 0 SCP1 SCPO R SCR2 SCR1 SCRO 0019 SCI Baud Rate Register Write SCBR Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved U
198. S2 RDS1 RDSO Write Reset 0 0 0 0 0 0 0 1 Unimplemented Figure 8 9 PLL Reference Divider Select Register PMDS RDS 3 0 Reference Divider Select Bits These read write bits control the modulo reference divider that selects the reference division factor R See 8 3 3 PLL Circuits and 8 3 6 Programming the PLL RDS 3 0 cannot be written when the PLLON bit in the PCTL is set A value of 00 in the reference divider select register configures the reference divider the same as a value of 01 See 8 3 7 Special Programming Exceptions Reset initializes the register to 01 for a default divide value of 1 NOTE The reference divider select bits have built in protection such that they cannot be written when the PLL is on PLLON 1 NOTE The default divide value of 1 is recommended for all applications MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 123 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM 8 6 Interrupts NOTE When the AUTO bit is set in the PLL bandwidth control register PBWC the PLL can generate a CPU interrupt request every time the LOCK bit changes state The PLLIE bit in the PLL control register PCTL enables CPU interrupts from the PLL PLLF the interrupt flag in the PCTL becomes set whether interrupts are enabled or not When the AUTO bit is clear CPU interrupts from the PLL are disabled and PLLF
199. STRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH CLEAR STAGES 5 12 COP TIMEOUT COPCTL WRITE COP CLOCK COPEN FROM SIM COP DISABLE 6 BIT COP COUNTER COPD FROM CONFIG1 RESET COPCTL WRITE J COP COUNTER COP RATE SEL COPRS FROM CONFIG1 Figure 21 1 COP Block Diagram MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 395 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Computer Operating Properly NOTE NOTE 21 3 1 0 Signals 21 3 1 The COP counter is free running 6 bit counter preceded by a 12 bit prescaler counter If not cleared by software the COP counter overflows and generates an asynchronous reset after 219 2 or 213 2 CLK cycles depending on the state of the COP rate select bit COPRS in the register With a 213 2 cycle overflow option a 24 kHz gives a COP timeout period of 341 ms Writing any value to location FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the prescaler Service the COP immediately after reset and before entering or after exiting STOP Mode to guarantee the maximum time before the first COP counter overflow A COP reset pulls the RST pin low for 32 ICLK cycles and sets the COP bit in the SIM reset status register SRSR In monitor mode the
200. Section 1 General Description The MC68HC908AP64 is a member of the low cost high performance M68HCO08 Family of 8 bit microcontroller units MCUs The M68HC08 Family is based on the customer specified integrated circuit CSIC design strategy All MCUs in the family use the enhanced M68HCO08 central processor unit CPU08 and are available with a variety of modules memory sizes and types and package types Table 1 1 Summary of Device Variations Device ROR eu id Se Size MC68HC908AP64 2 048 62 368 MC68HC908AP32 2 048 32 768 MC68HC908AP16 1 024 16 384 MC68HC908AP8 1 024 8 192 Features of the MC68HC908AP64 include the following e High performance M68HCO8 architecture e Fully upward compatible object code with M6805 M146805 and M68HC05 Families e Maximum internal bus frequency 8 MHzat 5V or 3V operating voltage e Clock input options RC oscillator 32 kHz crystal oscillator with 32 MHZ internal phase lock loop MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA For More Information On This Product Go to www freescale com 23 Freescale Semiconductor Inc General Description e User program FLASH memory with security feature 62 368 bytes for MC68HC908AP64 32 768 bytes for MC68HC908AP32 16 384 bytes for MC68HC908AP16 8 192 bytes for MC68HC908AP8 e On chip RAM 2 048 bytes for MC68HC908AP64 and MC68HC908AP32 1 024 bytes for MC68
201. Section 22 Low Voltage Inhibit LVI 1 LVI circuit disabled 0 LVI circuit enabled NOTE IfLVIPWRD 1 and LVIREGD 1 set LVIRSTD 1 before entering stop mode SSREC Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK cycle delay 1 Stop mode recovery after 32 ICLK cycles 0 Stop mode recovery after 4096 ICLK cycles NOTE Exiting stop mode by pulling reset will result in the long stop recovery If using an external crystal oscillator do not set the SSREC bit When the LVI is disabled stop mode LVISTOP 0 the system stabilization time for long stop recovery 4096 ICLK cycles gives a delay longer than the LVI s turn on time There is no period where the MCU is not protected from a low power condition However when using the short stop recovery configuration option the 32 ICLK delay is less than the LVI s turn on time and there exists a period in start up where the LVI is not protecting the MCU STOP STOP Instruction Enable Bit STOP enables the STOP instruction 1 STOP instruction enabled 0 STOP instruction treated as illegal opcode Data Sheet MC68HC908AP Family Rev 2 5 68 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Configuration amp Mask Option Registers CONFIG amp MOR Configuration Register 2 CONFIG2 COPD COP Disable Bit COPD
202. Sheet MOTOROLA 333 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC MMTXBE MMIIC Transmit Buffer Empty This flag indicates the status of the data transmit register MMDTR When the CPU writes the data to the MMDTR the MMTXBE flag will be cleared MMTXBE is set when MMDTR is emptied by a transfer of its data to the output circuit Reset sets this bit 1 Data transmit register empty 0 Data transmit register full MMRXBF MMIIC Receive Buffer Full This flag indicates the status of the data receive register MMDRR When the CPU reads the data from the MMDRR the MMRXBF flag will be cleared MMRXBF is set when MMDRR is full by a transfer of data from the input circuit to the MMDRR Reset clears this bit 1 Data receive register full 0 Data receive register empty 16 6 5 MMIIC Data Transmit Register MMDTR Address 004 Bit 7 6 5 4 3 2 1 Bit 0 MMTD7 MMTD6 5 MMTD4 MMTD3 MMTD2 MMTD1 MMTDO Reset 0 0 0 0 0 0 0 0 Figure 16 8 MMIIC Data Transmit Register MMDTR When the MMIIC module is enabled MMEN 1 data written into this register depends on whether module is in master or slave mode In slave mode the data in MMDTR will be transferred to the output circuit when the module detects a matched calling address MMATCH 1 with the calling master requesting data M
203. Stack Push X SP lt SP 1 89 2 PULA Pull A from Stack SP lt SP 1 Pull A INH 86 2 PULH Pull H from Stack SP lt SP 1 Pull H INH 8A 2 PULX Pull X from Stack SP lt SP 1 Pull X INH 88 2 ROL opr DIR 39 dd 4 ROLA INH 49 1 ROLX INH 59 1 Rotate Left through Carry C m 2 1 21 7 ROLX i B x is ROL opr SP SP1 9E69 ff 5 ROR opr DIR 36 dd 4 RORA INH 46 1 RORX INH 56 1 Rotate Right through Carry Es 2 71 ROR X bo x opr SP SP1 9E66 ff 5 RSP Reset Stack Pointer SP lt FF 9 1 Data Sheet MC68HC908AP Family Rev 2 5 86 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Opcode Map Table 6 1 Instruction Set Summary Sheet 7 of 8 Effect on Operation Description CCR 9 3 S 9 Form 5 3 9 E 5 lt SP lt SP 1 Pull CCR SP lt SP 1 Pull A RTI Return from Interrupt SP lt SP 1 Pull X INH 80 7 SP lt SP 1 Pull PCH SP lt SP 1 Pull PCL gt SP lt SP 1 Pull PCH RTS Return from Subroutine SP lt SP 1 Pull PCL INH 81 4 SBC opr IMM A2 2 SBC opr DIR B2 dd 3 SBC opr EXT C2 hhil 4 SBC opr X IX2 02 4 SBC oprX Subtract
204. Stop mode or wait mode was exited by break interrupt 0 Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break interrupt routine The user can modify the return address on the stack by subtracting 1 from it The following code is an example This code works if the H register has been pushed onto the stack in the break Service routine software This code should be executed at the end of the break Service routine software HIBYTE EQU 5 LOBYTE EQU 6 i If not SBSW do RTI BRCLR SBSW SBSR RETURN See if wait mode or stop mode was exited by break TST LOBYTE SP If RETURNLO is not zero BNE DOLO then just decrement low byte DEC HIBYTE SP Else deal with high byte too DOLO DEC LOBYTE SP Point to WAIT STOP opcode RETURN PULH Restore H register RTI MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 413 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK 23 5 4 SIM Break Flag Control Register The SIM break flag control register SBFCR contains a bit that enables software to clear status bits while the MCU is in a break state Address FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read BCFE R R R R R R R Write Reset 0 R Reserved Figure 23 7 SIM Break Flag Control Register SBFCR BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by a
205. TED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE 4 DATUMS T U AND Z TO BE DETERMINED AT 0 200 AB T U Z nm DATUM PLANE AB 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 250 PER SIDE DIMENSIONS A AND B DO NCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0 350 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0 0076 A EXACT SHAPE OF EACH CORNER IS OPTIONAL MILLIMETERS DIM MIN MAX A 7 000 BSC A1 3 500 BSC B 7 000 BSC B1 3 500 BSC 1 400 1 600 DETAIL Y D 0 170 0270 4X E 1350 1450 F 0 170 0 230 0 200 AC T U 2 G 0 500 BSC H 0 050 0 150 J 0 090 0 200 K 0 500 0 700 L 19 5 0 080 AC M 12 REF N 0 090 0 160 P 0 250 BSC R 0 150 0 250 S 9 000 BSC 51 4 500 BSC 9 000 BSC Vi 4 500 BSC W 0 200 REF AA 1 000 REF M TOP amp BOTTOM lt N W 513 C E m 0 08
206. TOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Voltage Inhibit LVI Functional Description STOP INSTRUCTION LVISTOP i FROM CONFIG1 EM FROM CONFIG1 FROM CONFIG1 A LOW Vpp Vpp gt 0 DETECTOR vpp Vrae 1 LVI RESET LOW VREG VREG gt VrniPR2 0 DETECTOR Vaca lt 2 1 LVIOUT FROM CONFIG1 TO LVISR LVIREGD FROM CONFIG1 Bye LVISTOP STOP INSTRUCTION Figure 22 2 LVI Module Block Diagram Vpp 9 VREG 22 3 1 Low Vpp Detector The low Vpp detector circuit monitors the Vpp voltage and forces a LVI reset when the Vpp voltage falls below the trip voltage Vrpipr1 The LVI circuit can be disabled by the setting the LVIPWRD bit in CONFIG1 register 22 3 2 Low Detector The low Vpgg detector circuit monitors the Vngg voltage and forces a LVI reset when the voltage falls below the trip voltage Vtpipro LVI circuit can be disabled by the setting the LVIREGD bit in CONFIG1 register MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 403 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Voltage Inhibit LVI 22 3 3 Polled LVI Operation In applications that can operate at Vpp levels below the V pr pf1 level sof
207. Write 7 T6 T5 T4 T3 T2 T1 TO Reset Unaffected by reset Read 0 5046 IRSCI Baud Rate Register Vh CKS SCP1 SCPO R SCR2 SCR1 SCRO IRSCBR Reset 0 0 0 0 0 0 0 0 Read 0 0 0 IRSCI Infrared Control R R TNP1 TNPO IREN 0047 Register Write IRSCIRCR Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Figure 14 1 IRSCI I O Registers Summary MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 251 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications 14 3 Pin Name Conventions The generic names of the IRSCI I O pins are e RxD receive data e TxD transmit data IRSCI input output lines are implemented by sharing parallel I O port pins The full name of an IRSCI input or output reflects the name of the shared port pin Table 14 1 shows the full names and the generic names of the IRSCI I O pins The generic pin names appear in the text of this section Table 14 1 Pin Name Conventions Generic Pin Names RxD TxD Full Pin Names PTC7 SCRxD PTC6 SCTxD NOTE When the IRSCI is enabled the SCTxD pin is an open drain output and requires a pullup resistor to be connected for proper SCI operation 14 4 IRSCI Module Overview The IRSCI consists of a serial communications interface SCI and a infrared interface sub module as shown in Figure 14 2 lt INTERNAL BUS li SCI_TxD CGMXCLK
208. Writing a logic 0 clears SBSW R Reserved Figure 9 20 SIM Break Status Register SBSR SBSW Break Wait Bit This status bit is set when a break interrupt causes an exit from wait mode or stop mode Clear SBSW by writing a logic 0 to it Reset clears SBSW 1 Stop mode or wait mode was exited by break interrupt 0 Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break interrupt routine The user can modify the return address on the stack by subtracting 1 from it The following code is an example This code works if the H register has been pushed onto the stack in the break service routine software This code should be executed at the end of the break service routine software HIBYTE EQU 5 LOBYTE EQU 6 If not SBSW do RTI BRCLR SBSW SBSR RETURN See if wait mode or stop mode was exited by break TST LOBYTE SP If RETURNLO is not zero BNE DOLO then just decrement low byte DEC HIBYTE SP Else deal with high byte too DOLO DEC LOBYTE SP Point to WAIT STOP opcode RETURN PULH Restore H register RTI MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 149 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM 9 7 2 SIM Reset Status Register Data Sheet This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared Clear the
209. XCLK e Phase locked loop PLL The PLL generates the programmable VCO frequency clock CGMVCLK and the divided VCO clock CGMPCLK Base clock selector circuit This software controlled circuit selects either CGMXCLK divided by two or the divided VCO clock CGMPCLK divided by two as the base clock CGMOUT The SIM derives the system clocks from either CGMOUT or CGMXCLK Figure 8 1 shows the structure of the CGM Figure 8 2 is a summary of the CGM registers Data Sheet MC68HC908AP Family Rev 2 5 102 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Functional Description osts OSCILLATOR OSC MODULE See Section 7 Oscillator OSC ICLK INTERNAL OSCILLATOR OSCCLK CGMXCLK OSCSEL 1 0 gt RC OSCILLATOR MUX To ADC gt To SIM and COP To Timebase Module TBM CRYSTAL OSCILLATOR CGMRCLK OSCCLK 1 0 3 SIMOSCEN From SIM PHASE LOCKED LOOP PLL CGMRDV REFERENCE CGMRCLK DIVIDER CLOCK BCS SELECT ToSIM CIRCUIT RDS 3 0 WHEN 1 E CGMXFC Vssa CGMOUT B From SIM VPR 1 0 VRS 7 0 28 r 4
210. a Direction Register B DDRB Data direction register B determines whether each port B pin is an input or an output Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin a logic O disables the output buffer Address 0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 1 DDRBO Write Reset 0 0 0 0 0 0 0 0 Figure 18 7 Data Direction Register B DDRB DDRB 7 0 Data Direction Register B Bits These read write bits control port B data direction Reset clears DDRB 7 0 configuring all port B pins as inputs 1 Corresponding port B pin configured as output 0 Corresponding port B pin configured as input MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 371 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports Data Sheet Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from to 1 Figure 18 8 shows the port B logic READ DDRB 0005 WRITE DDRB 0005 e DDRBx 2 RESET E e WRITE PTB 0001 4 PTBx oc READ 0001 DA PTB3 PTBO are open drain pins when configured as outputs PTB7 PTB4 have schmitt trigger inputs Figure 18 8 Port B I O Circuit When DDRBx is a logic 1 reading address 0001 re
211. a Sheet MOTOROLA For More Information On This Product Go to www freescale com 357 Freescale Semiconductor Inc Converter ADC 17 7 3 ADC Data Register 0 ADRHO and ADRLO The ADC data register 0 consist of a pair of 8 bit registers high byte ADRHO and low byte ADRLO This pair form a 16 bit register to store the 10 bit ADC result for the selected ADC result justification mode In 8 bit truncated mode the ADRLO holds the eight most significant bits MSBs of the 10 bit result The ADRLO is updated each time an ADC conversion completes In 8 bit truncated mode ADRLO contains no interlocking with ADRHO See Figure 17 5 ADRHO and ADRLO in 8 Bit Truncated Mode Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 0 0 ADC Data Register HighO 0059 ADRHO Write R R R R R R R Reset 0 0 0 0 0 0 0 0 Read 9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data Register 0 gt oo oS Or 005A ADRLO Wr te R R R R R R R R Reset 0 0 0 0 0 0 0 0 Figure 17 5 ADRHO and ADRLO in 8 Bit Truncated Mode In right justified mode the ADRHO holds the two MSBs and the ADRLO holds the eight least significant bits LSBs of the 10 bit result ADRHO and ADRLO are updated each time a single channel ADC conversion completes Reading ADRHO latches the contents of ADRLO Until ADRLO is read all subsequ
212. a Sheet MOTOROLA 289 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI 15 3 Pin Name Conventions and I O Register Addresses The text that follows describes the SPI The SPI I O pin names are SS slave select SPSCK SPI serial clock CGND clock ground MOSI master out slave in and MISO master in slave out The SPI shares four I O pins with four parallel I O ports The full names of the SPI I O pins are shown in Table 15 1 The generic pin names appear in the text that follows Table 15 1 Pin Name Conventions SPI Generic a Pin Names MISO MOSI SS SPSCK CGND Full SPI sp PTC2 MISO PTC3 MOSI 4 55 PTC5 SPSCK V Pin Names SS Figure 15 1 summarizes the SPI I O registers Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read soo Control Register rtg SPRIE R 5 CPOL SPE SPTIE SPCR Reset 0 0 1 0 1 0 0 0 Read SPRF OVRF MODF SPTE SPI Status and Control ERRIE MODFEN SPR1 SPRO 0011 Register Write SPSCR Reset 0 0 0 0 1 0 0 0 Read R7 R6 R5 R4 R3 R2 R1 RO SPI Data Register 0012 SPDR Write T7 T6 T5 T4 2 T1 TO Reset Unaffected by reset Unimplemented R Reserved Figure 15 1 SPI I O Register Summary Data Sheet MC68HC908AP Family
213. a transfer can proceed byte by byte in the direction specified by the R W bit sent by the calling master Each data byte is 8 bits Data can be changed only when SCL is low and must be held stable when SCL is high as shown in Figure 16 2 The MSB is transmitted first and each byte has to be followed by an acknowledge bit This is signalled by the receiving device by pulling the SDA low on the 9th clock cycle Therefore one complete data byte transfer requires 9 clock cycles If the slave receiver does not acknowledge the master the SDA line should be left high by the slave The master can then generate a STOP signal to abort the data transfer or a START signal repeated START to commence a new transfer MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 323 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC If the master receiver does not acknowledge the slave transmitter after a byte has been transmitted it means an end of data to the slave The slave should release the SDA line for the master to generate a STOP or START signal 16 5 4 Repeated START Signal 16 5 5 STOP Signal As shown in Figure 16 2 a repeated START signal is used to generate START signal without first generating a STOP to terminate the communication This is used by the master to communicate with another slave or with the same slave in a different mode transmit recei
214. able The COPD signal reflects the state of the COP disable bit COPD in the CONFIG1 register See Figure 21 2 Configuration Register 1 CONFIG1 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 397 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Computer Operating Properly 21 3 8 COPRS COP Rate Select The COPRS signal reflects the state of the COP rate select bit COPRS in the CONFIG1 register Address 001F Bit 7 6 5 4 3 2 1 Bit 0 Read COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD Write Reset 0 0 0 0 0 0 0 0 Figure 21 2 Configuration Register 1 CONFIG1 COPRS COP Rate Select Bit COPRS selects the COP time out period Reset clears COPRS 1 COP time out period 213 2 cycles 0 COP time out period 218 2 cycles COPD COP Disable Bit COPD disables the COP module 1 COP module disabled 0 COP module enabled 21 4 COP Control Register The COP control register is located at address FFFF and overlaps the reset vector Writing any value to FFFF clears the COP counter and starts a new timeout period Reading location FFFF returns the low byte of the reset vector Address FFFF Bit 7 6 5 4 3 2 1 Bit 0 Read Low byte of reset vector Write Clear COP counter Reset Unaffected by reset Figure 21 3 COP Control Register COPCTL D
215. able bit SCRIE in SCC2 is also set the SCRF bit generates a receiver CPU interrupt request MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 221 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface INTERNAL BUS lt SCIBDSRC FROM CONFIG2 SCP SCI DATA REGISTER SCPO CGMXCLK a SE E PRE BAUD 712 gt 4 SCALER DIVIDER 11 BIT SL 0 gt X A RECEIVE SHIFT REGISTER 5 SL 1 gt X B DATA RxD RECOVERY 7161514131211 L ALL BKF wn 2 fe M RWU E 2 4 gt IDLE c gu ILTY gt Zu 5 PARITY E gt en PTY CHECKING ese IDLE ILIE ILIE C pe SCRIE DE l SCRF SCRIE DMARE OMARE OR OR ORIE FE EE an d FEIE mE PE pen PEIE Figure 13 5 SCI Receiver Block Diagram Data Sheet MC68HC908AP Family Rev 2 5 222 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communi
216. ads the PTBx data latch When DDRBx is a logic 0 reading address 0001 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 18 3 summarizes the operation of the port B pins Table 18 3 Port B Pin Functions Accesses to Accesses to i Read Write Read Write 0 x Input Hi Z DDRB 7 0 Pin 7 0 9 1 X Output DDRB 7 0 PTB 7 0 PTB 7 0 Notes 1 X don t care 2 Hi Z high impedance 3 Writing affects data register but does not affect input MC68HC908AP Family Rev 2 5 372 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output I O Ports Port C 18 4 Port C Port C is an 8 bit special function port that shares one of its pins with the IRQ2 four of its pins with the SPI module and two of its pins with the IRSCI module 18 4 1 Port C Data Register PTC The port C data register contains a data latch for each of the eight port C pins Address 0002 Bit 7 6 5 4 3 2 1 Bit 0 Read PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTCO Write Reset Unaffected by reset Alternative Function SCRxD SCTxD SPSCK SS MOSI MISO IRQ2 Figure 18 9 Port C Data Register PTC PTC 7 0 Port C Data Bits These read write bits are software programmable Data direction o
217. ake and processes the characters that follow If they are not the same software can set the RWU bit and put the receiver back into the standby state e Idle input line condition When the WAKE bit is clear an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit The idle character that wakes the receiver does not set the receiver idle bit IDLE or the SCI receiver full bit SCRF The idle line type bit ILTY determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit NOTE With the WAKE bit clear setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately Data Sheet MC68HC908AP Family Rev 2 5 228 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Functional Description 13 4 3 7 Receiver Interrupts The following sources can generate CPU interrupt requests from the SCI receiver e SCI receiver full SCRF The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR SCRF can generate a receiver CPU interrupt request Setting the SCI receive interrupt enable bit SCRIE in SCC2 enables the SCREF bit to generate receiver CPU interrupts Idle input IDLE The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted i
218. amily Rev 2 5 56 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FLASH Memory FLASH Control Register 4 3 FLASH Control Register The FLASH control register FLCR controls FLASH program and erase operation Address FE08 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 HVEN MASS ERASE PGM Write Reset 0 0 0 0 0 0 0 0 Figure 4 2 FLASH Control Register FLCR HVEN High Voltage Enable Bit This read write bit enables the charge pump to drive high voltages for program and erase operations in the array HVEN can only be set if either PGM 1 or ERASE 1 and the proper sequence for program or erase is followed 1 High voltage enabled to array and charge pump on 0 High voltage disabled to array and charge pump off MASS Mass Erase Control Bit This read write bit configures the memory for mass erase operation or page erase operation when the ERASE bit is set 1 Mass erase operation selected 0 Page erase operation selected ERASE Erase Control Bit This read write bit configures the memory for erase operation ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time 1 Erase operation selected 0 Erase operation not selected PGM Program Control Bit This read write bit configures the memory for program operation PGM is interlocked with the ERASE b
219. and other MCU sub systems is selected by programming the mask option register located at FFCF The reference clock for the timebase module TBM is selected by the two bits OSCCLK1 and OSCCLKO in the CONFIG2 register The internal oscillator runs continuously after a POR or reset and is always available The RC and crystal oscillator cannot run concurrently one is disabled while the other is selected because the RC and x tal circuits share the same OSC1 pin NOTE oscillator circuits are powered by the on chip Vreg regulator therefore the output swing on OSC1 and OSC2 is from Vss to VREG Figure 7 1 shows the block diagram of the oscillator module MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 91 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc fo Ko M 6109 To CGM and others To CGM PLL To TBM A A CGMXCLK CGMRCLK OSCCLK MOR CONFIG2 OSCSEL1 OSCSELO OSCCLK1 OSCCLKO To SIM and COP X TAL OSCILLATOR RC OSCILLATOR INTERNAL OSCILLATOR BUS CLOCK From SIM Figure 7 1 Oscillator Module Block Diagram 7 2 Clock Selection Reference clocks are selectable for the following sub systems CGMXCLK and CGMRCLK Reference clock for clock generator module CGM and other MCU sub systems other than TBM and COP This is the main reference clock for the M
220. ar in the text that follows Table 11 1 Pin Name Conventions TIM Generic Pin Names T 1 2 CHO T 1 2 CH1 Full TIM TIM1 PTB4 T1CHO PTB5S T1CH1 Pin Names TIM2 PTB6 T2CHO PTB7 T2CH1 References to either timer 1 or timer 2 may be made in the following text by omitting the timer number For example TCHO may refer generically to and T2CHO TCH1 may refer to T1CH1 2 1 11 4 Functional Description Data Sheet Figure 11 1 shows the structure of the TIM The central component of the TIM is the 16 bit TIM counter that can operate as a free running counter or a modulo up counter The TIM counter provides the timing reference for the input capture and output compare functions The TIM counter modulo registers TMODH TMODL control the modulo value of the TIM counter Software can read the TIM counter value at any time without affecting the counting sequence The two TIM channels per timer are programmable independently as input capture or output compare channels MC68HC908AP Family Rev 2 5 182 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM Functional Description PRESCALER SELECT
221. aracter Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress 1 Reception in progress 0 No reception in progress Data Sheet MC68HC908AP Family Rev 2 5 244 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI I O Registers 13 8 6 SCI Data Register The SCI data register SCDR is the buffer between the internal data bus and the receive and transmit shift registers Reset has no effect on data in the SCI data register Address 0018 Bit 7 6 5 4 3 2 1 Bit 0 Read R7 R6 R5 R4 R3 R2 R1 RO Write 7 T6 T5 T4 T3 T2 T1 TO Reset Unaffected by reset Figure 13 15 SCI Data Register SCDR R7 T7 RO TO Receive Transmit Data Bits Reading the SCDR accesses the read only received data bits R7 RO Writing to the SCDR writes the data to be transmitted T7 TO Reset has no effect on the SCDR NOTE not use read modify write instructions on the SCI data register MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 245 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface 13 8 7 SCI Baud Rate Register The baud rate register SCBR selects the baud rate for both the receiver and the transmitter Address 0019
222. at the MCU as Figure 1 5 shows Place the bypass capacitors as close to the MCU power pins as possible Use high frequency response ceramic capacitor for Cpu x are optional bulk current bypass capacitors for use in applications that require the port pins to source high current level VppA and are the power supply and ground pins for the analog circuits of the MCU These pins should be decoupled as per the digital power supply pins MCU Vpp Vss VDDA Vssa 4 5 C1 a C1 b 0 1 0 1 uF V V C2 a C2 b O E Ea NOTE Component values shown represent typical applications Figure 1 5 Power Supply Bypassing MC68HC908AP Family Rev 2 5 32 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description Regulator Power Supply Configuration VREG 1 7 Regulator Power Supply Configuration VREG is the output from the on chip regulator All internal logics except for the I O pads are powered by output requires an external ceramic bypass capacitor of 100 nF as Figure 1 6 shows Place the bypass capacitor as close to the pin as possible MCU VREG Vss CyREGBYPASS 100 nF Figure 1 6 Regulator Power Supply Bypassing MC68HC908AP Family Rev 2 5 Data Sheet 33 MOTOROLA For More Information On This Produ
223. ata Byte High STOP c Write Word Protocol START Slave Address Wack Command Code Data Byte Low Data Byte High PEC STOP d Write Word Protocol with PEC Figure 16 16 Write Byte Word 16 8 5 Read Byte Word START Slave Address Wack Command Code START Slave Address STOP a Read Byte Protocol START Slave Address w Command Code START Slave Address R PEC NAK STOP b Read Byte Protocol with PEC START Slave Address Wack Command Code START Slave Address Black Data Byte Low ACK Data Byte High NAK STOP c Read Word Protocol START Slave Address Wack Command Code START Slave Address Black Data Byte Low ACK Data Byte High ACK PEC STOP d Read Word Protocol with PEC Figure 16 17 Read Byte Word MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 341 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC 16 8 6 Process Calll START Slave Address Wack Command Code Data Byte Low ACK Data Byte High START Slave Address Black Data Byte Low ACK Data Byte High STOP a Process Call START Slave Address Wack Command Code Data Byte Low Data Byte High START Address Black Data Byte Low ACK Data Byte High ACK 5 NAK STOP b Process Call with PEC Figure 16 18 Process Call 16 8 7 Block Read Write START Slave Address w Command Code Byte Coun
224. ata Register 0 ADRHO and ADRLO 358 17 7 4 ADC Auto Scan Mode Data Registers ADRL1 ADRL3 360 17 7 5 ADC Auto Scan Control Register ADASCR 360 Section 18 Input Output Ports WUC CR nies bd at oo ed o dero 363 ING PUB Lb aa day Ea diam 366 18 21 Port A Data Register 366 MC68HC908AP Family Rev 2 5 18 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 18 2 2 Data Direction Register DDRA 367 18 23 Port A LED Control Register LEDA 369 lt lt POTE ele es 370 18 3 1 Port B Data Register 370 18 3 2 Data Direction Register B DDRB 371 TOME Earn rana o cac odd dede aae e Mec dee ed do ol ded d o ded 373 18 4 1 Port C Data Register 373 18 4 2 Data Direction Register C DDRC 374 INS PULL gente cae d xdi 376 18 5 1 Port D Data Register 376 18 5 2 Data Direction Register D DDRD 377 Section 19 External Interrupt IRQ 19 1 a ura ios oc wad ewe oe ed ak ee wee 379 192 TTL 379 19 3 Functional Description 380 19 4 and IRQ2 Ping soca oe kb gba Qua Es ERR ee ues 382 19 5 IRQ Module Dur
225. ata Sheet MC68HC908AP Family Rev 2 5 398 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Computer Operating Properly COP Interrupts 21 5 Interrupts The COP does not generate CPU interrupt requests 21 6 Monitor Mode When monitor mode is entered with on the 1 pin the COP is disabled as long as remains on the IRQ1 pin or the RST pin When monitor mode is entered by having blank reset vectors and not having on the IRQ1 pin the COP is automatically disabled until a POR occurs 21 7 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 21 7 1 Wait Mode The COP remains active during wait mode To prevent a COP reset during wait mode periodically clear the COP counter in a CPU interrupt routine 21 7 2 Stop Mode Stop mode turns off the ICLK input to the COP and clears the COP prescaler Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode To prevent inadvertently turning off the COP with a STOP instruction a configuration option is available that disables the STOP instruction When the STOP bit in the configuration register has the STOP instruction is disabled execution of a STOP instruction results in an illegal opcode reset MC68HC908AP Family Rev 2 5 Data Sheet M
226. ata not transferred to transmit shift register TC Transmission Complete Bit This read only bit is set when the SCTE bit is set and no data preamble or break character is being transmitted TC generates an SCI transmitter CPU interrupt request if the TCIE bit in IRSCC2 is also set TC is automatically cleared when data preamble or break is queued and ready to be sent There may be up to 1 5 transmitter clocks of latency between queueing data preamble and break and the transmission actually starting Reset sets the TC bit 1 No transmission in progress 0 Transmission in progress SCRF SCI Receiver Full Bit This clearable read only bit is set when the data in the receive shift register transfers to the SCI data register SCRF can generate an SCI receiver CPU interrupt request When the SCRIE bit in IRSCC2 is set SCRF generates a CPU interrupt request In normal operation clear the SCRF bit by reading IRSCS1 with SCRF set and then reading the IRSCDR Reset clears SCRF 1 Received data available in IRSCDR 0 Data not available in IRSCDR IDLE Receiver Idle Bit This clearable read only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in IRSCC2 is also set Clear the IDLE bit by reading IRSCS1 with IDLE set and then reading the IRSCDR After the receiver is enabled it must receive a valid character that sets the SCRF bi
227. ation subroutine is the same as the coding example for PRGRNGE see 10 5 1 PRGRNGE LDRNGE MAIN BSR LDHX JSR MC68HC908AP Family Rev 2 5 EQU SFCOO INITIALIZATION FILE PTR LDRNGE Data Sheet MOTOROLA 173 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor 10 5 4 PRGRNGE In monitor mode PRGRNGE is used to program range of FLASH locations with data loaded into the data array Table 10 14 MON PRGRNGE Routine Routine Name MON PRGRNGE Routine Description Program a range of locations in monitor mode Calling Address FF24 Stack Used 17 bytes Data Block Format Bus speed Data size Starting address high byte Starting address low byte Data 1 Data N The MON_PRGRNGE routine is designed to be used in monitor mode It performs the same function as the PRGRNGE routine see 10 5 1 PRGRNGE except that MON_PRGRNGE returns to the main program via an SWI instruction Aftera MON PRGRNGE call the SWI instruction will return the control back to the monitor code Data Sheet MC68HC908AP Family Rev 2 5 174 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON ROM Resident Routines 10 5 5 MON ERARNGE In monitor mode ERARNGE is used to erase a range of locations in FLASH Table 10 15 MON ERARNGE
228. base Register Description 12 4 Timebase Register Description The timebase has one register the TBCR which is used to enable the timebase interrupts and set the rate Address 0051 Bit 7 6 5 4 3 2 1 Bit 0 Read TBIF 0 TBR2 TBR1 TBRO TBIE TBON R Write TACK Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 12 2 Timebase Control Register TBCR TBIF Timebase Interrupt Flag This read only flag bit is set when the timebase counter has rolled over 1 Timebase interrupt pending 0 Timebase interrupt not pending TBR 2 0 Timebase Rate Selection These read write bits are used to select the rate of timebase interrupts as shown in Table 12 1 Table 12 1 Timebase Rate Selection for OSCCLK 32 768 kHz Timebase Interrupt Rate TBR2 TBR1 TBRO Divider Hz ms 0 0 0 262144 0 125 8000 0 0 1 131072 0 25 4000 0 1 0 65536 0 5 2000 0 1 1 32768 1 1000 1 0 0 64 512 2 1 0 1 32 1024 1 1 1 0 16 2048 0 5 1 1 1 8 4096 0 24 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 207 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Module TBM NOTE 12 5 Interrupts Data Sheet Do not change TBR 2 0 bits while the timebase is enabled TBON 1 TACK Timebase ACKnowledge The TACK bit is a write only bit and always reads as 0 Writing a
229. base clock signal CGMOUT which is based on either the oscillator clock divided by two or the divided phase locked loop PLL clock CGMPCLK divided by two CGMOUT is the clock from which the SIM derives the system clocks including the bus clock which is at a frequency of CGMOUT 2 The PLL is a frequency generator designed for use with a low frequency crystal typically 32 768kHz to generate a base frequency and dividing to a maximum bus frequency of 8MHz Features of the CGM include Phase locked loop with output frequency in integer multiples of an integer dividend of the crystal reference Low frequency crystal operation with low power operation and high output frequency resolution Programmable prescaler for power of two increases in frequency Programmable hardware voltage controlled oscillator VCO for low jitter operation Automatic bandwidth control mode for low jitter operation Automatic frequency lock detector CPU interrupt on entry or exit from locked condition Configuration register bit to allow oscillator operation during stop mode MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 101 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module 8 3 Functional Description The CGM consists of three major sub modules e Oscillator module The oscillator module generates the constant reference frequency clock CGMRCLK buffered CGM
230. base module remains active after execution of the WAIT instruction In wait mode the timebase register is not accessible by the CPU If the timebase functions are not required during wait mode reduce the power consumption by stopping the timebase before enabling the WAIT instruction 12 6 2 Stop Mode The timebase module may remain active after execution of the STOP instruction if the oscillator has been enabled to operate during stop mode through the stop mode oscillator enable bit STOP ICLKDIS STOP RCLKEN or STOP XCLKEN for the selected oscillator in the CONFIG2 register The timebase module can be used in this mode to generate a periodic walk up from stop mode If the oscillator has not been enabled to operate in stop mode the timebase module will not be active during stop mode In stop mode the timebase register is not accessible by the CPU If the timebase functions are not required during stop mode reduce the power consumption by stopping the timebase before enabling the STOP instruction MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 209 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Module TBM Data Sheet MC68HC908AP Family Rev 2 5 210 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 13 Serial Communications Interface
231. be recognized It is possible for a smaller pulse width to cause a reset 24 7 5V Oscillator Characteristics Table 24 6 Oscillator Specifications 5V For More Information On This Product Go to www freescale com Characteristic Symbol Min Typ Max Unit Internal oscillator clock frequency 16k 22k 2 26k Hz External reference clock to OSC1 9 fosc dc 16M Hz Crystal reference frequency XTALCLK 32k Hz Crystal load capacitance CL Crystal fixed capacitance C4 2 Crystal tuning capacitance 2 Feedback bias resistor Rp 10MO Series resistor Rs 100kQ External RC clock frequency RCCLK 7 6M Hz RC oscillator external R Rext See Figure 24 1 Q RC oscillator external C Cext 10 pF Notes 1 The oscillator circuit operates at Vngg 2 Typical value reflect average measurements at midpoint of voltage range 25 C only 3 No more than 10 duty cycle deviation from 50 The max frequency is limited by an EMC filter 4 Fundamental mode crystals only 5 Consult crystal vendor data sheet MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 419 Freescale Semiconductor Inc Electrical Specifications 24 8 5V ADC Electrical Characteristics Table 24 7 ADC Electrical Characteristics 5V Characteristic Symbol Min Max Unit Notes Vppa is
232. bled NEIE Receiver Noise Error Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the noise error bit NE Reset clears NEIE 1 SCI error CPU interrupt requests from NE bit enabled 0 SCI error CPU interrupt requests from NE bit disabled FEIE Receiver Framing Error Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the framing error bit FE Reset clears FEIE 1 SCI error CPU interrupt requests from FE bit enabled 0 SCI error CPU interrupt requests from FE bit disabled MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 239 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface PEIE Receiver Parity Error Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the parity error bit PE See 13 8 4 SCI Status Register 1 Reset clears PEIE 1 SCI error CPU interrupt requests from PE bit enabled 0 SCI error CPU interrupt requests from PE bit disabled 13 8 4 SCI Status Register 1 SCI status register 1 SCS1 contains flags to signal these conditions e Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete Receiver input idle e Receiver overrun e Noisy data e Framing error e Parity error Address 0016
233. c does not detect a logic 1 where the stop bit should be in an incoming character it sets the framing error bit FE in IRSCS1 The FE flag is set at the same time that the SCRF bit is set A break character that has no stop bit also sets the FE bit 14 6 3 5 Baud Rate Tolerance Data Sheet A transmitting device may be operating at a baud rate below or above the receiver baud rate Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit Then a noise error occurs If more than one of the samples is outside the stop bit a framing error occurs In most applications the baud rate tolerance is much more than the degree of misalignment that is likely to occur MC68HC908AP Family Rev 2 5 264 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI SCI Functional Description As the receiver samples an incoming character it resynchronizes the RT clock on any valid falling edge within the character Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times Slow Data Tolerance Figure 14 10 shows how much a slow received character can be misaligned without causing a noise error or a framing error The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8 RT9 and
234. cale Semiconductor Inc Central Processor Unit CPU Table 6 1 Instruction Set Summary Sheet 4 of 8 Effect on c Source Operation Description CCR 9 g S 9 Form 3 3 9 2 33 8 8 4 CMP opr IMM A1 jii 2 CMP opr DIR B1 dd 3 CMP opr EXT C1 hhli 4 CMP opr X IX2 D1 eeff 4 oprX Compare A with M A M xi E1 ff 3 CMP X IX F1 2 CMP opr SP SP1 9EE1 ff 4 CMP opr SP SP2 9ED1 5 COM opr M lt M FF M DIR 33 dd 4 COMA lt A FF M INH 43 1 COMX X lt X FF M INH 53 1 opr X Complement One s Complement M lt M FF 0 712 1 xi 63 m 4 COM X M lt FF M IX 73 3 COM opr SP M lt M FF M SP1 9E63 5 CPHX stopr Or KE m IMM 65 jiiii 1 3 CPHX opr Compare H X with M H X M M 1 TITIS DIR 75 lad 4 CPX stopr IMM A3 jii 2 CPX opr DIR B3 dd 3 CPX opr EXT C3 hhil 4 CPX X IX2 D3 jeeff 4 CPX opr X Compare X with M X M xi E3 f 3 CPX opr X IX F3 2 CPX opr SP SP1 4 CPX opr SP SP2 9ED3 jee ff 5 DAA Decimal Adjust A A 4o 1 1 1 1 INH 72 2 lt lt M 1 orX lt X 1 DBNZ opr rel PC lt 3 rel result 0 DIR 5 DBNZA rel PC lt 2 rel result 0 INH 4B 3 DBNZX rel Decrement and Branch if Not Zero PC lt
235. cations Interface Module SCI Functional Description 13 4 3 3 Data Sampling RxD The receiver samples the RxD pin at the RT clock rate The RT clock is an internal signal with a frequency 16 times the baud rate To adjust for baud rate mismatch the RT clock is resynchronized at the following times see Figure 13 6 e After every start bit e After the receiver detects a data bit change from logic 1 to logic 0 after the majority of data bit samples at RT8 RT9 and RT10 returns a valid logic 1 and the majority of the next RT8 RT9 and RT10 samples returns a valid logic 0 To locate the start bit data recovery logic does an asynchronous search for a logic O preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock begins to count to 16 START gt a LSB d of ttt START BIT START BIT DATA SAMPLES QUALIFICATION VERIFICATION SAMPLING RT CLOCK Hook x ecc opo Ecce poro eee STATE tr Gm tle ee Gm c c Gm rm m m cm m ele cm m cm RT CLOCK RESET oY VY Y Figure 13 6 Receiver Data Sampling MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 223 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
236. cations in FF24 17 monitor mode MON ERARNGE Erase a page or the entire array in FF28 11 monitor mode Emulated EEPROM write Data size EE WRITE ranges from 7 to 15 bytes at a time ED a0 Emulated EEPROM read Data size READ ranges from 7 to 15 bytes at a time arbor m The routines are designed to be called as stand alone subroutines in the user program or monitor mode The parameters that are passed to a routine are in the form of a contiguous data block stored in RAM The index register H X is loaded with the address of the first byte of the data block acting as a pointer and the subroutine is called JSR Using the start address as a pointer multiple data blocks can be used any area of RAM be used A data block has the control and data bytes in a defined order as shown in Figure 10 9 During the software execution it does not consume any dedicated RAM location the run time heap will extend the system stack all other RAM location will not be affected MC68HC908AP Family Rev 2 5 168 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON ROM Resident Routines FILE PTR R A M NNNM XXXX BUS SPEED BUS SPD ADDRESS AS POINTER DATA SIZE DATASIZE START ADDRESS HIGH ADDRH START ADDRESS LOW ADDRL DATA 0 DATA DATA 1 BLOCK DATA ARRAY i DATAN Figure 10 9 Data Block Format for ROM Resident Routine
237. ccessing status registers while the MCU is in a break state To clear status bits during the break state the BCFE bit must be set 1 Status bits clearable during break 0 Status bits not clearable during break Data Sheet MC68HC908AP Family Rev 2 5 414 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 24 Electrical Specifications 24 1 Introduction This section contains electrical and timing specifications 24 2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it NOTE This device is not guaranteed to operate properly at the maximum ratings Refer to DC Electrical Characteristics for guaranteed operating conditions Table 24 1 Absolute Maximum Ratings Characteristic Symbol Value Unit Supply voltage Vpp 0 3 to 6 0 V Input voltage All pins except IRQ1 Vin Vss 0 3 to Vpp 0 3 V IRQ1 pin Vag 0 3 to 8 5 V EO us Maximum current out of Vas IMvss 100 mA Maximum current into Vpp IMVDD 100 mA Storage temperature TsrG 55 to 150 Notes 1 Voltages referenced to Vas NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields however it is advised that normal precautions be taken to avoid application of any voltage h
238. ch remains set until one of the following actions occurs e Vector fetch A vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch Software clear Software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register INTSCR Writing a logic 1 to the ACK bit clears the IRQ latch Reset A reset automatically clears the interrupt latch The external interrupt pin is falling edge triggered and is software configurable to be either falling edge or falling edge and low level triggered The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin When an interrupt pin is edge triggered only the interrupt remains set until a vector fetch software clear or reset occurs When an interrupt pin is both falling edge and low level triggered the interrupt remains set until both of the following occur e Vector fetch or software clear e Return of the interrupt pin to logic 1 The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1 As long as the pin is low the interrupt request remains pending A reset will clear the latch and the MODE 1 control bit thereby clearing the interrupt even if the pin stays low When set the IMASK bit in the INTSCR mask all external interrupt requests A latched interrupt request is not presented to the interrupt
239. channel x pin When channel x is an output compare channel CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers When CPU interrupt requests are enabled CHxIE 1 clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a logic O to CHxF If another interrupt request occurs before the clearing sequence is complete then writing logic O to CHxF has no effect Therefore an interrupt request cannot be lost due to inadvertent clearing of CHxF Reset clears the CHxF bit Writing a logic 1 to CHxF has no effect 1 Input capture or output compare on channel x 0 No input capture or output compare on channel x CHxIE Channel x Interrupt Enable Bit This read write bit enables TIM CPU interrupt service requests on channel x Reset clears the CHxIE bit 1 Channel x CPU interrupt requests enabled 0 Channel x CPU interrupt requests disabled MSxB Mode Select Bit B This read write bit selects buffered output compare PWM operation MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and control registers Setting MSOB disables the channel 1 status and control register and reverts TCH1 to general purpose Reset clears the MSxB bit 1 Buffered output compare PWM operation enabled 0 Buffered output compare PWM operation disabled MSxA Mode Select Bit A When ELSxB ELSxA 0 0 this read write bit selects either in
240. characters with no logic 1s between them Reset clears the SBK bit 1 Transmit break characters 0 No break characters being transmitted NOTE not toggle the SBK bit immediately after setting the SCTE bit Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 237 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface 13 8 3 SCI Control Register 3 SCI control register 3 e Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted Enables these interrupts Receiver overrun interrupts Noise error interrupts Framing error interrupts e Parity error interrupts Address 0015 Bit 7 6 5 4 3 2 1 Bit 0 Read R8 T8 DMARE DMATE ORIE NEIE FEIE PEIE Write Reset U U 0 0 0 0 0 0 Unimplemented U Unaffected Figure 13 11 SCI Control Register 3 SCC3 R8 Received Bit 8 When the SCI is receiving 9 bit characters R8 is the read only ninth bit bit 8 of the received character R8 is received at the same time that the SCDR receives the other 8 bits When the SCI is receiving 8 bit characters R8 is a copy of the eighth bit bit 7 Reset has no effect on the R8 bit T8 Transmitted Bit 8 When the SCI is transmitting 9 bit characters T8 is the read wr
241. ck pointer 16 bit offset addressing mode ff Offset byte in indexed 8 bit offset addressing SP Stack pointer H Half carry bit U Undefined H Index register high byte V Overflow bit hh II High and low bytes of operand address in extended addressing X Index register low byte Interrupt mask Z Zero bit ii Immediate operand byte amp Logical AND IMD Immediate source to direct destination addressing mode Logical OR IMM Immediate addressing mode Logical EXCLUSIVE OR INH Inherent addressing mode Contents of IX Indexed no offset addressing mode Negation two s complement 1 Indexed no offset post increment addressing mode Immediate value IX D Indexed with post increment to direct addressing mode Sign extend 1 1 Indexed 8 bit offset addressing mode lt Loaded with IX1 Indexed 8 bit offset post increment addressing mode If IX2 Indexed 16 bit offset addressing mode Concatenated with M Memory location t Set or cleared N Negative bit affected Data Sheet MC68HC908AP Family Rev 2 5 88 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Opcode Map Ne L L e gt L L ax lt L lt Q E x 0 a lt QE Ox tn e L o ax NS N 2 7 x ul
242. com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI SCI Functional Description The maximum percent difference between the receiver count and the transmitter count of a fast 9 bit character with no errors is a x 100 3 53 170 14 6 3 6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple receiver systems the receiver can be put into a standby state Setting the receiver wakeup bit RWU in IRSCC2 puts the receiver into a standby state during which receiver interrupts are disabled Depending on the state of the WAKE bit in IRSCC1 either of two conditions on the RxD pin can bring the receiver out of the standby state e Address mark An address mark is a logic 1 in the most significant bit position of a received character When the WAKE bit is set an address mark wakes the receiver from the standby state by clearing the RWU bit The address mark also sets the SCI receiver full bit SCRF Software can then compare the character containing the address mark to the user defined address of the receiver If they are the same the receiver remains awake and processes the characters that follow If they are not the same software can set the RWU bit and put the receiver back into the standby state e Idle input line condition When the WAKE bit is clear an idle character on the RxD pin wakes the receiver from the standby state by clearing
243. communicate with a host computer via a standard RS 232 interface Simple monitor commands can access any memory address In monitor mode the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions All communication between the host computer and the MCU is through the PTAO pin A level shifting and multiplexing interface is required between PTAO and the host computer PTAO is used in a wired OR configuration and requires a pullup resistor The monitor code allows enabling the PLL to generate the internal clock provided the reset vector is blank when the device is being clocked by a low frequency crystal This entry method which is enabled when IRQ1 is held low out of reset is intended to support serial communication programming at 9600 baud in monitor mode by stepping up the external frequency assumed to be 32 768 kHz by a fixed amount to generate the desired internal frequency 2 4576 MHz Since this feature is enabled only when IRQ1 is held low out of reset it cannot be used when the reset vector is non zero because entry into monitor mode in this case requires on IRQ1 MC68HC908AP Family Rev 2 5 154 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Functional Description
244. ct Go to www freescale com Freescale Semiconductor Inc Converter ADC 17 4 Interrupts When the AIEN bit is set the ADC module is capable of generating a CPU interrupt after each ADC conversion or after an auto scan conversion cycle A CPU interrupt is generated if the COCO bit is at logic 0 The COCO bit is not used as a conversion complete flag when interrupts are enabled The interrupt vector is defined in Table 2 1 Vector Addresses 17 5 Low Power Modes 17 5 1 Wait Mode 17 5 2 Stop Mode 17 6 1 O Signals Data Sheet The STOP and WAIT instructions put the MCU in low power consumption standby modes The ADC continues normal operation in wait mode Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode If the ADC is not required to bring the MCU out of wait mode power down the ADC by setting the ADCH 4 0 bits to logic 1 s before executing the WAIT instruction The ADC module is inactive after the execution of a STOP instruction Any pending conversion is aborted ADC conversions resume when the MCU exits stop mode Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode The ADC module has eight channels shared with port A I O pins MC68HC908AP Family Rev 2 5 352 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
245. ct Go to www freescale com Freescale Semiconductor Inc General Description Data Sheet MC68HC908AP Family Rev 2 5 34 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 2 Memory Map 2 1 Introduction The 08 can address 64k bytes of memory space The memory shown in Figure 2 1 includes e 62 368 bytes of user FLASH MC68HC908AP64 32 768 bytes of user FLASH MC68HC908AP32 16 384 bytes of user FLASH MC68HC908AP16 8 192 bytes of user FLASH MC68HC908AP8 e 2 048 bytes of RAM MC68HC908AP64 and MC68HC908AP32 1 024 bytes of RAM MC68HC908AP16 and MC68HC908AP8 48 bytes of user defined vectors e 959 bytes of monitor ROM 2 2 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled In the memory map Figure 2 1 and in register figures in this document unimplemented locations are shaded 2 3 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation In the Figure 2 1 and in register figures in this document reserved locations are marked with the word Reserved or with the letter R MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memor
246. ct Go to www freescale com Freescale Semiconductor Inc General Description Pin Assignment 1 4 Pin Assignment 52era o x 0 m xX X X LOL e E X lt o MAAADHAH AOA OF AOE EF gt gt n n 5 PTB6 T2CHO VREFH VREG 2 VREFL PTB5 T1CH1 3 NC VDD 4 NC OSC1 5 PTAO ADCO OSC2 6 NC VSS 7 PTA1 ADC1 PTB4 T1CHO 8 PTA2 ADC2 IRQ1 9 PTAS ADC3 PTB3 RxD 10 PTA4 ADC4 RST 11 PTA5 ADC5 PTB2 TxD PTA6 ADC6 2 s 29228B8R2 85858 Dn to la Qa 0 59 lt 2 9 BN p ue NC No connection Figure 1 2 48 Pin LQFP Pin Assignments MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description 5 g qum om m x E Xx x Z 6 lt lt 9 2 maaqgdeadagaaoa a Or FF F FF gt gt co PTB6 T2CHO PTD7 KBI7 VREG 2 VREFH PTB5 T1CH1 VREFL VDD 714 PTAO ADCO osci 5 PTA1 ADC1 osc2 6 PTA2 ADC2 vss 7 PTA3 ADC3 4 1 0 8 PTA4 ADC4 9 PTAS ADC5 PTB3 RxD 10 PTA6 ADC6 RST PTA7 ADC7 S lt ri 52200203000 6
247. cter before the previous character was read from the IRSCDR The previous character remains in the IRSCDR and the new character is lost The overrun interrupt enable bit ORIE in IRSCC3 enables OR to generate SCI error CPU interrupt requests Noise flag NF The NF bit is set when the SCI detects noise on incoming data or break characters including start data and stop bits The noise error interrupt enable bit NEIE in IRSCC3 enables NF to generate SCI error CPU interrupt requests Framing error FE The FE bit IRSCS1 is set when a logic 0 occurs where the receiver expects a stop bit The framing error interrupt enable bit FEIE in IRSCC3 enables FE to generate SCI error CPU interrupt requests Parity error PE The PE bit in IRSCS1 is set when the SCI detects a parity error in incoming data The parity error interrupt enable bit PEIE in IRSCCS enables PE to generate SCI error CPU interrupt requests MC68HC908AP Family Rev 2 5 268 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI Low Power Modes 14 7 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 14 7 1 Wait Mode The SCI module remains active after the execution of a WAIT instruction In wait mode the SCI module registers are not accessible by the CPU Any enabled CPU interru
248. ctional Description 17 3 Functional Description The ADC provides eight pins for sampling external sources at pins PTAO ADCO PTA7 ADC7 An analog multiplexer allows the single ADC converter to select one of eight ADC channels as ADC voltage in Vanin Vanin is converted by the successive approximation register based analog to digital converter When the conversion is completed ADC places the result in the ADC data register high and low byte ADRHO and ADRLO and sets a flag or generates an interrupt An additional three ADC data registers ADRL1 ADRL3 are available to store the individual converted data for ADC channels ADC1 ADC3 when the auto scan mode is enabled Data from channel ADCO is stored in ADRLO in the auto scan mode Figure 17 2 shows the structure of the ADC module 17 3 1 ADC Port I O Pins are general purpose I O pins that are shared with the ADC channels The channel select bits ADCH 4 0 define which ADC channel port pin will be used as the input signal The ADC overrides the port I O logic by forcing that pin as input to the ADC The remaining ADC channels port pins are controlled by the port I O logic and can be used as general purpose I O Writes to the port data register or data direction register will not have any affect on the port pin that is selected by the ADC Read of a port pin which is in use by the ADC will return the pin condition if the corresponding DDR bit is at logic O If the DD
249. ctor Inc Configuration amp Mask Option Registers Data Sheet MC68HC908AP Family Rev 2 5 72 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 6 Central Processor Unit CPU 6 1 Introduction The M68HC08 CPU central processor unit is an enhanced and fully object code compatible version of the M68HC05 CPU The CPU08 Reference Manual Motorola document order number CPUOBRM AD contains a description of the CPU instruction set addressing modes and architecture 6 2 Features Feature of the CPU include e Object code fully upward compatible with M68HCO05 Family e 16 bit stack pointer with stack manipulation instructions e 16 Bit index register with X register manipulation instructions e 8 MHz CPU internal bus frequency e 64 Kbyte program data memory space e 16 addressing modes Memory to memory data moves without using accumulator e Fast 8 bit by 8 bit multiply and 16 bit by 8 bit divide instructions Enhanced binary coded decimal BCD data handling e Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes Low power stop and wait modes MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 73 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU 6 3 CPU Register
250. ctrical Specifications 3V SPI Characteristics 24 16 3V SPI Characteristics Diagram 7 Characteristic Symbol Min Max Unit Operating frequency Master fop 1 28 fop 2 MHz Slave foP s dc fop MHz Cycle time 1 Master 2 128 tcvc Slave lcvo s 1 tcvc 2 Enable lead time li ead s 1 3 Enable lag time li ag s 1 Clock SPSCK high time 4 Master 5 tcvc 35 64 ns Slave tsckH S 1 2 35 ns Clock SPSCK low time 5 Master tscKL M tcvc 35 64 ns Slave 5 6 1 2 tcyc 35 ns Data setup time inputs 6 Master 40 ns Slave tsu s 40 ns Data hold time inputs 7 Master tum 40 ns Slave tus 40 ns Access time slave 9 8 CPHA 0 0 50 ns CPHA 1 1 0 50 ns 9 Disable time slave tpis s 50 ns Data valid time after enable edge 10 Master tv 60 ns Slave tv s 60 ns Data hold time outputs after enable edge 11 Master 0 ns Slave thio s 0 ns Notes 1 Numbers refer to dimensions in Figure 24 3 and Figure 24 4 2 All timing is shown with respect to 20 Vpp and 70 Vpp unless noted 100 pF load on all SPI pins 3 Time to data active from high impedance state 4 Hold time to high impedance state 5 With 100 pF on all SPI pins MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 429 For More Informati
251. d The MMCRCBYTE bit should not be set in transmit mode This bit is cleared by the next START signal Reset also clears this bit 1 Next receiving byte is the packet error checking PEC data 0 Next receiving byte is not PEC data MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 329 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC 16 6 3 MMIIC Control Register 2 MMCR2 Address 004A Bit 7 6 5 4 3 2 1 Bit 0 Read MMALIF MMBB 0 0 MMAST MMRW MMCRCEF Write 0 0 Reset 0 0 0 0 0 0 0 Unaffected Unimplemented Figure 16 6 MMIIC Control Register 2 MMCR2 MMALIF Arbitration Loss Interrupt Flag This flag is set when software attempt to set MMAST but the MMBB has been set by detecting the start condition on the lines or when the MMIIC is transmitting a 1 to SDA line but detected a 0 from SDA line in master mode an arbitration loss This bit generates an interrupt request to the CPU if the MMIEN bit in MMCR 1 is set This bit is cleared by writing O to it or by reset 1 Lost arbitration in master mode 0 No arbitration lost MMNAKIF No AcKnowledge Interrupt Flag Master Mode This flag is only set in master mode MMAST 1 when there is no acknowledge bit detected after one data byte or calling address is transferred This flag also clears MMAST
252. d 0 No parity error detected MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 243 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface 13 8 5 SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions e Break character detected e Incoming data Address 0017 Bit 7 6 5 4 3 2 1 Bit 0 Read BKF RPF Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 14 SCI Status Register 2 SCS2 BKF Break Flag Bit This clearable read only bit is set when the SCI detects a break character on the RxD pin In SCS1 the FE and SCRF bits are also set In 9 bit character transmissions the R8 bit SCC3 is cleared BKF does not generate a CPU interrupt request Clear BKF by reading SCS2 with BKF set and then reading the SCDR Once cleared BKF can become set again only after logic 1s again appear on the RxD pin followed by another break character Reset clears the BKF bit 1 Break character detected 0 No break character detected RPF Reception in Progress Flag Bit This read only bit is set when the receiver detects a logic O during the RT1 time period of the start bit search RPF does not generate an interrupt request RPF is reset after the receiver detects false start bits usually from noise or a baud rate mismatch or when the receiver detects an idle ch
253. d sign mode the ADRHO holds the eight MSBs with the MSB complemented and the ADRLO holds the two least significant bits LSBs of the 10 bit result The ADRHO and ADRLO are updated each time a single channel ADC conversion completes Reading ADRHO latches the contents of ADRLO Until ADRLO is read all subsequent ADC results will be lost See Figure 17 8 ADRHO and ADRLO in Left Justified Sign Data Mode Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data Register HighO 0059 ADRHO Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 Read AD1 ADO 0 0 0 0 0 0 ADC Data RegisterLow0 005A ADRLO Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 Figure 17 8 ADRHO and ADRLO in Left Justified Sign Data Mode MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 359 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Converter ADC 17 7 4 ADC Auto Scan Mode Data Registers ADRL1 ADRL3 The ADC data registers 1 to ADRL1 ADRLS are 8 bit registers for conversion results in 8 bit truncated mode for channels ADC1 to ADC3 when the ADC is operating in auto scan mode MODE 1 0 00 Address ADRL1 005B ADRL2 005C and ADRL3 005D Read AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reser
254. de e dedicated external interrupt IRQ1 e An external interrupt pin shared with a port pin PTCO IRQ2 Separate IRQ interrupt control bits for IRQ1 and IRQ2 e Hysteresis buffers e Programmable edge only or edge and level interrupt sensitivity e Automatic interrupt acknowledge Internal pullup resistor with disable option on IRQ2 NOTE References to either IRQ1 or IRQ2 may be made the following text by omitting the IRQ number For example IRQF may refer generically to IRQ1F and IRQ2F and IMASK may refer to IMASK1 and IMASK2 Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 IRQ2 Status and Control Read 0 PUCOENB 0 0 IRQ2F 0 IMASK2 MODE2 001C Register Write 2 INTSCR2 Reset 0 0 0 0 0 0 0 0 IRQ1 Status and Control Read 0 0 0 0 IRQ1F 0 IMASK1 MODE1 001E Register Write ACK1 NTSCR nocet 0 0 0 0 0 0 0 0 Unimplemented Figure 19 1 External Interrupt Register Summary MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 379 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ 19 3 Functional Description Data Sheet A logic O applied to the external interrupt pin can latch a CPU interrupt request Figure 19 2 and Figure 19 3 shows the structure of the IRQ module Interrupt signals on the IRQ pin are latched into the IRQ latch An interrupt lat
255. duct Go to www freescale com Freescale Semiconductor Inc Input Output I O Ports Port A LED drive Direct LED drive pins PTA7 PTAO pins can be configured for direct LED drive See 18 2 3 Port A LED Control Register LEDA 18 2 2 Data Direction Register DDRA Data direction register A determines whether each port A pin is an input or an output Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin a logic O disables the output buffer Address 0004 Bit 7 6 5 4 3 2 1 Bit 0 Read DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRAO Write Reset 0 0 0 0 0 0 0 0 Figure 18 3 Data Direction Register A DDRA DDRA 7 0 Data Direction Register A Bits These read write bits control port A data direction Reset clears DDRA 7 0 configuring all port A pins as inputs 1 Corresponding port A pin configured as output 0 Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from O to 1 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 367 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports Data Sheet Figure 18 4 shows the port A logic Z w READ DDRA 0004 lt WRITE 0004 WRITE PTA 0000
256. ductor Inc Table of Contents 24 6 24 7 24 8 24 9 5V Control TID casu aaa dme Rh robe aei aie RR Oscillator Characteristics 5V ADC Electrical Characteristics 3V DC Electrical Characteristics 2410 3V Control 24 11 Oscillator Characteristics 24 12 ADC Electrical Characteristics 24 13 MMIIC Electrical Characteristics 24 14 CGM Electrical Specification 2415 SPI Characteristics sueco s use eset 24 16 SPI 24 17 FLASH Memory 25 1 25 2 25 3 25 4 26 1 26 2 Section 25 Mechanical Specifications Life m MEE CPC c rr 48 Pin Low Profile Quad Flat LQFP 44 Pin Quad Flat Pack 42 Pin Shrink Dual In Line Package SDIP Section 26 Ordering Information ces uar d ador A Rd e aod dec RU REA ERE RE x MC Order Numbers MC68HC908AP Family Rev 2 5 22 MOTOROLA For More Information On This Product Go to www freescale com Data Sheet MC68HC908AP Family Freescale Semiconductor Inc 1 1 Introduction 1 2 Features
257. e MDDRR Reset o 0 0 0 0 0 0 0 Read MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCDO MMIIC CRC Data Register pn 004E MMCRDR Write Reset 0 0 0 0 0 0 0 0 MMIIC Frequency Divider Read 0 0 0 0 0 MMBR2 MMBR1 MMBRO 004F Register Write MMFDR Reset o 0 0 0 0 1 0 0 Unimplemented Figure 16 1 MMIIC I O Register Summary Data Sheet MC68HC908AP Family Rev 2 5 321 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC 16 4 Multi Master System Configuration The multi master IIC system uses a serial data line SDA and a serial clock line SCL for data transfer All devices connected to it must have open collector drain outputs and the logical AND function is performed on both lines by two pull up resistors 16 5 Multi Master IIC Bus Protocol Normally a standard communication is composed of four parts 1 START signal 2 slave address transmission 3 data transfer and 4 STOP signal These are described briefly in the following sections and illustrated in Figure 16 2 9th clock pulse 9th clock pulse MSB LSB MSB LSB se f Je fo fo fol PURI DALAL PAARL soa W 1 U ACK Data must be stable No ACK START when SCL is HIGH STOP signal signal MSB LSB MSB LSB _ WV
258. e MISO signal is the output from the slave and the MOSI signal is the output from the master The SS line is the slave select input to the slave The slave SPI drives its MISO output only when its slave select input SS is at logic 0 so that only the selected slave drives to the master The SS pin of the master is not shown but is assumed to be inactive The SS pin of the master must be high or must be reconfigured as general purpose not affecting the SPI See 15 7 2 Mode Fault Error When CPHA 1 the master begins driving its MOSI pin on the first SPSCK edge Therefore the slave uses the first SPSCK edge as a start transmission signal The SS pin can remain low between transmissions This format may be preferable in systems having only one master and only one slave driving the MISO data line SPSCK CYCLE FOR REFERENCE SPSCK 0 VI VS VS MI LS MEM SPSCK CPOL 1 Lg A Jl FROM 9 Y erre X 2 Y Y cse OU SIN SI Y Bra Y LSB 55 TO SLAVE CAPTURE STROBE 4 A A A Figure 15 6 Transmission Format CPHA 1 MC68HC908AP Family Rev 2 5 Data Sheet For More Information On This Product Go to www freescale com 297 Freescale Semiconductor Inc Serial Peripheral Interface Module SPI When CPHA
259. e PRGRNGE Routine Description Program a range of locations Calling Address FC34 Stack Used 15 bytes Data Block Format Bus speed BUS SPD Data size DATASIZE Start address high ADDRH Start address ADDRL Data 1 DATA1 Data N DATAN The start location of the FLASH to be programmed is specified by the address ADDRH ADDRL and the number of bytes from this location is specified by DATASIZE The maximum number of bytes that can be programmed in one routine call is 255 bytes max DATASIZE is 255 ADDRH ADDRL do not need to be at a page boundary the routine handles any boundary misalignment during programming A check to see that all bytes in the specified range are erased is not performed by this routine prior programming Nor does this routine do a verification after programming so there is no return confirmation that programming was successful User must assure that the range specified is first erased The coding example below is to program 64 bytes of data starting at FLASH location EEOO with a bus speed of 4 9152 MHz The coding assumes the data block is already loaded in RAM with the address pointer FILE pointing to the first byte of the data block Data Sheet MC68HC908AP Family Rev 2 5 170 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FILE PTR BUS SPD DATASIZE START ADDR DATAARRAY PRGRNGE FLASH STA
260. e Semiconductor Inc Timer Interface Module TIM Registers 11 9 4 TIM Channel Status and Control Registers Each of the TIM channel status and control registers Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture output compare or PWM operation e Selects high low or toggling output on output compare Selects rising edge falling edge or any edge as the active input capture trigger e Selects output toggling on TIM overflow e Selects 0 and 100 PWM duty cycle Selects buffered or unbuffered output compare PWM operation Address 15 0 0025 and 25 0 0030 Bit 7 6 5 4 3 2 1 Bit 0 Read CHOF CHOIE MSOB 50 ELSOB ELSOA TOVO CHOMAX Write 0 Reset 0 0 0 0 0 0 0 0 Figure 11 9 TIM Channel 0 Status and Control Register TSCO Address T1SC1 0028 and T2SC1 0033 Bit 7 6 5 4 3 2 1 Bit 0 Read CHF 0 CHIIE MS1A ELS1B ELS1A TOV1 CH1MAX Write 0 Reset 0 0 0 0 0 0 0 0 Figure 11 10 TIM Channel 1 Status and Control Register TSC1 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 199 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module CHxF Channel x Flag Bit When channel x is an input capture channel this read write bit is set when an active edge occurs on the
261. e choice of crystal frequency fyc and the value programmed in the reference divider See 8 3 3 PLL Circuits 8 3 6 Programming the PLL and 8 5 5 PLL Reference Divider Select Register Another critical parameter is the external filter network The PLL modifies the voltage on the VCO by adding or subtracting charge from capacitors in this network Therefore the rate at which the voltage changes for a given frequency error thus change in charge is proportional to the capacitance The size of the capacitor also is related to the stability of the PLL If the capacitor is too small the PLL cannot make small enough adjustments to the voltage and the system cannot lock If the capacitor is too large the PLL may not be able to adjust the voltage in a reasonable time See 8 8 3 Choosing a Filter Also important is the operating voltage potential applied to Vppa The power supply potential alters the characteristics of the PLL A fixed value is best Variable supplies such as batteries are acceptable if they vary within a known range at very slow speeds Noise on the power supply is not acceptable because it causes small frequency errors which continually change the acquisition time of the PLL Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change The part operates as specified as long as these influences stay within the specified limits External factors however can cause d
262. e enabled the software can wait for a PLL interrupt request and then check the LOCK bit If interrupts are disabled software can poll the LOCK bit continuously during PLL start up usually or at periodic intervals In either case when the LOCK bit is set the VCO clock is safe to use as the source for the base clock See 8 3 8 Base Clock Selector Circuit If the VCO is selected as the source for the base clock and the LOCK bit is clear the PLL has suffered a severe noise hit and the software must take appropriate action depending on the application See 8 6 Interrupts for information and precautions on using interrupts MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 107 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM The following conditions apply when the PLL is in automatic bandwidth control mode The ACQ bit See 8 5 2 PLL Bandwidth Control Register is a read only indicator of the mode of the filter See 8 3 4 Acquisition and Tracking Modes The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance See 8 8 Acquisition Lock Time Specifications for more information The LOCK bit is a read only indicator of the locked state of the PLL The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out
263. e highest priority interrupt request is serviced first A return from interrupt RTI instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack After any reset the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction CLI N Negative Flag The CPU sets the negative flag when an arithmetic operation logic operation or data manipulation produces a negative result setting bit 7 of the result 1 Negative result 0 Non negative result Z Zero Flag The CPU sets the zero flag when an arithmetic operation logic operation or data manipulation produces a result of 00 1 Zero result Non zero result Data Sheet MC68HC908AP Family Rev 2 5 78 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Arithmetic Logic Unit ALU C Carry Borrow Flag The CPU sets the carry borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow Some instructions such as bit test and branch shift and rotate also clear or set the carry borrow flag 1 Carry out of bit 7 No carry out of bit 7 6 4 Arithmetic Logic Unit ALU The ALU performs the arithmetic and logic operations defined by the instruction set Refer to the CPUO8 Heference Manual Motorola document order
264. e programmable Data direction of each port B pin is under the control of the corresponding bit in data direction register B Reset has no effect on port B data SDA and SCL Multi Master 1 Data and Clock The SDA and SCL pins are multi master IIC data and clock pins Setting the MMEN bit in the MMIIC control register 1 1 configures the PTBO SDA and PTB1 SCL pins for MMIIC function and overrides any control from the port I O logic Data Sheet MC68HC908AP Family Rev 2 5 370 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output I O Ports Port B TxD and RxD SCI Transmit and Receive Data The TxD and RxD pins are SCI transmit and receive data pins Setting the ENSCI bit in the SCI control register 1 SCC1 configures the PTB2 TxD and PTB3 RxD pins for SCI function and overrides any control from the port I O logic T1CHO and T1CH1 Timer 1 Channel I O The T1CHO and T1CH1 pins are the TIM1 input capture output compare pins The edge level select bits ELSxB ELSxA determine whether the PTBA T1CHO PTB5 T1CH 1 pins are timer channel I O pins or general purpose pins T2CHO and T2CH1 Timer 2 Channel I O The T2CHO and T2CH1 pins are the TIM2 input capture output compare pins The edge level select bits ELSxB ELSxA determine whether the PTB6 T2CHO PTB7 T2CH 1 pins are timer channel I O pins or general purpose pins 18 3 2 Dat
265. ead ADRL after ADRH or else the interlocking will prevent all new conversions from being stored Right justification will place only the two MSBs in the corresponding ADC data register high ADRH and the eight LSB bits in ADC data register low ADRL This mode of operation typically is used when a 10 bit unsigned result is desired Left justified sign data mode is similar to left justified mode with one exception The MSB of the 10 bit result AD9 located in ADRH is complemented This mode of operation is useful when a result represented as a signed magnitude from mid scale is needed Finally 8 bit truncation mode will place the eight MSBs in ADC data register low ADRL The two LSBs are dropped This mode of operation is used when compatibility with 8 bit ADC designs are required No interlocking between ADRH and ADRL is present 17 3 7 Data Register Interlocking 17 3 8 Monotonicity Reading ADRH in any 10 bit mode latches the contents of ADRL until ADRL is read Until ADRL is read all subsequent ADC results will be lost This register interlocking can also be reset by a write to the ADC status and control register or ADC clock control register A power on reset or reset will also clear the interlocking Note that an external conversion request will not reset the lock The conversion process is monotonic and has no missing codes MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 351 For More Information On This Produ
266. ector Circuit Reset clears the BCS bit 1 CGMPCLK divided by two drives CGMOUT 0 CGMXCLK divided by two drives CGMOUT PLLON and BCS have built in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off Therefore PLLON cannot be cleared when BCS is set and BCS cannot be set when PLLON is clear If the PLL is off PLLON 0 selecting CGMPCLK requires two writes to the PLL control register See 8 3 8 Base Clock Selector Circuit PRE1 and PREO Prescaler Program Bits These read write bits control a prescaler that selects the prescaler power of two multiplier P See 8 3 3 PLL Circuits and 8 3 6 Programming the PLL PRE1 and PREO cannot be written when the PLLON bit is set Reset clears these bits These prescaler bits affects the relationship between the VCO clock and the final system bus clock MC68HC908AP Family Rev 2 5 118 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM CGM Registers Table 8 2 PRE1 and PREO Programming PRE1 and PREO P Prescaler Multiplier 00 0 1 01 1 2 10 2 4 11 3 8 VPR1 and VPRO VCO Power of Two Range Select Bits These read write bits control the VCO s hardware power of two range multiplier E that in conjunction with L See 8 3 3 PLL Circuits 8 3 6 Programming the PLL and 8 5 4 P
267. egister 2 SCC2 3 Clear the SCI transmitter empty bit by first reading SCI status register 1 SCS1 and then writing to the SCDR 4 Repeat step 3 for each subsequent transmission At the start of a transmission transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s After the preamble shifts out control logic transfers the SCDR data into the transmit shift register A logic O start bit automatically goes into the least significant bit position of the transmit shift register A logic 1 stop bit goes into the most significant bit position The SCI transmitter empty bit SCTE in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register The SCTE bit indicates that the SCDR can accept new data from the internal data bus If the SCI transmit interrupt enable bit SCTIE in SCC2 is also set the SCTE bit generates a transmitter CPU interrupt request When the transmit shift register is not transmitting a character the TxD pin goes to the idle condition logic 1 If at any time software clears the ENSCI bit in SCI control register 1 SCC1 the transmitter and receiver relinquish control of the port pin MC68HC908AP Family Rev 2 5 218 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Functional Description 13 42 3 Break Characters Writing a logic 1 to
268. eiver is always in SCI format It makes no difference to the SCI module whether the IR sub module is enabled or disabled NOTE This SCI module is a standard 8 SCI module with the following modifications e A control bit CKS is added to the SCI baud rate control register to select between two input clocks for baud rate clock generation e The TXINV bit is removed from the SCI control register 1 14 6 1 Data Format The SCI uses the standard non return to zero mark space data format illustrated in Figure 14 6 8 BIT DATA FORMAT PARITY BIT M IN IRSCC1 CLEAR BIT NEXT VB f 2 X Brra 4 STOP BP 9 BIT DATA FORMAT BIT M IN IRSCC1 SET NEXT START START Y Y Brra 4 5 Bits J STOP Figure 14 6 SCI Data Formats Data Sheet MC68HC908AP Family Rev 2 5 256 MOTOROLA For More Information On This Product Go to www freescale com 14 6 2 Transmitter CKS CGMXCLK BUS CLOCK SL 0 gt X A SL 1 gt X B Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI SCI Functional Description Figure 14 7 shows the structure of the SCI transmitter The baud rate clock source for the SCI can be selected by the CKS bit in the SCI baud rate register see 14 10 7 IRSCI Baud Rate Register INTERNAL BUS SCI DATA
269. eneral purpose pin In buffered output compare operation do not write new output compare values to the currently active channel registers User software should track the currently active channel to prevent writing a new value to the active channel Writing to the active channel registers is the same as generating unbuffered output compares 11 4 4 Pulse Width Modulation PWM Data Sheet By using the toggle on overflow feature with an output compare channel the TIM can generate a PWM signal The value in the TIM counter modulo registers determines the period of the PWM signal The channel pin toggles when the counter reaches the value in the TIM counter modulo registers The time between overflows is the period of the PWM signal As Figure 11 3 shows the output compare value in the TIM channel registers determines the pulse width of the PWM signal The time between overflow and output compare is the pulse width Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1 Program the TIM to set the pin if the state of the PWM pulse is logic O MC68HC908AP Family Rev 2 5 188 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM Functional Description The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output The frequency of an 8 b
270. ent ADC results will be lost See Figure 17 6 ADRHO and ADRLO in Right Justified Mode Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 AD9 AD8 ADC Data Register HighO ar 0059 Write R R R R R R R Reset 0 0 0 0 0 0 0 0 Read 07 AD6 AD5 AD4 AD3 AD2 AD1 ADO ADC Data Register Low 0 005A ADRLO Wr te R R R R R R R Reset 0 0 0 0 0 0 0 0 Figure 17 6 ADRHO and ADRLO in Right Justified Mode Data Sheet MC68HC908AP Family Rev 2 5 358 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC I O Registers In left justified mode the ADRHO holds the eight most significant bits MSBs and the ADRLO holds the two least significant bits LSBs of the 10 bit result The ADRHO and ADRLO are updated each time a single channel ADC conversion completes Reading ADRHO latches the contents of ADRLO Until ADRLO is read all subsequent ADC results will be lost See Figure 17 7 ADRHO and ADRLO in Left Justified Mode Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data Register HighO 0059 ADRHO Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 Read AD1 ADO 0 0 0 0 0 0 ADC Data RegisterLow0 005A ADRLO Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 Figure 17 7 ADRHO and ADRLO in Left Justified Mode In left justifie
271. er MOR The mask option register MOR is used for selecting one of the three clock options for the MCU The MOR is a byte located in FLASH memory and is written to by a FLASH programming routine Address FFCF Bit 7 6 5 4 3 2 1 Bit 0 Read OSCSEL1 OSCSELO R R R R R R Write Reset Unaffected by reset Erased 1 1 1 1 1 1 1 1 R Reserved Figure 5 4 Mask Option Register MOR OSCSEL1 OSCSELO Oscillator Selection Bits OSCSEL1 and OSCSELO select which oscillator is used for the MCU CGMXCLK clock The erase state of these two bits is logic 1 These bits are unaffected by reset See Table 5 1 Bits 5 0 Should be left as 1 s Table 5 1 CGMXCLK Clock Selection OSCSEL1 OSCSELO CGMXCLK OSC2 pin Comments 0 0 Not used 0 1 ICLK fgus Internal oscillator generates the CGMXCLK RC oscillator generates the CGMXCLK 1 0 RCCLK fgus Internal oscillator is available after each POR or reset Inverting X tal oscillator generates the CGMXCLK 1 1 X TAL output of Internal oscillator is available after each POR XTAL or reset NOTE Theinternal oscillator is a free running oscillator and is available after each POR or reset It is turned off in stop mode by setting the STOP ICLKDIS bit in CONFIG2 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 71 For More Information On This Product Go to www freescale com Freescale Semicondu
272. es all registers to be returned to their default values and all modules to be returned to their reset states An internal reset clears the SIM counter see 9 4 SIM Counter but an external reset does not Each of the resets sets a corresponding bit in the SIM reset status register SRSR See 9 7 SIM Registers MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 133 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM 9 3 1 External Pin Reset The RST pin circuit includes an internal pull up device Pulling the asynchronous RST pin low halts all processing The PIN bit of the SIM reset status register SRSR is set as long as RST is held low for a minimum of 67 ICLK cycles assuming that neither the POR nor the LVI was the source of the reset See Table 9 2 for details Figure 9 4 shows the relative timing Table 9 2 PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR LVI 4163 4096 64 3 All others 67 64 3 CE CEE Y Figure 9 4 External Reset Timing 9 3 2 Active Resets from Internal Sources NOTE Data Sheet All internal reset sources actively pull the RST pin low for 32 ICLK cycles to allow resetting of external peripherals T
273. es Rd 194 Registers hd kot ae RR RR RR 194 11 9 1 Status and Control Register 195 11 9 2 TIM Counter lt 197 11 9 3 Counter Modulo Registers 198 11 94 Channel Status and Control Registers 199 11 8 5 TIM 1 5 5 202 Section 12 Timebase Module TBM Lay dp RH OR RR Hp eR ed 4 205 TES 205 12 3 Functional Description Lise wa ducks eom RO RR 206 12 4 Timebase Register lt 207 Tus 5525944 dy dedo OR eres 208 12 6 Low Power Modes 209 1261 Wat Mode FOTTOCROTRIT TIPP 209 126 2 ee RR RR en 209 Section 13 Serial Communications Interface Module SCI 13 1 introduch kat tie des BOR MCCC do 211 182 ida dod ERE SOEUR Oh Renda RE Rhea eee ee CR 212 13 3 Pin Name 213 13 4 Functional Description 213 13 4 1 Data FOIE 216 134 2 22222050445 dS EE ox toe oe d a b 216 13 4 2 1 Character Lengi HER HER Rr ERR ER ER CAR 218 13 4 2 2 Character 218 13 4 2 3 Break
274. es as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances Therefore the acquisition or lock time varies according to the original error in the output Minor errors may not even be registered Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error 8 8 2 Parametric Influences on Reaction Time Data Sheet Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability These reaction times are not constant however Many factors directly and indirectly affect the acquisition time MC68HC908AP Family Rev 2 5 126 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Acquisition Lock Time Specifications The most critical parameter which affects the reaction times of the PLL is the reference frequency fapy This frequency is the input to the phase detector and controls how often the PLL makes corrections For stability the corrections must be small compared to the desired frequency so several corrections are required to reduce the frequency error Therefore the slower the reference the longer it takes to make these corrections This parameter is under user control via th
275. es the receiver Enables SCI wakeup e Transmits SCI break characters Data Sheet MC68HC908AP Family Rev 2 5 274 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI Registers Address 0041 Bit 7 6 5 4 3 2 1 Bit 0 Read SCTIE TCIE SCRIE ILIE TE RE RWU SBK Write Reset 0 0 0 0 0 0 0 0 Figure 14 13 IRSCI Control Register 2 IRSCC2 SCTIE SCI Transmit Interrupt Enable Bit This read write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests Reset clears the SCTIE bit 1 SCTE enabled to generate CPU interrupt 0 SCTE not enabled to generate CPU interrupt TCIE Transmission Complete Interrupt Enable Bit This read write bit enables the TC bit to generate SCI transmitter CPU interrupt requests Reset clears the TCIE bit 1 TC enabled to generate CPU interrupt requests 0 TC not enabled to generate CPU interrupt requests SCRIE SCI Receive Interrupt Enable Bit This read write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests Reset clears the SCRIE bit 1 SCRF enabled to generate CPU interrupt 0 SCRF not enabled to generate CPU interrupt ILIE Idle Line Interrupt Enable Bit This read write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests Reset clears the ILIE bit 1
276. eset SWI software interrupt and break interrupt than those for user mode The alternate vectors are in the FE page instead of the FF page and allow code execution from the internal monitor firmware instead of user code Exiting monitor mode after it has been initiated by having a blank reset vector requires a power on reset POR Pulling RST low will not exit monitor mode in this situation Table 10 2 summarizes the differences between user mode and monitor mode vectors Table 10 2 Mode Differences Vectors Functions Modes Reset Reset Break Break SWI SWI Vector Vector Vector Vector Vector Vector High Low High Low High Low User FFFE FFFF FFFC FFFD FFFC FFFD Monitor FEFE FEFF FEFC FEFD FEFC FEFD MC68HC908AP Family Rev 2 5 Data Sheet 159 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor 10 3 2 Data Format 10 3 3 Break Signal 10 3 4 Baud Rate Data Sheet Communication with the monitor ROM is in standard non return to zero NRZ mark space data format Transmit and receive baud rates must be identical NEXT START START B BIT1 BIT2 BITS BIT4 BIT7 STOP Figure 10 3 Monitor Data Format A start bit logic O followed by nine logic O bits is a break signal When the monitor receives a break signal it drives the PTAO pin high
277. ete Receiver full Idle receiver input Receiver overrun Noise error Framing error Parity error Receiver framing error detection Hardware parity checking 1 16 bit time noise detection Configuration register bit SCIBDSRC to allow selection of baud rate clock source MC68HC908AP Family Rev 2 5 212 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Pin Name Conventions 13 3 Pin Name Conventions NOTE The generic names of the SCI I O pins are e RxD receive data TxD transmit data SCI input output lines are implemented by sharing parallel I O port pins The full name of an SCI input or output reflects the name of the shared port pin Table 13 1 shows the full names and the generic names of the SCI I O pins The generic pin names appear in the text of this section Table 13 1 Pin Name Conventions Generic Pin Names RxD TxD Full Pin Names PTB3 RxD PTB2 TxD When the SCI is enabled the TxD pin is an open drain output and requires a pullup resistor to be connected for proper SCI operation 13 4 Functional Description MC68HC908AP Family Rev 2 5 Figure 13 1 shows the structure of the SCI module The SCI allows full duplex asynchronous NRZ serial communication among the MCU and remote devices including other MCUs The transmitter and
278. evel low 00 01 Capture on rising edge only 00 10 Input capture Capture on falling edge only 00 11 Capture on rising or falling edge 01 01 Toggle output on compare Output 01 10 compare or Clear output on compare PWM 01 11 Set output on compare 1X 01 Buffered Toggle output on compare 1X 10 output Clear output on compare compare or 1X 11 buffered PWM Set output on compare MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 201 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module Before enabling a TIM channel register for input capture operation make sure that the TCHx pin is stable for at least two bus clocks TOVx Toggle On Overflow Bit When channel x is an output compare channel this read write bit controls the behavior of the channel x output when the TIM counter overflows When channel x is an input capture channel TOVx has no effect Reset clears the TOVx bit 1 Channel x pin toggles on TIM counter overflow 0 Channel x pin does not toggle on TIM counter overflow When is set a TIM counter overflow takes precedence over channel x output compare if both occur at the same time CHxMAX Channel x Maximum Duty Cycle Bit When the TOVXx bit is at logic 1 setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100 As Figure 11 11 shows the CHxMAX bit takes effect in the cycle after it is se
279. f each port C pin is under the control of the corresponding bit in data direction register C Reset has no effect on port C data IRQ2 IRQ2 input pin The 2 pin is always available as input pin to the IRQ2 module Care must be taken to available unwanted interrupts when this pin is used as general purpose I O PTCO IRQ2 pin has internal pullup and can be disabled by setting the PUCOENB bit in the IRQ2 status and control register INTSCR2 MISO MOSI SS and SPSCK SPI Data I O Select and Clock Pins These pins are the SPI data in out select and clock pins Setting the SPE bit in the SPI control register SPCR configures PTC2 MISO PTC3 MOSI PTC4 SS and PTC5 SPSCK pins for SPI function and overrides any control from the port I O logic MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 373 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports SCTxD and SCRxD IrSCI Transmit and Receive Data The SCTxD and SCRxD pins are IRSCI transmit and receive data pins Setting the ENSCI bit in the IRSCI control register 1 IRSCC1 configures the PTC6 SCTxD and PTC7 SCRxD pins for IRSCI function and overrides any control from the port I O logic 18 4 2 Data Direction Register C DDRC Data direction register C determines whether each port C pin is an input or an output Writing a logic 1 to a DDRC bit enables the output buffer for t
280. fails to read the SCDR before the receive shift register receives the next character The OR bit generates an SCI error CPU interrupt request if the ORIE bit in SCC3 is also set The data in the shift register is lost but the data already in the SCDR is not affected Clear the OR bit by reading SCS1 with OR set and then reading the SCDR Reset clears the OR bit 1 Receive shift register full and SCRF 1 0 No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag clearing sequence Figure 13 13 shows the normal flag clearing sequence and an example of an overrun caused by a delayed flag clearing sequence The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read Byte 2 caused the overrun and is lost The next flag clearing sequence reads byte 3 in the SCDR instead of byte 2 In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun the flag clearing routine can check the OR bit in a second read of SCS1 after reading the data register NF Receiver Noise Flag Bit This clearable read only bit is set when the SCI detects noise on the RxD pin NF generates an SCI error CPU interrupt request if the NEIE bit in SCC3 is also set Clear the NF bit by reading SCS1 and then reading the SCDR Reset clears the NF bit 1 Noise detected 0 No noise detected FE Receiver Framing E
281. fications Diagram UH Characteristic Symbol Min Max Unit Operating frequency Master fop 1 28 fop 2 MHz Slave fop s dc fop MHz Cycle time 1 Master tcyc m 2 128 tcvc Slave lcvc s 1 tcvc 2 Enable lead time ll ead S 1 tcvc 3 Enable lag time li ag S 1 Clock SPSCK high time 4 Master 5 tcvc 25 64 tcvc ns Slave lscKH S 1 2 25 ns Clock SPSCK low time 5 Master tscKL M tcvc 25 64 tcvc ns Slave 5 6 1 2 tcyc 25 ns Data setup time inputs 6 Master 0 30 ns Slave tsu s 30 ns Data hold time inputs 7 Master 30 ns Slave tH s 30 ns Access time slave 9 8 0 0 40 ns CPHA 1 1 0 40 ns 9 Disable time slave tpis s 40 ns Data valid time after enable edge 10 Master tv 50 ns Slave tv s 50 ns Data hold time outputs after enable edge 11 Master tuoi 0 ns Slave thio s 0 ns Notes 1 Numbers refer to dimensions in Figure 24 3 and Figure 24 4 2 All timing is shown with respect to 20 Vpp and 70 Vpp unless noted 100 pF load on all SPI pins 3 Time to data active from high impedance state 4 Hold time to high impedance state 5 With 100 pF on all SPI pins Data Sheet MC68HC908AP Family Rev 2 5 428 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Ele
282. figured as a general purpose output pin PTC7 a pullup resistor must be connected to this pin MC68HC908AP Family Rev 2 5 270 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI I O Registers Table 14 5 shows a summary of I O pin functions when the SCI is enabled Table 14 5 SCI Pin Functions Standard and Infrared REI TxD Pin RxD Pin 1 0 0 0 Hi Z Input ignored terminate externally 1 0 0 1 Hi Z Input sampled pin should idle high 1 0 1 0 Output SCI idle high Input ignored terminate externally 1 0 1 1 Output SCI idle high Input sampled pin should idle high 1 1 0 0 Hi Z Input ignored terminate externally 1 1 0 1 Hi Z Input sampled pin should idle high 1 1 1 0 Output IR SCI idle high Input ignored terminate externally 1 1 1 1 Output IR SCI idle high Input sampled pin should idle high 0 X X X Pins under port control standard I O port Notes 1 After completion of transmission in progress 14 10 1 O Registers The following I O registers control and monitor SCI operation e RSCI control register 1 IRSCC1 e IRSCI control register 2 IRSCC2 e RSCI control register IRSCC3 e IRSCI status register 1 IRSCS1 e RSCI status register 2 IRSCS2 e IRSCI data register IRSCDR e IRSCI baud rate register IRSCBR
283. freely read and written during break mode without losing status flag information Setting the BCFE bit enables the clearing mechanisms Once cleared in break mode a flag remains cleared even when break mode is exited Status flags with a 2 step clearing mechanism for example a read of one register followed by the read or write of another are protected even when the first step is accomplished prior to entering break mode Upon leaving break mode execution of the second step will clear the flag as normal MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 145 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM 9 6 Low Power Modes 9 6 1 Wait Mode Data Sheet Executing the WAIT or STOP instruction puts the MCU in a low power consumption mode for standby situations The SIM holds the CPU in a non clocked state The operation of each of these modes is described in the following subsections Both STOP and WAIT clear the interrupt mask 1 in the condition code register allowing interrupts to occur In wait mode the CPU clocks are inactive while the peripheral clocks continue to run Figure 9 15 shows the timing for wait mode entry A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred I
284. g this time CGMOUT is held in stasis The output of the transition control circuit is then divided by two to correct the duty cycle Therefore the bus clock frequency which is one half of the base clock frequency is one fourth the frequency of the selected clock CGMXCLK or CGMPCLK The BCS bit in the PLL control register PCTL selects which clock drives CGMOUT The divided VCO clock cannot be selected as the base clock source if the PLL is not turned on The PLL cannot be turned off if the divided VCO clock is selected The PLL cannot be turned on or off simultaneously with the selection or deselection of the divided VCO clock The divided VCO clock also cannot be selected as the base clock source if the factor L is programmed to a O This value would set up a condition inconsistent with the operation of the PLL so that the PLL would be disabled and the oscillator clock would be forced as the source of the base clock MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 113 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM 8 3 9 CGM External Connections In its typical configuration the CGM requires up to four external components Figure 8 3 shows the external components for the PLL e Bypass capacitor Cgyp Filter network Care should be taken with PCB routing in order to minimize signal cross talk and noise See 8 8 Acquisition Lock Time Specif
285. g to the SPI control register SPCR Reset clears the MODF bit 1 SS pin at inappropriate logic level 0 SS pin at appropriate logic level SPTE SPI Transmitter Empty Bit This clearable read only flag is set each time the transmit data register transfers a byte into the shift register SPTE generates an SPTE CPU interrupt request if the SPTIE bit in the SPI control register is set also NOTE Do not write to the SPI data register unless the SPTE bit is high During an SPTE CPU interrupt the CPU clears the SPTE bit by writing to the transmit data register Reset sets the SPTE bit 1 Transmit data register empty 0 Transmit data register not empty Data Sheet MC68HC908AP Family Rev 2 5 316 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI I O Registers MODFEN Mode Fault Enable Bit This read write bit when set to 1 allows the MODF flag to be set If the MODF flag is set clearing the MODFEN does not clear the MODF flag If the is enabled as a master and the MODFEN bit is low then the SS pin is available as a general purpose If the MODFEN bit is set then this pin is not available as a general purpose I O When the SPI is enabled as a slave the 55 pin is not available as a general purpose regardless of the value of MODFEN See 15 12 4 SS Slave Select If the MODFEN bit is low the
286. gration Module SIM 95 12 SWI Instruction The SWI instruction is a non maskable instruction that causes an interrupt regardless of the state of the interrupt mask I bit in the condition code register NOTE A software interrupt pushes PC onto the stack A software interrupt does not push PC 1 as a hardware interrupt does 95 1 3 Interrupt Status Registers The flags in the interrupt status registers identity maskable interrupt sources Table 9 3 summarizes the interrupt sources and the interrupt status register flags that they set The interrupt status registers can be useful for debugging 9 5 1 4 Interrupt Status Register 1 Address FE04 Bit 7 6 5 4 3 2 1 Bit 0 6 IF5 IF4 IF3 IF2 IF1 0 0 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 9 12 Interrupt Status Register 1 INT1 IF6 IF1 Interrupt Flags 6 1 These flags indicate the presence of interrupt requests from the sources shown in Table 9 3 1 Interrupt request present 0 No interrupt request present Bit O and Bit 1 Always read 0 Data Sheet MC68HC908AP Family Rev 2 5 142 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Exception Control Table 9 3 Interrupt Sources
287. gure 14 9 e After every start bit e After the receiver detects a data bit change from logic 1 to logic 0 after the majority of data bit samples at RT8 RT9 and RT10 returns a valid logic 1 and the majority of the next RT8 RT9 and RT10 samples returns a valid logic 0 START BIT gt a LSB SCI_RxD Mise aaa START BIT START BIT DATA SAMPLES QUALIFICATION VERIFICATION SAMPLING RT CLOCK RTCLOCK e e e e e SS SS Se a me EEE EEE EIF EERE RT CLOCK Reser VY Y Y g Figure 14 9 Receiver Data Sampling Data Sheet MC68HC908AP Family Rev 2 5 262 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI SCI Functional Description To locate the start bit data recovery logic does an asynchronous search for a logic O preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock begins to count to 16 To verify the start bit and to detect noise data recovery logic takes samples at RT3 RT5 and RT7 Table 14 2 summarizes the results of the start bit verification samples Table 14 2 Start Bit Verification
288. h PCL SP lt SP 1 Push PCH SP lt SP 1 Push X SP SP 1 Push A E SWI Software Interrupt SP lt SP 1 Push CCR 1 INH 83 9 SP lt 1 1 lt 1 lt Interrupt Vector High Byte PCL lt Interrupt Vector Low Byte TAP Transfer A to CCR CCR lt A INH 84 2 TAX Transfer A to X X lt A INH 97 1 TPA Transfer CCR to A A lt CCR 85 1 TST DIR 3D 3 TSTA INH 4D 1 TSTX 5D 1 TST Test for Negative or Zero A 00 or X 00 or M 00 0 C 60 l 3 TST IX 7D 2 TST opr SP SP1 9 6 4 TSX Transfer SP to H X H X lt SP 1 95 2 Transfer X to A lt X INH 9F 1 TXS Transfer H X to SP SP lt H X 1 94 2 Accumulator n Any bit C Carry borrow bit opr one or two bytes CCR Condition code register PC Program counter dd Direct address of operand PCH Program counter high byte ddrr Direct address of operand and relative offset of branch instruction PCL Program counter low byte DD Direct to direct addressing mode REL Relative addressing mode DIR Direct addressing mode Relative program counter offset byte DIX Direct to indexed with post increment addressing mode rr Relative program counter offset byte ee ff High and low bytes of offset in indexed 16 bit offset addressing SP1 Stack pointer 8 bit offset addressing mode EXT Extended addressing mode SP2 Sta
289. he ACKK bit in the keyboard status and control register to clear any false interrupts 4 Clear the IMASKK bit An interrupt signal on an edge triggered pin can be acknowledged immediately after enabling the pin An interrupt signal on an edge and level triggered interrupt pin must be acknowledged after a delay that depends on the external load Another way to avoid a false interrupt 1 Configure the keyboard pins as outputs by setting the appropriate DDR bits in data direction register MC68HC908AP Family Rev 2 5 390 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt Module KBI Keyboard Interrupt Registers 2 Write logic 1s to the appropriate data register bits 3 Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register 20 5 Keyboard Interrupt Registers Two registers control the operation of the keyboard interrupt module Keyboard Status and Control Register 001A e Keyboard Interrupt Enable Register 001B 20 5 1 Keyboard Status and Control Register Flags keyboard interrupt requests e Acknowledges keyboard interrupt requests Masks keyboard interrupt requests e Controls keyboard interrupt triggering sensitivity Address 001 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 KEYF 0 IMASKK MODEK Write ACKK Reset 0 0 0 0 0 0 0 0 Unimplemented
290. he corresponding port C pin a logic O disables the output buffer Address 0006 Bit 7 6 5 4 3 2 1 Bit 0 Read DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRCO Write Reset 0 0 0 0 0 0 0 0 Figure 18 10 Data Direction Register C DDRC DDRC 7 0 Data Direction Register C Bits These read write bits control port C data direction Reset clears DDRC 7 0 configuring all port C pins as inputs 1 Corresponding port C pin configured as output 0 Corresponding port C pin configured as input NOTE Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from O to 1 Figure 18 11 shows the port C logic NOTE Forthose devices packaged in a 42 pin shrink dual in line package PTCO and PTC1 are not connected DDRCO and DDRC1 should be set to a 1 to configure PTCO and PTC1 as outputs Data Sheet MC68HC908AP Family Rev 2 5 374 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ZN READ DDRC 0006 Input Output I O Ports Port C gt PTOx E WRITE DDRC 0006 eo DDRCx RESET E WRITE 0002 ra Lu z READ PTC 0002 lt PTCO has schmitt trigger input Figure 18 11 Port C I O Circuit When DDRCx is a logic 1 reading address 0002 reads the PTCx data latch When DDRCx is a logic 0
291. he internal reset signal IRST continues to be asserted for an additional 32 cycles see Figure 9 5 An internal reset can be caused by an illegal address illegal opcode COP timeout LVI or POR see Figure 9 6 For LVI or POR resets the SIM cycles through 4096 32 ICLK cycles during which the SIM forces the RST pin low The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 9 5 MC68HC908AP Family Rev 2 5 134 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc IRST RST ICLK IAB System Integration Module SIM Reset and System Initialization RST PULLED LOW BY MCU H4 32 CYCLES 32 CYCLES 3 C 22 MAMMA VECTOR HIGH Figure 9 5 Internal Reset Timing The COP reset is asynchronous to the bus clock ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST gt gt INTERNAL RESET LVI POR Figure 9 6 Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU 93 2 1 Power On Reset When power is first applied to the MCU the power on reset module POR generates a pulse to indicate that power on has occurred The external reset pin RST is held low while the SIM counter counts out 4096 32 ICLK cycles Thi
292. here the write to the SPDR occurs relative to the slower SPSCK This uncertainty causes the variation in the initiation delay shown in Figure 15 7 This delay is no longer than a single SPI bit time That is the maximum delay is two MCU bus cycles for DIV2 eight MCU bus cycles for DIV8 32 MCU bus cycles for DIV32 and 128 MCU bus cycles for DIV128 Data Sheet MC68HC908AP Family Rev 2 5 298 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Transmission Formats WRITE ro INITIATION DELAY BUS A U Ne Ar A MOSI MSB BIT 6 BIT 5 SPSCK CPHA 1 SPSCK 0 SPSCK CYCLE NUMBER 3 poen DELAY FROM WRITE SPDR TO TRANSFER BEGIN OF WRITE TO SPDR CLOCK SPSCK INTERNAL CLOCK 2 EARLIEST 2 POSSIBLE START POINTS WRITE LATEST TO SPDR ac v U NU uer NM EE NM NE UNE EARLIEST SPSCK INTERNAL CLOCK 8 LATEST WRITE 8 POSSIBLE START POINTS TO SPDR D ee PN Ne Ne NT EN M NM EARLIEST SPSCK INTERNAL CLOCK 32 LATEST WRITE 32 POSSIBLE START POINTS TO SPDR As epe Neg es od od Mrs c EARLIEST SPSCK INTERNAL CLOCK 128 LATEST 128 POSSIBLE START POINTS Figure 15 7 Transmission Start Delay Master MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 299 For More Information On This Product Go to www f
293. i Po Industrial Estate Tai Po N T Hong Kong 852 26668334 HOME PAGE http motorola com semiconductors MOTOROLA Information in this document is provided solely to enable system and software implementers to use Motorola products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application i
294. ications for routing information filter network and its effects on PLL performance MCU CGMXFC VssA VppA Vpp T 10 nF T BYP 0 1 0 22 uF T e Note Filter network in box can be replaced with 0 47 uF capacitor but will degrade stability Figure 8 3 CGM External Connections 8 4 1 Signals The following paragraphs describe the CGM signals Data Sheet MC68HC908AP Family Rev 2 5 114 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Signals 8 4 1 External Filter Capacitor Pin CGMXFC The CGMXFC pin is required by the loop filter to filter out phase corrections An external filter network is connected to this pin See Figure 8 3 NOTE prevent noise problems the filter network should be placed as close to the CGMXFC pin as possible with minimum routing distances and no routing of other signals across the network 8 4 2 PLL Analog Power Pin VppA VppA is a power pin used by the analog portions of the PLL Connect the Vppa to the same voltage potential as the Vpp pin NOTE Route VppA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package 8 4 3 PLL Analog Ground Pin Vssa VssA iS a ground pin used by the analog portions of the PLL Connect the Vssa to the same voltage potential as the Vas pin N
295. igh T FFDB SPI Transmit Vector Low FFDC SPI Receive Vector High d FFDD SPI Receive Vector Low FFDE ADC Conversion Complete Vector High di FFDF ADC Conversion Complete Vector Low FFEO Keyboard Vector High iis FFE1 Keyboard Vector Low FFE2 SCI Transmit Vector High i FFE3 SCI Transmit Vector Low FFE4 SCI Receive Vector High ida FFE5 SCI Receive Vector Low FFE6 SCI Error Vector High i FFE7 SCI Error Vector Low FFE8 MMIIC Interrupt Vector High is FFE9 MMIIC Interrupt Vector Low FFEA TIM2 Overflow Vector High ii FFEB TIM2 Overflow Vector Low Data Sheet MC68HC908AP Family Rev 2 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Input Output I O Section Table 2 1 Vector Addresses Continued Priority INT Flag Address Vector FFEC TIM2 Channel 1 Vector High i FFED TIM2 Channel 1 Vector Low FFEE TIM2 Channel 0 Vector High n FFEF TIM2 Channel 0 Vector Low FFFO TIM1 Overflow Vector High FFF1 TIM1 Overflow Vector Low FFF2 TIM1 Channel 1 Vector High ii FFF3 TIM1 Channel 1 Vector Low FFF4 TIM1 Channel 0 Vector High 75 FFF5 TIM1 Channel 0 Vector Low FFF6 PLL Vector High FFF7 PLL Vector Low FFF8 IRQ2 Vector High ii FFF9 IRQ2 Vector Low FFFA
296. igher than MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 415 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications maximum rated voltages to this high impedance circuit For proper operation it is recommended that and be constrained to the range Vss lt Vin Vout lt Vpp Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level for example either Vss or Vpp 24 3 Functional Operating Range Table 24 2 Operating Range Characteristic Symbol Value Unit Operating temperature range TA 40 to 85 Operating voltage range Vpp 2 7 to 5 5 V 24 4 Thermal Characteristics Table 24 3 Thermal Characteristics Characteristic Symbol Value Unit Thermal resistance 42 Pin SDIP 0 60 C W 44 Pin QFP JA 95 C W 48 Pin LQFP 80 C W pin power dissipation User determined W Pp lpp Vpp Pio Power dissipation Pp 273 C 2 Pp 273 C Constant K gt Pp x OJA Average junction temperature Ty Pp x Osa C Maximum junction temperature Tym 100 Notes 1 Power dissipation is a function of temperature 2 constant unique to the device can be determined for a known T4 and measured With this value of K Pp and Tj can be determined for any value of
297. ignal Name Conventions Signal Name Description ICLK Internal oscillator clock CGMXCLK Selected oscillator clock from oscillator module CGMVCLK CGMPCLK PLL output and the divided PLL output CGMPCLK based or oscillator based clock output from CGM module MUT Bus clock CGMOUT 2 IAB Internal address bus IDB Internal data bus PORRST Signal from the power on reset module to the SIM IRST Internal reset signal R W Read write signal Data Sheet MC68HC908AP Family Rev 2 5 130 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM SIM Bus Clock Control and Generation Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 6 SBSW a FEO0 SIM Break Status poss Write NOTE Reset 0 0 0 0 0 0 0 0 Note Writing a logic 0 clears SBSW Read POR PIN COP ILOP ILAD MODRST LVI 0 FEO1 SIM Reset Status pen Write POR 1 0 0 0 0 0 0 0 SIM Break Flag Control i BCFE R R R R R R R areas Register SBFCR TR Reset 0 Read IF6 IF5 IF4 IF3 IF2 IF1 0 0 greg erupt Status Wite R R R R R R R Reset 0 0 0 0 0 0 0 0 Read 1 14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 dregs Wite R R R R R R R Reset 0 0 0 0 0 0 0 0 Read 0 IF21 IF20 IF19 IF18 IF17 IF16 IF15
298. igned Operands lt 2 rel N 6 V 1 REL 91 rr 3 BNC rel Branch if Interrupt Mask Clear lt PC 2 rel 1 0 REL 2C 3 BMI rel Branch if Minus PC lt PC 2 rel 1 REL 2B 3 BMS rel Branch if Interrupt Mask Set PC lt 2 rel I 1 REL 2D 3 BNE rel Branch if Not Equal lt PC 2 rel 2 0 REL 26 3 BPL rel Branch if Plus lt 2 rel 0 REL 2 3 BRA rel Branch Always PC lt 2 rel REL 20 3 Data Sheet MC68HC908AP Family Rev 2 5 82 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Opcode Map Table 6 1 Instruction Set Summary Sheet 3 of 8 Effect on Source Operation Description CCR 9 g 6 9 3 3 9 2 1 2 33 8 8 4 DIR bO 01 ddr 5 DIR b1 03 5 DIR 62 05 5 5 DIR b3 07 5 BRCLR n opr rel Branch if Bit n in M Clear PC lt 3 rel Mn 0 t DIR b4 09 5 65 5 DIR 66 OD ddr 5 DIR 67 OF 5 BRN rel Branch Never PC lt 2 REL 21 rr 3 DIR bO 00 5 DIR b1 02 5 DIR b2 04 5 82 63 06 5 2 BRSET n opr rel Bra
299. ime the recovery period Figure 9 18 shows stop mode entry timing NOTE Tominimize stop current all pins configured as inputs should be driven to a logic 1 or logic O CPUSTOP IAB STOPADDR STOPADDR 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME RW NOTE Previous data can be operand data or the STOP opcode depending on the last instruction Figure 9 18 Stop Mode Entry Timing gt STOP RECOVERY PERIOD INT BREAK 9 1 IAB STOP 1 Jerez sro sp 1 sP 2 3 y Figure 9 19 Stop Mode Recovery from Interrupt or Break 9 7 SIM Registers The SIM has three memory mapped registers SIM Break Status Register SBSR FE00 e SIM Reset Status Register SRSR FE01 e SIM Break Flag Control Register SBFCR FE03 Data Sheet MC68HC908AP Family Rev 2 5 148 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM SIM Registers 9 7 1 SIM Break Status Register The SIM break status register SBSR contains a flag to indicate that a break caused an exit from stop mode or wait mode Address FE00 Bit 7 6 5 4 3 2 1 Bit 0 Read SBSW R R R R R R R Write Note Reset 0 Note
300. ing Break Interrupts 383 196 383 19 6 1 IRQ1 Status and Control 384 19 6 2 IRQ 2 Status and Control Register 385 Section 20 Keyboard Interrupt Module 20 1 NURSES db ix eee ROR R 387 20 2 387 CHR erm 388 20 4 Functional Description 388 20 41 Keyboard Initialization 390 20 5 Keyboard Interrupt Registers 391 20 5 1 Keyboard Status and Control Register 391 20 5 2 Keyboard Interrupt Enable Register 392 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Data Sheet 20 6 Low Power 393 CH EE c d RARER RE RRAE KENT ER 393 20602 393 20 7 Keyboard Module During Break Interrupts 393 Section 21 Computer Operating Properly COP 21 1 395 Functional Description 395 213 POSAS ko AE RU 396 EUNT 396 21 32 STOP INSWUCHON hne Ra 396 21 3 3 COPCTL WE cs hee Sk hee E rutt ee ia 397 21 34 Power On 1 397 21 3 5
301. interrupt instruction RTI in the break routine ends the break interrupt and returns the MCU to normal operation Figure 23 1 shows the structure of the break module IAB15 IAB8 BREAK ADDRESS REGISTER HIGH 8 BIT COMPARATOR IAB15 IABO CONTROL BREAK IAB7 IABO Figure 23 1 Break Module Block Diagram Data Sheet MC68HC908AP Family Rev 2 5 408 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK Functional Description Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read B 8 B SBSW SIM Break Status Register FE00 SBSR Write Note Reset 0 Read SIM Break Flag Control BCFE R R R R R R R FE03 Register Write BEECH Reset 0 Read Break Address Bit 15 14 13 12 11 10 9 Bit 8 FEOC Register High Write BRKH Reset 0 0 0 0 0 0 0 0 Read Break Address pit 6 5 4 3 2 1 Bit 0 FEOD Register Low Write RKL eset 0 0 0 0 0 0 0 0 Break Status and Control Read BRKE BRKA _ 7 FEOE Register Write BRKSCH Reset 0 0 0 0 0 0 0 0 Note Writing a logic 0 clears BW Unimplemented R Reserved Figure 23 2 Break Module I O Register Summary 23 3 1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state 23 3 2 CPU Duri
302. ired AND logic is performed on SCL line a high to low transition on the SCL line will affect the devices connected to the bus The devices start counting their low period once a device s clock has gone low it will hold the SCL line low until the clock high state is reached However the change of low to high in this device clock may not change the state of the SCL line if another device clock is still in its low period Therefore the synchronized clock SCL will be held low by the device which last releases SCL to logic high Devices with shorter low periods enter a high wait state during this time When all devices concerned have counted off their low period the synchronized SCL line will be released and go high and all devices will start counting their high periods The first device to complete its high period will again pull the SCL line low Figure 16 3 illustrates the clock synchronization waveforms WAIT Start counting high period Internal counter reset Figure 16 3 Clock Synchronization The clock synchronization mechanism can be used as a handshake in data transfer A slave device may hold the SCL low after completion of one byte data transfer and will halt the bus clock forcing the master clock into a wait state until the slave releases the SCL line MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 325 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
303. is bit is set to disable the MMIIC from sending out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits When MMTXAK is cleared an acknowledge signal will be sent at the 9th clock bit Reset clears this bit 1 MMIIC does not send acknowledge signals at 9th clock bit MMIIC sends acknowledge signal at 9th clock bit REPSEN Repeated Start Enable This bit is to enable repeated START signal to be generated when in master mode transfer MMAST 1 The REPSEN bitis cleared by hardware after the completion of repeated START signal or when the MMAST bit is cleared Reset clears this bit 1 Repeated START signal will be generated if MMAST bit is set 0 No repeated START signal will be generated MMCRCBYTE MMIIC CRC Byte In receive mode this bit is set by software to indicate that the next receiving byte will be the packet error checking PEC data In master receive mode after completion of CRC generation on the received PEC data an acknowledge signal is sent if MMTXAK 0 no acknowledge is sent If MMTXAK 1 In slave receive mode no acknowledge signal is sent if a CRC error is detected on the received PEC data If no CRC error is detected an acknowledge signal is sent if MMTXAK 0 no acknowledge is sent If MMTXAK 1 Under normal operation the user software should clear MMTXAK bit before setting MMCRCBYTE bit to ensure that an acknowledge signal is sent when no CRC error is detecte
304. ister Write SBFCR Reset 0 Read IF6 IF5 IF4 IF3 IF2 IF1 0 0 grgo Interrupt Status Write R R R R R R R Reset 0 0 0 0 0 0 0 0 Read IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 gros Interrupt Status go Write R R R R R R R Reset 0 0 0 0 0 0 0 0 Read 0 IF21 IF20 IF19 IF18 IF17 IF16 IF15 grEog Interrupt Status NT Write R R R R R R R Reset 0 0 0 0 0 0 0 0 Read R R R R R R R R FE07 Reserved Write Reset ides 9 HVEN MASS ERASE PGM FLASH Control Register qM FE08 FLCR Write Reset 0 0 0 0 0 0 0 0 FLASH Block Protect 1984 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPRO 5 09 Register Write FLBPR 0 0 0 0 0 0 0 0 Read R R R R R R R R FEOA Reserved Write Reset Read R R R R R R R R FEOB Reserved Write Reset Read Break Address Bit 15 14 13 12 11 10 9 Bit 8 FEOC Register High Write BRKH Reset 0 0 0 0 0 0 0 0 U Unaffected X Indeterminate Unimplemented R Reserved Figure 2 2 Control Status and Data Registers Sheet 11 of 12 Data Sheet MC68HC908AP Family Rev 2 5 48 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Addr Register Name Break Address neag FEOD Register Low Write BRKL Break Status and Control FEOE Register Read Write Reset LVI Status Register SEDE LVISR Read Write Read Write Mask Option Register FFCF MOR Erased Reset Read COP
305. it When the AUTO bit is set LOCK is a read only bit that becomes set when the VCO clock CGMVCLK is locked running at the programmed frequency When the AUTO bit is clear LOCK reads as logic O and has no meaning The write one function of this bit is reserved for test so this bit must a ways be written a Reset clears the LOCK bit 1 VCO frequency correct or locked 0 VCO frequency incorrect or unlocked ACQ Acquisition Mode Bit When the AUTO bit is set ACQ is a read only bit that indicates whether the PLL is in acquisition mode or tracking mode When the AUTO bit is clear ACQ is a read write bit that controls whether the PLL is in acquisition or tracking mode In automatic bandwidth control mode AUTO 1 the last written value from manual operation is stored in a temporary location and is recovered when manual operation resumes Reset clears this bit enabling acquisition mode 1 Tracking mode 0 Acquisition mode Data Sheet MC68HC908AP Family Rev 2 5 120 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM CGM Registers 8 5 3 PLL Multiplier Select Registers The PLL multiplier select registers PMSH and PMSL contain the programming information for the modulo feedback divider Address 0038 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 MUL11 MUL10 MUL9 MUL8 Write Reset 0 0 0 0 0 0 0 0
306. it PWM signal is variable in 256 increments Writing 255 to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000 See 11 9 1 TIM Status and Control Register OVERFLOW OVERFLOW OVERFLOW H 4 PERIOD lt gt PULSE WIDTH OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE Figure 11 3 PWM Period and Pulse Width The value in the TIM channel registers determines the pulse width of the PWM output The pulse width of an 8 bit PWM signal is variable in 256 increments Writing 0080 128 to the TIM channel registers produces a duty cycle of 128 256 or 50 1144 1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 11 4 4 Pulse Width Modulation PWM The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods For example writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period Also using a TIM overflow interrupt routine to write a new smaller pulse width value may cause the compare to be missed The TIM may pass the new va
307. it SCI characters WAKE Wakeup Condition Bit This read write bit determines which condition wakes up the a logic 1 address mark in the most significant bit position of a received character or an idle condition on the RxD pin Reset clears the WAKE bit 1 Address mark wakeup 0 Idle line wakeup ILTY Idle Line Type Bit This read write bit determines when the SCI starts counting logic 1s as idle character bits The counting begins either after the start bit or after the stop bit If the count begins after the start bit then a string of logic 1s preceding the stop bit may cause false recognition of an idle character Beginning the count after the stop bit avoids false idle character recognition but requires properly synchronized transmissions Reset clears the ILTY bit 1 Idle character bit count begins after stop bit 0 Idle character bit count begins after start bit PEN Parity Enable Bit This read write bit enables the SCI parity function See Table 13 5 When enabled the parity function inserts a parity bit in the most significant bit position See Figure 13 3 Reset clears the PEN bit 1 Parity function enabled 0 Parity function disabled Data Sheet MC68HC908AP Family Rev 2 5 234 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Registers PTY Parity Bit This read write bit
308. it and to detect noise recovery logic takes samples at RT8 RT9 and 10 Table 13 4 summarizes the results of the stop bit samples Table 13 4 Stop Bit Recovery mr 8 8 710 Framing Noise Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 13 4 3 4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character it sets the framing error bit FE in SCS1 A break character also sets the FE bit because a break character has no stop bit The FE bit is set at the same time that the SCRF bit is set 13 43 5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit Then a noise error occurs If more than one of the samples is outside the stop bit a framing error occurs In most applications the baud rate tolerance is much more than the degree of misalignment that is likely to occur MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 225 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Data Sheet As the receiver samples an incoming character it resynchronizes the RT clock on any valid falling edge within the character Resynchronization within characters corrects
309. it in IRSCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit Reset clears the RWU bit 1 Standby state 0 Normal operation SBK Send Break Bit Setting and then clearing this read write bit transmits a break character followed by a logic 1 The logic 1 after the break character guarantees recognition of a valid start bit If SBK remains set the transmitter continuously transmits break characters with no logic 1s between them Reset clears the SBK bit 1 Transmit break characters 0 No break characters being transmitted NOTE not toggle the SBK bit immediately after setting the SCTE bit Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble Data Sheet MC68HC908AP Family Rev 2 5 276 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI I O Registers 14 10 3 IRSCI Control Register 3 IRSCI control register 3 e Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted Enables the following interrupts Receiver overrun interrupts Noise error interrupts Framing error interrupts Parity error interrupts Address 0042 Bit 7 6 5 4 3 2 1 Bit 0 Read R8 T8 DMARE DMATE ORIE NEIE FEIE PEIE Write Rese
310. it such that both bits cannot be equal to 1 or set to 1 at the same time 1 Program operation selected 0 Program operation not selected MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 57 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FLASH Memory 4 4 FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory A page consists of 512 consecutive bytes starting from addresses X000 X200 X400 X600 X800 XA00 0 or The 48 byte user interrupt vectors cannot be erased by the page erase operation because of security reasons Mass erase is required to erase this page 1 O gir gr ue 509 Set the ERASE bit and clear the MASS bit in the FLASH control register Write any data to any FLASH location within the page address range desired Wait for a time tnvs 5 us Set the HVEN bit Wait for a time terase 20 ms Clear the ERASE bit Wait for a time 5 us Clear the HVEN bit After time 1 the memory can be accessed in read mode again NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory While these operations must be performed in the order as shown but other unrelated operations may occur between the steps Data Sheet MC68HC908AP Family Rev 2 5 58 MOTOROLA For More Information On This Product Go to
311. ite ninth bit bit 8 of the transmitted character T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register Reset has no effect on the 8 bit Data Sheet MC68HC908AP Family Rev 2 5 238 MOTOROLA For More Information On This Product Go to www freescale com CAUTION CAUTION Freescale Semiconductor Inc Serial Communications Interface Module SCI I O Registers DMARE DMA Receive Enable Bit The DMA module is not included on this MCU Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance 1 DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit SCI receiver CPU interrupt requests enabled 0 not enabled to service SCI receiver DMA service requests generated by the SCRF bit SCI receiver CPU interrupt requests enabled DMATE DMA Transfer Enable Bit The DMA module is not included on this MCU Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance 1 SCTE service requests enabled SCTE CPU interrupt requests disabled 0 SCTE DMA service requests disabled SCTE CPU interrupt requests enabled ORIE Receiver Overrun Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit OR 1 SCI error CPU interrupt requests from OR bit enabled 0 SCI error CPU interrupt requests from OR bit disa
312. itor mode The RUN command tells the MCU to execute the PULH and RTI instructions Before sending the RUN command the host can modify the stacked CPU registers to prepare to run the host program The READSP command returns the incremented stack pointer value SP 1 The high and low bytes of the program counter are at addresses SP 5 and SP 6 SP HIGH BYTE OF INDEX REGISTER SP 1 CONDITION CODE REGISTER SP 2 ACCUMULATOR SP 3 LOW BYTE OF INDEX REGISTER SP 4 HIGH BYTE OF PROGRAM COUNTER SP 5 LOW BYTE OF PROGRAM COUNTER SP 6 SP 7 Figure 10 7 Stack Pointer at Monitor Mode Entry MC68HC908AP Family Rev 2 5 Data Sheet 165 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor 10 4 Security Data Sheet NOTE A security feature discourages unauthorized reading of FLASH locations while in monitor mode The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations FFF6 FFFD Locations FFF6 FFFD contain user defined data Do not leave locations FFF6 SFFFD blank For security reasons program locations FFF6 FFFD even if they are not used for vectors During monitor mode entry the MCU waits after the power on reset for the host to send the eight security bytes on pin PTAO If the received bytes match those at locations FFF6 FFFD the host bypasses the security featu
313. k interrupt write a logic 1 to the BCFE bit If a status bit is cleared during the break state it remains cleared when the MCU exits the break state To protect status bits during the break state write a logic O to the BCFE bit With BCFE at logic O its default state software can read and write I O registers during the break state without affecting status bits Some status bits have a 2 step read write clearing procedure If software does the first step on such a bit before the break the bit cannot change during the break state as long as BCFE is at logic O After the break doing the second step clears the status bit MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 193 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module 11 8 Signals Port B shares four of its pins with the TIM The four TIM channel I O pins are T1CHO T1CH1 T2CHO and T2CH1 as described in 11 3 Pin Name Conventions Each channel I O pin is programmable independently as an input capture pin or an output compare pin T1CHO and T2CHO can be configured as buffered output compare or buffered PWM pins 11 9 O Registers NOTE References to either timer 1 or timer 2 may be made the following text by omitting the timer number For example TSC may generically refer to both T1SC AND T2SC These registers control and monitor operation of the TIM e status and con
314. k state write a logic O to the BCFE bit With BCFE at logic O its default state writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags 19 6 IRQ Registers Each IRQ is controlled and monitored by an status and control register e RQ1 Status and Control Register 001E e RQ Status and Control Register 001C MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 383 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ 19 6 1 IRQ1 Status and Control Register The IRQ1 status and control register INTSCR1 controls and monitors operation of IRQ1 The INTSCR 1 has the following functions e Shows the state of the IRQ1 flag e Clears the IRQ1 latch Masks IRQ1 interrupt request e Controls triggering sensitivity of the IRQ1 interrupt pin Address 001 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 IRQ1F 0 IMASK1 MODE1 Write ACK1 Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 19 4 IRQ1 Status and Control Register INTSCR1 IRQ1F IRQ1 Flag Bit This read only status bit is high when the IRQ1 interrupt is pending 1 IRQ1 interrupt pending 0 IRQ1 interrupt not pending ACK1 IRQ1 Interrupt Request Acknowledge Bit Writing a logic 1 to this write only bit clears the IRQ1 latch ACK1 always reads as logic 0 Reset clears ACK1
315. l the counter value reaches the value of AUTO 1 0 When this happens it indicates that the current channel is the last channel to be converted Upon the completion on the last channel the counter value will not be incremented and no further conversion will be performed To start another auto scan cycle a write to ADSCR must be performed The system only provides 8 bit data storage in auto scan code user must clear MODET 1 0 bits to select 8 bit truncation mode before entering auto scan mode It is recommended that user should disable the auto scan function before switching channel and also before entering STOP mode 17 3 6 Result Justification Data Sheet The conversion result may be formatted in four different ways e Left justified Right justified Left justified sign data mode e 8 bit truncation All four of these modes are controlled using MODEO and MODE1 bits located in the ADC clock control register ADICLK MC68HC908AP Family Rev 2 5 350 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC Functional Description Left justification will place the eight most significant bits MSB in the corresponding ADC data register high ADRH This may be useful if the result is to be treated as an 8 bit result where the least significant two bits located in the ADC data register low ADRL can be ignored However you must r
316. lag The CPU sets the overflow flag when a two s complement overflow occurs The signed branch instructions BGT BGE BLE and BLT use the overflow flag 1 Overflow No overflow H Half Carry Flag The CPU sets the half carry flag when a carry occurs between accumulator bits 3 and 4 during an add without carry ADD or add with carry ADC operation The half carry flag is required for binary coded decimal BCD arithmetic operations The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor 1 Carry between bits 3 and 4 0 No carry between bits 3 and 4 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 77 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Interrupt Mask When the interrupt mask is set all maskable CPU interrupts are disabled CPU interrupts are enabled when the interrupt mask is cleared When a CPU interrupt occurs the interrupt mask is set automatically after the CPU registers are saved on the stack but before the interrupt vector is fetched 1 Interrupts disabled 0 Interrupts enabled NOTE Tomaintain M6805 Family compatibility the upper byte of the index register H is not stacked automatically If the interrupt service routine modifies H then the user must stack and unstack H using the PSHH and PULH instructions After the bit is cleared th
317. ld be tied to Vpp on the PCB with proper decoupling Input range VADIN 0 V Vann Resolution BAD 10 10 bits Includes quantization Absolute accuracy AAD 1 5 LSB 0 5 LSB 1 ADC step ADC internal clock 500k 2M Hz tanic l fApic Conversion range RAD VREFL VREFH V ADC voltage reference high VREFH pe 0 1 d ADC voltage reference low VREFL Vssa 0 1 V en t 1 17 Conversion time ADC 6 cycles let t Sample time ADS 5 cycles Monotonicity Map Guaranteed Zero input reading 000 001 HEX Vapin Full scale reading FADI 3FD 3FF HEX VapiN VnErH Input capacitance Capi EN 20 pF Not tested Input impedance RADI 20M VREFH V REFL lvnEF 1 6 mA Not tested Notes 1 Vpp 4 5 to 5 5 Vss 0 TA T to Ty unless otherwise noted Data Sheet MC68HC908AP Family Rev 2 5 424 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications MMIIC Electrical Characteristics 24 13 MMIIC Electrical Characteristics Table 24 12 MMIIC DC Electrical Characteristics Characteristic Symbol Min Typ Max Unit Comments Input low 0 5 0 8 V Data clock input low Input high 24 EE 5 5 V Data clock input high Output low VoL 0 4 V i Input leakage 5 Input leakage current Curre
318. le the SCI by writing a logic 1 to the enable SCI bit ENSCI in IRSCI control register 1 IRSCC1 2 Enable the transmitter by writing a logic 1 to the transmitter enable bit TE in IRSCI control register 2 IRSCC2 3 Clear the SCI transmitter empty bit by first reading IRSCI status register 1 IRSCS1 and then writing to the IRSCDR 4 Repeat step 3 for each subsequent transmission At the start of a transmission transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s After the preamble shifts out control logic transfers the IRSCDR data into the transmit shift register A logic O start bit automatically goes into the least significant bit position of the transmit shift register A logic 1 stop bit goes into the most significant bit position The SCI transmitter empty bit SCTE in IRSCS1 becomes set when the IRSCDR transfers a byte to the transmit shift register The SCTE bit indicates that the IRSCDR can accept new data from the internal data bus If the SCI transmit interrupt enable bit SCTIE in IRSCC2 is also set the SCTE bit generates a transmitter interrupt request When the transmit shift register is not transmitting a character the TxD pin goes to the idle condition logic 1 If at any time software clears the ENSCI bit in IRSCI control register 1 IRSCC1 the transmitter and receiver relinquish control of the port pins MC68HC908AP Family Rev 2 5 258 MOTOROLA
319. lects master mode and configures the SPSCK and MOSI pins as outputs and the MISO pin as an input Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin as an output The mode fault bit MODF becomes set any time the state of the slave select pin SS is inconsistent with the mode selected by SPMSTR To prevent SPI pin contention and damage to the MCU a mode fault error occurs if e The SS pin of a slave SPI goes high during a transmission e The SS pin of a master SPI goes low at any time For the MODF flag to be set the mode fault error enable bit MODFEN must be set Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 303 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Data Sheet NOTE NOTE MODF generates a receiver error CPU interrupt request if the error interrupt enable bit ERRIE is also set The SPRF MODF and OVRF interrupts share the same CPU interrupt vector See Figure 15 11 It is not possible to enable or OVRF individually to generate a receiver error CPU interrupt request However leaving MODFEN low prevents MODF from being set In a master SPI with the mode fault enable bit MODFEN set the mode fault flag MODF is set if SS goes to logic 0
320. llegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR and resetting the MCU A data fetch from an unmapped address does not generate a reset The SIM actively pulls down the RST pin for all internal reset sources 93 25 Low Voltage Inhibit LVD Reset The low voltage inhibit module LVI asserts its output to the SIM when the Vpp voltage falls to the LVI pipr voltage The LVI bit in the SIM reset status register SRSR is set and the external reset pin RST is held low while the SIM counter counts out 4096 32 ICLK cycles Thirty two ICLK cycles later the CPU is released from reset to allow the reset vector sequence to occur The SIM actively pulls down the RST pin for all internal reset sources 9 3 2 6 Monitor Mode Entry Module Reset The monitor mode entry module reset asserts its output to the SIM when monitor mode is entered in the condition where the reset vectors are blank FF See Section 10 Monitor ROM MON When MODRST gets asserted an internal reset occurs The SIM actively pulls down the RST pin for all internal reset sources MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 137 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM 9 4 SIM Counter The SIM counter
321. lo divider The pre scaler divides the VCO clock by a power of two factor P the CGMPCLK and the modulo divider reduces the VCO clock by a factor N The dividers output is the VCO feedback clock CGMVDV running at a frequency fypy fyc k N x 2 See 8 3 6 Programming the PLL for more information The phase detector then compares the VCO feedback clock CGMVDV with the final reference clock CGMRDV A correction pulse is generated based on the phase difference between the two signals The loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse The filter can make fast or slow corrections depending on its mode described in 8 3 4 Acquisition and Tracking Modes The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL The lock detector compares the frequencies of the VCO feedback clock CGMVDV and the final reference clock CGMRDV Therefore the speed of the lock detector is directly proportional to the final reference frequency fapy The circuit determines the mode of the PLL and the lock condition based on this comparison MC68HC908AP Family Rev 2 5 106 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Functional Description 8 3 4 Acquisition and Tracking Mode
322. logic 1 to this bit clears TBIF the timebase interrupt flag bit Writing a logic to this bit has no effect 1 Clear timebase interrupt flag 0 No effect TBIE Timebase Interrupt Enabled This read write bit enables the timebase interrupt when the TBIF bit becomes set Reset clears the TBIE bit 1 Timebase interrupt enabled 0 Timebase interrupt disabled TBON Timebase Enabled This read write bit enables the timebase Timebase may be turned off to reduce power consumption when its function is not necessary The counter can be initialized by clearing and then setting this bit Reset clears the TBON bit 1 Timebase enabled 0 Timebase disabled and the counter initialized to O s The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR 2 0 When the timebase counter chain rolls over the TBIF flag is set If the TBIE bit is set enabling the timebase interrupt the counter chain overflow will generate a CPU interrupt request The interrupt vector is defined in Table 2 1 Vector Addresses Interrupts must be acknowledged by writing a logic 1 to the TACK bit MC68HC908AP Family Rev 2 5 208 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timebase Module TBM Low Power Modes 12 6 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 12 6 1 Wait Mode The time
323. lue before it is written MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 189 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module NOTE Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x When changing to a shorter pulse width enable channel x output compare interrupts and write the new value in the output compare interrupt routine The output compare interrupt occurs at the end of the current pulse The interrupt routine has until the end of the PWM period to write the new value e When changing to a longer pulse width enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine The TIM overflow interrupt occurs at the end of the current PWM period Writing a larger value in an output compare interrupt routine at the end of the current pulse could cause two output compares to occur in the same PWM period In PWM signal generation do not program the PWM channel to toggle on output compare Toggling on output compare prevents reliable 096 duty cycle generation and removes the ability of the channel to self correct in the event of software error or noise Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new much larger value 1L442 Buffered PWM Signal Generation Data Sheet Channels 0 and 1 can be li
324. m of the FLASH memory FFFF When the memory is protected the HVEN bit cannot be set in either erase or program operations The mask option register FFCF and the 48 bytes of user interrupt vectors FFDO SFFFF are always protected regardless of the value in the FLASH block protect register A mass erase is required to erase these locations 4 7 1 FLASH Block Protect Register The FLASH block protect register is implemented as 8 bit I O register The value in this register determines the starting address of the protected range within the FLASH memory Address 9 09 Bit 7 6 5 4 3 2 1 Bit 0 Read BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPRO Write Reset 0 0 0 0 0 0 0 0 Figure 4 4 FLASH Block Protect Register FLBPR BPR 7 0 FLASH Block Protect Bits BPR 7 1 represent bits 15 9 of a 16 bit memory address Bits 8 0 are logic O s 16 bit memory address Start address of FLASH block protect 0000000010 BPR 7 1 Data Sheet MC68HC908AP Family Rev 2 5 62 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FLASH Memory FLASH Protection BPRO is used only for BPR 7 0 FF for no block protection The resultant 16 bit address is used for specifying the start address of the FLASH memory for block protection The FLASH is protected from this start address
325. mation On This Product Go to www freescale com Freescale Semiconductor Inc fo Ko E 01103 7 2 2 TBM Reference Clock Selection The timebase module reference clock OSCCLK is selected by configuring two bits in the CONFIG2 register at 001D See 5 4 Configuration Register 2 CONFIG2 Address 001D Bit 7 6 5 4 3 2 1 Bit 0 Read stop_ STOP STOP 0 0 Reset 0 0 0 0 0 0 0 0 Figure 7 3 Configuration Register 2 CONFIG2 Table 7 2 Timebase Module Reference Clock Selection OSCCLK1 OSCCLKO Timebase Clock Source 0 0 Internal oscillator ICLK 0 1 RC oscillator RCCLK 1 0 X tal oscillator XCLK 1 1 Not used The RCCLK or XCLK is only available if that clock is selected as the CGM reference clock whereas the ICLK is always available 7 3 Internal Oscillator Data Sheet The internal oscillator clock with a frequency of fic is a free running clock that requires no external components It can be selected as the CGMXCLK for the CGM and MCU sub systems and the OSCCLK clock for the TBM The ICLK is also the reference clock input to the computer operating properly COP module Due to the simplicity of the internal oscillator it does not have the accuracy and stability of the RC oscillator or the x tal oscillator Therefore the ICLK is not suitable where an accurate bus clock is required and it should not be used as the CGMRCLK to the CGM PL
326. mmable stop mode operation MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 401 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Voltage Inhibit LVI Addr FEOF Register Name LVI Status Register LVISR Bit 7 6 5 4 3 2 1 Bit 0 Read LVIOUT 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 22 1 LVI Register Summary 22 3 Functional Description Data Sheet Figure 22 2 shows the structure of the LVI module The LVI is enabled out of reset The LVI module contains independent bandgap reference circuit and comparator for monitoring the Vpp voltage and the VREG voltage An LVI reset performs a MCU internal reset and drives the RST pin low to provide low voltage protection to external peripheral devices LVISTOP LVIPWRD LVIRSTD and LVIREGD are in the CONFIG1 register See Section 5 Configuration amp Mask Option Registers CONFIG amp MOR for details of the L VI configuration bits Once an LVI reset occurs the MCU remains in reset until Vpp rises above VTRIPR1 and rises above which causes the MCU to exit reset The output of the comparator controls the state of the LVIOUT flag in the LVI status register LVISR An LVI reset also drives the RST pin low to provide low voltage protection to external peripheral devices MC68HC908AP Family Rev 2 5 402 MO
327. mpleted To prevent this either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit Figure 15 10 illustrates this process Generally to avoid this second SPSCR read enable the OVRF to the CPU by setting the ERRIE bit MC68HC908AP Family Rev 2 5 302 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Error Conditions BYTE 1 BYTE 2 BYTE 3 BYTE 4 SPI RECEIVE COMPLETE e e p READ 9 vo 9 READ SPDR 1 BYTE 1 SETS SPRF CPU READS BYTE 2 IN SPDR CLEARING SPRF BIT CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR CPU READS SPSCR AGAIN CPU READS BYTE 1 IN SPDR TO CHECK OVRF BIT GEEARINGISPBEJBLE CPU READS BYTE 2 SPDR CPU READS SPSCR AGAIN CLEARING OVRF BIT TO CHECK OVRF BIT 5 BYTE 2 SETS SPRF BIT 11 BYTE 4 SETS SPRF BIT 12 CPU READS SPSCR 6 CPU READS SPSCR WITH SPRF BIT SET CPU READS BYTE 4 IN SPDR AND OVRF BIT CLEAR CLEARING SPRF BIT T BYTE 3 SETS OVRF BIT BYTE 3 IS LOST CPU READS SPSCR AGAIN TO CHECK OVRF BIT Figure 15 10 Clearing SPRF When Interrupt Is Not Enabled 15 7 2 Mode Fault Error Setting the SPMSTR bit se
328. n wait mode the CPU clocks are inactive Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode Some modules can be programmed to be active in wait mode Wait mode also can be exited by a reset or break A break interrupt during wait mode sets the SIM break stop wait bit SBSW in the SIM break status register SBSR If the COP disable bit COPD in the mask option register is logic 0 then the computer operating properly module COP is enabled and remains active in wait mode IAB WAITADDR WAITADDR 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME RAN NOTE Previous data can be data or the WAIT opcode depending on the last instruction Figure 9 15 Wait Mode Entry Timing Figure 9 16 and Figure 9 17 show the timing for WAIT recovery MC68HC908AP Family Rev 2 5 146 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Low Power Modes IAB 6E0B seEoc ooFF soorE 0020 soorc IDB 6 5 6 346 so soB Y y EXITSTOPWAIT NOTE EXITSTOPWAIT RST pin OR CPU interrupt OR break interrupt Figure 9 16 Wait Recovery from Interrupt or Break 32 4 32 CYCLES CYCLES 2 6 IAB 6E0B Y T 229
329. n 9 bit character transmissions the R8 bit in IRSCC3 is cleared BKF does not generate a CPU interrupt request Clear BKF by reading IRSCS2 with BKF set and then reading the IRSCDR Once cleared BKF can become set again only after logic 1s again appear on the RxD pin followed by another break character Reset clears the BKF bit 1 Break character detected 0 No break character detected RPF Reception in Progress Flag Bit This read only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search RPF does not generate an interrupt request RPF is reset after the receiver detects false start bits usually from noise or a baud rate mismatch or when the receiver detects an idle character Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress 1 Reception in progress 0 No reception in progress MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 283 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications 14 10 6 IRSCI Data Register Data Sheet The IRSCI data register is the buffer between the internal data bus and the receive and transmit shift registers Reset has no effect on data in the IRSCI data register Address 0045 Bit 7 6 5 4 3 2 1 Bit 0 Read R7 R6 R5 R4 R3 R2 R1 RO Write T7 T6 T5 T4 T3 T2 Ti TO
330. n On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Registers logic 1 Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted Reset clears the TE bit 1 Transmitter enabled 0 Transmitter disabled NOTE Writing to the TE bit is not allowed when the enable SCI bit ENSCI is clear ENSCI is in SCI control register 1 RE Receiver Enable Bit Setting this read write bit enables the receiver Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits Reset clears the RE bit 1 Receiver enabled 0 Receiver disabled NOTE Writing to the RE bit is not allowed when the enable SCI bit ENSCI is clear ENSCI is in SCI control register 1 RWU Receiver Wakeup Bit This read write bit puts the receiver in a standby state during which receiver interrupts are disabled The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit Reset clears the RWU bit 1 Standby state 0 Normal operation SBK Send Break Bit Setting and then clearing this read write bit transmits a break character followed by a logic 1 The logic 1 after the break character guarantees recognition of a valid start bit If SBK remains set the transmitter continuously transmits break
331. n This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Input Output I O Section Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 IRQ1 Status and Control Read 0 0 0 0 0 IMASK1 MODE1 001E Register Write ACK1 INTSCR Reset 0 0 0 0 0 0 0 0 Read 001F Configuration Register 1 COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD rite CONFIG1 Reset 0 0 0 0 0 0 0 0 1 One time writable register after each reset Read TOF 0 0 TimeriStatusand TOIE TSTOP PS 51 PSO 0020 Control Register Write 0 TRST TISO Reset 0 0 0 0 0 0 0 Timer 1 Counter Read Bit 15 14 13 12 11 10 9 Bit 8 0021 Register High Write TICNTH Reset 0 0 0 0 0 0 0 Timer 1 Counter Read Bit 7 6 5 4 3 2 1 Bit 0 0022 Register Low Write TICNTD Reset o 0 0 0 0 0 0 0 Read Timer 1 Counter Modulo Bit 15 14 13 12 11 10 9 Bit 8 0023 Register High Write TIMODH Reset 1 1 1 1 1 1 1 1 Read Timer 1 Counter Modulo Bit 7 6 5 4 3 2 1 Bit 0 0024 Register Low Write JFIMSOD Reset 1 1 1 1 1 1 1 1 Read CHOF Timer 1 Channel 0 Status CHOIE 50 MS0A ELSOB ELSOA TOVO CHOMAX 0025 and Control Register Write 0 TISCO Reset 0 0 0 0 0 0 0 0 Read Timer 1 Channel 0 Bit 15 14 13 12 11 10 9 Bit 8 0026 Register High Write
332. n from the RxD pin The idle line interrupt enable bit ILIE in SCC2 enables the IDLE bit to generate CPU interrupt requests 13 4 3 8 Error Interrupts The following receiver error flags in SCS1 can generate CPU interrupt requests Receiver overrun OR The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR The previous character remains in the SCDR and the new character is lost The overrun interrupt enable bit ORIE in SCC3 enables OR to generate SCI error CPU interrupt requests Noise flag NF The NF bit is set when the SCI detects noise on incoming data or break characters including start data and stop bits The noise error interrupt enable bit NEIE in SCC3 enables NF to generate SCI error CPU interrupt requests Framing error FE The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit The framing error interrupt enable bit FEIE in SCC3 enables FE to generate SCI error CPU interrupt requests e Parity error PE The PE bit in SCS1 is set when the SCI detects a parity error in incoming data The parity error interrupt enable bit PEIE in SCC3 enables PE to generate SCI error CPU interrupt requests MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 229 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface
333. n interrupt request into the IRQ latch A vector fetch software clear or reset clears the IRQ latch If the MODE bit is set the IRQ pin is both falling edge sensitive and low level sensitive With MODE set both of the following actions must occur to clear IRQ e Vector fetch or software clear A vector fetch generates an interrupt acknowledge signal to clear the latch Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK bit in the interrupt status and control register INTSCR The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise Setting ACK does not affect subsequent transitions on the IRQ pin A falling edge that occurs after writing to the ACK bit another interrupt request If the IRQ mask bit IMASK is clear the CPU loads the program counter with the vector address at location defined in Table 2 1 Vector Addresses Return of the IRQ pin to logic 1 As long as the IRQ pin is at logic 0 IRQ remains active The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any order The interrupt request remains pending as long as the IRQ pin is at logic 0 A reset will clear the latch and the MODE control bit thereby clearing the interrupt even if the pin stays low If the MODE bit is clear the
334. n which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2003 MC68HC908AP64 D Rev 2 5 10 2003 For More Information On This Product Go to www freescale com
335. nal is cleared when the data register ADRO is read or the ADSCR is written Reset clears the AIEN bit 1 ADC interrupt enabled 0 ADC interrupt disabled Data Sheet MC68HC908AP Family Rev 2 5 354 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC I O Registers ADCO ADC Continuous Conversion Bit When set the ADC will convert samples continuously and update the ADC data register at the end of each conversion Only one conversion is allowed when this bit is cleared Reset clears the ADCO bit 1 Continuous ADC conversion 0 One ADC conversion This bit should not be set when auto scan mode is enabled i e when ASCAN 1 ADCH 4 0 ADC Channel Select Bits ADCH 4 0 form a 5 bit field which is used to select one of the ADC channels when not in auto scan mode The five channel select bits are detailed in Table 17 1 NOTE Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal Recovery from the disabled state requires one conversion cycle to stabilize Table 17 1 MUX Channel Select ADCH4 ADCH3 ADCH2 ADCH1 ADCHO ADC Channel Input Select 0 0 0 0 0 ADCO PTAO 0 0 0 0 1 ADC1 PTA1 0 0 0 1 0 ADC2 PTA2 0 0 0 1 1 ADC3 PTA3 0 0 1 0 0 ADC4 PTA4 0 0 1 0 1 ADC5
336. nch if Bit nin M Set lt 3 rel Mn 1 t DIR b4 08 5 DIR 65 5 DIR 66 5 DIR 67 OE ddr 5 DIR 60 10 dd 4 DIR b1 12 4 DIR 62 14 dd 4 oer DIR 63 16 dd 4 BSET n opr Set Bit nin M Mn lt 1 7 7 7 7 DIR 18 Idd 4 DIR b5 dd 4 DIR b6 1C dd 4 DIR b7 4 PC lt PC 2 push PCL 2 SP lt SP 1 push PCH 210101010 BSR rel Branch to Subroutine SP lt SP 1 REL AD jrr 4 PC lt PC rel CBEQ PC lt PC 3 rel A 00 DIR 31 ddrr 5 CBEQA opr rel PC 3 rel M 00 IMM 41 ii rr 4 CBEQX opr rel PC lt 3 rel X M 00 51 ii rr 4 CBEG opr X rel and Branch if Equal PC 3 rel A 00 1 1 61 5 CBEQ rel PC lt 2 rel M 00 1 71 jrr 4 opr SP rel PC lt PC 4 rel A M 00 SP1 9 61 ffrr 6 CLC Clear Carry Bit Cc 0 0 INH 98 1 CLI Clear Interrupt Mask 1 0 0 INH 9A 2 CLR opr lt 00 DIR dd 3 CLRA lt 00 INH 4F 1 CLRX X lt 00 INH 5F 1 CLRH Clear lt 00 1 011 INH 8C 1 CLR opr X M lt 00 1 1 6F 3 CLR X M lt 00 IX 7F 2 CLR opr SP M lt 00 SP1 9E6F f 4 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 83 For More Information On This Product Go to www freescale com Frees
337. nded to the nearest integer number 1 MC68HC908AP Family Rev 2 5 Choose the desired bus frequency fguspgs or the desired VCO frequency fyci pes and then solve for the other The relationship between fpys and fyc is governed by the equation P P 2 fcaupcik 2 4 X where P is the power of two multiplier and can be O 1 2 or 3 Choose a practical PLL reference frequency fpc and the reference clock divider R Typically the reference is 32 768kHz 1 Frequency errors to the PLL are corrected at a rate of fpc For stability and lock time reduction this rate must be as fast as possible The VCO frequency must be an integer multiple of this rate Data Sheet MOTOROLA 109 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Data Sheet The relationship between the VCO frequency and the reference frequency fpc is g where is the integer range multiplier between 1 4095 In cases where desired bus frequency has some tolerance choose fpc to a value determined either by other module requirements such as modules which are clocked by CGMXCLK cost requirements or ideally as high as the specified range allows See Section 24 Electrical Specifications Choose the reference divider R 1 When the tolerance on the bus fre
338. nerates a reset the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 ICLK cycle POR timeout has completed The RST pin is driven low by the SIM during this entire period The IBUS clocks start upon completion of the timeout Data Sheet MC68HC908AP Family Rev 2 5 132 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Reset and System Initialization 9 2 3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt break or reset the SIM allows ICLK to clock the SIM counter The CPU and peripheral clocks do not become active until after the stop delay timeout This timeout is selectable as 4096 or 32 ICLK cycles See 9 6 2 Stop Mode In wait mode the CPU clocks are inactive The SIM also produces two sets of clocks for other modules Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode Some modules can be programmed to be active in wait mode 9 3 Reset and System Initialization The MCU has these reset sources e Power on reset module POR e External reset RST Computer operating properly module COP e Low voltage inhibit module LVI e Illegal opcode e address All of these resets produce the vector FFFE FFFF FEFE FEFF in monitor mode and assert the internal reset signal IRST IRST caus
339. nformation On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Table 13 8 SCI Baud Rate Selection Examples SCP1 and Prescaler SCR2 SCR1 Baud Rate Baud Rate SCPO Divisor PD and SCRO Divisor BD fgus 4 9152 MHz 00 1 000 1 76 800 00 1 001 2 38 400 00 1 010 4 19 200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25 600 01 3 001 2 12 800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19 200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 Data Sheet MC68HC908AP Family Rev 2 5 248 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 14 Infrared Serial Communications Interface Module IRSCI 14 1 Introduction The MC68HC908AP64 has two SCI modules e SCl1 is a standard SCI module and e SCI2isan infrared SCI module This section describes SCI2 the infrared serial communications interface IRSCI module which allows high
340. ng Break Interrupts The CPU starts a break interrupt by Loading the instruction register with the SWI instruction e Loading the program counter with FFFC and FFFD FEFC and FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress If the break address register match occurs on the last cycle of a CPU instruction the break interrupt begins immediately MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 409 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK 23 3 3 TIMI and TIM2 During Break Interrupts A break interrupt stops the timer counters 23 3 4 COP During Break Interrupts The COP is disabled during a break interrupt when is present on the RST pin 23 4 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 23 4 1 Wait Mode If enabled the break module is active in wait mode In the break routine the user can subtract one from the return address on the stack if SBSW is set see Section 9 System Integration Module SIM Clear the BW bit by writing logic O to it 23 4 2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register 23 5 Break Module Registers These registers control and monitor operation of the break module Break status and control register BRKSCR Break address regi
341. ng to read the SPI data register before the next full byte enters the shift register sets the OVRF bit The new byte does not transfer to the receive data register and the unread byte still can be read OVRF is in the SPI status and control register Mode fault error bit indicates that the voltage on the slave select pin SS is inconsistent with the mode of the SPI MODF is in the SPI status and control register 15 7 1 Overflow Error The overflow flag OVRF becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs The bit 1 capture strobe occurs in the middle of SPSCK cycle 7 See Figure 15 4 and Figure 15 6 If an overflow occurs all data received after the overflow and before the bit is cleared does not transfer to the receive data register and does not set the SPI receiver full bit SPRF The unread data that transferred to the receive data register before the overflow occurred can still be read Therefore an overflow error always indicates the loss of data Clear the overflow flag by reading the SPI status and control register and then reading the SPI data register OVHRF generates receiver error CPU interrupt request if the error interrupt enable bit ERRIE is also set The SPRF MODF and OVRF MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 301 For More Information On Thi
342. nked to form a buffered PWM channel whose output appears on the TCHO pin The TIM channel registers of the linked pair alternately control the pulse width of the output Setting the MSOB bit in TIM channel 0 status and control register TSCO links channel 0 and channel 1 The TIM channel 0 registers initially control the pulse width on the TCHO pin Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period At each subsequent overflow the TIM channel registers 0 or 1 that control the pulse width are the ones written to last TSCO controls and monitors the buffered PWM function and TIM channel 1 status and control register TSC1 is unused While the MSOB bit is set the channel 1 pin TCH1 is available as a general purpose pin MC68HC908AP Family Rev 2 5 190 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM Functional Description NOTE In buffered PWM signal generation do not write new pulse width values to the currently active channel registers User software should track the currently active channel to prevent writing a new value to the active channel Writing to the active channel registers is the same as generating unbuffered PWM signals 71 44 3 PWM Initialization To ensure correct operation when generating unbuffered or buffered
343. nt through pull up Pullup current IPULLUP 100 350 resistor or current source See note Notes 1 Vpp 2 7 to 5 5Vdc Vss 0 TA T to Ty unless otherwise noted 2 The Ipyj up max specification is determined primarily by the need to accommodate a maximum of 1 1kQ equivalent se ries resistor of removable SMBus devices such as the smart battery while maintaining the max of the bus SCL gt lt gt o gt lt IS 4 tHD STA tHIGH tsu DAT tHD DAT tsu sTA tsu sto Figure 24 2 MMIIC Signal Timings See Table 24 13 for MMIIC timing parameters MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 425 For More Information On This Product Go to www freescale com Electrical Specifications Freescale Semiconductor Inc Table 24 13 MMIIC Interface Input Output Signal Timing Characteristic Symbol Min Typ Max Unit Comments Operating frequency 10 100 kHz MMIIC operating frequency Bus free time t 47 m Bus free time between STOP and BUF H START condition Hold time after repeated START Repeated start hold time tip STA 4 0 us condition After this period the first clock is generated Repeated start setup time tsu sTa 4 7 us pica START condition setup Stop setup time tsu sto 4 0 us Stop condition setup time Hold time tup DAT 300 n
344. ntention 15 5 1 Clock Phase and Polarity Controls Data Sheet Software can select any of four combinations of serial clock SPSCK phase and polarity using two bits in the SPI control register SPCR The clock polarity is specified by the CPOL control bit which selects an active high or low clock and has no significant effect on the transmission format MC68HC908AP Family Rev 2 5 294 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Transmission Formats The clock phase CPHA control bit selects one of two fundamentally different transmission formats The clock phase and polarity should be identical for the master SPI device and the communicating slave device In some cases the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements NOTE Before writing to the CPOL bit or the CPHA bit disable the SPI by clearing the SPI enable bit SPE 15 5 2 Transmission Format When CPHA 0 Figure 15 4 shows an SPI transmission in which CPHA is logic 0 The figure should not be used as a replacement for data sheet parametric information Two waveforms are shown for SPSCK one for CPOL 0 and another for CPOL 1 The diagram may be interpreted as a master or slave timing diagram since the serial clock SPSCK master in slave out MISO
345. nternal 30kQ pullup device is also enabled on the pin 20 2 Features Features of the keyboard interrupt module include the following Eight keyboard interrupt pins with pullup devices Separate keyboard interrupt enable bits and one keyboard interrupt mask Programmable edge only or edge and level interrupt sensitivity Exit from low lower modes Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Rea 0 0 0 0 KEYF 0 Keyboard Status IMASKK MODEK 001A and Control Register Write ACKK KBSCR Reset 0 0 0 0 0 0 0 0 Read Keyboard Interrupt Enable A KBIE7 KBIE6 5 KBIE4 KBIE2 KBIE1 KBIEO Register KBIER Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 20 1 KBI Register Summary MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 387 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt Module KBI 20 3 1 O Pins The eight keyboard interrupt pins are shared with standard port I O pins The full name of the KBI pins are listed in Table 20 1 The generic pin name appear in the text that follows Table 20 1 Pin Name Conventions KBI F Pin Selected for KBI Function by Generic Pin Name FUILMCH Pin Name KBIEx Bit in KBIER KBIO KBI7 PTDO KBIO PTD7 KBI7 KBIEO KBIE7 20 4 Functional Description INTERNAL BUS VECTOR FETCH DECODER ACKK
346. number CPUO8RM AD for a description of the instructions and addressing modes and more detail about the architecture of the CPU 6 5 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 6 5 1 Wait Mode The WAIT instruction e Clears the interrupt mask I bit in the condition code register enabling interrupts After exit from wait mode by interrupt the bit remains clear After exit by reset the bit is set Disables the CPU clock MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 79 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU 6 5 2 Stop Mode The STOP instruction e Clears the interrupt mask I bit in the condition code register enabling external interrupts After exit from stop mode by external interrupt the bit remains clear After exit by reset the bit is set Disables the CPU clock After exiting stop mode the CPU clock begins running after the oscillator stabilization delay 6 6 CPU During Break Interrupts If the break module is enabled a break interrupt causes the CPU to execute the software interrupt instruction SWI at the completion of the current CPU instruction See Section 23 Break Module BRK The program counter vectors to SFFFC FFFD FEFC FEFD in monitor mode A return from interrupt instruction RTI in the break routine ends the break inte
347. ock Output CGMVCLK 116 CGM Base Clock Output 116 GPU Interrupt COOMINT 116 COM Rege os hi eee PVP soe RR ER CR 116 PLL Control 117 PLL Bandwidth Control Register 119 PLL Multiplier Select Registers 121 PLL VCO Range Select 122 PLL Reference Divider Select Register 123 neck a p DUE 124 Special Modes uo ara i aed AERA ER RR d 124 TEE MOUE 1 ox ap dos E CR ICT EC EXC EROR eee 124 Stop Mode asa da oem ar ah ah ae e e 125 CGM During Break 125 Acquisition Lock Time Specifications 126 Acquisition Lock Time Definitions 126 Parametric Influences on Reaction Time 126 Choosing 128 Section 9 System Integration Module SIM a am 129 SIM Bus Clock Control and Generation 131 BUS TM 35 ue E ed RE ct SE ORE eee ed 132 Clock Start up from POR or LVI Reset 132 Clocks in Stop Mode and Wait 133 Reset and System 133 External 134 MC68HC908AP
348. oduct Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Interrupts slave This happens because SS at logic 0 indicates the start of the transmission MISO driven out with the value of MSB for CPHA When CPHA 1 a slave can be selected and then later unselected with no transmission occurring Therefore MODF does not occur since a transmission was never begun In a slave SPI MSTR 0 the MODF bit generates an SPI receiver error CPU interrupt request if the ERRIE bit is set The MODF bit does not clear the SPE bit or reset the SPI in any way Software can abort the SPI transmission by clearing the SPE bit of the slave NOTE Alogic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state Also the slave SPI ignores all incoming SPSCK clocks even if it was already in the middle of a transmission To clear the MODF flag read the SPSCR with the MODF bit set and then write to the SPCR register This entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared 15 8 Interrupts Four SPI status flags can be enabled to generate CPU interrupt requests Table 15 2 SPI Interrupts Flag Request SPTE SPI transmitter CPU interrupt request Transmitter empty SPTIE 1 SPE 1 SPRF SPI receiver CPU interrupt request Receiver full SPRIE 1 OVRF Overflow SPI receiver error interru
349. odule hangs up due to a no STOP condition received The MMIIC can resume operation again by setting the MMEN bit Data Sheet MC68HC908AP Family Rev 2 5 338 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC Program Algorithm 16 7 1 Data Sequence a Master Transmit Mode START Address o TX Datai TXDataN ACK STOP MMTXBE 0 MMTXBE 1 MMTXBE 1 1 MMNAKIF 1 MMRW O MMTXIF 1 MMTXIF 1 1 MMAST 0 MMAST 1 Data gt MMDTR Data3 MMDTR DataN42 gt MMDTR 0 Data1 MMDTR b Master Receive Mode START Address RX Datat RXDataN STOP MMRXBF 0 Data MMDRR DataN gt MMDRR 1 MMRW 1 MMRXIF 1 MMRXIF 1 MMAST 0 MMRXBF 1 MMRXBF 1 dummy data MMDTR c Slave Transmit Mode START ACK TX Dalat ack TXDataN STOP MMTXBE 1 MMRXIF 1 MMTXBE 1 1 MMNAKIF 1 ica eor MMTXIF 1 MMTXIF 1 MMTXBE 0 1 Data2 gt MMDTR MMSRW 1 DataN 2 MMDTR 1 gt MMDTR d Slave Receive Mode START Address 0 ACK ACK RXDataN STOP MMTXBE 0 MMRXIF 1 Datal MMDRR DataN MMDRR MMRXBF 0 MMRXBF 1 MMRXIF 1 MMRXIF 1 MMATCH 1 MMRXBF 1 MMRXBF 1 MMSRW 0 Shaded data packets indicate transmissions by the MCU Figure 16 12 Data Transfer Sequences for Master Slave Transmit Receive Modes MC68HC
350. of next two addresses Opcode 1A Command Sequence FROM HOST ECHO RETURN MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 163 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Data Sheet Table 10 7 IWRITE Indexed Write Command Description Write to last address accessed 1 Operand Single data byte Data Returned None Opcode 19 Command Sequence NN AE A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64 Kbyte memory map Table 10 8 READSP Read Stack Pointer Command Description Reads stack pointer Operand None Data Returns incremented stack pointer value SP 1 in Returned high byte low byte order Opcode 0C Command Sequence FROM HOST 5 SP J READSP READSP HIGH LOW ECHO RETURN MC68HC908AP Family Rev 2 5 164 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Functional Description Table 10 9 RUN Run User Program Command Description Executes PULH and RTI instructions Operand None Data Returned None Opcode 28 Command Sequence FROM HOST ECHO The MCU executes the SWI and PSHH instructions when it enters mon
351. ol Register2 0014 SCC Write Reset 0 0 0 0 0 0 0 0 a is T8 DMARE DMATE ORIE NEIE FEIE PEIE SCI Control Register 3 0015 SCC3 Write Reset U U 0 0 0 0 0 0 Read SCTE TC SCRF IDLE OR NF FE PE SCI Status Register 1 0016 SCS1 Write Reset 1 1 0 0 0 0 0 0 Read 0 0 0 0 0 0 BKF RPF SCI Status Register 2 0017 SCS2 Write Reset 0 0 0 0 0 0 0 0 Read R7 R6 R5 R4 R3 R2 R1 RO SCI Data Register 0018 SCDR Write T7 T6 T5 T4 2 TO Reset Unaffected by reset d i SCP1 SCPO R SCR2 SCR1 SCRO SCI Baud Rate Register 0019 SCBR Write Reset 0 0 0 0 0 0 0 0 Keyboard Status and Read SENT IMASK MODE 001A Control Register Write ACK KBSCR Reset 0 0 0 0 0 0 0 0 Keyboard Interrupt Poad y p KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIEO 001B Enable Register Write KBIER poset 0 0 0 0 0 0 0 0 IRQ2 Status and Control Read 0 PUCOENB 0 0 IRQ2F 0 IMASK2 MODE2 001C Register Write 2 NTSCR2 Reset 0 0 0 0 0 0 0 0 ae Read STOP STOP STOP 0 0 SCIBD 001D Configuration Register 2 Write ICLKDIS RCLKEN XCLKEN OSCCLK1 SRC CONFIG2 Reset 0 0 0 0 0 0 0 0 1 One time writable register after each reset U Unaffected X Indeterminate Unimplemented R Reserved Figure 2 2 Control Status and Data Registers Sheet 3 of 12 Data Sheet MC68HC908AP Family Rev 2 5 40 MOTOROLA For More Information O
352. oltage Inhibit LVI LVI Interrupts LVIOUT LVI Output Bit This read only flag becomes set when the Vpp or falls below their respective trip voltages Reset clears the LVIOUT bit Table 22 1 LVIOUT Bit Indication Vpp VREG LVIOUT gt VrRIPRI gt VrniPR2 Vpp lt or Vpp lt VrniPF2 lt lt Vtripri or Previous value VrniPF2 Vrea lt VrniPR2 22 5 LVI Interrupts The LVI module does not generate interrupt requests 22 6 Low Power Modes The STOP and WAIT instructions put the MCU in low power consumption standby modes 22 6 1 Wait Mode If enabled the LVI module remains active in wait mode If enabled to generate resets the L VI module can generate a reset and bring the MCU out of wait mode 22 6 2 Stop Mode If enabled in stop mode LVISTOP 1 the LVI module remains active in stop mode If enabled to generate resets LVIRSTD 0 the LVI module can generate a reset and bring the MCU out of stop mode MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 405 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Voltage Inhibit LVI Data Sheet MC68HC908AP Family Rev 2 5 406 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 23 Break
353. on MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 311 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI When an SPI is configured as a master the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK See 15 7 2 Mode Fault Error For the state of the SS pin to set the MODF flag the MODFEN bit in the SPSCK register must be set If the MODFEN bit is low for an SPI master the SS pin can be used as a general purpose I O under the control of the data direction register of the shared I O port With MODFEN high it is an input only pin to the SPI regardless of the state of the data direction register of the shared I O port The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register See Table 15 3 Table 15 3 SPI Configuration SPE SPMSTR MODFEN SPI Configuration State of SS Logic General purpose 1 0 x Meat enabled SS ignored by SPI 1 0 X Slave Input only to SPI 1 1 0 Master without Mopr General purpose l O SS ignored by SPI 1 1 1 Master with MODF Input only to SPI Note 1 X Don t care 15 12 5 CGND Clock Ground CGND is the ground return for the serial clock pin SPSCK and the ground for the port output buffers It is internally connected to Vgs
354. on On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications SS INPUT SS PIN OF MASTER HELD HIGH a 1 NOTE 4 SPSCK OUTPUT 0 SPSCK OUTPUT 1 MISO INPUT MOSI OUTPUT MASTER MSB OUT MASTER LSB OUT Note This first clock edge is generated internally but is not seen at the SPSCK pin a SPI Master Timing CPHA 0 SS x INPUT SS PIN OF MASTER HELD HIGH SPSCK OUTPUT 8 0 NOTE SPSCK OUTPUT CPOL 1 MOSI OUTPUT MASTER LSB OUT Note This last clock edge is generated internally but is not seen at the SPSCK pin b SPI Master Timing CPHA 1 Figure 24 3 SPI Master Timing Data Sheet MC68HC908AP Family Rev 2 5 430 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 3V SPI Characteristics 55 INPUT SPSCK INPUT CPOL 0 SPSCK INPUT CPOL 1 Note Not defined but normally MSB of character just received a SPI Slave Timing CPHA 0 SS INPUT SPSCK INPUT CPOL 0 SPSCK INPUT CPOL 1 MISO OUTPUT MOSI INPUT Note Not defined but normally LSB of character previously transmitted b SPI Slave Timing CPHA 1 Figure 24 4 SPI Slave Timing MC68HC908AP Family Rev 2 5 Data Sheet
355. on port D data KBI7 KBIO Keyboard Interrupt Inputs The keyboard interrupt enable bits KBIE 7 0 in the keyboard interrupt enable register KBIER enable the port D pins as external interrupt pins See Section 20 Keyboard Interrupt Module KBI Data Sheet MC68HC908AP Family Rev 2 5 376 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output I O Ports Port D 18 5 2 Data Direction Register D DDRD Data direction register D determines whether each port D pin is an input or an output Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin a logic O disables the output buffer Address 0007 Bit 7 6 5 4 3 2 1 Bit 0 Read DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRDO Write Reset 0 0 0 0 0 0 0 0 Figure 18 13 Data Direction Register D DDRD DDRD 7 0 Data Direction Register D Bits These read write bits control port D data direction Reset clears DDRD 7 0 configuring all port D pins as inputs 1 Corresponding port D pin configured as output 0 Corresponding port D pin configured as input NOTE Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from O to 1 Figure 18 14 shows the port D logic Z w READ DDRD 0007 rat KBIEx
356. onitor mode without high voltage on IRQ1 above condition set 2 or 3 where applied voltage is either Vpp or Vss then all port A pin requirements and conditions including the PTBO frequency divisor selection are not in effect This is to reduce circuit requirements when performing in circuit programming MC68HC908AP Family Rev 2 5 156 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Functional Description q SI e1s uo NOW SUL eq 1snui diuo pessed HO ZHIN 7068 6 2516 e 51 Aq Joiuol E Joje roso diuo jo ZHIN 7068 6 26 L6 v 10 e1s u9 ZH 89 26 si Z Ov Ld jenas OVWLd 1 Jesn 3 Pm 19891 ssaippe ue jejunooue Jesn peiqeu3 JOWUOW Ul es sog peiqeue 0096 peigesiq Aq s ew e Aouenbea jeuJo1x3 0096 peigesiq ouenbeJj SseutiuJejep 091 ASIA LOHI peuinboJ Ajuo seBeyoA oVLd pue 1 0096 peigesiq 0914 4914 LOHI y peuinboj Ajuo seBeyoA oVLd pue 1 0096 peigesiq uiu seo ON peigesiq eS ojeH ouenbeJ4 1 pneg doo sng suondo
357. parity bit Idle character length depends on the M bit in IRSCC1 The preamble is a synchronizing idle character that begins every transmission If the TE bit is cleared during a transmission the TxD pin becomes idle after completion of the transmission in progress Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 259 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications NOTE When queueing an idle character return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin Setting TE after the stop bit appears on TxD causes data previously written to the IRSCDR to be lost Toggle the TE bit for a queued idle character when the SCTE bit becomes set and just before writing the next byte to the IRSCDR 14 6 2 Transmitter Interrupts 14 6 3 Receiver The following conditions can generate CPU interrupt requests from the SCI transmitter e transmitter empty SCTE The SCTE bit in IRSCS1 indicates that the IRSCDR has transferred a character to the transmit shift register SCTE can generate a transmitter CPU interrupt request Setting the SCI transmit interrupt enable bit SCTIE in IRSCC2 enables the SCTE bit to generate transmitter CPU interrupt requests Transmi
358. patible with hardware cyclic redundancy code CRC generation making it suitable for smart battery applications MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 319 For More Information On This Product Go to www freescale com 16 2 Features Freescale Semiconductor Inc Multi Master IIC Interface MMIIC Features of the MMIC module include Full SMBus version 1 0 1 1 compliance Multi master bus standard Software programmable for one of eight different serial clock frequencies Software controllable acknowledge bit generation Interrupt driven byte by byte data transfer Calling address identification interrupt Arbitration loss detection and no ACK awareness in master mode and automatic mode switching from master to slave Auto detection of R W bit and switching of transmit or receive mode accordingly Detection of START repeated START and STOP signals Auto generation of START and STOP condition in master mode Repeated start generation Master clock generator with eight selectable baud rates Automatic recognition of the received acknowledge bit Busy detection Software enabled 8 bit CRC generation decoding 16 3 I O Pins The MMIIC module uses two I O pins shared with standard port I O pins The full name of the MMIIC I O pins are listed in Table 16 1 The generic pin name appear in the text that follows The SDA and SDL pins are open drain When configured as general purpose output pins PTBO and PT
359. peration must be within the application s tolerance of fyc pgs and fyrs must be as close as possible to fyc NOTE Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 111 For More Information On This Product Go to www freescale com Data Sheet NOTE Frees 9 Prog a cale Semiconductor Inc Clock Generator Module CGM ram the PLL registers accordingly In the PRE bits of the PLL control register PCTL program the binary equivalent of P In the VPR bits of the PLL control register PCTL program the binary equivalent of E In the PLL multiplier select register low PMSL and the PLL multiplier select register high PMSH program the binary equivalent of N In the PLL VCO range select register PMRS program the binary coded equivalent of L In the PLL reference divider select register PMDS program the binary coded equivalent of R The values for P E L and can only be programmed when the PLL is off PLLON Table 8 1 provides numeric examples numbers are in hexadecimal notation Table 8 1 Numeric Examples CGMVCLK CGMPCLK fBus fRcLK R N L 8 0 MHz 8 0 MHz 2 0MHz 32 768 kHz F5 0 0 40 9 8304 MHz 9 8304 MHz 2 4576 MHz 32 768 kHz 120 0 1 27 10 0 MHz 10 0 MHz 2 5 MHz 32 768 kHz 132 0 1 28 16 MHz 16 MHz 4 0MHz 32 768 kHz 1
360. pt request ERRIE 1 MODF Mode fault SPI receiver error interrupt request ERRIE 1 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 305 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF The clearing mechanism for the SPTE flag is always just a write to the transmit data register The SPI transmitter interrupt enable bit SPTIE enables the SPTE flag to generate transmitter CPU interrupt requests provided that the SPI is enabled SPE 1 The SPI receiver interrupt enable bit SPRIE enables the SPRF bit to generate receiver CPU interrupt requests regardless of the state of the SPE bit See Figure 15 11 The error interrupt enable bit ERRIE enables both the MODF and bits to generate a receiver error CPU interrupt request The mode fault enable bit MODFEN can prevent the MODF flag from being set so that only the bit is enabled by the ERRIE bit to generate receiver error CPU interrupt requests NOT AVAILABLE gt SPTE SPTIE SPE SPI TRANSMITTER gt CPU INTERRUPT REQUEST R NOT AVAILABLE gt SPRIE SPRF 2 9 gt RECEIVER ERROR Lei ERRIE 15 CPU INTERRUPT REQUEST ap OVRF Figure 15 11 SPI Interrupt Request Generation
361. pt request from the SCI module can bring the MCU out of wait mode If SCI module functions are not required during wait mode reduce power consumption by disabling the module before executing the WAIT instruction Refer to 9 6 Low Power Modes for information on exiting wait mode 14 7 2 Stop Mode The SCI module is inactive after the execution of a STOP instruction The STOP instruction does not affect SCI register states SCI module operation resumes after an external interrupt Because the internal clock is inactive during stop mode entering stop mode during an SCI transmission or reception results in invalid data Refer to 9 6 Low Power Modes for information on exiting stop mode 14 8 SCI During Break Module Interrupts The system integration module SIM controls whether status bits in other modules can be cleared during interrupts generated by the break module The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state To allow software to clear status bits during a break interrupt write a logic 1 to the BCFE bit If a status bit is cleared during the break state it remains cleared when the MCU exits the break state MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 269 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications 14 9 1 Signals To protect status bits during the b
362. put capture operation or unbuffered output compare PWM operation See Table 11 3 1 Unbuffered output compare PWM operation 0 Input capture operation Data Sheet MC68HC908AP Family Rev 2 5 200 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM I O Registers When ELSxB ELSxA 0 0 this read write bit selects the initial output level of the TCHx pin See Table 11 3 Reset clears the MSxA bit 1 Initial output level low 0 Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSXA bit set the TSTOP and TRST bits in the TIM status and control register TSC ELSxB and ELSxA Edge Level Select Bits When channel x is an input capture channel these read write bits control the active edge sensing logic on channel x When channel x is an output compare channel ELSxB and ELSxA control the channel x output behavior when an output compare occurs When ELSxB and ELS XA are both clear channel x is not connected to an port and pin TCHx is available as a general purpose pin Table 11 3 shows how ELSxB and ELSxA work Reset clears the ELSxB and ELSxA bits Table 11 3 Mode Edge and Level Selection MSxB MSxA ELSxB ELSxA Mode Configuration Pin under port control e 99 initial output level high Output preset 00 Pin under port control initial output l
363. quency is tight choose fpc to an integer divisor of fguspgs and R 1 If fac cannot meet this requirement use the following equation to solve for R with practical choices of fac and choose the fpc that gives the lowest R f f R round Bmax spes integer vones Calculate Rxf N round d P facik x2 Calculate and verify the adequacy of the VCO and bus frequencies and fgus N g fBus MC68HC908AP Family Rev 2 5 110 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM Functional Description 5 Select the VCO s power of two range multiplier E according to this table Frequency Range E 0 lt lt 9 830 400 0 9 830 400 x lt 19 660 800 1 19 660 800 lt lt 39 321 600 2 NOTE Do not program E to a value of 3 6 Select a VCO linear range multiplier L where foy 125kHz f L rouna CL 2 xfwo 7 Calculate and verify the adequacy of the VCO programmed center of range frequency fyrs The center of range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL E fing Ex 2 For proper operation E f _ lt 2_ vns 5 8 Verify the choice of P E and L by comparing to fyrs and fyci pgs For proper o
364. r Address These seven bits represent the MMIIC interface s own specific slave address when in slave mode and the calling address when in master mode Software must update MMAD 7 1 as the calling address while entering master mode and restore its own slave address after master mode is relinquished This register is cleared as A0 upon reset MMEXTAD Multi Master Expanded Address This bit is set to expand the address of the MMIIC in slave mode When set the MMIIC will acknowledge the following addresses from a calling master MMAD 7 1 0000000 and 0001 100 Reset clears this bit 1 MMIIC responds to the following calling addresses MMADJ 7 1 0000000 and 0001 100 0 MMIIC responds to address MMADYJ 7 1 For example when MMADR is configured as MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD 1 1 0 1 0 1 0 1 The MMIIC module will respond to the calling address Bit 7 6 5 4 3 2 Bit 1 1 1 0 1 0 1 0 or the general calling address 0 0 0 0 0 0 0 or the calling address Bit 7 6 5 4 3 2 Bit 1 0 0 0 1 1 0 0 Note that bit O of the 8 bit calling address is the MMRW bit from the calling master MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 327 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC
365. r all internal reset sources To prevent a COP module timeout write any value to location FFFF Writing to location FFFF clears the COP counter and bits 12 through 5 of the SIM counter The SIM counter output which occurs at least every 213 _ 2 CLK cycles drives the COP counter The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout The COP module is disabled if the RST pin or the IRQ1 pin is held at Vtst while the MCU is in monitor mode The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ1 pin This prevents the COP from becoming disabled as a result of external noise During a break state on the RST pin disables the COP module MC68HC908AP Family Rev 2 5 136 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Reset and System Initialization 93 2 3 Oocode Reset The SIM decodes signals from the CPU to detect illegal instructions An illegal instruction sets the ILOP bit in the SIM reset status register SRSR and causes a reset If the stop enable bit STOP in the mask option register is logic O the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset The SIM actively pulls down the RST pin for all internal reset sources 93 24 I
366. r is a 16 bit register that contains the address of the next instruction or operand to be fetched Normally the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched Jump branch and interrupt operations load the program counter with an address other than that of the next sequential location During reset the program counter is loaded with the reset vector address located at FFFE and FFFF The vector address is the address of the first instruction to be executed after exiting the reset state 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Read Write Reset Loaded with Vector from FFFE and FFFF Figure 6 5 Program Counter PC Data Sheet MC68HC908AP Family Rev 2 5 76 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU CPU Registers 6 3 5 Condition Code Register The 8 bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed Bits 6 and 5 are set permanently to logic 1 The following paragraphs describe the functions of the condition code register Bit 7 6 5 4 3 2 1 Bit 0 Read V 1 1 H 7 Write Reset X 1 1 X 1 X X X X Indeterminate Figure 6 6 Condition Code Register CCR V Overflow F
367. r selectable oscillator clock source enable during stop mode to allow periodic wake up from stop MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 205 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Module TBM 12 3 Functional Description This module can generate a periodic interrupt by dividing the oscillator clock frequency OSCCLK The counter is initialized to all Os when TBON bit is cleared The counter shown in Figure 12 1 starts counting when the TBON bit is set When the counter overflows at the tap selected by TBR 2 0 the TBIF bit gets set If the TBIE bit is set an interrupt request is sent to the CPU The TBIF flag is cleared by writing a 1 to the TACK bit The first time the TBIF flag is set after enabling the timebase module the interrupt is generated at approximately half of the overflow period Subsequent events occur at the exact period The reference clock OSCCLK is derived from the oscillator module see 7 2 2 TBM Reference Clock Selection OSCCLK From OSC module See Section 7 Oscillator OSC 64 2048 262144 Data Sheet Figure 12 1 Timebase Block Diagram MC68HC908AP Family Rev 2 5 206 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timebase Module TBM Time
368. r supply for analog circuits In Vpp Vssa Power supply ground for analog circuits Out Vss VREFH ADC input reference high In VDDA VREFL ADC input reference low Out Vssa Internal 2 5V regulator output V 1 REG Require external capacitors for decoupling san 2 5V RST Reset input active low with internal pullup and schmitt in Von trigger input External IRQ1 pin with internal pullup and schmitt trigger in V IRQI input DD Used for mode entry selection In Vpp to Vtst OSC1 Crystal or RC oscillator input In VnEG Crystal OSC option crystal oscillator output inverted Out OSC1 0562 RC option bus clock output Out VREG Internal OSC option bus clock output Out VREG CGMXFC CGM external filter capacitor connection In Out Analog 8 bit general purpose I O port In Out Vpp PTAO ADCO Pins as ADC inputs ADCO ADC7 In VREFH PTA7 ADC7 Each pin has high current sink for LED Out VDD Data Sheet MC68HC908AP Family Rev 2 5 30 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description Pin Functions Table 1 2 Pin Functions VOLTAGE PIN NAME PIN DESCRIPTION IN OUT LEVEL 8 bit general purpose I O port are open drain when configured as output PTB4 PTB7 have schmitt In Out Vpp trigger inputs PTBO SDA PTBO as SDA of MMIIC In Out Vpp PTB1 SCL PTB2 TxD PT
369. raming error Parity error Receiver framing error detection Hardware parity checking 1 16 bit time noise detection Features of the infrared IR sub module include the following Data Sheet IR sub module enable disable for infrared SCI or conventional on SCTxD and SCRxD pins Software selectable infrared modulation demodulation 3 16 1 16 or 1 32 width pulses MC68HC908AP Family Rev 2 5 250 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI Features Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0 T IRSCI Control Register 1 Ws LOOPS ENSCI M WAKE ILTY PEN PTY IRSCC1 Reset 0 0 0 0 0 0 0 0 Read goo41 Control Register2 wi SCRIE TE RE RWU SBK IRSCC2 Reset 0 0 0 0 0 0 0 0 Read R8 wi IRSCI Control Register 3 n T8 DMARE DMATE ORIE NEIE FEIE PEIE IRSCC3 Reset U U 0 0 0 0 0 0 Read SCTE TC SCRF IDLE OR NF FE PE IRSCI Status Register 1 0043 IRSCS1 Write Reset 1 1 0 0 0 0 0 0 Read BKF RPF IRSCI Status Register2 0044 IRSCS2 Write Reset 0 0 0 0 0 0 0 0 Read R7 R6 R5 R4 R3 R2 R1 RO IRSCI Data Register 0045 IRSCDR
370. ransmits a 3 16 narrow pulse 01 SCI transmits a 1 16 narrow pulse 10 SCI transmits a 1 32 narrow pulse IREN Infrared Enable Bit This read write bit enables the infrared sub module for encoding and decoding the SCI data stream When this bit is clear the infrared sub module is disabled Reset clears the IREN bit 1 infrared sub module enabled 0 infrared sub module disabled Data Sheet MC68HC908AP Family Rev 2 5 288 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 15 Serial Peripheral Interface Module SPI 15 1 Introduction This section describes the serial peripheral interface SPI module which allows full duplex synchronous serial communications with peripheral devices 15 2 Features Features of the SPI module include the following Full duplex operation e Master and slave modes Double buffered operation with separate transmit and receive registers e Four master mode frequencies maximum bus frequency 2 e Maximum slave mode frequency bus frequency e Serial clock with programmable polarity and phase Two separately enabled interrupts SPRF SPI receiver full SPTE SPI transmitter empty e Mode fault error flag with CPU interrupt capability e Overflow error flag with CPU interrupt capability e Programmable wired OR mode MC68HC908AP Family Rev 2 5 Dat
371. rastic changes in the operation of the PLL These factors include noise injected into the PLL through the filter capacitor filter capacitor leakage stray impedances on the circuit board and even humidity or circuit board contamination MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 127 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module 8 8 3 Choosing a Filter As described in 8 8 2 Parametric Influences on Reaction Time the external filter network is critical to the stability and reaction time of the PLL The PLL is also dependent on reference frequency and supply voltage Either of the filter networks in Figure 8 10 is recommended when using a 32 768kHz reference clock CGMRCLK Figure 8 10 a is used for applications requiring better stability Figure 8 10 b is used in low cost applications where stability is not critical CGMXFC CGMXFC be 1 gt d eye BRE 022yF 0 22 e Vssa VssA a b Figure 8 10 PLL Filter Data Sheet MC68HC908AP Family Rev 2 5 128 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 9 System Integration Module SIM 9 Introduction This section describes the system integration module SIM Together with the CPU the SIM controls all MCU activities
372. rated in Figure 16 12 16 6 6 MMIIC Data Receive Register MMDRR Address 004D Bit 7 6 5 4 3 2 1 Bit 0 Read MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRDO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 16 9 MMIIC Data Receive Register MMDRR When the MMIIC module is enabled MMEN 1 data in this read only register depends on whether module is in master or slave mode MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 335 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC In slave mode the data in MMDRR is e the calling address from the master when the address match flag is set MMATCH 1 or e the last data received when MMATCH 0 In master mode the data in the MMDRR is e the last data received When the MMDRR is read by the CPU the receive buffer full flag is cleared MMRXBF 0 and the next received data is loaded to the MMDRR Each time when new data is loaded to the MMDRR the MMRXIF interrupt flag is set indicating that new data is available in MMDRR The sequence of events for slave receive and master receive are illustrated in Figure 16 12 16 6 7 MMIIC CRC Data Register MMCRCDR Data Sheet Address 004E Bit 7 6 5 4 3 2 1 Bit 0 Read MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCDO Write
373. re and can read all FLASH locations and execute code from FLASH Security remains bypassed until a power on reset occurs If the reset was not a power on reset security remains bypassed and security code entry is not required See Figure 10 8 4096 32 ICLK CYCLES 256 BUS CYCLES MINIMUM a lt e e gt gt gt Q m m m FROM HOST Ww DL CDIC FROM MCU 5 5 5 5 2 2 t amp 5 5 1 Echo delay 2 bit times Oo 2 Data return delay 2 bit times 4 Wait 1 bit time before sending next byte Figure 10 8 Monitor Mode Entry Timing MC68HC908AP Family Rev 2 5 166 MOTOROLA For More Information On This Product Go to www freescale com NOTE Freescale Semiconductor Inc Monitor ROM MON Security Upon power on reset if the received bytes of the security code do not match the data at locations FFF6 FFFD the host fails to bypass the security feature The MCU remains in monitor mode but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset After receiving the eight security bytes from the host the MCU transmits a break character signifying that itis ready to receive a command The MCU does not transmit a break character until after the host sends the eight security bits To de
374. re disabling the master SPI See 15 13 1 SPI Control Register Only a master SPI module can initiate transmissions Software begins the transmission from a master SPI module by writing to the transmit data register If the shift register is empty the byte immediately transfers to the shift register setting the SPI transmitter empty bit SPTE The byte begins shifting out on the MOSI pin under the control of the serial clock See Figure 15 3 MASTER MCU SLAVE MCU SHIFT REGISTER SHIFT REGISTER BAUD RATE GENERATOR Figure 15 3 Full Duplex Master Slave Connections MC68HC908AP Family Rev 2 5 292 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Functional Description The SPR1 and SPRO bits control the baud rate generator and determine the speed of the shift register See 15 13 2 SPI Status and Control Register Through the SPSCK pin the baud rate generator of the master also controls the shift register of the slave peripheral As the byte shifts out on the MOSI pin of the master another byte shifts in from the slave on the master s MISO pin The transmission ends when the receiver full bit SPRF becomes set At the same time that SPRF becomes set the byte from the slave transfers to the receive data register In normal operation SPRF signals the end of a transmission Software clears SPRF by
375. re of the SCI INTERNAL BUS SCI DATA SCI DATA REGISTER REGISTER Lic if 258 268 S82 s58 RECEIVE mee QEE TRANSMIT SOLD SHIFT REGISTER 255 Qus Sus SHIFT REGISTER 22 220 gt SCTIE TCIE SCRIE ILIE TE RE RWU SBK LOOPS LOOPS ENSCI gt WAKEUP RECEIVE FLAG TRANSMIT CONTROL CONTROL CONTROL CONTROL me BKF CKS ENSCI Es ILTY CGMXCLK BAUD SL 0 gt X A SLet gt X B m DATA SELECTION SCLR32XCLK CONTROL SCLRIGXCLK lt Figure 14 5 SCI Module Block Diagram MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 255 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications The SCI allows full duplex asynchronous NRZ serial communication between the MCU and remote devices including other MCUs The transmitter and receiver of the SCI operate independently although they use the same baud rate generator During normal operation the CPU monitors the status of the SCI writes the data to be transmitted and processes received data NOTE For SCI operations the sub module is transparent to the SCI module Data at going out of the SCI transmitter and data going into the SCI rec
376. reading address 0002 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 18 4 summarizes the operation of the port C pins Table 18 4 Port C Pin Functions DDRC PTC JOE Accesses to DDRC Accesses to PTC Bit Bit TOM Read Write Read Write 0 X input Hi Z DDRCTZ 0 Pin i 1 X Output DDRC 7 0 PTC 7 0 PTC 7 0 Notes 1 X don t care 2 Hi Z high impedance 3 Writing affects data register but does not affect input MC68HC908AP Family Rev 2 5 Data Sheet 375 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports 18 5 Port D Port D is an 8 bit special function port that shares all of its pins with the keyboard interrupt module 18 5 1 Port D Data Register PTD The port D data register contains a data latch for each of the eight port D pins Address 0003 Bit 7 6 5 4 3 2 1 Bit 0 Read PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTDO Write Reset Unaffected by reset Alternative Function 7 KBI6 KBI5 KBI4 KBI3 2 1 0 Figure 18 12 Port D Data Register PTD PTD 7 0 Port D Data Bits These read write bits are software programmable Data direction of each port D pin is under the control of the corresponding bit in data direction register D Reset has no effect
377. reading the SPI status and control register with SPRF set and then reading the SPI data register Writing to the SPI data register clears the SPTE bit 15 4 2 Slave Mode The SPI operates in slave mode when the SPMSTR bit is clear In slave mode the SPSCK pin is the input for the serial clock from the master MCU Before a data transmission occurs the SS pin of the slave SPI must be at logic 0 SS must remain low until the transmission is complete See 15 7 2 Mode Fault Error In a slave SPI module data enters the shift register under the control of the serial clock from the master SPI module After a byte enters the shift register of a slave SPI it transfers to the receive data register and the SPRF bit is set To prevent an overflow condition slave software then must read the receive data register before another full byte enters the shift register The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed which is twice as fast as the fastest master SPSCK clock that can be generated The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master Therefore the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 293 For More Information On This
378. reak state write a logic O to the BCFE bit With BCFE at logic O its default state software can read and write I O registers during the break state without affecting status bits Some status bits have a two step read write clearing procedure If software does the first step on such a bit before the break the bit cannot change during the break state as long as BCFE is at logic O After the break doing the second step clears the status bit The two IRSCI pins are e PTC6 SCTxD Transmit data PTC7 SCRxD Receive data 14 9 1 PTC6 SCTxD Transmit Data NOTE The PTC6 SCTXxD pin is the serial data standard or infrared output from the SCI transmitter The IRSCI shares the PTC6 SCTXD pin with port C When the IRSCI is enabled the PTC6 SCTXD pin is an output regardless of the state of the DDRC6 bit in data direction register C DDRC The PTC6 SCTXD pin is an open drain pin when configured as an output Therefore when configured as SCTxD or a general purpose output pin PTC6 a pullup resistor must be connected to this pin 14 9 2 PTC7 SCRxD Receive Data Data Sheet NOTE The PTC7 SCRxD pin is the serial data input to the IRSCI receiver The IRSCI shares the PTC7 SCRxD pin with port C When the IRSCI is enabled the PTC7 SCRxD pin is an input regardless of the state of the DDRC7 bit in data direction register C DDRC The PTC7 SCRxD pin is open drain pin when configured as an output Therefore when con
379. receiver of the SCI operate independently although they use the same baud rate generator During normal operation the CPU monitors the status of the writes the data to be transmitted and processes received data The baud rate clock source for the SCI can be selected via the configuration bit SCIBDSRC of the CONFIG2 register 001D Source selection values are shown in Figure 13 1 Data Sheet MOTOROLA 213 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface RxD CGMXCLI IT12 INTERNAL BUS SCI DATA REGISTER RECEIVE SHIFT REGISTER 50 az Lo zo TRANSMITTER INTERRUPT CONTROL RECEIVER INTERRUPT CONTROL ERROR INTERRUPT CONTROL TXINV R8 T8 DMARE OR DMATE NF ORIE FE NEIE PE FEIE PEIE SCTIE TCIE SCRIE SCTE RE TC RWU SCRF SBK IDLE WAKEUP CONTROL SCIBDSRC FROM CONFIG ENSCI m PRE BA X SCALER DIVI SL 0 gt X A SL 1 gt X B CGMXCLK is from CGM module IT12 fgus Data Sheet DER LOOPS BKF RPF LOOP
380. reescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI 15 6 Queuing Transmission Data Data Sheet The double buffered transmit data register allows a data byte to be queued and transmitted For an SPI configured as a master a queued data byte is transmitted immediately after the previous transmission has completed The SPI transmitter empty flag SPTE indicates when the transmit data buffer is ready to accept new data Write to the transmit data register only when the SPTE bit is high Figure 15 8 shows the timing associated with doing back to back transmissions with the SPI SPSCK has CPHA CPOL 1 0 WRITE SPDR CO GJ Y SPTE 8 5 SPSCK CPHA CPOL 1 0 MOSI MSB BIT BIT BIT BIT BIT BIT LSBIMSB BIT BIT BIT BIT LSBMSB BIT BIT 61514131211 61514131211 61514 BYTE BYTE2 BYTE3 SPRF 9 READ SPSCR Y D READ SPDR V 1 CPU WRITES BYTE 1 TO SPDR CLEARING SPTE BIT 2 BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER SETTING SPTE BIT 3 CPU WRITES BYTE 2 TO SPDR QUEUEING BYTE 2 AND CLEARING SPTE BIT 4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER SETTING SPRF BIT 5 BYTE 2 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER SETTING SPTE BIT 6 CPU READS SPSCR WITH SPRF BIT SET 7 CPU READS SPDR CLEARING SPRF BIT CPU WRITES BYTE 3 TO SPDR QUEUEIN
381. request and the MODEK bit clearing the interrupt request even if a keyboard interrupt pin stays at logic O MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 389 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt Module KBI NOTE The keyboard flag bit KEYF in the keyboard status and control register can be used to see if a pending interrupt exists The KEYF bit is not affected by the keyboard interrupt mask bit IMASKK which makes it useful in applications where polling is preferred To determine the logic level on a keyboard interrupt pin use the data direction register to configure the pin as an input and read the data register Setting a keyboard interrupt enable bit KBIEx forces the corresponding keyboard interrupt pin to be an input overriding the data direction register However the data direction register bit must be a logic O for software to read the pin 20 4 1 Keyboard Initialization Data Sheet When a keyboard interrupt pin is enabled it takes time for the internal pull up to reach a logic 1 Therefore a false interrupt can occur as soon as the pin is enabled To prevent a false interrupt on keyboard initialization 1 Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register 2 Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register 3 Write to t
382. reset states See 9 3 2 Active Resets from Internal Sources for counter control and internal reset recovery sequences MC68HC908AP Family Rev 2 5 138 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Exception Control 9 5 Exception Control Normal sequential program execution can be changed in three different ways e Interrupts Maskable hardware CPU interrupts Non maskable software interrupt instruction SWI Reset Break interrupts 9 5 1 Interrupts At the beginning of an interrupt the CPU saves the CPU register contents on the stack and sets the interrupt mask I bit to prevent additional interrupts At the end of an interrupt the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume Figure 9 8 shows interrupt entry timing and Figure 9 9 shows interrupt recovery timing MODULE INTERRUPT IAB Dummy sp sp 1 sP 2 sP s sP 4 6 ADDR Dummy pc 17 pc 1158 VDATAL OPCODE RW Figure 9 8 Interrupt Entry Timing MODULE INTERRUPT IAB sp 4 sp 3 j sp 2 sp 1 sp Pc sce Y Y A Y x Jjec tt58 PC 1701 OPCODE OPERAND RAW NA Figure 9 9 Interrupt Recovery Timing MC
383. rror Bit This clearable read only bit is set when a logic 0 is accepted as the stop bit FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set Clear the FE bit by reading SCS1 with FE set and then reading the SCDR Reset clears the FE bit 1 Framing error detected 0 No framing error detected Data Sheet MC68HC908AP Family Rev 2 5 242 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface Module SCI Registers NORMAL FLAG CLEARING SEQUENCE 0 I I I I I I LL LL LL LL LL LL tc tc tr tr tr 1 2 4 y A A A READ SCS1 E READ SCS1 E READ SCS1 SCRF 1 SCRF 1 SCRF 1 OR 0 OR 0 OR 0 READ SCDR READ SCDR READ SCDR BYTE 1 BYTE 2 BYTE 3 DELAYED FLAG CLEARING SEQUENCE 2 o o a Es We da e Eu tr tr BO BO 95 BO READ SCS1 READ SCS1 SCR F 1 SCRF 1 OR 0 OR 1 READ SCDR READ SCDR BYTE 1 BYTE 3 Figure 13 13 Flag Clearing Sequence PE Receiver Parity Error Bit This clearable read only bit is set when the SCI detects a parity error in incoming data PE generates an SCI error CPU interrupt request if the PEIE bit in SCC3 is also set Clear the PE bit by reading SCS1 with PE set and then reading the SCDR Reset clears the PE bit 1 Parity error detecte
384. rrupt llegal opcode detection with reset Illegal address detection with reset 48 pin low quad flat pack LQFP 44 pin quad flat pack QFP and 42 pin shrink dual in line package SDIP Specific features of the MC68HC908AP6E4 in 42 pin SDIP are 30 general purpose I Os only External interrupt on IRQ1 only Features of the CPUOS include the following Enhanced 5 programming model Extensive loop control functions 16 addressing modes eight more than the 5 16 bit Index register and stack pointer Memory to memory data transfers Fast 8 x 8 multiply instruction Fast 16 8 divide instruction Binary coded decimal BCD instructions Optimization for controller applications Efficient C language support 1 3 MCU Block Diagram Figure 1 1 shows the structure of the MC68HC908AP64 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description INTERNAL BUS M68HC08 CPU PTA7 ADC7 CPU ARITHMETIC LOGIC 10 BIT ANALOG TO DIGITAL PTAS ADCS REGISTERS UNIT ALU CONVERTER MODULE Eno tc alg PTA3 ADC3 CONTROL AND STATUS REGISTERS 96 BYTES TIMEBASE PTA2 ADC2 MODULE oy PTAT ADC1 USER FLASH SEE TABLE PTAO ADCO USER RAM SEE TABLE
385. rrupt and returns the MCU to normal operation if the break interrupt has been deasserted 6 7 Instruction Set Summary Table 6 1 provides a summary of the M68HCO8 instruction set 6 8 Opcode Map The opcode map is provided in Table 6 2 Data Sheet MC68HC908AP Family Rev 2 5 80 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Opcode Map Table 6 1 Instruction Set Summary Sheet 1 of 8 Effect on Operation Description CCR 9 g S 9 3 3 9 2 1 2 33 8 8 5 ADC opr IMM A9 2 ADC opr DIR B9 dd 3 ADC opr EXT C9 hhil 4 ADC opr X 1 2 09 4 ADC opr X Add with Carry A A M C 2 2 21 217 X1 Eg 3 ADC X IX F9 2 ADC opr SP SP1 9EE9 ff 4 ADC opr SP SP2 9ED9 5 ADD opr IMM AB 2 ADD opr DIR BB dd 3 ADD opr EXT CB 4 ADD opr X IX2 DB eeff 4 ADD opr X Add without Carry lt M 21 2 21 217 X1 EB lf 3 ADD X IX FB 2 ADD opr SP SP1 9EEB 4 ADD opr SP SP2 9EDB eeff 5 AIS opr Add Immediate Value Signed to SP SP lt SP 16 M A7 2 AIX opr Add Immediate Value Signed to H X lt 16 M AF ii 2 AND opr IMM 4
386. rty two ICLK cycles later the CPU and memories are released from reset to allow the reset vector sequence to occur At power on these events occur MC68HC908AP Family Rev 2 5 A POR pulse is generated The internal reset signal is asserted The SIM enables CGMOUT Internal clocks to the CPU and modules are held inactive for 4096 ICLK cycles to allow stabilization of the oscillator The pin is driven low during the oscillator stabilization time The POR bit of the SIM reset status register SRSR is set and all other bits in the register are cleared Data Sheet MOTOROLA 135 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM OSC1 PORRST IAB ft 4096 32 32 CYCLES CYCLES CYCLES i lt pel P5 P5 T A FFFF Figure 9 7 POR Recovery 93 22 Computer Operating Properly COP Reset Data Sheet An input to the SIM is reserved for the COP reset signal The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register SRSR The SIM actively pulls down the RST pin fo
387. rupt requests Transmission complete TC The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated The transmission complete interrupt enable bit TCIE in SCC2 enables the TC bit to generate transmitter CPU interrupt requests MC68HC908AP Family Rev 2 5 220 MOTOROLA For More Information On This Product Go to www freescale com 13 4 3 Receiver Freescale Semiconductor Inc Serial Communications Interface Module SCI Functional Description Figure 13 5 shows the structure of the SCI receiver 13 4 3 1 Character Length The receiver can accommodate either 8 bit or 9 bit data The state of the M bit in SCI control register 1 SCC1 determines character length When receiving 9 bit data bit R8 in SCI control register 2 SCC2 is the ninth bit bit 8 When receiving 8 bit data bit R8 is a copy of the eighth bit bit 7 13 43 2 Character Reception During an SCI reception the receive shift register shifts characters in from the RxD pin The SCI data register SCDR is the read only buffer between the internal data bus and the receive shift register After a complete character shifts into the receive shift register the data portion of the character transfers to the SCDR The SCI receiver full bit SCRF in SCI status register 1 SCS1 becomes set indicating that the received byte can be read If the SCI receive interrupt en
388. rupt requests by setting the error interrupt enable bit ERRIE See 15 8 Interrupts The SPI module is inactive after the execution of a STOP instruction The STOP instruction does not affect register conditions SPI operation resumes after an external interrupt If stop mode is exited by reset any transfer in progress is aborted and the SPI is reset MC68HC908AP Family Rev 2 5 308 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI SPI During Break Interrupts 15 11 SPI During Break Interrupts The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state See Section 9 System Integration Module SIM To allow software to clear status bits during a break interrupt write a logic 1 to the BCFE bit If a status bit is cleared during the break state it remains cleared when the MCU exits the break state To protect status bits during the break state write a logic O to the BCFE bit With BCFE at logic O its default state software can read and write I O registers during the break state without affecting status bits Some status bits have a 2 step read write clearing procedure If software does the first step on such a bit before the break the bit
389. s Figure 6 1 shows the five CPU registers CPU registers are not part of the memory map I ACCUMULATOR A H IIIXxII INDEX REGISTER H X STACK POINTER SP I PROGRAM COUNTER lt x z N e CONDITION CODE REGISTER CCR CARRY BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF CARRY FLAG TWO S COMPLEMENT OVERFLOW FLAG Figure 6 1 CPU Registers 6 3 1 Accumulator The accumulator is a general purpose 8 bit register The CPU uses the accumulator to hold operands and the results of arithmetic logic operations Bit 7 6 5 4 3 2 1 Bit 0 Read Write Reset Unaffected by reset Figure 6 2 Accumulator A Data Sheet MC68HC908AP Family Rev 2 5 74 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU CPU Registers 6 3 2 Index Register The 16 bit index register allows indexed addressing of a 64K byte memory space H is the upper byte of the index register and X is the lower byte H X is the concatenated 16 bit index register In the indexed addressing modes the CPU uses the contents of the index register to determine the conditional address of the operand The index register can serve also as a temporary data storage location Bit Bit
390. s The PLL filter is manually or automatically configurable into one of two operating modes e Acquisition mode In acquisition mode the filter can make large frequency corrections to the VCO This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency When in acquisition mode the ACQ bit is clear in the PLL bandwidth control register See 8 5 2 PLL Bandwidth Control Register Tracking mode In tracking mode the filter makes only small corrections to the frequency of the VCO PLL jitter is much lower in tracking mode but the response to noise is also slower The PLL enters tracking mode when the VCO frequency is nearly correct such as when the PLL is selected as the base clock source See 8 3 8 Base Clock Selector Circuit The PLL is automatically in tracking mode when not in acquisition mode or when the ACQ bit is set 8 3 5 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically Automatic mode is recommended for most users In automatic bandwidth control mode AUTO 1 the lock detector automatically switches between acquisition and tracking modes Automatic bandwidth control mode also is used to determine when the VCO clock CGMVCLK is safe to use as the source for the base clock CGMOUT See 8 5 2 PLL Bandwidth Control Register If PLL interrupts ar
391. s The control and data bytes are described below MC68HC908AP Family Rev 2 5 Bus speed This one byte indicates the operating bus speed of the MCU The value of this byte should be equal to 4 times the bus speed E g for a 4MHz bus the value is 16 10 This control byte is useful where the MCU clock source is switched between the PLL clock and the crystal clock Data size This one byte indicates the number of bytes in the data array that are to be manipulated The maximum data array size is 255 Routines EE WRITE and EE READ are restricted to manipulate a data array between 7 to 15 bytes Whereas routines ERARNGE and MON ERARNGE do not manipulate a data array thus this data size byte has no meaning Start address These two bytes high byte followed by low byte indicate the start address of the FLASH memory to be manipulated Data array This data array contains data that are to be manipulated Data in this array are programmed to FLASH memory by the programming routines PRGRNGE PRGRNGE WRITE For the read routines LDRNGE and EE READ data is read from FLASH and stored in this array Data Sheet MOTOROLA 169 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON 10 5 1 PRGRNGE PRGRNGE is used to program a range of FLASH locations with data loaded into the data array Table 10 11 PRGRNGE Routine Routine Nam
392. s Data hold time Setup time tsy DAT 250 ns Data setup time Clock low time out 25 35 ms Clock low time out Clock low ti ow 4 7 us Clock low period Clock high tHIGH 4 0 uS Clock high period Cumulative clock low extend time Slave clock low extend time tiowsEXT 25 ms slave device Cumulative clock low extend time Master clock low extend time ti ow MExT 10 ms 4 master device Fall time tr 300 ns Clock Data Fall Time Rise time 1000 ns Clock Data Rise Time Notes 1 Devices participating in a transfer will timeout when any clock low exceeds the value of Ttimeour min of 25 ms Devices that have detected a timeout condition must reset the communication no later than Timeout max of 35ms The maximum value specified must be adhered to by both a master and a slave as it incorporates the cumulative limit for both a master 10 ms and a slave 25 ms Software should turn off the MMIIC module to release the SDA and SCL lines THIGH Provides a simple guaranteed method for devices to detect the idle conditions Low sExr is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop If a slave device exceeds this time it is expected to release both its clock and data lines and reset itself 4 Ti ow MExr is the cumulative time a master device is allo
393. s Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Data Sheet interrupts share the same CPU interrupt vector See Figure 15 11 It is not possible to enable or individually to generate a receiver error CPU interrupt request However leaving MODFEN low prevents MODF from being set If the CPU SPRF interrupt is enabled and the interrupt is not watch for an overflow condition Figure 15 9 shows how it is possible to miss an overflow The first part of Figure 15 9 shows how it is possible to read the SPSCR and SPDR to clear the SPRF without problems However as illustrated by the second transmission example the OVRF bit can be set in between the time that SPSCR and SPDR are read 9 9 9 om sm E ne SPDR AO 1 BYTE 1 SETS SPRF BIT 5 CPU READS SPSCR WITH SPRF BIT SET 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR AND OVRF BIT CLEAR 6 BYTE 3 SETS OVRF BIT BYTE 3 IS LOST CPU READS BYTE 1 IN SPDR SPRF BIT 7 CPU READS BYTE 2 IN SPDR CLEARING SPRF BIT O SESS era BI BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED BYTE 4 IS LOST Figure 15 9 Missed Read of Overflow Condition In this case an overflow can be missed easily Since no more SPRF interrupts can be generated until this OVRF is serviced it is not obvious that bytes are being lost as more transmissions are co
394. s byte 3 in the IRSCDR instead of byte 2 In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun the flag clearing routine can check the OR bit in a second read of IRSCS1 after reading the data register NF Receiver Noise Flag Bit This clearable read only bit is set when the SCI detects noise on the RxD pin NF generates an SCI error CPU interrupt request if the NEIE bit in IRSCC3 is also set Clear the NF bit by reading IRSCS1 and then reading the IRSCDR Reset clears the NF bit 1 Noise detected 0 No noise detected FE Receiver Framing Error Bit This clearable read only bit is set when a logic 0 is accepted as the stop bit FE generates an SCI error CPU interrupt request if the FEIE bit in IRSCC3 also is set Clear the FE bit by reading IRSCS1 with FE set and then reading the IRSCDR Reset clears the FE bit 1 Framing error detected 0 No framing error detected MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 281 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications NORMAL FLAG CLEARING SEQUENCE 0 Il LL tc tc jam tc tr tc Q Q Q Q Q Q 9 1 i 9 1 2 BYTE 3 4 y A READ IRSCS1 E READ IRSCS1 E READ IRSCS1 3 SCRF 1 SCRF 1 SCRF 1 OR 0 OR
395. s in the FLASH page Once a page is filled up the EE WRITE routine automatically erases the page and starts reuse the page again In the 512 byte page an 9 byte control block is used by the routine to monitor the utilization of the page In effect only 503 bytes are used for data storage see Figure 10 10 The page control operations are transparent to the user FLASH PAGE BOUNDARY CONTROL 9 BYTES DATA ARRAY ONE PAGE 512 BYTES PAGE BOUNDARY Figure 10 10 EE WRITE FLASH Memory Usage When using this routine to store a 8 byte data array the FLASH page can be programmed 62 times before the an erase is required In effect the write erase endurance is increased by 62 times When a 15 byte data array is used the write erase endurance is increased by 33 times Due to the FLASH page size limitation the data array is limited from 7 bytes to 15 bytes The coding example below uses the EEOO0 EFFF page for data storage The data array size is 15 bytes and the bus speed is 4 9152 MHz The coding assumes the data block is already loaded in RAM with the address pointer FILE pointing to the first byte of the data block MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 177 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ORG RAM FILE PTR BUS SPD DS B 1 Indicates 4x bus frequency DATASIZE DS B 1 Data size to
396. set 0 0 0 0 0 0 0 0 Figure 13 9 SCI Control Register 1 SCC1 LOOPS Loop Mode Select Bit This read write bit enables loop mode operation In loop mode the RxD pin is disconnected from the and the transmitter output goes into the receiver input Both the transmitter and the receiver must be enabled to use loop mode Reset clears the LOOPS bit 1 Loop mode enabled 0 Normal operation enabled ENSCI Enable SCI Bit This read write bit enables the SCI and the SCI baud rate generator Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts Reset clears the ENSCI bit 1 SCI enabled 0 SCI disabled TXINV Transmit Inversion Bit This read write bit reverses the polarity of transmitted data Reset clears the TXINV bit 1 Transmitter output inverted 0 Transmitter output not inverted NOTE Setting the TXINV bit inverts all transmitted values including idle break start and stop bits MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 233 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface M Mode Character Length Bit This read write bit determines whether SCI characters are eight or nine bits long See Table 13 5 The ninth bit can serve as an extra stop bit as a receiver wakeup signal or as a parity bit Reset clears the M bit 1 9 bit SCI characters 0 8 b
397. set MMRXAK clear MMRXAK clear ACTION ACTION ACTION ACTION Read Data1 from MMDRR Read DataN from MMDRR 1 Set MMRW Load dummy FF to MMDTR 2 Set REPSEN 3 Clear MMTXAK 4 Load dummy FF to MMDTR OPERATION OPERATION Read received data and prepare for STOP Prepare for Master mode FLAGS ACTION MMRXIF set 1 Load slave address to MMADR ACTION 2 Clear MMRW 1 Set MMTXAK 3 Load command to MMDTR 2 Read Data N 1 from MMDRR 4 Set MMAST 3 Clear MMAST SLAVE MODE START Address 0 ACK Command START Address 1 TXDatal TXDataN STOP A A A A A OPERATION OPERATION OPERATION OPERATION Slave address match and Slave address match and Transmit data Last data sent check for data direction get ready to transmit data FLAGS FLAGS FLAGS FLAGS MMTXIF set MMTXIF set MMRXIF set MMRXIF set MMRXAK clear MMRXAK set MMATCH set MMATCH set ACTION MMSRW depends on 8th MMSRW depends on 8th ACTION bit of calling address byte bit of calling address byte Load Data3 to MMDTR Load dummy FF to MMDTR ACTION ACTION 1 Check MMSRW Check MMSRW 2 Read Slave address OPERATION OPERATION OPERATION Read and decode received command OPERATION Last data is going to be sent Prepare for Slave mode FLAGS Transmit data FLAGS ACTION MMRXIF set FLAGS Bree sd 1 Load slave address to MMADR clear MMTXIF set 2 ACTION ACTION ACTION 3 Clear MMAST Load Data to M
398. signals 7 6 1 Crystal Amplifier Input Pin OSCT OSC1 is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 97 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc fo Ko m 109 7 6 2 Crystal Amplifier Output Pin OSC2 When the x tal oscillator is selected OSC2 pin is the output of the crystal oscillator inverting amplifier When the RC oscillator or internal oscillator is selected OSC2 pin is the output of the internal bus clock 7 6 3 Oscillator Enable Signal SIMOSCEN The SIMOSCEN signal from the system integration module SIM enables disables the x tal oscillator the RC oscillator or the internal oscillator circuit 7 6 4 CGM Oscillator Clock CGMXCLK The CGMXCLK clock is output from the x tal oscillator RC oscillator or the internal oscillator This clock drives to CGM and other MCU sub systems 7 6 5 CGM Reference Clock CGMRCLK This is buffered signal of CGMXCLK it is used by the CGM as the phase locked loop PLL reference clock 7 6 6 Oscillator Clock to Time Base Module OSCCLK The OSCCLK is the reference clock that drives the timebase module See Section 12 Timebase Module TBM 7 7 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes Data Sheet MC68HC908AP Family Rev 2 5 98 M
399. speed asynchronous communications with peripheral devices and other MCUs This IRSCI consists of an SCI module for conventional SCI functions and a software programmable infrared encoder decoder sub module for encoding decoding the serial data for connection to infrared LEDs in remote control applications NOTE When the IRSCI is enabled the SCTxD pin is an open drain output and requires a pullup resistor be connected for proper SCI operation NOTE References DMA direct memory access and associated functions are only valid if the MCU has a DMA module This MCU does not have the DMA function Any DMA related register bits should be left in their reset state for normal MCU operation MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 249 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications 14 2 Features Features of the SCI module include the following Full duplex operation Standard mark space non return to zero NRZ format Programmable 8 bit or 9 bit character length Separately enabled transmitter and receiver Separate receiver and transmitter CPU interrupt requests Two receiver wakeup methods Idle line wakeup Address mark wakeup Interrupt driven operation with eight interrupt flags Transmitter empty Transmission complete Receiver full Idle receiver input Receiver overrun Noise error F
400. ss 0 Transmission in progress SCRF SCI Receiver Full Bit This clearable read only bit is set when the data in the receive shift register transfers to the SCI data register SCRF can generate an SCI receiver CPU interrupt request When the SCRIE bit in SCC2 is set SCRF generates a CPU interrupt request In normal operation clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR Reset clears SCRF 1 Received data available in SCDR 0 Data not available in SCDR IDLE Receiver Idle Bit This clearable read only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR After the receiver is enabled it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit Also after the IDLE bit has been cleared a valid character must again set the SCRF bit before an idle condition can set the IDLE bit Reset clears the IDLE bit 1 Receiver input idle 0 Receiver input active or idle since the IDLE bit was cleared MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 241 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface OR Receiver Overrun Bit This clearable read only bit is set when software
401. ssion complete TC The TC bit in IRSCS1 indicates that the transmit shift register and the IRSCDR are empty and that no break or idle character has been generated The transmission complete interrupt enable bit TCIE in IRSCC2 enables the TC bit to generate transmitter CPU interrupt requests Figure 14 8 shows the structure of the SCI receiver 14 6 3 1 Character Length Data Sheet The receiver can accommodate either 8 bit or 9 bit data The state of the M bit in IRSCI control register 1 IRSCC1 determines character length When receiving 9 bit data bit R8 in IRSCI control register 2 IRSCC2 is the ninth bit bit 8 When receiving 8 bit data bit R8 is a copy of the eighth bit bit 7 MC68HC908AP Family Rev 2 5 260 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI SCI Functional Description INTERNAL BUS SCI DATA REGISTER SCRO 11 BIT RECEIVE SHIFT REGISTER 7161514131211 RECOVERY CGMXCLK PRE BAUD BUS CLOCK SCALER DIVIDER r START SCI_RxD ALL 0s B R A F Fo U
402. ssion in progress Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 219 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface NOTE When queueing an idle character return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost Toggle the TE bit for a queued idle character when the SCTE bit becomes set and just before writing the next byte to the SCDR 13 42 5 Inversion of Transmitted Output The transmit inversion bit TXINV in SCI control register 1 SCC1 reverses the polarity of transmitted data All transmitted values including idle break start and stop bits are inverted when TXINV is at logic 1 See 13 8 1 SCI Control Register 1 73 42 6 Transmitter Interrupts Data Sheet These conditions can generate CPU interrupt requests from the SCI transmitter e transmitter empty SCTE The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register SCTE can generate a transmitter CPU interrupt request Setting the SCI transmit interrupt enable bit SCTIE in SCC2 enables the SCTE bit to generate transmitter CPU inter
403. ster high BRKH Break address register low BRKL SIM break status register SBSR SIM break flag control register SBFCR Data Sheet MC68HC908AP Family Rev 2 5 410 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK Break Module Registers 23 5 1 Break Status and Control Register The break status and control register BRKSCR contains break module enable and status bits Address FEOE Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 BRKE BRKA Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 23 3 Break Status and Control Register BRKSCR BRKE Break Enable Bit This read write bit enables breaks on break address register matches Clear BRKE by writing a logic 0 to bit 7 Reset clears the BRKE bit 1 Breaks enabled on 16 bit address match 0 Breaks disabled on 16 bit address match BRKA Break Active Bit This read write status and control bit is set when a break address match occurs Writing a logic 1 to BRKA generates a break interrupt Clear BRKA by writing a logic 0 to it before exiting the break routine Reset clears the BRKA bit 1 When read Break address match 0 When read No break address match MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 411 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break
404. ster to the shift register Reset clears the SPTIE bit 1 SPTE CPU interrupt requests enabled 0 SPTE CPU interrupt requests disabled Data Sheet MC68HC908AP Family Rev 2 5 314 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Module SPI Registers 15 13 2 SPI Status and Control Register The SPI status and control register contains flags to signal these conditions Receive data register full Failure to clear SPRF bit before next byte is received overflow error Inconsistent logic level on SS pin mode fault error Transmit data register empty The SPI status and control register also contains bits that perform these functions Enable error interrupts Enable mode fault error detection Select master SPI baud rate Address 0011 Bit 7 6 5 4 3 2 1 Bit 0 Read SPRF OVRF MODF SPTE ERRIE MODFEN SPRI SPRO Write Reset 0 0 0 0 1 0 0 0 Unimplemented Figure 15 14 SPI Status and Control Register SPSCR SPRF SPI Receiver Full Bit This clearable read only flag is set each time a byte transfers from the shift register to the receive data register SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also During an SPRF CPU interrupt the CPU clears SPRF by reading the SPI status and control register with SPR
405. sults in a fractional ADC cycle and is represented as the 17th cycle 17 3 4 Continuous Conversion In the continuous conversion mode the ADC continuously converts the selected channel filling the ADC data register with new data after each conversion Data from the previous conversion will be overwritten whether that data has been read or not Conversions will continue until the ADCO bit is cleared The COCO bit is set after each conversion and can be cleared by writing to the ADC status and control register or reading of the ADRLO data register MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 349 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Converter ADC 17 3 5 Auto Scan Mode NOTE In auto scan mode the ADC input channel is selected by the value of the 2 bit up counter instead of the channel select bits ADCH 4 0 The value of the counter also defines the data register ADRLx to be used to store the conversion result When ASCAN bit is set a write to ADC status and control register ADSCR will reset the auto scan up counter and ADC conversion will start on the channel 0 up to the channel number defined by the integer value of AUTO 1 0 After a channel conversion is completed data is stored in ADRLx and the COCO bit will be set The counter value will be incremented by 1 and a new conversion will start This process will continue unti
406. t MOTOROLA 191 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module 11 5 Interrupts Setting MSOB links channels 0 and 1 and configures them for buffered PWM operation The TIM channel 0 registers TCHOH TCHOL initially control the buffered PWM output TIM channel 0 status and control register TSCO controls and monitors the PWM signal from the linked channels Clearing the toggle on overflow bit TOVx inhibits output toggles on TIM overflows Subsequent output compares try to force the output to a state it is already in and have no effect The result is a 0 duty cycle output Setting the channel x maximum duty cycle bit CHxMAX and setting the TOVXx bit generates a 100 duty cycle output See 11 9 4 TIM Channel Status and Control Registers The following TIM sources can generate interrupt requests TIM overflow flag TOF The TOF bit is set when the counter reaches the modulo value programmed in the TIM counter modulo registers The TIM overflow interrupt enable bit TOIE enables TIM overflow CPU interrupt requests TOF and TOIE are in the TIM status and control register e channel flags CH1F CHOF The CHxF bit is set when an input capture or output compare occurs on channel x Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit CHxIE Channel x TIM CPU interrupt requests are enabled
407. t N Data Byte 1 ACK Data Byte 2 ACK Data Byte N STOP a Block Read START Slave Address w Command Code Byte Count N Data Byte 1 ACK Data Byte2 Data Byte N ACK PEC STOP b Block Read with PEC START Slave Address w Command Code START Slave Address R Byte Count N ACK Data Byte 1 ACK Data Byte 2 ACK Data Byte N NAK STOP c Block Write START Slave Address Wack Command Code START Slave Address Byte Count ACK Data Byte1 ACK DataByte2 ACK Data ByteN ACK NAK STOP d Block Write with PEC Figure 16 19 Block Read Write Data Sheet MC68HC908AP Family Rev 2 5 342 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC SMBus Protocol Implementation 16 9 SMBus Protocol Implementation Shaded data packets indicate transmissions by the MCU MASTER MODE START Address 9 Command 5 Address Bj RX Datal ACK RXDataN NAK STOP A A A OPERATION OPERATION OPERATION OPERATION Prepare for repeated START Get ready to receive data Read received data Generate STOP FLAGS FLAGS FLAGS FLAGS MMTXIF set MMTXIF set MMRXIF set MMRXIF
408. t MOTOROLA 7 For More Information On This Product Go to www freescale com Data Sheet Freescale Semiconductor Inc Table of Contents 4 4 4 5 4 6 4 7 4 7 1 FLASH Page Erase 58 FLASH Mass Erase 59 FLASH Program 60 gt 62 FLASH Block Protect 62 Section 5 Configuration amp Mask Option Registers CON 5 1 5 2 5 3 5 4 mo 6 1 6 2 6 3 6 3 1 6 3 2 6 3 3 6 3 4 6 3 5 6 4 6 5 6 5 1 6 5 2 6 6 6 7 6 8 FIG amp aca aco GORGE AE SURE 65 Functional Description 66 Configuration Register 1 CONFIG1 67 Configuration Register 2 CONFIG2 69 Mask Option Register 71 Section 6 Central Processor Unit CPU DR RR 78 FERRI KE EROR REA 73 eet Meee dq ead dota 74 pos d uio AIRE 74 Index Register 75 Slack POMO CR OCC 75 icon ufu o MP PPP ce 76 Condition Code Register 77 Arithmetic Logic Unit ALU 79 Low Power Modes 79 Won NOUE 79 caedi TT 80 CPU During Break
409. t U U 0 0 0 0 0 0 Unimplemented U Unaffected Figure 14 14 IRSCI Control Register 3 IRSCC3 R8 Received Bit 8 When the SCI is receiving 9 bit characters R8 is the read only ninth bit bit 8 of the received character R8 is received at the same time that the IRSCDR receives the other 8 bits When the SCI is receiving 8 bit characters R8 is a copy of the eighth bit bit 7 Reset has no effect the R8 bit T8 Transmitted Bit 8 When the SCI is transmitting 9 bit characters T8 is the read write ninth bit bit 8 of the transmitted character T8 is loaded into the transmit shift register at the same time that the IRSCDR is loaded into the transmit shift register Reset has no effect on the T8 bit MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 277 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications CAUTION CAUTION Data Sheet DMARE DMA Receive Enable Bit The DMA module is not included on this MCU Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance 1 DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit SCI receiver CPU interrupt requests enabled 0 DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit SCI receiver CPU interrupt requests enabled DMATE DMA Transfer Enable Bit The DMA module is no
410. t 15 14 13 12 11 10 9 Bit 8 002E Register High Write T2MODH Reset 1 1 1 1 1 1 1 1 Read Timer 2 Counter Modulo Bit 7 6 5 4 3 2 1 Bit 0 002F Register Low Write T2MODL Reset 1 1 1 1 1 1 1 1 Read CHOF Timer 2 Channel 0 Status CHOIE 50 MS0A ELSOB ELSOA TOVO CHOMAX 0030 and Control Register Write 0 T2SCO Reset 0 0 0 0 0 0 0 0 Timer 2 Channel o 168 p imer 2 Channe Bit 15 14 13 12 11 10 9 Bit 8 0031 Register High Write T2CHOH Reset Indeterminate after reset U Unaffected X Indeterminate Unimplemented R Reserved Figure 2 2 Control Status and Data Registers Sheet 5 of 12 Data Sheet MC68HC908AP Family Rev 2 5 42 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Memory Map Input Output I O Section Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Timer 2 Channel 0 Bit 7 6 5 4 3 2 1 Bit 0 0032 Register Low Write T2CHOL Reset Indeterminate after reset Read 0 Timer 2 Channel 1 Status CHIIE MS1A ELS1B ELS1A TOV1 CH1MAX 0033 and Control Register Write 0 12801 Reset 0 0 0 0 0 0 0 0 Timer 2 Channel 1 Read i shanne Bit 15 14 13 12 11 10 9 Bit 0034 Register High Write T2CH1H Reset Indeterminate after reset Timer 2 Channel 1 P 4 6 5 4 3
411. t before an idle condition can set the IDLE bit Also after the IDLE bit has been cleared a valid character must again set the SCRF bit before an idle condition can set the IDLE bit Reset clears the IDLE bit 1 Receiver input idle 0 Receiver input active or idle since the IDLE bit was cleared MC68HC908AP Family Rev 2 5 280 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI I O Registers OR Receiver Overrun Bit This clearable read only bit is set when software fails to read the IRSCDR before the receive shift register receives the next character The OR bit generates an SCI error CPU interrupt request if the ORIE bit in IRSCC3 is also set The data in the shift register is lost but the data already in the IRSCDR is not affected Clear the OR bit by reading IRSCS1 with OR set and then reading the IRSCDR Reset clears the OR bit 1 Receive shift register full and SCRF 1 0 No receiver overrun Software latency may allow an overrun to occur between reads of IRSCS1 and IRSCDR in the flag clearing sequence Figure 14 16 shows the normal flag clearing sequence and an example of an overrun caused by a delayed flag clearing sequence The delayed read of IRSCDR does not clear the OR bit because OR was not set when IRSCS1 was read Byte 2 caused the overrun and is lost The next flag clearing sequence read
412. t included on this MCU Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance 1 SCTE DMA service requests enabled SCTE CPU interrupt requests disabled 0 SCTE DMA service requests disabled SCTE CPU interrupt requests enabled ORIE Receiver Overrun Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit OR Reset clears ORIE 1 SCI error CPU interrupt requests from OR bit enabled 0 SCI error CPU interrupt requests from OR bit disabled NEIE Receiver Noise Error Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the noise error bit NE Reset clears NEIE 1 SCI error CPU interrupt requests from NE bit enabled 0 SCI error CPU interrupt requests from NE bit disabled FEIE Receiver Framing Error Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the framing error bit FE Reset clears FEIE 1 SCI error CPU interrupt requests from FE bit enabled 0 SCI error CPU interrupt requests from FE bit disabled MC68HC908AP Family Rev 2 5 278 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI I O Registers PEIE Receiver Parity Error Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated
413. t or cleared The output stays at the 100 duty cycle level until the cycle after CHxMAX is cleared OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW 4 PERIOD Y Y TCHx OUTPUT OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE COMPARE CHxMAX Figure 11 11 CHxMAX Latency 11 9 5 TIM Channel Registers Data Sheet These read write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function The state of the TIM channel registers after reset is unknown MC68HC908AP Family Rev 2 5 202 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM I O Registers In input capture mode MSxB MSxA 0 0 reading the high byte of the TIM channel x registers TCHxH inhibits input captures until the low byte TCHxL is read In output compare mode MSxB MSxA 0 0 writing to the high byte of the TIM channel x registers TCHxH inhibits output compares until the low byte TCHxL is written Address T1CHOH 0026 and T2CHOH 0031 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset Figure 11 12 TIM Channel 0 Register High TCHOH Address T1CHOL 0027 and T2CHOL 0032 Bit 7 6 5 4 3 2 1 Bit 0 Read
414. tains a bit that enables software to clear status bits while the MCU is in a break state Address FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read BCFE R R R R R R R Write Reset 0 R Reserved Figure 9 22 SIM Break Flag Control Register SBFCR BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by accessing status registers while the MCU is in a break state To clear status bits during the break state the BCFE bit must be set 1 Status bits clearable during break 0 Status bits not clearable during break MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 151 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Data Sheet MC68HC908AP Family Rev 2 5 152 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 10 Monitor ROM MON 10 1 Introduction This section describes the monitor ROM MON and the monitor mode entry methods The monitor ROM allows complete testing of the MCU through a single wire interface with a host computer Monitor mode entry can be achieved without use of the higher test voltage Vrs7 as long as vector addresses FFFE and FFFF are blank thus reducing the hardware requirements for in circuit programming In addition to simplif
415. tal Oscillator Stop Mode Enable Bit STOP XCLKEN enables the crystal x tal oscillator to continue operating during stop mode Setting the STOP XCLKEN bit allows the x tal oscillator to operate continuously even during stop mode This is useful for driving the timebase module to allow it to generate periodic wake up while in stop mode See Section 7 Oscillator OSC Reset clears this bit 1 X tal oscillator enabled to operate during stop mode 0 X tal oscillator disabled during stop mode OSCCLK1 OSCCLKO Oscillator Output Control Bits OSCCLK1 and OSCCLKO select which oscillator output to be driven out as OSCCLK to the timebase module TBM Reset clears these two bits OSCCLK1 OSCCLKO Timebase Clock Source 0 0 Internal oscillator ICLK 0 1 RC oscillator RCCLK 1 0 X tal oscillator XTAL 1 1 Not used SCIBDSRC SCI Baud Rate Clock Source SCIBDSRC selects the clock source used for the standard SCI module non infrared SCI The setting of this bit affects the frequency at which the SCI operates 1 Internal data bus clock fgys is used as clock source for SCI 0 Oscillator clock CGMXCLK is used as clock source for SCI Data Sheet MC68HC908AP Family Rev 2 5 70 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Configuration amp Mask Option Registers CONFIG amp MOR Mask Option Register MOR 5 5 Mask Option Regist
416. te PTA Reset Unaffected by reset a PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTBO 0001 Port B Data Register Write PTB Reset Unaffected by reset ui PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTCO 0002 Port C Data Register Write PTC Reset Unaffected by reset jp PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTDO 0003 Port D Data Register Write PTD Reset Unaffected by reset Read Data Direction Register A DDRA7 DDRA6 DDRAS DDRA4 DDRA3 DDRA2 DDRA1 DDRAO 0004 Write DDRA Reset 0 0 0 0 0 0 0 0 Read Data Direction Register B DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRBO 0005 Write DDRB Reset 0 0 0 0 0 0 0 0 Read 0006 Write DDRC Reset 0 0 0 0 0 0 0 0 Read Data Direction Register D DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRDO 0007 Write DDRD Reset 0 0 0 0 0 0 0 0 Read 0008 Unimplemented Write Reset Read 0009 Unimplemented Write Reset U Unaffected X Indeterminate Unimplemented R Reserved Figure 2 2 Control Status and Data Registers Sheet 1 of 12 Data Sheet MC68HC908AP Family Rev 2 5 38 MOTOROLA For More Information On This Product Go to www freescale com Addr 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 Freescale Semiconductor Inc Memory Map Input Output I O Section Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read Unimplemented Write Reset
417. te bits control the hardware center of range linear multiplier L which in conjunction with E See 8 3 3 PLL Circuits 8 3 6 Programming the PLL and 8 5 1 PLL Control Register controls the hardware center of range frequency fygs VRS 7 0 cannot be written when the PLLON bit in the PCTL is set See 8 3 7 Special Programming Exceptions A value of 00 in the VCO range select register disables the PLL and clears the BCS bit in the PLL control register PCTL See 8 3 8 Base Clock Selector Circuit and 8 3 7 Special Programming Exceptions Reset initializes the register to 40 for a default range multiply value of 64 The VCO range select bits have built in protection such that they cannot be written when the PLL is on PLLON 1 and such that the VCO clock cannot be selected as the source of the base clock BCS 1 ifthe VCO range select bits are all clear The PLL VCO range select register must be programmed correctly Incorrect programming can result in failure of the PLL to achieve lock MC68HC908AP Family Rev 2 5 122 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGM CGM Registers 8 5 5 PLL Reference Divider Select Register The PLL reference divider select register PMDS contains the programming information for the modulo reference divider Address 003B Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 RDS3 RD
418. termine whether the security code entered is correct check to see if bit 6 of RAM address 60 is set If it is then the correct security code has been entered and FLASH can be accessed If the security sequence fails the device should be reset by a power on reset and brought up in monitor mode to attempt another entry After failing the security sequence the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM The mass erase operation clears the security code locations so that all eight security bytes become FF blank MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 167 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor 10 5 ROM Resident Routines Data Sheet Seven routines stored in the monitor ROM area thus ROM resident are provided for FLASH memory manipulation Five of the seven routines are intended to simplify FLASH program erase and load operations The other two routines are intended to simplify the use of the FLASH memory as EEPROM Table 10 10 shows a summary of the ROM resident routines Table 10 10 Summary of ROM Resident Routines Routine Name Routine Description Adds giten PRGRNGE Program a range of locations FC34 15 ERARNGE Erase a page or the entire array FCE4 9 LDRNGE Loads data from a range of locations FCOO 7 MON PRGRNGE Program a range of lo
419. that is also not used The coding example below is to perform a page erase from 00 The Initialization subroutine is the same as the coding example for PRGRNGE see 10 5 1 PRGRNGE ERARNGE EQU SFCE4 MAIN BSR INITIALISATION LDHX FILE PTR JSR ERARNGE MC68HC908AP Family Rev 2 5 172 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 10 5 3 LDRNGE Monitor ROM MON ROM Resident Routines LDRNGE is used to load the data array in RAM with data from a range of FLASH locations Table 10 13 LDRNGE Routine Routine Name LDRNGE Routine Description Loads data from a range of locations Calling Address FCOO Stack Used 7 bytes Data Block Format Bus speed BUS SPD Data size DATASIZE Starting address ADDRH Starting address ADDRL Data 1 Data N The start location of FLASH from where data is retrieved is specified by the address ADDRH ADDRL and the number of bytes from this location is specified by DATASIZE The maximum number of bytes that can be retrieved in one routine call is 255 bytes The data retrieved from FLASH is loaded into the data array in RAM Previous data in the data array will be overwritten User can use this routine to retrieve data from FLASH that was previously programmed The coding example below is to retrieve 64 bytes of data starting from EEOO0 in FLASH The Initializ
420. the RWU bit The idle character that wakes the receiver does not setthe receiver idle bit IDLE or the SCI receiver full bit SCRF The idle line type bit ILTY determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit NOTE Clearing the WAKE bit after the RxD pin has been idle may cause the receiver to wake up immediately MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 267 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications 714 6 3 7 Receiver Interrupts The following sources can generate CPU interrupt requests from the SCI receiver 714 6 3 8 Error Interrupts Data Sheet SCI receiver full SCRF The SCRF bit in IRSCS1 indicates that the receive shift register has transferred a character to the IRSCDR SCRF can generate a receiver interrupt request Setting the SCI receive interrupt enable bit SCRIE in IRSCC2 enables the SCRF bit to generate receiver CPU interrupts Idle input IDLE The IDLE bit in IRSCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the RxD pin The idle line interrupt enable bit ILIE in IRSCC2 enables the IDLE bit to generate CPU interrupt requests The following receiver error flags in IRSCS1 can generate CPU interrupt requests Receiver overrun OR The OR bit indicates that the receive shift register shifted in a new chara
421. the send break bit SBK in SCC2 loads the transmit shift register with a break character A break character contains all logic Os and has no start stop or parity bit Break character length depends on the M bit in SCC1 As long as SBK is at logic 1 transmitter logic continuously loads break characters into the transmit shift register After software clears the SBK bit the shift register finishes transmitting the last break character and then transmits at least one logic 1 The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be Receiving a break character has these effects on SCI registers e Sets the framing error bit FE in SCS1 e Sets the SCI receiver full bit SCRF SCS1 e Clears the SCI data register SCDR e Clears the R8 bit in SCC3 e Sets the break flag bit SCS2 May set the overrun OR noise flag NF parity error PE or reception in progress flag RPF bits 13 42 4 Idle Characters An idle character contains all logic 1s and has no start stop or parity bit Idle character length depends on the M bit in SCC1 The preamble is a synchronizing idle character that begins every transmission If the TE bit is cleared during a transmission the TxD pin becomes idle after completion of the transmi
422. the stack to save the contents of the CPU registers NOTE For M6805 compatibility the H register is not stacked During a subroutine call the CPU uses two bytes of the stack to store the return address The stack pointer decrements during pushes and increments during pulls NOTE Be careful when using nested subroutines The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 53 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Random Access Memory RAM Data Sheet MC68HC908AP Family Rev 2 5 54 MOTOROLA For More Information On This Product Go to www freescale com Data Sheet MC68HC908AP Family Freescale Semiconductor Inc Section 4 FLASH Memory 4 1 Introduction This section describes the operation of the embedded FLASH memory This memory can be read programmed and erased from a single external supply The program and erase operations are enabled through the use of an internal charge pump FLASH Memory Size Device Bytes Memory Address Range MC68HC908AP64 62 368 0860 FBFF MC68HC908AP32 32 768 0860 885F MC68HC908AP16 16 384 0860 485F MC68HC908AP8 8 192 0860 285 Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 ioc HVEN MASS ERASE PGM FL
423. tion 437 MC68HC908AP Family Rev 2 5 Data Sheet 5 re Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Sections Data Sheet MC68HC908AP Family Rev 2 5 6 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Table of Contents Section 1 General Description dd Rura deans 23 TE 54422505555 Ward dde ador ics ibd wa MO de arde Rehd 23 13 MCU e RBS LIRE RES 25 1 PMASSIOMMEN 2222 ua xe d acd d dedu dee eee ib de ded 27 tS Pn FUNCIONS te needa een 30 1 6 Power Supply Bypassing VDD VDDA VSS VSSA 32 1 7 Regulator Power Supply Configuration VREG 33 Section 2 Memory Map Oia ina ok wad apia E a 35 2 2 Unimplemented Memory Locations 35 2 3 Reserved Memory Locations 35 2 4 Input Output I O 36 Section 3 Random Access Memory RAM er MOJU 25555355 spend ide eo 53 ae Funcional DSSORDBON oue ERE R9 e RO 53 Section 4 FLASH Memory AP HE CR ee Ue peg 55 4 2 Functional Description 56 43 FLASH Control 57 MC68HC908AP Family Rev 2 5 Data Shee
424. to the end of FLASH memory at FFFF With this mechanism the protect start address can be X000 X200 X400 X0600 X800 00 00 or 00 at page boundaries 512 bytes within the FLASH memory Examples of protect start address Table 4 1 FLASH Block Protect Range BPR 7 0 Protected Range 00 to 09 The entire FLASH memory is protected A B 000 1015 0 00 to FFFF D 0 00 to FFFF and so on FA FB a to FFFF FC or FD or FE FFCF to FFFF FF The entire FLASH memory is NOT protected Notes 1 Except for the mask option register SFFCF and the 48 byte user vectors FFDO FFFF These FLASH locations are always protected MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 63 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FLASH Memory Data Sheet MC68HC908AP Family Rev 2 5 64 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Sheet MC68HC908AP Family Section 5 Configuration amp Mask Option Registers CONFIG amp MOR 5 1 Introduction This section describes the configuration registers CONFIG1 and CONFIG2 and the mask option register MOR The configuration registers enable or disable these options Computer operating properly module COP COP timeout period 218 2 or 213 24 IC
425. trol register TSC e counter registers TCNTH TCNTL e counter modulo registers TMODH TMODL channel status and control registers TSCO TSC1 e channel registers TCHOH TCHOL TCH1H TCH1L Data Sheet MC68HC908AP Family Rev 2 5 194 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM Registers 11 9 1 TIM Status and Control Register The TIM status and control register TSC Enables TIM overflow interrupts Flags TIM overflows e Stops the TIM counter e Resets the TIM counter e Prescales the TIM counter clock Address T1SC 0020 and T2SC 002B Bit 7 6 5 4 3 2 1 Bit 0 Read TOF 0 0 TOIE TSTOP PS2 PS1 PSO Write 0 TRST Reset 0 0 1 0 0 0 0 0 Unimplemented Figure 11 4 TIM Status and Control Register TSC TOF TIM Overflow Flag Bit This read write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF If another TIM overflow occurs before the clearing sequence is complete then writing logic O to TOF has no effect Therefore a TOF interrupt request cannot be lost due to inadvertent clearing of TOF Reset clears the TOF bit Writing a logic 1 to TOF has no effect 1 TIM counter
426. tware can monitor Vpp by polling the LVIOUT bit In the CONFIG1 register the LVIPWRD bit must be at logic 0 to enable the LVI module and the LVIRSTD bit must be at logic 1 to disable LVI resets 22 3 4 Forced Reset Operation In applications that require Vpp to remain above the 1 level enabling LVI resets allows the LVI module to reset the MCU when Vpp falls below the 1 level In the CONFIG1 register the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets 22 3 5 Voltage Hysteresis Protection Once the LVI has triggered by having Vpp fall below the LVI will maintain a reset condition until Vpp rises above the rising trip point voltage This prevents a condition in which the MCU is continually entering and exiting reset if Vpp is approximately equal to VTRIPF1 VTRIPR1 is greater than VTRIPF1 by the hysteresis voltage Vuys 22 4 LVI Status Register The LVI status register LVISR indicates if the Vpp voltage was detected below 1 Or Vreg voltage was detected below Vrpippo Address FEOF Bit 7 6 5 4 3 2 1 Bit 0 Read LVIOUT 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 22 3 LVI Status Register Data Sheet MC68HC908AP Family Rev 2 5 404 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low V
427. uency 16k 22 2 26k Hz External reference clock to OSC1 9 fosc dc 16M Hz Crystal reference frequency fXTALCLK 32k Hz Crystal load capacitance CL Crystal fixed capacitance C4 2x0 Crystal tuning capacitance E 2x0 Feedback bias resistor 10MQ Series resistor Rs 100kQ External RC clock frequency fRccLK 7 6M Hz RC oscillator external R Rext See Figure 24 1 Q RC oscillator external C Cext 10 pF Notes 1 The oscillator circuit operates at Vaga 2 Typical value reflect average measurements at midpoint of voltage range 25 C only 3 No more than 10 duty cycle deviation from 50 The max frequency is limited by an EMC filter 4 Fundamental mode crystals only 5 Consult crystal vendor data sheet N L 8 Cext 10 pF d Vpp 5V 25 C amp 6 S 4 o 2 8 2 0 10 20 30 40 Resistor Rext 50 Figure 24 1 RC vs Frequency MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA For More Information On This Product Go to www freescale com 423 Freescale Semiconductor Inc Electrical Specifications 24 12 3V ADC Electrical Characteristics Table 24 11 ADC Electrical Characteristics 3V Characteristic Symbol Min Max Unit Notes is an dedicated and Supply voltage VDDA 2 7 3 3 V shou
428. uency When the counter reaches the value in the registers of an output compare channel the TIM can set clear or toggle the channel pin Output compares can generate TIM CPU interrupt requests 11 4 3 1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 11 4 3 Output Compare The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods For example writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period Also using a TIM overflow interrupt routine to write a new smaller output compare value may cause the compare to be missed The TIM may pass the new value before it is written Use the following methods to synchronize unbuffered changes in the output compare value on channel x When changing to a smaller value enable channel x output compare interrupts and write the new value in the output compare interrupt routine The output compare interrupt occurs at the end of the current output compare pulse The interrupt routine has until the end of the counter overflow period to write the new value e When changing to a
429. ulses to the TxD pin The narrow pulse is sent with a duration of 1 32 1 16 or 3 16 of a data bit width When two consecutive zeros are sent the two consecutive narrow pulses will be separated by a time equal to a data bit width DATA BIT WIDTH DETERMINED BY BAUD RATE scipata V V V V T EES PULSE WIDTH 1 32 1 16 OR 3 16 DATA BIT WIDTH Figure 14 4 Infrared SCI Data Example 14 5 2 Infrared Receive Decoder The infrared receive decoder converts low narrow pulses from the RxD pin to standard SCI data bits The reference clock R16XCLK clocks a four bit internal counter which counts from 0 to 15 An incoming pulse starts the internal counter and a O is sent out to the IR RxD output Subsequent incoming pulses are ignored when the counter count is between 0 and 7 IR RxD remains 0 Once the counter passes 7 an incoming pulse will reset the counter IR RxD remains 0 When the counter reaches 15 the IR RxD output returns to 1 the counter stops and waits for further pulses A pulse is interpreted as jitter if it arrives shortly after the counter reaches 15 IR RxD remains 1 Data Sheet MC68HC908AP Family Rev 2 5 254 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Infrared Serial Communications Interface Module IRSCI SCI Functional Description 14 6 SCI Functional Description Figure 14 5 shows the structu
430. upts are not masked I bit clear in the condition code register and if the corresponding interrupt enable bit is set the SIM proceeds with interrupt processing otherwise the next instruction is fetched and executed If more than one interrupt is pending at the end of an instruction execution the highest priority interrupt is serviced first Figure 9 11 demonstrates what happens when two interrupts are pending If an interrupt is pending upon exit from the original interrupt service routine the pending interrupt is serviced before the LDA instruction is executed CLI IL une INTI PSHH I INT1 INTERRUPT SERVICE ROUTINE PULH RTI 4 INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI _ Figure 9 11 Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions However in the case of the INT1 RTI prefetch this is a redundant operation NOTE Tomaintain compatibility with the M6805 Family the H register is not pushed on the stack during interrupt entry If the interrupt service routine modifies the H register or uses the indexed addressing mode software should save the H register and then restore it prior to exiting the routine MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 141 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Inte
431. ve mode without releasing the bus The master can terminate the communication by generating a STOP signal to free the bus However the master may generate a START signal followed by a calling command without first generating a STOP signal This is called repeat START A STOP signal is defined as a low to high transition of SDA while SCL is at logic high see Figure 16 2 16 5 6 Arbitration Procedure Data Sheet The interface circuit is a multi master system which allows more than one master to be connected If two or more masters try to control the bus at the same time a clock synchronization procedure determines the bus clock The clock low period is equal to the longest clock low period and the clock high period is equal to the shortest one among the masters A data arbitration procedure determines the priority A master will lose arbitration if it transmits a logic 1 while another transmits a logic 0 The losing master will immediately switch over to slave receive mode and stops its data and clock outputs The transition from master to slave will not generate a STOP condition Meanwhile a software bit will be set by hardware to indicates loss of arbitration MC68HC908AP Family Rev 2 5 324 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multi Master IIC Interface MMIIC Multi Master IIC Bus Protocol 16 5 7 Clock Synchronization 16 5 8 Handshaking Since w
432. ved Figure 17 9 ADC Data Register Low 1 to 3 ADRL1 ADRL3 17 7 5 ADC Auto Scan Control Register ADASCR The ADC auto scan control register ADASCR enables and controls the ADC auto scan function Address 005 Read 0 0 0 0 0 AUTO1 AUTOO ASCAN Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 17 10 ADC Scan Control Register ADASCR AUTO 1 0 Auto Scan Mode Channel Select Bits AUTO1 and AUTOO form a 2 bit field which is used to define the number of auto scan channels used when in auto scan mode Reset clears these bits Table 17 4 Auto scan Mode Channel Select AUTO1 AUTOO Auto Scan Channels 0 0 ADCO only 0 1 ADCO to ADC1 1 0 ADCO to ADC2 1 1 ADCO to ADC3 Data Sheet MC68HC908AP Family Rev 2 5 360 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC I O Registers ASCAN Auto scan Mode Enable Bit This bit enable disable the auto scan mode Reset clears this bit 1 Auto scan mode is enabled Auto scan mode is disabled Auto scan mode should not be enabled when ADC continuous conversion is enabled i e when ADCO 1 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 361 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
433. w freescale com Freescale Semiconductor Inc Converter ADC 17 7 1 O Registers These I O registers control and monitor ADC operation ADC status and control register ADSCR 0057 ADC clock control register ADICLK 0058 ADC data register high low 0 ADRHO ADRLO 0059 005 e ADC data register low 1 3 ADRL1 ADRL3 005B 005D e ADC auto scan control register ADASCR 005E 17 7 1 ADC Status and Control Register Function of the ADC status and control register is described here Address 0057 Read COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCHO Write Reset 0 0 0 1 1 1 1 1 Figure 17 3 ADC Status and Control Register ADSCR COCO Conversions Complete Bit When the AIEN bit is a logic 0 the COCO is a read only bit which is Set each time a conversion is completed This bit is cleared whenever the ADSCR is written or whenever the ADC clock control register is written or whenever the ADC data register low ADRLx is read If the AIEN bit is logic 1 the COCO bit always read as logic 0 ADC interrupt will be generated at the end if an ADC conversion Reset clears the COCO bit 1 Conversion completed AIEN 0 0 Conversion not completed AIEN 0 CPU interrupt AIEN 1 AIEN ADC Interrupt Enable Bit When this bit is set an interrupt is generated at the end of an ADC conversion The interrupt sig
434. wed to extend its clock cycles within each byte of a message as defined from start to ack ack to ack or ack to stop Data Sheet Rise and fall time is defined as follows TR ViLMAX 0 15 to 0 15 TE 0 9xVpp to ViLMAX 0 15 MC68HC908AP Family Rev 2 5 426 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 24 14 CGM Electrical Specification Table 24 14 CGM Electrical Specifications Electrical Specifications CGM Electrical Specification Characteristic Symbol Min Typ Max Unit Reference frequency fapv 30 32 768 100 kHz Range nominal multiplies 125 kHz VCO center of range frequency fvrs 125k 40M Hz VCO range linear range multiplier L 1 255 VCO power of two range multiplier 2 1 4 VCO multiply factor N 1 4095 VCO prescale multiplier 2 1 8 Reference divider factor R 1 1 15 VCO operating frequency 125k 40M Hz Manual acquisition time ti ock 50 ms Automatic lock time li ocK 50 ms PLL jitter fy 0 0 02596 x Hz 2 N A Notes 1 Deviation of average bus frequency over 2ms N VCO multiplier MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 427 For More Information On This Product Go to www freescale com 24 15 5V SPI Characteristics Freescale Semiconductor Inc Electrical Speci
435. with Carry A lt A M C 21 2 Eo 3 SBC X IX F2 2 SBC oprSP SP1 9EE2 4 SBC opr SP SP2 9ED2 5 SEC Set Carry Bit C 1 INH 99 1 SEI Set Interrupt Mask 1 1 1 9 2 STA DIR B7 dd 3 STA opr EXT C7 hhl 4 STA opr X IX2 D7 4 STA opr X Store A in M M lt A 21 2 1 1 E7 3 STA IX F7 2 STA opr SP SP1 9EE7 4 STA opr SP SP2 9 07 5 STHX opr Store H X in M M M 1 lt H X 212 DIR 35 dd 4 STOP Enable IRQ Pin Stop Oscillator lt 0 Stop Oscillator 0 8E 1 STX opr DIR BF dd 3 STX opr EXT CF hhll 4 STX IX2 DF 4 STX opr X Store X in M M lt X 21 2 1 1 EF 3 STX IX FF 2 STX opr SP SP1 9EEF ff 4 STX oprSP SP2 9EDF 5 SUB opr IMM AO fii 2 SUB opr DIR BO dd 3 SUB opr EXT CO hhl 4 SUB opr X IX2 DO jeeff 4 SUB Subtract A lt A M 21 2 X1 Eo lf 3 SUB X IX FO 2 SUB opr SP SP1 9EEO ff 4 SUB opr SP SP2 9EDO jee ff 5 MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 87 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Table 6 1 Instruction Set Summary Sheet 8 of 8 Effect on Sorco Operation Description CCR 9 2 3 S 8 5 o o o o is PC lt PC 1 Pus
436. www freescale com Freescale Semiconductor Inc FLASH Memory FLASH Mass Erase Operation 4 5 FLASH Mass Erase Operation MC68HC908AP Family Rev 2 5 NOTE Use the following procedure to erase the entire FLASH memory 1 Sgen COP cues Set both the ERASE bit and the MASS bit in the FLASH control register Write any data to any FLASH location within the FLASH memory address range Wait for a time thys 5 us Set the HVEN bit Wait for a time tme 200 ms Clear the ERASE bit Wait for a time 1 100 us Clear the HVEN bit After time 1 us the memory can be accessed in read mode again Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory While these operations must be performed in the order as shown but other unrelated operations may occur between the steps Data Sheet MOTOROLA 59 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FLASH Memory 4 6 FLASH Program Operation Data Sheet NOTE NOTE Programming of the FLASH memory is done on a row basis A row consists of 64 consecutive bytes starting from addresses XX00 XX40 XX80 or XXCO Use the following procedure to program a row of FLASH memory Figure 4 3 shows a flowchart of the programming algorithm 1 Setthe PGM bit This configures the memory for program operation and enables the
437. y Map 2 4 Input Output I O Section Most of the control status and data registers are in the zero page area of 0000 005F Additional I O registers have these addresses SIM break status register SBSR FE01 SIM reset status register SRSR FEO02 Reserved FEO3 SIM break flag control register SBFCR FEO04 interrupt status register 1 INT 1 FEO5 interrupt status register 2 INT2 interrupt status register 3 INT3 FEO07 Reserved FEO08 FLASH control register FLCR FEO09 FLASH block protect register FLBPR FEOA Reserved FEOB Reserved FEOC Break address register high BRKH FEOD Break address register low BRKL FEOE Break status and control register BRKSCR FEOF LVI Status register LVISR FFCF Mask option register MOR FLASH register FFFF COP control register COPCTL Data registers are shown in Figure 2 2 Table 2 1 is a list of vector locations Data Sheet MC68HC908AP Family Rev 2 5 36 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Input Output I O Section VP MCGBHC908AP32 68 90 16 68 90 005F 96 Bytes 0060 RAM 0060 M 0060 M 0060 1 024 Byt 1 024 Bytes 2 048 Bytes d 024 Bytes 045 1 024 By
438. y user coding routines are also stored in the monitor ROM area for FLASH memory program erase and EEPROM emulation 10 2 Features Features of the monitor ROM include e Normal user mode pin functionality e One pin dedicated to serial communication between monitor ROM and host computer e Standard mark space non return to zero NRZ communication with host computer e Execution of code in RAM or FLASH FLASH memory security feature e FLASH memory programming interface Enhanced PLL phase locked loop option to allow use of external 32 768 kHz crystal to generate internal frequency of 2 4576 MHz 1 No security feature is absolutely secure However Motorola s strategy is to make reading or copying the FLASH difficult for unauthorized users MC68HC908AP Family Rev 2 5 Data Sheet MOTOROLA 153 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor e 959 bytes monitor ROM code size FCOO FDFF and FE10 FFCE e Monitor mode entry without high voltage if reset vector is blank FFFE and FFFF contain FF e Standard monitor mode entry if high voltage is applied to IRQ1 Resident routines for in circuit programming and EEPROM emulation 10 3 Functional Description Data Sheet The monitor ROM receives and executes commands from a host computer Figure 10 1 shows an example circuit used to enter monitor mode and

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