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ANALOG DEVICES AD8396 handbook

1. 40 20 e 0 5 0 01 0 1 1 10 FREQUENCY MHz Figure 10 Differential Output Noise vs Frequency Typical ADSL ADSL2 Application Circuit Vout V 07022 009 AMPLITUDE V 20 5 0 02 04 06 08 10 12 14 16 18 2 TIME us Figure 11 Output Overdrive Recovery Typical ADSL ADSL2 Application Circuit Vout 3 3 Vrms CF 5 47 Ru 1000 07022 011 Rev C Page 7 of 12 FEEDTHROUGH dB 1 FREQUENCY MHz Figure 12 Feedthrough vs Frequency Typical ADSL ADSL2 Application Circuit Vour 2 Vp p R 1000 AD8396 07022 012 1 eo AD8396 THEORY OF OPERATION The AD8396 is a current feedback amplifier with high output current capability With a current feedback amplifier the current into the inverting input is the feedback signal and the open loop behavior is that of a transimpedance dVo dIw or Tz The open loop transimpedance is analogous to the open loop voltage gain ofa voltage feedback amplifier Figure 13 shows a simplified model of a current feedback amplifier Because Ri is proportional to 1 gm the equivalent voltage gain is Tz x gm where gm is the transconductance of the input stage Basic analysis of the follower with the gain circuit yields Vo _ 7 T S Vin T S Gx Ry Ry where G 1 Ry Rc Rw 1 gm 50 Q Because G x Rm lt lt Rr for low gains a current feedback amplifier has relatively constant bandwidth vs gain The 3 dB point is set when Tz Rr In a noni
2. the AD8396 between active bias and shutdown states The PD A pin controls Port A and the PD_B pin controls Port B These pins can be controlled directly with either 3 3 V or 5 V CMOS logic with the DGND pins as a reference If left unconnected the PD pins float high placing the amplifier in the shutdown state See the Specifications section for the quiescent current for each of the available bias states TYPICAL ADSL ADSL2 APPLICATION In a typical ADSL ADSL2 application a differential line driver takes the signal from the analog front end AFE and drives it onto the twisted pair telephone line Referring to the typical circuit representation in Figure 14 the differential input appears at Vins and Vn from the AFF while the differential output is transformer coupled to the telephone line at TIP and RING The common mode operating point generally midway between the supplies is set internally and is available at VCOM RING 07022 014 Figure 14 Typical ADSL ADSL2 Application Circuit MULTITONE POWER RATIO MTPR The DMT signal used in ADSL ADSL2 systems carries data in discrete tones or bins which appear in the frequency domain in evenly spaced 4 3125 kHz intervals In applications using this type of waveform MTPR is a commonly used measure of linearity Generally designers are concerned with two types of MTPR in band and out of band In band MTPR is defined as the measured difference from the peak of one tone that is lo
3. ANALOG DEVICES Low Power High Output Current Dual Port ADSL ADSL2 Line Driver AD8396 PIN CONFIGURATION q z o o gt o e FEATURES 2 differential DSL channels comprised of current feedback high output current amplifiers Integrated feedback and gain resistors Integrated biasing network Ideal for use as ADSL ADSL2 dual channel Central Office CO line drivers Low power consumption Dual supply operation from 6 V to 12 V Single supply operation from 12 V to 24 V 10 8 mA quiescent supply current in full power mode 1 4 mA quiescent supply current in shutdown mode Less than 700 mW internal power dissipation while driving 20 4 dBm line power 1 1 transformer High output voltage and current drive 43 4 V p p differential output voltage Low distortion 66 dBc typical MTPR 20 4 dBm 26 kHz to 2 2 MHz High speed 170 V ps differential slew rate APPLICATIONS ADSL ADSL2 CO line drivers GENERAL DESCRIPTION The AD8396 is comprised of four high output current low power consumption operational amplifiers It is particularly well suited for the CO driver interface in digital subscriber line systems such as ADSL and ADSL2 The driver can deliver 20 4 dBm to a line while compensating for losses due to hybrid insertion and back termination resistors The low power consumption high output current high output voltage swing and robust thermal packaging enable the AD8396 to be used as the CO line driver in ADSL and o
4. E GROUND PLANE Figure 4 Pin Configuration 07022 004 AD8396 Pin No Mnemonic Description 1 INPA Port A Input P 2 INNA Port A Input N 3 11 DGND Ground 4 INPB Port B Input P 5 INNB Port B Input N 6 VCOM B Port B Bias 7 PD B Port B Shutdown 8 VEE Negative Power Supply 9 VONB Port B Output N 10 VOPB Port B Output P 12 VONA Port A Output N 13 VOPA Port A Output P 14 VCC Positive Power Supply 15 PD_A Port A Shutdown 16 VCOM A Port A Bias Exposed Pad No Connection Rev C Page 5 of 12 AD8396 TYPICAL PERFORMANCE CHARACTERISTICS NORMALIZED GAIN dB 7 8 eo 0 1 1 FREQUENCY MHz 10 Figure 5 Differential Gain vs Frequency R 100 Q 45 40 OUTPUT SWING V p p 50 LOAD Q 60 Figure 6 DC Differential Output Swing vs Load 1000 INTERNAL POWER CONSUMPTION mW 12 14 16 18 OUTPUT POWER dBm Figure 7 Internal Power Consumption vs Output Power Typical ADSL ADSL2 Application Circuit 100 Q Resistive Load Only o 07022 005 07022 006 07022 007 N N CROSSTALK dB 07022 008 0 1 1 10 FREQUENCY MHz Figure 8 Crosstalk vs Frequency Typical ADSL ADSL2 Application Circuit Vpp V Rev C Page 6 of 12 Vour 2 Vp p R 1000 6 2 0 5 1 5 4 1 0 3 0 5 2 0 1 0 5 0 1 0 1 1 5 2 2 0 0 2 4 6 8 10 12 14 16 18 20 TIME us Figure 9 Power Down Power Up Transition 160 140 120 100 80 Lu o 9 60
5. PLANE 0 20 REF COMPLIANT TO JEDEC STANDARDS MO 220 WGGC Figure 17 16 Lead Lead Frame Chip Scale Package LFCSP_WQ 4mm x 4 mm Very Very Thin Quad CP 16 26 Dimensions shown in millimeters SECTION OF THIS DATA SHEET 042709 A AD8396 ORDERING GUIDE Model Temperature Range Package Description Package Option AD8396ACPZ R2 40 C to 85 C 16 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 16 26 AD8396ACPZ RL 40 C to 85 C 16 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 16 26 AD8396ACPZ R7 40 C to 85 C 16 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 16 26 1 Z RoHS Compliant Part Rev C Page 11 of 12 AD8396 NOTES 2007 2009 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D07022 0 8 09 C DEVICES www analo g com Rev C Page 12 of 12
6. Typical ADSL ADSL2 Application eee 9 Absolute Maximum Ratings eerte 4 Multitone Power Ratio MTPR sse 9 Thermal Resistance sasas a etel ie reli 4 Lightning and AC Power Fault sss 10 Maximum Power Dissipation sss 4 Outline Dimensions ie PERI REESE URS 11 ESD Caution A ARE 4 Ordering Guilde te Ce qum 11 Pin Configuration and Function Descriptions 5 REVISION HISTORY 8 09 Revision C Initial Version Rev C Page 2 of 12 SPECIFICATIONS AD8396 Vcc Vre 24 V Ri 100 Q Gorr 13 fixed PD 0 T 25 C typical DSL application circuit unless otherwise noted Table 1 Parameter Min Typ Max Unit Test Conditions Comments DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth 8 MHz Vout 0 1 V p p differential 3 dB Large Signal Bandwidth 8 MHz Vout 2V p p differential Slew Rate 170 V us Vout 4 V p p differential Differential Gain 12 8 13 13 2 VN NOISE DISTORTION PERFORMANCE Second Harmonic Distortion 90 dBc fc 2 MHz Vout 2 V p p differential Third Harmonic Distortion 62 dBc fc 2 MHz Vout 2 V p p differential Multitone Input Power Ratio MTPR 66 dBc 26 kHz to 2 2 MHz Zune 100 O differential load Differential Output Noise 140 nV VHz f 10kHz INPUT CHARACTERISTICS RTO Offset Voltage 15 0 7 15 mV Single ended 15 40 3 15 mV Differential RTO Offset Vol
7. aded with data to the peak of an adjacent tone that is intentionally left empty Out of band MTPR is more loosely defined as the spurious emissions that occur in the receive band located between 25 875 kHz and the first downstream tone at 138 kHz Figure 15 and Figure 16 show the AD8396 in band MTPR for a 5 5 crest factor waveform for empty bins in the ADSL and extended ADSL2 bandwidths eo MAGNITUDE dBm b A db b o5 S i e e e e e e e e 07022 015 73dBc b o 100 642 131 644 503 646 875 649 247 651 6 FREQUENCY kHz Figure 15 In Band MTPR at 646 875 kHz o 68dBc MAGNITUDE dBm l a o S b amp e e e 07022 016 o a N 1 9618 1 9641 1 9665 1 9689 FREQUENCY MHz Figure 16 In Band MTPR at 1 9665 MHz Rev C Page 9 of 12 AD8396 LIGHTNING AND AC POWER FAULT When the AD8396 is an ADSL ADSL2 line driver it is transformer coupled to the twisted pair telephone line In this environment the AD8396 is subject to large line transients resulting from events such as lightning strikes or downed power lines Additional circuitry is required to protect the AD8396 from damage due to these events Rev C Page 10 of 12 OUTLINE DIMENSIONS PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 0 80 FOR PROPER CONNECTION OF 0 75 THE EXPOSED PAD REFER TO 0 70 f 0 05 MAX THE PIN CONFIGURATION AND 7 L porot ino FUNCTION DESCRIPTIONS LY COPLANARITY SEATING 0 08
8. deal amplifier there are additional poles that contribute excess phase and there is a value for Rr below which the amplifier is unstable Tolerance for peaking and desired flatness determines the optimum Rr in each application lt o c 07022 013 Figure 13 Simplified Block Diagram Rev C Page 8 of 12 AD8396 APPLICATIONS INFORMATION SUPPLIES GROUNDING AND LAYOUT The AD8396 can be powered from either single or dual supplies with the total supply voltage ranging from 12 V to 24 V For optimum performance use well regulated low ripple supplies As with all high speed amplifiers pay close attention to supply decoupling grounding and overall board layout Provide low frequency supply decoupling with 10 uF tantalum capacitors from each supply to ground In addition decouple all supply pins with 0 1 uF quality ceramic chip capacitors placed as close as possible to the driver Use an internal low impedance ground plane to provide a common ground point for all driver and decoupling capacitor ground requirements Whenever possible use separate ground planes for analog and digital circuitry Follow high speed layout techniques to minimize parasitic capacitance Keep input and output traces as short as possible and as far apart from each other as practical to minimize crosstalk Keep all differential signal traces as symmetrical as possible POWER MANAGEMENT A digitally programmable logic pin switches each port of
9. ns above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE Oya is specified in still air with exposed pad soldered to 4 layer JEDEC test board O c is specified at the exposed pad Table 3 Package Type Osa Osc Unit 16 Lead LFCSP 56 9 1 C W MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the AD8396 is limited by its junction temperature on the die The maximum safe junction temperature of plastic encapsulated devices as determined by the glass transition temperature of the plastic is 150 C Exceeding this limit can temporarily cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package Exceeding this limit for an extended period can result in device failure Figure 3 shows the maximum power dissipation in the package vs the ambient temperature for the 16 lead LFCSP on a JEDEC standard 4 layer board Oja values are approximations 3 5 MAXIMUM POWER DISSIPATION W 07022 003 AMBIENT TEMPERATURE C Figure 3 Maximum Power Dissipation vs Ambient Temperature for a 4 Layer Board The power dissipated in the package Pp is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs The quie
10. scent power is the voltage between the supply pins Vs times the quiescent current Is Assuming that the load Ri is referenced to midsupply the total drive power is Vs 2 x Iovr part of which is dissipated in the package and part in the load Vour x Iour RMS output voltages should be considered If Ri is referenced to Vis as in single supply operation the total power is Vs x Iour In single supply with Ri to Ves worst case is Vout Vs 2 Airflow increases heat dissipation effectively reducing bja In addition more copper in direct contact with the package leads from PCB traces through holes ground and power planes reduces 054 ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy 4 may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev C Page4 of 12 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS T z e o gt ce o Table 4 Pin Function Descriptions 13 VOPA zs ET E 2142 VONA INNA 2 AD8396 cz 41 DGND DGND 3 lt 2710 VOPB NOTE THE EXPOSED PAD IS NOT CONNECTED INTERNALLY FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO TH
11. tage PD 1 30 10 1 30 mV Differential Input Bias Current 5 1 5 5 uA Input Resistance 8 kQ Differential Input Capacitance 1 pF Differential OUTPUT CHARACTERISTICS Differential Output Voltage Swing 42 6 43 4 44 V p p AVour R 100 Q Single Ended Output Voltage Swing 21 3 21 7 22 V p p AVour R 50Q Output Leakage Current 100 100 uA PD 1 POWER SUPPLY Operating Range Dual Supply t6 t12 V Operating Range Single Supply 12 24 V Total Quiescent Current PD 0 9 0 10 8 13 0 mA PD 1 Shutdown State 0 1 4 3 0 mA Common Mode Voltage 10 0 2 10 mV Vem PD 0 Threshold 0 8 V 0 20V PD 1 Threshold 1 6 V 1 25V PD 0 Input Current 100 47 100 yA 0 20V PD 1 Input Current 100 1 100 yA 1 5V Power Supply Rejection Ratio 80 60 dB AVos om atn AVcc AVcc 1 V differential Power Supply Rejection Ratio 80 60 dB AVos om aty AVee AVe 1 V differential Rev C Page 3 of 12 AD8396 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating Supply Voltage Vcc Vee 264V Power Dissipation Storage Temperature Range 65 C to 150 C Operating Temperature Range 40 C to 85 C Lead Temperature Soldering 10 sec 300 C Junction Temperature 150 C See Figure 3 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditio
12. ther xDSL systems The AD8396 is available in a 4 mm x 4 mm 16 lead LFCSP Rev C Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result fromits use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 13 VOPA De INPA TRES 4 lt 12 VONA lt 2 11 DGND C 10 VOPB INPB 4 2 gt 0 7 gt 777 77 9 VONB P 07022 001 O VONA 07022 002 Figure 2 Channel A Internal Schematics One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2007 2009 Analog Devices Inc All rights reserved AD8396 TABLE OF CONTENTS Features eso vecti gne rdc dei ons 1 Typical Performance Characteristics eene 6 Pii I M 1 Theory Of Operation iiio eite die entendi tei dn 8 General Descriptions eite tette aee eet debetur 1 Applications Information seen 9 Pin Configurations noe eere even a i e Ra 1 Supplies Grounding and Layout sss 9 REVISION HISEOEy eene escis ste esed e d EE 2 Power Management srep n r R nene 9 Specifications es a T E E LES 3

ANALOG DEVICES AD8396 handbook

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