ANALOG DEVICES AD1896 English products handbook Rev A
Contents
1. 110 110 115 115 120 120 125 125 130 130 135 135 140 140 8 145 145 150 150 155 155 160 160 165 165 170 170 175 175 180 180 25 50 75 100 125 150 175 200 25 50 75 100 125 150 175 200 FREQUENCY kHz FREQUENCY kHz TPC 49 THD 4 N vs Frequency Input 48 kHz 44 1 kHz TPC 51 THD N vs Frequency Input 48 kHz 96 kHz 0 dBFS 0 dBFS 110 110 115 115 120 120 125 125 130 130 135 135 140 140 145 8 145 150 150 155 155 160 160 165 165 170 170 175 175 180 180 25 50 75 100 125 150 175 200 25 50 75 100 125 150 175 200 FREQUENCY kHz FREQUENCY kHz TPC 50 THD N vs Frequency Input 44 1 kHz 48 kHz TPC 52 THD N vs Frequency Input 96 kHz 48 kHz 0 dBFS 0 dBFS 16 REV A AD1896 Continued from Page 1 The digital servo loop measures the time difference between the input and output sample rates within 5 ps This is necessary in order to select the correct polyphase filter coefficient The digital servo loop has excellent jitter rejection for both input and output sample rates as well as the master clock The jitter rejec tion begins at less than 1 Hz This requires long settling time whenever RESET is deasserted or when the input or output sample rate changes To reduce the settling time upon2. 110 110 115 115 120 120 125 125 130 130 135 135 140 140 8 145 145 150 150 155 155 160 160 165 165 170 170 175 175 180 180 140 120 100 80 60 40 20 0 140 120 100 80 60 40 20 0 INPUT LEVEL dBFS INPUT LEVEL dBFS TPC 43 THD N vs Input Amplitude 48 kHz 44 1 kHz TPC 46 THD N vs Input Amplitude 48 kHz 96 kHz 1 kHz Tone 1 kHz Tone 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 140 120 100 80 60 40 20 0 140 120 100 80 60 40 20 0 INPUT LEVEL dBFS INPUT LEVEL dBFS TPC 44 THD N vs Input Amplitude 96 kHz 48 kHz TPC 47 THD N vs Input Amplitude 44 1 kHz 192 kHz 1 kHz Tone 1 kHz Tone 110 110 115 115 120 120 125 125 130 130 135 135 140 140 amp 145 i 145 150 150 155 155 160 160 165 165 170 170 175 175 180 180 140 120 100 80 60 40 20 0 140 120 100 80 60 40 20 0 INPUT LEVEL dBFS INPUT LEVEL dBFS TPC 45 THD N vs Input Amplitude 44 1 kHz 48 kHz TPC 48 THD N vs Input Amplitude 192 kHz 48 kHz 1 kHz Tone 1 kHz Tone REV A 15 AD1896
3. alc ce is Roam aswa aaa 24 Update to OUTLINE DIMENSIONS sue desde dee RN aU hale EE rt Gure ed aa 26 REV A 27 W 0 E 0 E07Z09 V S N NI GALNIYd 28
4. 138 139 140 141 DNR dBFS 142 143 144 145 80 105 130 155 OUTPUT SAMPLE RATE kHz 180 TPC 30 DNR vs Output Sample Rate fs iy 32 kHz 60 dBFS 1 kHz Tone REV A AD1896 130 135 181 132 136 133 134 E 137 E _ 9 135 z 136 138 a 137 138 139 139 140 140 30 55 80 105 130 155 180 30 55 80 105 130 155 180 OUTPUT SAMPLE RATE kHz OUTPUT SAMPLE RATE kHz TPC 31 DNR vs Output Sample Rate fs jy 96 kHz TPC 34 DNR vs Output Sample Rate fs jj 44 1 kHz 60 dBFS 1 kHz Tone 60 dBFS 1 kHz Tone Ga 192kHz 48kHz 192kHz 96kH dBFS dBFS 0 10 20 30 40 50 60 0 2 4 6 8 10 12 14 16 18 20 22 24 FREQUENCY kHz FREQUENCY kHz TPC 32 Digital Filter Frequency Response TPC 35 Pass Band Ripple 192 kHz 48 kHz 135 5 136 4 137 3 138 2 139 1 140 Eo l gt E Ad E a lt 142 2 ud 143 3 144 4 145 5 30 55 80 105 130 155 180 140 120 100 80 60 2 40 20 0 OUTPUT SAMPLE RATE kHz AREA TPC 33 DNR vs Output Sample Rate fs jy 48 kHz TPC 36 Linearity Error 48 kHz 48 kHz 0 dBFS to 60 dBFS 1 kHz Tone 140 dBFS Input 200 Hz Tone REV 13
5. AD1896 5 5 4 4 3 3 T dE I I 1 1 B o T o gt gt E 1 lt lt 5 2 2 2 a a 3 3 4 4 q a20 100 80 60 240 200 0 120 100 0 0 0 20 0 INPUT LEVEL dBFS INPUT LEVEL dBFS 37 Linearity Error 48 kHz 44 1 kHz 0 dBFS to 40 Linearity Error 48 kHz 96 kHz 0 dBFS to 140 dBFS Input 200 Hz Tone 140 dBFS Input 200 Hz Tone 5 5 4 4 3 3 B 2 1 5 1 1 G o i o gt E Sa lt lt 2 2 2 2 a a 3 3 5 5 140 120 100 80 60 40 0 0 144 120 100 80 60 40 20 0 INPUT LEVEL dBFS INPUT LEVEL dBFS TPC 38 Linearity Error 96 kHz 48 kHz 0 dBFS to 41 Linearity Error 44 1 kHz 192 kHz 0 dBFS to 140 dBFS Input 200 Hz Tone 140 dBFS Input 200 Hz Tone 5 5 4 4 3 3 gt 2 tc 2 9 1 Eo B o gt gt 1 i lt lt 2 2 2 2 a a 3 3 4 4 pe 40 120 100 80 60 40 20 0 Ee 40 120 100 80 60 40 20 0 INPUT LEVEL dBFS INPUT LEVEL dBFS TPC 39 Linearity Error 44 1 kHz 48 kHz 0 dBFS to 42 Linearity Error 192 kHz 44 1 kHz 0 dBFS to 140 dBFS Input 200 Hz Tone 140 dBFS Input 200 Hz Tone 14 REV A AD1896
6. 105 130 155 180 TPC 24 THD N vs Output Sample Rate fs w 192 kHz 0 dBFS 1 kHz Tone 11 AD1896 119 121 123 125 127 THD N dBFS 129 131 133 135 30 55 80 105 130 155 180 TPC 25 THD vs Output Sample Rate fs ij 48 kHz OUTPUT SAMPLE RATE kHz 0 dBFS 1 kHz Tone 119 121 123 125 127 THD N dBFS 129 131 133 135 30 55 80 105 130 155 180 TPC 26 THD N vs Output Sample Rate fs w 44 1 kHz OUTPUT SAMPLE RATE kHz 0 dBFS 1 kHz Tone 121 123 125 THD N dBFS L 131 133 135 30 55 80 105 130 155 180 TPC 27 THD N vs Output Sample Rate fs ij 32 kHz OUTPUT SAMPLE RATE kHz 0 dBFS 1 kHz Tone 12 119 121 123 125 127 THD N dBFS 129 131 133 135 30 55 80 105 130 155 OUTPUT SAMPLE RATE kHz 180 TPC 28 THD N vs Output Sample Rate fs ij 96 kHz 0 dBFS 1 kHz Tone 130 131 132 133 134 135 136 DNR dBFS 137 138 139 140 30 55 80 105 130 155 OUTPUT SAMPLE RATE kHz 180 TPC 29 DNR vs Output Sample Rate fs jy 192 kHz 60 dBFS 1 kHz Tone 135 136 137
7. deassertion of RESET or a change in a sample rate the digital servo loop enters the fast settling mode When the digital servo loop has adequately settled in the fast mode it switches into the normal or slow settling mode and continues to settle until the time difference measurement between input and output sample rates is within 5 ps During fast mode the MUTE OUT signal is asserted high Normally the MUTE OUT is connected to the MUTE IN pin The MUTE IN signal is used to softly mute the AD1896 upon assertion and softly unmute the AD1896 when it is deasserted sample rate ratio circuit is used to scale the filter length of the FIR filter for decimation Hysteresis in measuring the sample rate ratio is used to avoid oscillations in the scaling of the filter length which would cause distortion on the output REV A However when multiple AD1896s are used with the same serial input port clock and the same serial output port clock the hys teresis causes different group delays between multiple AD1896s A phase matching mode feature was added to the AD1896 to address this problem In phase matching mode one AD1896 the master transmits its sample rate ratio to the other AD1896s the slaves so that the group delay between the multiple AD1896s remains the same The group delay of the AD1896 can be adjusted for short or long delay An address offset is added to the write pointer of the FIFO in the sample rate converter This offs
8. 10 kHz and 11 kHz 0 dBFS Tone 60 dBFS 1 kHz Tone 48 kHz 44 1 kHz dBFS 2 5 5 0 7 5 10 0 12 5 15 0 17 5 20 0 22 5 2 5 5 0 75 10 0 12 5 15 0 175 200 22 5 FREQUENCY kHz FREQUENCY kHz 15 IMD 10 kHz and 11 kHz 0 dBFS Tone TPC 18 Wideband FFT Plot 16k Points 44 1 kHz 48 kHz 44 1 kHz 48 kHz 0 dBFS 20 kHz Tone 10 REV A AD1896 dBFS 30 40 50 60 FREQUENCY kHz TPC 19 Wideband FFT Plot 16k Points 192 kHz 192 kHz 0 5 80 kHz Tone 25 50 7 5 10 0 12 5 15 0 17 5 20 0 22 5 FREQUENCY kHz TPC 20 Wideband FFT Plot 16k Points 48 kHz 48 kHz 0 dBFS 20 kHz Tone 2 5 5 0 7 5 100 12 5 FREQUENCY kHz TPC 21 Wideband FFT Plot 16k Points 48 kHz 44 1 kHz 0 dBFS 20 kHz Tone 15 0 17 55 200 REV A 5 10 15 20 25 30 FREQUENCY kHz 35 40 45 TPC 22 Wideband FFT Plot 16k Points 48 kHz 96 kHz 0 5 20 kHz Tone 25 50 7 5 100 125 15 0 FREQUENCY kHz 17 5 20 0 22 5 23 Wideband FFT Plot 16k Points 96 kHz 48 kHz 0 5 20 kHz Tone THD N dBFS 55 80 OUTPUT SAMPLE RATE kHz
9. 4 Wideband FFT Plot 16k Points 44 1 kHz 192 kHz 48 kHz 48 kHz Asynchronous 0 dBFS 1 kHz Tone o m 100 120 140 160 180 200 25 50 75 100 125 15 0 17 5 20 0 22 5 0 75 100 125 FREQUENCY kHz FREQUENCY kHz TPC 2 Wideband FFT Plot 16k Points 0 dBFS 1 kHz Tone TPC 5 Wideband FFT Plot 16k Points 48 kHz 44 1 kHz 44 1 kHz 48 kHz Asynchronous 0 dBFS 1 kHz Tone dBFS 180 5 10 15 20 25 30 35 40 45 25 50 7 5 100 125 150 17 5 200 22 5 FREQUENCY kHz FREQUENCY kHz TPC 3 Wideband FFT Plot 16k Points 48 kHz 96 kHz TPC 6 Wideband FFT Plot 16k Points 96 kHz 48 kHz 0 dBFS 1 kHz Tone 0 dBFS 1 kHz Tone 8 REV A AD1896 25 50 75 100 125 15 0 17 5 200 22 5 FREQUENCY kHz TPC 7 Wideband FFT Plot 16k Points 192 kHz 48 kHz 0 dBFS 1 kHz Tone dBFS 25 50 7 5 10 0 12 5 15 0 17 5 20 0 22 5 FREQUENCY kHz TPC 8 Wideband FFT Plot 16k Points 60 dBFS 1 kHz Tone 48 kHz 48 kHz Asynchronous dBFS 2 5 5 0 7 5 10 0 12 5 15 0
10. PLEASE REFERTO FIGURE 14 Figure 10 Input Output Serial Data Formats TDM MODE APPLICATION In TDM mode several AD1896s can be daisy chained together and connected to the serial input port of a SHARC DSP The AD1896 contains 64 bit parallel load shift register When the LRCLK pulse arrives each AD1896 parallel loads its left and right data into the 64 bit shift register The input to the shift register is connected to TDM IN while the output is connected to SDATA O By connecting the SDATA O to the TDM IN AD1896 AD1896 TDM IN SDATA O LRCLK O SCLK O TDM IN SDATA O LRCLK O SCLK O PHASE MASTER SLAVE 1 of the next AD1896 a large shift register is created which is clocked by SCLK O The number of AD1896s that can be daisy chained together is limited by the maximum frequency of SCLK O which is about 25 MHz For example if the output sample rate fs is 48 kHz up to eight AD1896s could be connected since 512 x fs is less than 25 MHz In master TDM mode the number of AD1896s that can be daisy chained is fixed to four AD1896 TDM IN SDATA O LRCLK O SCLK O SLAVEn STANDARD MODE MATCHED PHASE MODE Figure 11 Daisy Chain Configuration for TDM Mode All AD1896s Being Clock Slaves REV A 23 AD1896 AD1896 AD1896 IN SDATA_O LRCLK_O SCLK O TDM IN SDATA O LRCLK O CLOCK MASTER AND PHASE MASTER AD1896 TDM IN SDATA O LRCLK O STANDARD MODE MATCHED P
11. fs m dc signal images of the zero order hold are infinitely attenuated Since the ratio of T2 to T1 is an irrational number the error resulting from the resampling at fs our can never be eliminated However the error be sig nificantly reduced through interpolation of the input data at fs m The AD1896 is conceptually interpolated by a factor of 2 IN ZERO ORDER OUT HOLD 1 15 1 1 71 fs our 1 72 A ORIGINAL SIGNAL t tt d SAMPLED AT fs iN SIN X X OF ZERO ORDER HOLD SPECTRUM OF ZERO ORDER HOLD OUTPUT SPECTRUM OF fs oy SAMPLING alll fs our 2 fs our FREQUENCY RESPONSE OF fs oyr CONVOLVED WITH ZERO ORDER HOLD SPECTRUM Figure 4 Zero Order Hold Being Used by fs our to Resample Data from fs IN THE CONCEPTUAL HIGH INTERPOLATION MODEL Interpolation of the input data by a factor of 2 involves placing 229 1 samples between each fs sample Figure 5 shows both the time domain and the frequency domain of interpolation by a factor of 27 Conceptually interpolation by 270 would involve the steps of zero stuffing 220 1 number of samples 18 between each fs sample and convolving this interpolated signal with a digital low pass filter to suppress the images In the time domain it can be seen that f our selects the closest fs X 220 sample from the zero order hold as opposed to the nearest fs sample in th
12. the sample rate and input frequency 142 dB A Weighted dynamic range 192 kHz sampling frequencies for both input and output sample rates improved jitter rejection and 1 8 upsampling and 7 75 1 downsampling ratios Additional features include more serial formats a bypass mode better interfacing to digital signal pro cessors and a matched phase mode The AD1896 has a 3 wire interface for the serial input and output ports that supports left justified LS and right justified 16 18 20 24 bit modes Additionally the serial output REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies FUNCTIONAL BLOCK DIAGRAM GRPDLYS RESET VDD_IO VDD_CORE MUTE SDATA SDATA_O SCLK SCLK O LRCLK LRCLK O SMODE IN 0 TDM IN SMODE IN 1 SERIAL n SMODE IN 2 OUTPUT SMODE O 0 BYPASS SMODE O 1 MUTE O WLNGTH O 0 WLNGTH O 1 MCLK O MSMODE 1 port supports TDM mode for daisy chaining multiple AD1896s to a digital signal processor The serial output data is dithered down to 20 18 or 16 bits when 20 18 or 16 bit output data is se lected The
13. 17 5 20 0 22 5 FREQUENCY kHz TPC 9 Wideband FFT Plot 16k Points 44 1 kHz 48 kHz 60 dBFS 1 kHz Tone REV A e EEE 5 10 15 3 25 30 35 40 45 FREQUENCY kHz TPC 10 Wideband FFT Plot 16k Points 48 kHz 96 kHz 60 dBFS 1 kHz Tone Bit dBFS 10 20 30 40 50 60 70 80 90 FREQUENCY kHz TPC 11 Wideband FFT Plot 16k Points 44 1 kHz 192 kHz 60 dBFS 1 kHz Tone dk DIZ Huizi 2 5 5 0 7 5 10 0 12 5 dee 17 5 20 0 FREQUENCY kHz TPC 12 Wideband FFT Plot 16k Points 48 kHz 44 1 kHz 60 dBFS 1 kHz Tone AD1896 dBFS 2 5 5 0 7 5 100 12 5 150 17 5 20 0 22 5 FREQUENCY kHz 25 50 7 5 10 0 12 5 15 0 17 5 20 0 22 5 FREQUENCY kHz TPC 13 Wideband FFT Plot 16k Points 96 kHz 48 kHz TPC 16 IMD 10 kHz and 11 kHz 0 dBFS Tone 60 dBFS 1 kHz Tone 96 kHz 48 kHz dBFS 100 120 140 160 d ic Lo MEAT 25 50 7 5 100 125 150 17 5 200 22 5 Jm 25 50 75 100 125 150 175 200 FREQUENCY kHz FREQUENCY kHz TPC 14 Wideband FFT Plot 16k Points 192 kHz 48 kHz TPC 17 IMD
14. AD1896 sample rate converts the data from the serial input port to the sample rate of the serial output port The sample rate at the serial input port can be asynchronous with respect to the output sample rate of the output serial port The master clock to the AD1896 MCLK can be asynchronous to both the serial input and output ports MCLK can be generated either off chip or on chip by the AD1896 master clock oscillator Since MCLK can be asynchronous to the input or output serial ports a crystal can be used to generate MCLK internally to reduce noise and EMI emissions on the board When MCLK is synchronous to either the output or input serial port the AD1896 can be configured in a master mode where MCLK is divided down and used to generate the left right and bit clocks for the serial port that is synchronous to MCLK The AD1896 supports master modes of 256 x fs 512 x fs and 768 x fs for both input and output serial ports Conceptually the AD1896 interpolates the serial input data by a rate of 220 and samples the interpolated data stream by the output sample rate In practice a 64 tap FIR filter with 270 polyphases a FIFO a digital servo loop that measures the time difference between the input and output samples within 5 ps and a digital circuit to track the sample rate ratio are used to perform the interpolation and output sampling Refer to the Theory of Operation section The digital servo loop and sample rate ratio circuit automatical
15. AD1896AYRSRL 40 C to 105 C 28 Lead SSOP RS 28 on 13 Reel CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although WARN NG el the AD1896 features proprietary ESD protection circuitry permanent damage may occur on Sprit ai devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE 6 REV A AD1896 PIN CONFIGURATION GRPDLYS MCLK MCLK OUT SDATA I SCLK LRCLK VDD DGND BYPASS SMODE 0 SMODE 1 SMODE IN 2 RESET MUTE IN MMODE 2 MMODE 1 MMODE 0 AD1896 SCLK O TOP VIEW NOT TO SCALE LRCLK O SDATA O VDD CORE DGND TDM IN SMODE OUT 0 SMODE OUT 1 WLNGTH OUT 0 WLNGTH OUT 1 MUTE OUT PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Description 1 IN GRPDLYS Group Delay High Short Low Long 2 IN Master Clock or Crystal Input 3 OUT MCLK OUT Master Clock Output or Crystal Output 4 IN SDATAI Input Serial Data at Input Sample Rate 5 IN OUT SCLK I Master Slave Input Serial Bit Clock 6 IN OUT LRCLKI Master Slave Input Left Right Clock 7 IN VDD IO 3 3 V 5 V Input Output Digital Supply Pin 8 IN DGND Digital Ground Pin 9 IN BYPASS ASRC Bypass Mode Active High 10 IN S
16. ANALOG DEVICES 192 kHz Stereo Asynchronous Sample Rate Converter AD1896 FEATURES Automatically Senses Sample Frequencies No Programming Required Attenuates Sample Clock Jitter 3 3 V 5 V Input and 3 3 V Core Supply Voltages Accepts 16 18 20 24 Bit Data Up to 192 kHz Sample Rate Input Output Sample Ratios from 7 75 1 to 1 8 Bypass Mode Multiple AD1896 Daisy Chain Mode Multiple AD1896 Matched Phase Mode 142 dB Signal to Noise and Dynamic Range A Weighted 20 Hz 20 kHz BW Up to 133 dB THD N Linear Phase FIR Filter Hardware Controllable Soft Mute Supports 256 x fs 512 x fs or 768 x fs Master Mode Clock Flexible 3 Wire Serial Data Port with Left Justified 125 Right Justified 16 18 20 24 Bits and TDM Serial Port Modes Master Slave Input and Output Modes 28 Lead SSOP Plastic Package APPLICATIONS Home Theater Systems Studio Digital Mixers Automotive Audio Systems DVD Set Top Boxes Digital Audio Effects Processors Studio to Transmitter Links Digital Audio Broadcast Equipment DigitalTape Varispeed Applications PRODUCT OVERVIEW AD1896 is a 24 bit high performance single chip second generation asynchronous sample rate converter Based on Analog Devices experience with its first asynchronous sample rate converter the AD1890 the AD1896 offers improved performance and additional features This improved performance includes a THD N range of 117 dB to 133 dB depending on
17. DOMAIN OF SAMPLES AT fs IN fs IN FREQUENCY DOMAIN OFTHE INTERPOLATION 220x fc IN SIN X X OF ZERO ORDER HOLD 4 FREQUENCY DOMAIN OF fs RESAMPLING 220 FREQUENCY DOMAIN AFTER 220 x fs IN RESAMPLING E Figure 6 Frequency Domain of the Interpolation and Resampling HARDWARE MODEL output rate of the low pass filter of Figure 5 would be the interpolation rate 22 x 192000 kHz 201 3 GHz Sampling at a rate of 201 3 GHz is clearly impractical not to mention the number of taps required to calculate each interpolated sample However since interpolation by 2 involves zero stuffing 22 1 samples between each fs rx sample most of the multiplies in the low pass FIR filter are by zero A further reduction can be realized by the fact that since only one interpolated sample is taken at the output at the fs our rate only one convolution needs to be performed per fs our period instead of 2 convo lutions 64 tap FIR filter for each fs our sample is sufficient to suppress the images caused by the interpolation difficulty with the above approach is that the correct inter polated sample needs to be selected upon the arrival of fs our Since there are 270 possible convolutions per fs our period the arrival of the fs our clock must be measured with an accuracy of 1 201 3 GHz 4 96 ps Measuring the fg our period with a clock of 201 3 GHz frequency is clearly impossible instead several coarse me
18. D_CORE supply voltage should not exceed VDD IO Specifications subject to change without notice REV A AD1896 POWER SUPPLIES VDD CORE 3 3 V 5 VDD IO 5 0 V 10 Parameter Min Typ Max Unit Total Active Power Dissipation 48 kHz 48 kHz 65 mW 96 kHz 96 kHz 85 mW 192 kHz 192 kHz 132 mW Total Power Down Dissipation RESET LO 2 mW Specifications subject to change without notice TEMPERATURE RANGE Parameter Min Typ Max Unit Specifications Guaranteed 25 C Functionality Guaranteed 40 105 C Storage 55 150 C Thermal Resistance pra Junction to Ambient 109 C W Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Parameter Min Max Unit Power Supplies VDD_CORE 0 3 3 6 V VDD IO 0 3 6 0 V Digital Inputs Input Current 10 mA Input Voltage DGND 0 3 VDD IO 0 3 V Ambient Temperature Operating 40 105 C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ORDERING GUIDE Model Temperature Range Package Description Package Option AD1896AYRS 40 C to 105 C 28 Lead SSOP RS 28
19. HASE MODE Figure 12 Daisy Chain Configuration for TDM Mode First AD1896 Being Clock Master MATCHED PHASE MODE NON TDM MODE APPLICATION LRCLK fs iN LK AD1896 SLAVE1 IN AD1896 PHASE MASTER 7 TDM IN gt SDATA spama o LRCLK LRCLK O SCLK SCLK_O MCLK SDATA SDATA_O LRCLK LRCLK O SCLK_ SCLK_O MCLK RESET M2 1 0 RESET M2 M1 MO AD1896 SLAVE2 IN SDATA SDATA_O LRCLK LRCLK O SCLK O SCLK I MCLK RESET M2 1 MO SDOm SDO1 SDO2 AD1896 SLAVEn TDM IN SDATA sparA o spon LRCLK LRCLK O SCLK_I ScCLK O MCLK RESET 2 1 0 LRCLKo fs ou SCLKo 64fs out MCLK RESET Figure 13 Typical Configuration for Matched Phase Mode Operation Serial Data Port Master Clock Modes Either of the AD1896 serial ports can be configured as a master serial data port However only one serial port can be a master while the other has to be a slave In master mode the AD1896 requires a 256 x fs 512 x fs or 768 x fs master clock MCLK D For a maximum master clock frequency of 30 MHz the maxi mum sample rate is limited to 96 kHz In slave mode sample rates up to 192 kHz can be handled When either of the serial ports is operated in master mode the master clock is divided down to derive the associated left right subframe clock LRCLK and serial bit clock SCLK master clock frequency can be selected for 256 512 or 768 time
20. IO 5 0 V 10 AD1896 Parameter Min Typ Max Unit Pass Band 0 4535 fs Hz Pass Band Ripple 0 016 dB Transition Band 0 4535 fs 0 5465 fs our Hz Stop Band 0 5465 fs Hz Stop Band Attenuation 125 Group Delay Refer to the Group Delay Equations section Specifications subject to change without notice DIGITAL I O CHARACTERISTICS VDD_CORE 3 3 5 VDD 10 5 0 V 10 Parameter Min Unit Input Voltage High 2 4 Input Voltage Low 0 8 V Input Leakage Im 5 V 2 Input Leakage 0 V 2 Input Leakage 1 5 150 UA Input Leakage 0 150 UA Input Capacitance 5 10 pF Output Voltage High 4 mA VDD CORE 0 5 VDD CORE 0 4 V Output Voltage Low Vor Lar 4 mA 0 2 0 5 V Output Source Current High 4 mA Output Sink Current Low Ior 4 mA NOTES input pins except GRPDLYS 2GRPDLYS pin only Specifications subject to change without notice POWER SUPPLIES Parameter Min Unit Supply Voltage VDD_CORE 3 135 3 3 3 465 V VDD IO VDD CORE 3 3 5 0 5 5 V Active Supply Current I CORE ACTIVE 48 kHz 48 kHz 20 mA 96 kHz 96 kHz 26 mA 192 kHz 192 kHz 43 mA IIO ACTIVE 2 mA Power Down Supply Current All Clocks Stopped I CORE PWRDN 0 5 mA IIO PWRDN 10 uA For 3 3 V tolerant inputs VDD IO supply should be set to 3 3 V however VD
21. K I cycles The mute control counter which controls the soft mute attenuation of the input samples is initialized to maximum attenuation 144 dB see the Mute Control section When asserting RESET and deasserting RESET the RESET should be held low for a minimum of five MCLK I cycles During power up the RESET should be held low until the power supplies have stabilized It is recommended that the AD1896 be reset when changing modes Power Supply and Voltage Reference AD1896 is designed for 3 V operation with 5 V input toler ance on the input pins VDD CORE is the 3 V supply that is used to power the core logic of the AD1896 and to drive the output pins VDD IO is used to set the input voltage tolerance of the input pins In order for the input pins to be 5 V input tolerant VDD IO must be connected to a 5 V supply If the input pins do not have to be 5 V input tolerant then VDD can be connected to VDD CORE VDD IO should never be less than VDD CORE VDD CORE and VDD IO should be bypassed with 100 nF ceramic chip capacitors as close to the pins as possible to minimize power supply and ground bounce caused by inductance in the traces A bulk alu minium electrolytic capacitor of 47 uF should also be provided on the same PC board as the AD1896 REV A Digital Filter Group Delay group delay of the digital filter may be selected by the logic pin GRPDLYS As mentioned in the Theory of Operation section this
22. MODE IN 0 Input Port Serial Interface Mode Select Pin 0 11 IN SMODE IN 1 Input Port Serial Interface Mode Select Pin 1 12 IN SMODE IN 2 Input Port Serial Interface Mode Select Pin 2 13 IN RESET Reset Pin Active Low 14 IN MUTE IN Mute Input Pin Active High Normally Connected to MUTE OUT 15 OUT MUTE OUT Output Mute Control Active High 16 IN WLNGTH OUT Hardware Selectable Output Wordlength Select Pin 1 17 IN WLNGTH OUT 0 Hardware Selectable Output Wordlength Select Pin 0 18 IN SMODE OUT 1 Output Port Serial Interface Mode Select Pin 1 19 IN SMODE OUT 0 Output Port Serial Interface Mode Select Pin 0 20 IN TDM IN Serial Data Input Only for Daisy Chain Mode Ground when not used 21 IN DGND Digital Ground Pin 22 IN VDD CORE 3 3 V Digital Supply Pin 23 OUT SDATA O Output Serial Data at Output Sample Rate 24 IN OUT LRCLK O Master Slave Output Left Right Clock 25 IN OUT SCLK O Master Slave Output Serial Bit Clock 26 IN MMODE 0 Master Slave Clock Ratio Mode Select Pin 0 27 IN MMODE 1 Master Slave Clock Ratio Mode Select Pin 1 28 IN MMODE 2 Master Slave Clock Ratio Mode Select Pin 2 Also used to input matched phase mode data REV A AD1896 Typical Performance Characteristics 25 50 7 5 100 12 5 15 0 17 5 200 22 5 FREQUENCY kHz FREQUENCY kHz 1 Wideband FFT Plot 16k Points 0 dBFS 1 kHz Tone TPC
23. Phase Data Transmission Left Justified 125 and TDM Mode MATCHED PHASE AUDIO DATA LEFT CHANNEL MATCHED PHASE AUDIO DATA RIGHT CHANNEL DATA 8 BITS 16 BITS 24 BITS DATA 8 BITS 16 BITS 24 BITS Figure 14b Matched Phase Data Transmission Right Justified Mode REV A 25 AD1896 OUTLINE DIMENSIONS 28 Lead Shrink Small Outline Package SSOP RS 28 Dimensions shown in millimeters 28 15 5 60 8 20 5 30 7 80 5 00 7 40 1 14 175 2 nn MAX 1 65 0 25 TT 0 09 EE Y m sse 028 8 o s e EE RN S 0 PLANE COMPLIANT TO JEDEC STANDARDS MO 150AH 26 REV A AD1896 Revision History Location Page 3 03 Data Sheet changed from REV 0 to REV Edits to DIGITAL PERFORMANCE done een D Atay dsp kus en ein lee mie does 2 Edits to DIGITAL TIMING ob tok RSW Pa EE e arc a a Pe err eS pao E R 3 Edits to ORDBRING GUIDE doge ce Gun b dek Gide bitarte bidek Bug geban eee are Ace ab ie 6 Edits to RESETand Power Down section 21 Edits to Figures 9a and 9b esri oe oe anes ats due ne den IHE A ERE eo ee amp 22 Edits to Serial Data Ports Data Format section iss 55 E gite RO ELEA CR E egn e pen Ee pu 22 Edits to Eigut 13 222252955 donna pur
24. Z A frequency of 30 MHz is more than sufficient to sample rate convert sampling frequencies of 192 kHz 12 The minimum required frequency for the master clock generation for the AD1896 depends upon the input and output sample rates The master clock has to be at least 138 times greater than the maximum input or output sample rate Serial Data Ports Data Format serial data input port mode is set by the logic levels on the SMODE IN 0 SMODE IN l SMODE IN 2 pins The serial data input port modes available are left justified PS and right justified RJ 16 18 20 or 24 bits as defined in Table I 22 Table I Serial Data Input Port Mode SMODE IN 0 2 Interface Format Left Justified PS Undefined Undefined Right Justified 16 Bits Right Justified 18 Bits Right Justified 20 Bits Right Justified 24 Bits OOO 2 ba GO O b be CO SO b GO KO GO SO The serial data output port mode is set by the logic levels on the SMODE OUT 0 SMODE OUT 1 and WLNGTH OUT 0 WLNGTH OUT 1 pins The serial mode can be changed to left justified LS right justified or TDM as defined in the fol lowing table The output word width can be set by using the OUT 0 WLNGTH OUT 1 pins as shown in Table III When the output word width is less than 24 bits dither is added to the truncated bits The right justified serial data out mode assumes 64 SCLK cycles per fr
25. ach other in this mode Another requirement of the matched phase mode is that there must be 32 SCLK_O cycles per subframe The AD1896 will support the matched phase mode for all serial output data formats left justified IS right justified and TDM In the case of TDM the AD1896 shown in the TDM mode operation figure with its TDM IN tied to ground would be configured as the master while the rest of the AD1896s in the chain would be configured as slaves with their MMODE 2 MMODE 1 and 0 pins set to 100 respectively Please note that in the left justified S and TDM modes the lower eight bits of each channel subframe are used to transmit the matched phase data In right justified mode the upper eight bits are used to transmit the matched phase data This is shown in Figures 14a and 14b Bypass Mode When the BYPASS pin is asserted high the input data bypasses the sample rate converter and is sent directly to the serial output port Dithering of the output data when the word length is set to less than 24 bits is disabled This mode is ideal when the input and output sample rates are the same and LRCLK I and LRCLK are synchronous with respect to each other This mode can also be used for passing through non AUDIO data since no processing is performed on the input data in this mode MATCHED PHASE MATCHED PHASE AUDIO DATA LEFT CHANNEL 24 BITS DATA 8 BITS AUDIO DATA RIGHT CHANNEL 24 BITS DATA 8 BITS Figure 14a Matched
26. al Harmonic Distortion Noise 20 Hz to fs our 2 1 kHz 0 dBFS Input No Filter Worst Case 32 kHz 48 kHz 117 dB 44 1 kHz 48 kHz 123 48 kHz 44 1 kHz 124 48 kHz 96 kHz 120 44 1 kHz 192 kHz 123 96 kHz 48 kHz 132 192 kHz 32 kHz 133 Interchannel Gain Mismatch 0 0 dB Interchannel Phase Deviation 0 0 Degrees Mute Attenuation 24 Bits Word Width A Weighted 144 NOTES Lower sampling rates than given by this formula are possible but the jitter rejection will decrease Refer to the Typical Performance Characteristics section for DNR and THD N numbers over wide range of input and output sample rates For any other sample rate ratio the minimum THD N will be better than 117 dB Please refer to detailed performance plots Specifications subject to change without notice REV A DIGITAL TIMING 40 C lt T lt 105 C VDD CORE 3 3 V 5 VDD IO 5 0 V 10 AD1896 Parameter Min Typ Max Unit tMCLKI I Period 33 3 ns MCLK I Frequency 30 022 MHZ I Pulsewidth High ns tMPWL MCLK I Pulsewidth Low 12 ns Input Serial Port Timing tr RIS LRCLK I Setup to SCLK I 8 ns SCLK I Pulsewidth High 8 ns SCLK I Pulsewidth Low 8 ns SDATA I Setup to SCLK I Rising Edge 8 ns tor SDATA_I Hold from SCLK_I Rising Edge 3 ns Propagation Delay from MCLK_I Rising Edge to SCLK_I Rising Edge Serial Input Port MASTER 12 ns P
27. ame divided evenly for left and right Please note that 8 bits of each 32 bit subframe are used for transmitting matched phase mode data Please refer to Figure 14 The AD1896 also supports 16 bit 32 clock packed input and output serial data in LJ and PS format Table II Serial Data Output Port Mode SMODE OUT 0 1 Interface Format 1 0 0 Left Justified L J 0 1 PS 1 0 TDM Mode 1 1 Right Justified RJ Table III Word Width WLNGTH OUT 0 1 Word Width 1 0 0 0 24 Bits 0 1 20 Bits 1 0 18 Bits 1 1 16 Bits The following timing diagrams show the serial mode formats REV A AD1896 LRCLK SEERTCHANNELT CHANNEL SCLK LRCLK SCLK SDATA LEFT CHANNEL LRCLK SCLK SDATA LRCLK SCLK SDATA NOTES LEFT JUSTIFIED MODE 16 BITS TO 24 BITS PER CHANNEL LEFT CHANNEL 2 PS MODE 16 BITS TO 24 BITS PER CHANNEL RIGHT JUSTIFIED MODE SELECT NUMBER OF BITS PER CHANNEL TDM MODE 16 BITS TO 24 BITS PER CHANNEL RIGHT CHANNEL gt RIGHT CHANNEL S RIGHT CHANNEL RNA AC XS CE 1 LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY fs 2 SCLK FREQUENCY IS NORMALLY 64 x LRCLK EXCEPT FOR TDM MODE WHICH IS N x 64 x fe WHERE N NUMBER OF STEREO CHANNELS IN THE TDM CHAIN IN MASTER MODE N 4 3 PLEASE NOTE THAT 8 BITS OF EACH 32 BIT SUBFRAME ARE USED FORTRANSMITTING MATCHED PHASE MODE DATA
28. asurements of the fs our clock period are made and averaged over time Another difficulty with the above approach is the number of coefficients required Since there 220 possible convolutions with a 64 tap FIR filter there needs to be 22 polyphase coeffi cients for each tap which requires a total of 226 coefficients To reduce the amount of coefficients in ROM the AD1896 stores a small subset of coefficients and performs a high order interpola tion between the stored coefficients So far the above approach works for the case of fs our gt fs However in the case when the output sample rate fs our is less than the input sample rate fs ma the ROM starting address input data and the length of the convolution must be scaled As the input sample rate rises over the output sample rate the antialiasing filter s cutoff frequency has to be lowered because the Nyquist frequency of REV A the output samples is less than the Nyquist frequency of the input samples To move the cutoff frequency of the antialiasing filter the coefficients are dynamically altered and the length of the convolution is increased by a factor of fs N fs our This technique is supported by the Fourier transform property that if f t is F then t is F w k Thus the range of decimation is simply limited by the size of the RAM THE SAMPLE RATE CONVERTER ARCHITECTURE The architecture of the sample rate converter is shown in Figure 7 The samp
29. e case of no interpolation This significantly reduces the resampling error IN INTERPOLATE LOW PASS ZERO ORDER OUT FILTER HOLD fs IN 15 our o o O O TIME DOMAIN OF fs iy SAMPLES QUE E GEko O 28807 TIME DOMAIN OUTPUT OF THE LOW PASS FILTER ERN NS M TIME DOMAIN OF fs our RESAMPLING TIME DOMAIN OF THE ZERO ORDER HOLD OUTPUT Figure 5 Time Domain of the Interpolation and Resampling In the frequency domain shown in Figure 6 the interpolation expands the frequency axis of the zero order hold The images from the interpolation can be sufficiently attenuated by a good low pass filter The images from the zero order hold are now pushed by a factor of 229 closer to the infinite attenuation point of the zero order hold which is fs x 22 The images at the zero order hold are the determining factor for the fidelity of the output at fs our The worst case images be computed from the zero order hold frequency response maximum image sin X F fs T Flfs inrerp F is the frequency of the worst case image that would be 270 X fs iN fs 1N 2 and fs irERp is fs X 279 The following worst case images would appear for fs 192 kHz Image 8t fs INTERP 96 kHz 125 1 dB Image at fs 96 kHz 125 1 dB REV A AD1896 OUT INTERPOLATE LOW PASS ZERO ORDER BYN FILTER HOLD fs IN fs our FREQUENCY
30. et is set to 16 for short delay and 64 for long delay In long delay the group delay is effectively increased by 48 input sample clocks The sample rate converter of the AD1896 can be bypassed altogether using the bypass mode In bypass mode the AD1896 s serial input data is directly passed to the serial output port with out any dithering This is useful for passing through nonaudio data or when the input and output sample rates are synchronous to one another and the sample rate ratio is exactly 1 to 1 The AD1896 is a 3 3 V 5 V input tolerant part and is available in a 28 lead SSOP package The AD1896 is 5 V input tolerant only when the VDD IO supply pin is supplied with 5 V 17 AD1896 ASRC FUNCTIONAL OVERVIEW THEORY OF OPERATION Asynchronous sample rate conversion is converting data from one clock source at some sample rate to another clock source at the same or a different sample rate The simplest approach to an asynchronous sample rate conversion is the use of a zero order hold between the two samplers shown in Figure 4 In an asyn chronous system T2 is never equal to T1 nor is the ratio between T2 and rational As result samples at f our will be repeated or dropped producing an error in the resampling process The frequency domain shows the wide side lobes that result from this error when the sampling of fs our is convolved with the attenuated images from the sin x x nature of the zero order hold The images at
31. le rate converter s FIFO block adjusts the left and right input samples and stores them for the FIR filter s convolution cycle The fs counter provides the write address to the FIFO block and the ramp input to the digital servo loop The ROM stores the coefficients for the FIR filter convo lution and performs a high order interpolation between the stored coefficients The sample rate ratio block measures the sample rate for dynamically altering the ROM coefficients and scaling of the FIR filter length as well as the input data The digital servo loop automatically tracks the fg and fs our sample rates and provides the RAM and ROM start addresses for the start of the FIR filter convolution RIGHT DATA IN LEFT DATA IN DIGITAL fs in COUNTER SERVO LOOP L RDATA OUT EXTERNAL RATIO Figure 7 Architecture of the Sample Rate Converter The FIFO receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the sample rate converter and the scaling of the input data by the sample rate ratio before storing the samples in the RAM The input data is scaled by the sample rate ratio because as the FIR filter length of the convolution increases so does the amplitude of the convolution output To keep the output of the FIR filter from saturating the input data is scaled down by multiplying it by fs our fs when fs our lt fs The FIFO also scales the input data for
32. ly track the input and output sample rates Continued on Page 17 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved 01896 5 0 5 TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages VDD CORE 3 3 V VDD IO 5 0 or 3 3 V Ambient Temperature 25 C Input Clock 30 0 MHz Input Signal 1 000 kHz 0 dBES Measurement Bandwidth 20 to fs our 2 Hz Word Width 24 Bits Load Capacitance 50 pF Input Voltage High 2 4V Input Voltage Low 0 8 V Specifications subject to change without notice DIGITAL PERFORMANCE VDD CORE 3 3 V 5 VDD IO 5 0 V 10 Parameter Min Typ Max Unit Resolution 24 Bits Sample Rate 4 MCLK 30 MHz 6 215 kHz Sample Rate Other Master Clocks I 5000 lt f lt MCLK 1 7138 kHz Sample Rate Ratios Upsampling 1 8 Downsampling Short GRPDLYS 7 75 1 Downsampling Long GRPDLYS 7 0 1 Dynamic Range 20 Hz to fs 2 1 2 60 dBFS Input A Weighted Worst Case 192 kHz 48 kHz 132 dB 44 1 kHz 48 kHz 142 dB 48 kHz 44 1 kHz 141 dB 48 kHz 96 kHz 142 dB 44 1 kHz 192 kHz 141 5 dB 96 kHz 48 kHz 140 dB 192 kHz 32 kHz 140 dB 20 Hz to fs our 2 1 kHz 60 dBFS Input No Filter Worst Case 192 kHz 48 kHz 132 dB 44 1 kHz 48 kHz 139 dB 48 kHz 44 1 kHz 139 dB 48 kHz 96 kHz 139 dB 44 1 kHz 192 kHz 137 dB 96 kHz 48 kHz 137 dB 192 2 32 kHz 138 dB Tot
33. muting and unmuting of the AD1896 The RAM in the FIFO is 512 words deep for both left and right channels An offset to the write address provided by the fs counter is added to prevent the RAM read pointer from ever overlapping the write address The offset is selectable by the GRPDLYS group delay select signal small offset 16 is added to the write address pointer when GRPDLYS 15 high and a large offset 64 is added to the write address pointer when GRPDLYS is low Increasing the offset of the write address pointer is useful for applications when small changes in the sample rate ratio between fs and fs our are expected The maximum deci mation rate can be calculated from the RAM word depth and GRPDLYS as 512 16 64 taps 7 75 for short group delay and 512 64 64 taps 7 for long group delay 19 AD1896 40 SLOW MODE FAST MODE 0 01 0 1 1 10 100 1e3 1e4 1e5 FREQUENCY Hz Figure 8 Frequency Response of the Digital Servo Loop fs jy Is the X Axis fs our 192 kHz Master Clock Frequency Is 30 MHz The digital servo loop is essentially a ramp filter that provides the initial pointer to the address in RAM and ROM for the start of the FIR convolution The RAM pointer is the integer outpu
34. nd the ROM address pointer from the digital servo loop at the start of the fs our period FIR filter then steps through the RAM by decrementing its address by 1 for each tap and the ROM pointer increments its address by the fs our fs m x 2 ratio for fs w gt fs our or 220 for fs our gt Once the ROM address rolls over the con volution is completed The convolution is performed for both the left and right channels and the multiply accumulate circuit used for the convolution is shared between the channels The fs wits our sample rate ratio circuit is used to dynamically alter the coefficients in the ROM for the case when fg n gt fs our The ratio is calculated by comparing the output of an fs our counter to the output of an fs counter If fs our gt fs m the ratio is held at one If fs m gt fs our the sample rate ratio is updated if it is different by more than two f our periods from the previous fs our to fs comparison This is done to provide some hysteresis to prevent the filter length from oscillat ing and causing distortion REV A AD1896 However the hysteresis of the fs our fs x ratio circuit can cause phase mismatching between two AD1896s operating with the same input clock and the same output clock Since the hyster esis requires a difference of more than two fs our periods for the fs out fs iN ratio to be updated two AD1896s may have dif ferences in their ratios from 0 to 4 f our period c
35. ounts The fs our fs ratio adjusts the filter length of the AD1896 which corresponds directly with the group delay Thus the magnitude in the phase difference will depend upon the resolution of the fs our and fs m counters The greater the resolution of the counters the smaller the phase difference error will be The fs m and fs our counters of the AD1896 have three bits of extra resolution over the AD1890 which reduces the phase mismatch error by a factor of 8 However an additional feature was added to the AD1896 to eliminate the phase mismatching completely AD1896 can set the fs our fs ratio of other AD1896s by transmitting its fs our fs ratio through the serial output port OPERATING FEATURES RESET and Power Down When RESET is asserted low the AD1896 will turn off the master clock input to the AD1896 MCLK initialize all of its internal registers to their default values and three state all of the I O pins While RESET is active low the AD1896 is consuming minimum power For the lowest possible power consumption while RESET is active low all of the input pins to the AD1896 should be static When RESET is deasserted the AD1896 begins its initialization routine where all locations in the FIFO are initialized to zero MUTE OUT is asserted high and any I O pins configured as outputs are enabled When RESET is deasserted the master serial port clock pins SCLK I O and LRCLK I O become active after 1024 MCL
36. pin is particularly useful in varispeed applications The GRPDLYS pin has an internal pull up resistor of approximately 33 to VDD CORE When GRPDLYS is high the filter group delay will be short and is given by the equation 16 GDS seconds for fs gt fs S_IN 16 32 I GDS 4 do seconds for fs our lt fs IN fs our 5 E For short filter group delay the GRPDLYS can be left open When GRPDLYS is low the group delay of the filter will be long and is given by the equation 64 GDL seconds for fs our gt fs IN fsm 2 2 64 32 GDL d do seconds for fs our lt fs IN fs our u NOTE For the long group delay mode the decimation ratio is limited to less than 7 1 Mute Control When the MUTE IN is asserted high the MUTE IN control will perform a soft mute by linearly decreasing the input data to the AD1896 FIFO to zero 144 dB attenuation When IN is deasserted low the MUTE IN control will linearly decrease the attenuation of the input data to 0 dB A 12 bit counter clocked by is used to control the mute attenuation Therefore the time it will take from the assertion of MUTE IN to 144 dB full mute attenuation is 4096 LRCLK seconds Likewise the time it will take to reach 0 dB mute attenuation from the deassertion of MUTE IN is 4096 LRCLK seconds Upon RESET or a change in the sample rate be
37. ropagation Delay from MCLK_I Rising Edge to LRCLK_I Rising Edge Serial Input Port MASTER 12 ns Output Serial Port Timing trDMS IN Setup to SCLK Falling Edge 3 ns IN Hold from SCLK_O Falling Edge 3 ns tpopp SDATA_O Propagation Delay from SCLK_O LRCLK_O 20 ns tpoH Hold from SCLK 3 ns ty ROS LRCLK O Setup to SCLK_O TDM Mode Only 5 ns trgoH LRCLK Hold from SCLK TDM Mode Only 3 ns SCLK Pulsewidth High 10 ns SCLK Pulsewidth Low 5 ns tRSTL RESET Pulsewidth Low 200 ns Propagation Delay from MCLK I Rising Edge to SCLK_O Rising Edge Serial Output Port MASTER 12 ns Propagation Delay from MCLK I Rising Edge to LRCLK Rising Edge Serial Output Port MASTER 12 ns NOTES Refer to Timing Diagrams section The maximum possible sample rate is FSmax 138 of up to 34 MHz is possible under the following conditions 0 C lt lt 70 C 45 55 or better MCLK I duty cycle Specifications subject to change without notice REV A 3 AD1896 TIMING DIAGRAMS LRCLK SCLK SDATA LRCLK O SCLK O SDATA O LRCLK O SCLK O TDM IN Figure 1 Input and Output Serial Port Timing SCLK I O trpus 4 TE L LRCLK 1 0 SDATA 1 0 TDM IN AN TN RESET L Figure 2 RESET Timing tupwx Figure 3 MCLK Timing REV DIGITAL FILTERS VDD CORE 3 3 V 5 VDD
38. s the input or output sample rate Both the input and out put serial ports will support master mode LRCLK and SCLK generation for all serial modes left justified PS right justified and TDM for the output serial port Table IV Serial Data Port Clock Modes MMODE 0 MMODE 1 MMODE 2 Interface Format 2 1 0 0 0 0 Both serial ports are in slave mode 0 0 1 Output serial port is master with 768 x fs our 0 1 0 Output serial port is master with 512 x fs our 0 1 1 Output serial port is master with 256 x fs our 1 0 0 Matched phase Mode 1 0 1 Input serial port is master with 768 x fs 1 1 0 Input serial port is master with 512 x fs yy 1 1 1 Input serial port is master with 256 x fs qn 24 REV A AD1896 Matched Phase Mode The matched phase mode is the mode discussed in the Theory of Operation section that eliminates the phase mismatch between multiple AD1896s The master AD1896 device transmits its fs our fs ratio through the SDATA pin to the slave AD1896 s TDM IN pins The slave AD1896s receive the transmitted fs ratio and use the transmitted fs fs ratio instead of their own internally derived fs our fs IN ratio The master device can have both its serial ports in slave mode as depicted or either one in master mode The slave AD1896s must have their MMODE 2 MMODE 1 and MMODE 0 pins set to 100 respectively LRCLK I and LRCLK may be asynchronous with respect to e
39. t of the ramp filter while the ROM is the fractional part The digital servo loop must be able to provide excellent rejection of jitter on the fs i and fs our clocks as well as measure the arrival of the fs our clock within 4 97 ps The digital servo loop will also divide the fractional part of the ramp output by the ratio of fs our for the case when fs w gt fs our to dynamically alter the ROM coefficients digital servo loop is implemented with a multirate filter settle the digital servo loop filter quicker upon start up or a change in the sample rate a fast mode was added to the filter When the digital servo loop starts up or the sample rate is changed the digital servo loop kicks into fast mode to adjust and settle on the new sample rate Upon sensing the digital servo loop settling down to some reasonable value the digital servo loop will kick into normal or slow mode During fast mode the MUTE_OUT signal of the sample rate converter is asserted to let the user know that they should mute the sample rate converter to avoid any clicks or pops The frequency response of the digital servo loop for fast mode and slow mode are shown in Figure 8 20 The FIR filter is 64 tap filter in the case of fs our 2 fs and is fs our X 64 taps for the case when fs x gt fs our The FIR filter performs its convolution by loading in the starting address of the RAM address pointer a
40. tween LRCLK I and LRCLK the MUTE OUT pin will be asserted high The MUTE OUT pin will remain asserted high until the digital servo loop s internal fast settling mode has completed When the digital servo loop has switched to slow settling mode the MUTE OUT pin will deassert While MUTE OUT is asserted the MUTE IN pin should be asserted as well to prevent any major distortion in the audio output samples Master Clock A digital clock connected to the MCLK I pin or a fundamental or third overtone crystal connected between MCLK I and MCLK can be used to generate the master clock MCLK I The MCLK I pin can be 5 V input tolerant just like any of the other AD1896 input pins A fundamental mode crystal can be inserted between MCLK I and O for master clock frequency generation up to 27 MHz For master clock fre quency generation with a crystal beyond 27 MHz it is recommended that the user use a third overtone crystal and to add an LC filter at the output of MCLK to filter out the fundamental do not notch filter the fundamental Please refer to your quartz crystal supplier for values for external capaci tors and inductor components 21 AD1896 AD1896 C1 c2 T I E Figure 9b Third Overtone Circuit Configuration There are of course maximum and minimum operating fre quencies for the AD1896 master clock The maximum master clock frequency at which the AD1896 is guaranteed to operate is 30 ME
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ANALOG DEVICES AD1896 English products handbook Rev A