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CIRRUS LOGIC CS5509 Manual

1. DS125F2 CS5509 SS SSS ad ENVIRONMENTAL MANUFACTURING amp HANDLING INFORMATION Model Peak Relfow Temp MSL Rating Maximum Floor Life CS5509 AP 260 C 1 No Limit CS5509 AS 240 C 2 365 Days CS5509 ASZ lead free 260 C 3 7 Days MSL Moisture Sensitivity Level as specified by IPC JEDEC J STD 020 REVISION HISTORY Revision Date Changes F1 Aug 97 First final release F2 Aug 05 Added lead free device ordering info Added legal notice Added MSL data Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative To find the one nearest to you go to www cirrus com IMPORTANT NOTICE Cirrus Logic Inc and its subsidiaries Cirrus believe that the information contained in this document is accurate and reliable However the information is subject t change without notice and is provided AS IS without warranty of any kind express or implied Customers are advised to obtain the latest version of relevant infor mation to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplie at the time of order acknowledgment including those pertaining to warranty indemnification and limitation of liability No responsibility is assumed by Cirrus for thi use of this information including use o
2. 5V 10 Input Levels Logic 0 OV Logic 1 VD C 50 pF Note 2 Parameter Symbol Min Typ Max Unit Master Clock Frequency Internal Oscillator XIN 30 0 32 768 53 0 kHz External Clock Jo 30 330 kHz Master Clock Duty Cycle 40 60 9 6 Rise Times Any Digital Input Note 10 1 0 us Any Digital Output trise 50 ns Fall Time Any Digital Input Note 10 1 0 US Any Digital Output bat 20 ns Start Up Power On Reset Period Note 11 tres 10 ms Oscillator Start up Time XTAL 32 768 kHz Note 12 tosu 500 ms Wake up Period Note13 twp 1800 s Calibration CONV Pulse Width CAL 1 Note 14 Lon 100 ns CONV and CAL High to Start of Calibration Il 2 f 200 ns Start of Calibration to End of Calibration teal 3246 fcik S Conversion CONV Pulse Width Low 100 ns CONV High to Start of Conversion Lon 2 fy 200 ns Set Up Time BP UP stable prior to DRDY falling tbus Dia s Hold Time BP UP stable after DRDY falls tbuh 0 ns Start of Conversion to End of Conversion Note 15 Lon 1624 foK S Notes 10 11 An internal power on reset is activated whenever power is applied to the device Specidified using 1096 and 9096 points on waveform of interest 12 Oscillator start up time varies with the crystal parameters This specification does not apply when using an external clock
3. 60 uA Power Dissipation Note 7 1 7 2 25 mW Power Supply Rejection 80 dB Notes 1 Both source resistance and shunt capacitance are critical in determining the CS5509 s source impedance requirements Refer to the text section Analog Input Impedance Considerations Specifications guaranteed by design characterization and or test Applies after calibration at the temperature of interest Total drift over the specified temperature range since calibration at power up at 25 C The input is differential Therefore GND lt Signal Common Mode Voltage lt VA The CS5509 can accept input voltages up to the VA analog supply In unipolar mode the CS5509 will output all 1 s if the dc input magnitude AIN AIN exceeds VREF VREF and will output all O s if the input becomes more negative than 0 Volts In bipolar mode the CS5509 will output all 1 s if the dc input magnitude AIN AIN exceeds VREF VREF and will output all O s if the input becomes more negative in magnitude than VREF VREF 7 All outputs unloaded All inputs CMOS levels Refer to the Specification Definitions immediately following the Pin Description Section E Fb nb 2 DS125F2 CS5509 DYNAMIC CHARACTERISTICS Parameter Symbol Ratio Unit Modulator Sampling Frequency fs Low Hz Output Update Rate CONV 1 fout fek 1622 Hz Filter Corner Frequency f adp fc 1928 Hz Settling Time to 1 2 LSB FS S
4. Analog 11 13 EN SKS i VA VD Ka Optional T eu pes em hal SCLK Serial Source lo de 15 Data 32 768 kHz lt XOUT SDATA pn Interface CS5509 Analog gt AIN Signal 8 AIN A CS 1 CONV a CAL Ls Control 9 gt VREF 6 Logic Voltage BP UP K J Reference 10 deen TT 18 GND 12 DS125F2 Figure 9a System Connection Diagram Using a Single Supply 17 Note VD must never be more positive than VA e 3 3V to 45V 5V uF 0 1 uF Digital Analog 11 13 mE Supply Sm bd VA VD 7 Optional 4 T eu ueste SUN SCLK Source i pate 1 5 15 ata 32 768 kHz lt XOUT SDATA pn Interface CS5509 M 7 Analog gt AIN Signal 8 AIN n CS e CONV 2 CAL S Control 2 VREF BENE Logic Voltage BP UP 4 7 Reference 10 eee DRDY 19 gt GND 12 e sm Figure 9b System Connection Diagram Using Split Supplies 18 DS125F2 EECH PIN DESCRIPTIONS CHIP SELECT CS 1e 16 DRDY DATA READY CONVERT CONV 2 15 SDATA SERIAL DATA OUTPUT CALIBRATE CAL 3 14 SCLK SERIAL CLOCK INPUT CRYSTAL IN XIN 4 13 VD POSITIVE DIGITAL POWER CRYSTAL OUT XOUT 5 12 GND GROUND BIPOLAR UNIPOLAR BPIUP 6 11
5. Ground Pin 12 Ground 20 DS125F2 CSI g r p Cm MM g TT UU n M SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the A D Converter transfer function One endpoint is located 1 2 LSB below the first code transition and the other endpoint is located 1 2 LSB beyond the code transition to all ones Units in percent of full scale Differential Nonlinearity The deviation of a code s width from the ideal width Units in LSBs Full Scale Error The deviation of the last code transition from the ideal VREF VREF LSB Units are in LSBs Unipolar Offset The deviation of the first code transition from the ideal LSB above the voltage on the AIN pin when in unipolar mode BP UP low Units are in LSBs Bipolar Offset The deviation of the mid scale transition 011 111 to 100 000 from the ideal LSB below the voltage on the AIN pin when in bipolar mode BP UP high Units are in LSBs DS125F2 21 CS5509 PACKAGE DIMENSIONS SEATING PLANE v VEU a NOTES SAG h gh gu gu AN 16 9 1 8 lt m l V r V a a P V r 16 pin Plastic DIP 1 POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0 13mm 0 005 AT MAXIMUM MATERIAL CONDITION IN RELATION TO SEATING PLANE AND EACH OTHER 2 DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL 3 DIMENSION E1 DOES NOT INCL
6. high When DRDY goes high just prior to a port up date it checks to see if the port is either empty or unselected CS 1 If the port is empty or unse lected the digital filter will update the port with a new output word When new data is put into the port DRDY will go low Reading Serial Data SDATA is the output pin for the serial data When CS goes low after new data becomes available DRDY goes low the SDATA pin comes out of Hi Z with the MSB data bit present SCLK is the input pin for the serial clock If the MSB data bit is on the SDATA pin the first rising edge of SCLK enables the shifting mechanism This allows the falling edges of SCLK to shift subsequent data bits out of the port Note that if the MSB data bit is out put and the SCLK signal is high the first falling edge of SCLK will be ignored because the shifting mechanism has not become activated After the first rising edge of SCLK each subsequent falling edge will shift out the serial data Once the LSB is present the falling edge of SCLK will cause the SDATA output to go to Hi Z and DRDY to return high The serial port register will be updated with a new data word upon the completion of another con version if the serial port has been emptied or if the CS is inactive high CS can be operated asynchronously to the DRDY signal The DRDY signal need not be monitored as long as the CS signal is taken low for at least two XIN clock cycles plus 200ns prior
7. 4th order Digital 18 DRDY delta sigma i Filter AIN 4 8 modulator T 2 CAL Calibration uC 6 BP UP Calibration SRAM OSC 12 la 5 CONV XIN XOUT CIRRUS LOGIC 3 Copyright Cirrus Logic Inc 2005 http www cirrus com All Rights Reserved AUG 05 DS125F2 1 CS5509 ANALOG CHARACTERISTICS T 25 c VA 5V 10 VD 3 3V 5 VREF 2 5V VREF OV fc x 32 768 kHz Bipolar Mode Rsource 40 Q with a 10 nF to GND at AIN AIN 2 5V unless oth erwise specified Notes 1 and 2 Parameter Min Typ Max Unit Accuracy Linearity Error feyk 32 768 kHz S 0 0015 0 003 FS fork 165 kHz 0 0015 0 003 FS feyk 247 5 kHz 0 0015 0 003 FS fork 330 kHz 0 005 0 0125 FS Differential Nonlinearity 0 25 0 5 LSB Full Scale Erro Note 3 0 25 2 LSB Full Scale Drift Note 4 0 5 LSB Unipolar Offset Note 3 0 5 2 LSB Unipolar Offset Drift Note 4 0 5 LSB Bipolar Offset Note 3 0 25 1 LSB Bipolar Offset Drift Note 4 0 25 LSB Noise Referred to Output 0 16 LSBrms Analog Input Analog Input Range Unipolar 0 to 2 5 V Bipolar Notes 5 and 6 2 5 V Common Mode Rejection dc 105 dB fei k 32 768 kHz 50 60 Hz Note 2 120 z dB Input Capacitance 15 pF DC Bias Current Note 1 5 nA Power Supplies DC Power Supply Currents Total 350 450 uA lAnalog 300 HA IDigital
8. Hz Frequency Minimum Hz Attenuation dB 50 21 60 H 100 21 200 1 240 1 Table 2 Filter Notch Attenuation XIN 32 768 kHz Anti Alias Considerations for Spectral Measurement Applications Input frequencies greater than one half the output word rate CONV 1 may be aliased by the con verter To prevent this input signals should be lim ited in frequency to no greater than one half the output word rate of the converter when CONV 1 Frequencies close to the modulator sample rate XIN 2 and multiples thereof may also be aliased If the signal source includes spectral components above one half the output word rate when CONV 1 these components should be removed by means of low pass filtering prior to the A D input DS125F2 CS5509 to prevent aliasing Spectral components greater than one half the output word rate on the VREF in puts VREF and VREF may also be aliased Fil tering of the reference voltage to remove these spectral components from the reference voltage is desirable Crystal Oscillator The CS5509 is designed to be operated using a 32 768kHz tuning fork type crystal One end of the crystal should be connected to the XIN input The other end should be attached to XOUT Short lead lengths should be used to minimize stray ca pacitance Over the industrial temperature range 40 to 85 C the on chip gate oscillator will oscillate with other crystals in the range of 30kHz to 53 k
9. bipolar modes At the end of the calibration cycle the on chip mi crocontroller checks the logic state of the CONV signal If the CONV input is low the device will en ter the standby mode where it waits for further in struction If the CONV signal is high at the end of the calibration cycle the converter will enter the conversion state and perform a conversion on the input channel The CAL signal can be returned low any time after calibration is initiated CONV can also be returned low but it should never be taken low and then taken back high until the calibration period has ended and the converter is in the standby state If CONV is taken low and then high again with CAL high while the converter is calibrating the device will interrupt the current calibration cy cle and start a new one If CAL is taken low and CONV is taken low and then high during calibra tion the calibration cycle will continue as the con version command is disregarded The state of BP UP is not important during calibrations If an end of calibration signal is desired pulse the CAL signal high while leaving the CONV signal high continuously Once the calibration is complet ed a conversion will be performed At the end of the conversion DRDY will fall to indicate the first valid conversion after the calibration has been completed Conversion The conversion state can be entered at the end of the calibration cycle or whenever the converter is idle in t
10. to SCLK being toggled This ensures that CS has gained control over the serial port 15 CS5509 Power Supplies and Grounding The analog and digital supply pins to the CS5509 are brought out on separate pins to minimize noise coupling between the analog and digital sections of the chip In the digital section of the chip the supply current flows into the VD pin and out of the GND pin As a CMOS device the CS5509 requires that the supply voltage on the VA pin always be more positive than the voltage on any other pin of the de vice If this requirement is not met the device can latch up or be damaged In all circumstances the VA voltage must remain more positive than the VD or GND pins VD must remain more posi tive than the GND pin 16 Figure 9a illustrates the System Connection Dia gram for the CS5509 Note that all supply pins are bypassed with 0 1 pF capacitors and that the VD digital supply is derived from the VA supply Fig ure 9b illustrates the CS5509 operating from a 5V analog supply and 3 3V digital supply When using separate supplies for VA and VD VA must be established first VD should never become more positive than VA under any operat ing condition Remember to investigate transient power up conditions when one power supply may have a faster rise time DS125F2 CS5509 102 e s vip TOM 0 1 pF 0 1 uF
11. 15 5 0 5 5 V Positive Analog VA 4 5 5 0 5 5 V VREF Analog Reference Voltage Note 2011 VREF 1 0 2 5 3 6 V Analog Input Voltage Note 6 Unipolar VAIN 0 VREF VREF V Bipolar VAIN VREF VREF VREF VREF V Notes 19 All voltages with respect to ground 20 The CS5509 can be operated with a reference voltage as low as 100 mV but with a corresponding reduction in noise free resolution The common mode voltage of the voltage reference may be any value as long as VREF and VREF remain inside the supply values of VA and GND ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Typ Max Unit DC Power Supplies Ground Note 21 GND 0 3 VD 0 3 V Positive Digital Note 22 VD 0 3 6 0 V Positive Analog VA 0 3 6 0 V Input Current Any Pin Except Supplies Notes 23 and 24 lin 10 mA Output Current lout 25 mA Power Dissipation Total Note 25 500 mW Analog Input Voltage AIN and VREF pins Vina 0 3 VA 0 3 _ V Digital Input Voltage VIND 0 3 VD 0 3 _ V Ambient Operating Temperature TA 40 85 C Storage Temperature Tstg 65 150 C Notes 21 No pin should go more positive than VA 0 3 V 22 VD must always be less than VA 0 3 V and can never exceed 6 0 V 23 Applies to all pins including continuous overvoltage conditions at the analog input AIN pin 24 Transient currents of up to 100 mA will not cause
12. B Note Table excludes common mode voltage on the signal and reference inputs Table 1 Output Coding offset and gain The CS5509 device has no missing code performance to 16 bits Figure4 illustrates the DNL of the CS5509 The converter achieves Com mon Mode Rejection CMR at dc of 105dB typi cal and CMR at 50 and 60Hz of 120dB typical The CS5509 can experience some drift as tempera ture changes The CS5509 uses chopper stabilized techniques to minimize drift Measurement errors due to offset or gain drift can be eliminated at any time by recalibrating the converter Analog Input Impedance Considerations The analog input of the CS5509 can be modeled as illustrated in Figure 5 Capacitors 15 pF each are used to dynamically sample each of the inputs AIN and AIN Every half XIN cycle the switch alternately connects the capacitor to the output of the buffer and then directly to the AIN pin When ever the sample capacitor is switched from the out put of the buffer to the AIN pin a small packet of charge a dynamic demand of current is required from the input source to settle the voltage of the sample capacitor to its final value The voltage on the output of the buffer may differ up to 100 mV from the actual input voltage due to the offset volt age of the buffer Timing allows one half of a XIN clock cycle for the voltage on the sample capacitor to settle to its final value DS125F2 CS5509 lrir iiin
13. EE E EE dg I I poi AA bee E ENG E E l i i l i i EU XIN 32 768 kHz ME WASSER E KE E KR E E A x1 0 40 80 120 160 200 240 X2 0 402 83 805 66 1208 5 1611 3 2014 2 2416 9 Frequency Hz Figure 6 Filter Magnitude Plot to 260 Hz 07 E F T T T T T T T i i I 1 S i i f f l f f f f f I f i eg i Frequency dB i i i 7 1 0 010 LEE ee ae 3 amp uem E A E de 4 0 186 1 L n dlanabandanabanld i 5 0 259 c i 6 0 374 i i I i f E RM a f e M f f f f f AMNEM 100 4 9 0846 4 4 1 047 XIN 32 768 kHz 7 3 093 120 24 deeem oua Xe c4 0 de we 3 i i I f f f i f f 140 0 5 10 15 20 25 30 35 40 45 50 Frequency Hz Figure 7 Filter Magnitude Plot to 50 Hz line frequency interference will occur with the CS5509 running at 32 768kHz 14 180 I T I IET NC I I T 1 T L Y WE fe ies e oec ine e en Sod fons b O3 b P oF X w 05 3 90 2 c 2 iL L 4L tL 2 242 L FON I l N E ee ar E E S N l l BE D K olive 9 SSES Ux F por O A5 coeno ee a eee IND fF 3 ww me 4 ee 000 0 0 XIN 32 768 kHz EE EE EE EE Lodo rw E E 4 180 4 P 0 5 10 15 20 25 30 35 40 45 50 Frequency Hz Figure 8 Filter Phase Plot to 50
14. Hz The chip will operate with external clock frequen cies from 30kHz to 330kHz over the industrial tem perature range The 32 768 kHz crystal is normally specified as a time keeping crystal with tight spec ifications for both initial frequency and for drift over temperature To maintain excellent frequency stability these crystals are specified only over lim ited operating temperature ranges i e 10 C to 60 C by the manufacturers Applications of these crystals with the CS5509 does not require tight initial tolerance or low tempco drift There fore a lower cost crystal with looser initial toler ance and tempco will generally be adequate for use with the CS5509 Also check with the manufactur er about wide temperature range application of their standard crystals Generally even those crys tals specified for limited temperature range will op erate over much larger ranges if frequency stability over temperature is not a requirement The frequen cy stability can be as bad as 3000 ppm over the operating temperature range and still be typically better than the line frequency 50 Hz or 60Hz sta bility over cycle to cycle during the course of a day DS125F2 Serial Interface Logic The digital filter in the CS5509 takes 1624 clock cycles to compute an output word once a conver sion begins At the end of the conversion cycle the filter will attempt to update the serial port Two clock cycles prior to the update DRDY will go
15. ODUCT THAT IS USED IN SUCH MANNER IF THE CUSTOMER OR CUSTOMER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS CUSTOM ER AGREES BY SUCH USE TO FULLY INDEMNIFY CIRRUS ITS OFFICERS DIRECTORS EMPLOYEES DISTRIBUTORS AND OTHER AGENTS FROM AN AND ALL LIABILITY INCLUDING ATTORNEYS FEES AND COSTS THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES Cirrus Logic Cirrus and the Cirrus Logic logo designs are trademarks of Cirrus Logic Inc All other brand and product names in this document may be trademarks c service marks of their respective owners DS125F2 23
16. SCR latch up Maximum input current for a power supply pin is 50 mA 25 Total power dissipation including all input currents and output currents WARNING Operation at or beyond these limits may result in permanent damage to the device Normal operation is not guaranteed at these extremes DS125F2 9 CS5509 GENERAL DESCRIPTION The CS5509 is a low power 16 bit monolithic CMOS A D converter designed specifically for measurement of dc signals The CS5509 includes a delta sigma charge balance converter a voltage reference a calibration microcontroller with SRAM a digital filter and a serial interface The CS5509 is optimized to operate from a 32 768 kHz crystal but can be driven by an external clock whose frequency is between 30kHz and 330kHz When the digital filter is operated with a 32 768 kHz clock the filter has zeros precisely at 50 and 60 Hz line frequencies and multiples thereof The CS5509 uses a start convert command to start a convolution cycle on the digital filter Once the filter cycle is completed the output port is up dated When operated with a 32 768kHz clock the ADC converts and updates its output port at 20 samples sec The output port operates in a synchro nous externally clocked interface format THEORY OF OPERATION Basic Converter Operation The CS5509 A D converter has three operating states These are stand by calibration and conver sion When power is first applied an internal pow e
17. UDE MOLD FLASH 22 Da SOIC L MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX 3 94 5 08 0 155 0 200 0 51 1 02 0 020 0 040 0 38 0 46 0 53 0 015 0 021 0 89 1 27 1 65 0 035 0 065 0 20 0 25 0 38 0 008 0 015 18 93 19 43 19 93 0 745 0 785 6 10 6 35 6 60 0 240 0 260 2 41 2 67 0 095 0 105 2 54 7 62 8 25 0 300 0 325 3 18 3 81 0 125 0 150 0 15 0 15 pins MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX 9 91 10 16 10 41 0 390 0 400 0 410 12 45 12 70 12 95 0 490 0 500 0 510 14 99 15 24 15 50 0 590 0 600 0 610 17 53 17 78 18 03 0 690 0 700 0 710 MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX 2 41 2 54 2 67 0 095 0 100 0 105 0 127 0 300 0 005 0 012 2 29 2 41 2 54 0 090 0 095 0 100 0 33 0 46 0 51 0 013 0 018 0 020 0 203 0 280 0 381 0 008 0 011 0 015 see table a bove 10 11 10 41 10 67 0 398 0 410 0 420 7 42 7 49 7 57 0 292 0 295 0 298 1 14 1 27 1 40 0 040 0 050 0 055 0 41 0 89 0 016 0 035 0 8 0 8
18. VA POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT AIN 7 10 VREF VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT AIN 8 9 VREF VOLTAGE REFERENCE INPUT Pinout applies to both PDIP and SOIC Clock Generator XIN XOUT Crystal In Crystal Out Pins 4 5 A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device Alternatively an external CMOS compatible clock can be supplied into the XIN pin to provide the master clock for the device Loss of clock will put the device into a lower powered state approximately 70 power reduction Serial Output I O CS Chip Select Pin 1 This input allows an external device to access the serial port DRDY Data Ready Pin 16 Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new output word has been placed into the serial port DRDY will return high after all data bits are shifted out of the serial port or two master clock cycles before new data becomes available if the CS pin is inactive high SDATA Serial Data Output Pin 15 SDATA is the output pin of the serial output port Data from this pin will be output at a rate determined by SCLK Data is output MSB first and advances to the next data bit on the falling edges of SCLK SDATA will be in a high impedance state when not transmitting data SCLK Serial Clock Input Pin 14 A clock signal on this
19. chronous CS SCLK i should not be taken high sooner than 2 fo 200 ns after CS goes low 17 SDATA transitions on the falling edge of SCLK Note that a rising SCLK must occur to enable the serial port shifting mechanism before falling edges can be recognized 18 IfCS is returned high before all data bits are output the SDATA output will complete the current data bit and then go to high impedance 3 3V SWITCHING CHARACTERISTICS 1 25 C VA 5V 10 VD 3 3V 5 Input Levels Logic 0 OV Logic 1 VD C 50 pF Note 2 Parameter Symbol Min Typ Max Unit Serial Clock fscik 0 1 25 MHz Serial Clock Pulse Width High ton 200 ns Pulse Width Low tpi 200 ns Access Time CS Low to data valid Note 16 tesa 100 200 ns Maximum Delay Time Note 17 SCLK falling to new SDATA bit tad 400 600 ns Output Float Delay CS High to output Hi Z Note 18 rai 70 150 ns SCLK falling to Hi Z bas 320 500 ns DS125F2 7 CS5509 DRDY Cs F OH SDATA o Hi Z fd 2 SCLK i 3 tesd R SDATA o Hi Z MSB MSB 1 tdd lt SCLK i 1 Figure 3 Timing Relationships Not to Scale LSB 2 LSB 1 LSB AAAA Mii 8 DS125F2 CS5509 RECOMMENDED OPERATING CONDITIONS DGND OV Note 19 Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital VD 3
20. d Single supply 16 bit A D Converter Features Description o Delta sigma A D Converter The CS5509 is a single supply 16 bit serial output SC CMOS A D converter The CS5509 uses charge bal 16 bit No Missing Codes anced delta sigma techniques to provide low cost Linearity Error 0 0015 FS high resolution measurements at output word rates up to 200 samples per second e Differential Input The on chip digital filter offers superior line rejection at Pin selectable Unipolar Bipolar Ranges 50Hz and 60Hz when the device is operated from a Common Mode Rejection 32 768 kHz clock output word rate 20 Sps 105 dB dc The CS5509 has on chip self calibration circuitry which 120 dB 50 60 Hz can be initiated at any time or temperature to ensure minimum offset and full scale errors e Either SV or 3 3V Digital Interface Low power high resolution and small package size M make the CS5509 an ideal solution for loop powered e On chip Self calibration Circuitry transmitters panel meters weigh scales and battery powered instruments e Output Update Rates up to 200 second ORDERING INFORMATION CS5509 AP 40 C to 85 C 16 pin PDIP e Ultra Low Power 1 7 mW CS5509 AS 40 Cto 85 C 16 pin SOIC CS5509 ASZ 40 C to 85 C 16 pin SOIC Lead Free VREF VREF VAt GND VD 9 10 11 12 13 K 1 ER Serial Loa d SCLK 7 Interface 15 AINt m Differential Loi m SDATA
21. d 8 illustrate the magnitude and phase characteristics of the filter Figure 6 illustrates the filter attenua tion from dc to 260 Hz At exactly 50 60 100 and 120 Hz the filter provides over 120 dB of rejection Table 2 indicates the filter attenuation for each of the potential line interference frequencies when the converter is operating with a 32 768 kHz clock The converter yields excellent attenuation of these interference frequencies even if the fundamental line frequency should vary 1 from its specified frequency The 3 dB corner frequency of the filter when operating from a 32 768 kHz clock is 17 Hz Figure 8 illustrates that the phase characteristics of the filter are precisely linear phase If the CS5509 is operated at a clock rate other than 32 768kHz the filter characteristics including the comb filter zeros will scale with the operating clock frequency Therefore optimum rejection of 13 CIRRUS LOGIC CS5509 0 4 U l I I I I I I N I INI l J 20 W b d l L X12 32 768kHz X2 330 00kHz rem Tdi NP bu u a Img 2 B dise A redis ud ec ses 5 d a om rA NOE roro m 80 aded esce cbe ce e ess G I I f as ul i E l 400 smod Edd uec be dee de oped E i Carb or dodorde dod s DEIER EE EE EE SE EE D
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23. he standby mode If CONV is taken high to initiate a calibration cycle CAL also high and re mains high until the calibration cycle is completed CAL is taken low after CONV transitions high the converter will begin a conversion upon comple tion of the calibration period DS125F2 The BP UP pin is not a latched input The BP UP pin controls how the output word from the digital filter is processed In bipolar mode the output word computed by the digital filter is offset by 8000H see Understanding Converter Calibration BP UP can be changed after a conversion is started as long as it is stable for 82 clock cycles of the conversion period prior to DRDY falling If one wishes to in termix measurement of bipolar and unipolar signals on various input signals it is best to switch the BP UP pin immediately after DRDY falls and leave BP UP stable until DRDY falls again The digital filter in the CS5509 has a Finite Im pulse Response and is designed to settle to full ac curacy in one conversion time If CONV is left high the CS5509 will perform con tinuous conversions The conversion time will be 1622 clock cycles If conversion is initiated from the standby state there may be up to two XIN clock cycles of uncertainty as to when conversion actual ly begins This is because the internal logic oper ates at one half the external clock rate and the exact phase of the internal clock may be 180 out of phase relative to the XIN clock W
24. hen a new con version is initiated from the standby state it will take up to two XIN clock cycles to begin Actual conversion will use 1624 clock cycles before DRDY goes low to indicate that the serial port has been updated See the Serial Interface Logic sec tion of the data sheet for information on reading data from the serial port In the event the A D conversion command CONV going positive is issued during the conversion state the current conversion will be terminated and a new conversion will be initiated Voltage Reference The CS5509 uses a differential voltage reference input The positive input is VREF and the nega tive input is VREF The voltage between VREF and VREF can range from 1 volt minimum to 3 6 volts maximum The gain slope will track changes 11 in the reference without recalibration accommo dating ratiometric applications Analog Input Range The analog input range is set by the magnitude of the voltage between the VREF and VREF pins In unipolar mode the input range will equal the magnitude of the voltage reference In bipolar mode the input voltage range will equate to plus and minus the magnitude of the voltage reference While the voltage reference can be as great as 3 6 volts its common mode voltage can be any value as long as the reference inputs VREF and VREF stay within the supply voltages VA and GND The differential input voltage can also have any common mode value as long a
25. i T tk kki k e 0 2 Q 42 A ret T ges brp esce EE EE aped 0 32 768 65 535 Codes Figure 4 CS5509 Differential Nonlinearity Plot The VREF and VREF inputs have nearly the AIN s 8 same structure as the AIN and AIN inputs mn _15 pF Therefore the discussion on analog input imped e NE Pee ance applies to the voltage reference inputs as well Volt se e AIN art BE age Digital Filter Characteristics Vos lt 100 WEIT S 7 The digital filter in the CS5509 is the combination E of a comb filter and a low pass filter The comb fil ter has zeros in its transfer function which are opti mally placed to reject line interference frequencies Figure 5 Analog Input Model An equation for the maximum acceptable source resistance is derived 1 max M v 15pF 100mV 15pF CE kr 2XIN 15pF Cp x In This equation assumes that the offset voltage of the buffer is 100 mV which is the worst case The val ue of Ve is the maximum error voltage which is ac ceptable Cor is the combination of any external or stray capacitance For a maximum error voltage Ve of 10 pV in the CS5509 1 ALSB at 16 bits the above equation in dicates that when operating from a 32 768 kHz XIN source resistances up to 110 kQ are accept able in the absence of external capacitance CExT 0 DS125F2 50 and 60 Hz and their multiples when the CS5509 is clocked at 32 768 kHz Figures 6 7 an
26. ill not be executed until the end of the 1800 clock cycle wake up period If CAL and CONV become active high during the 1800 clock cycle wake up time the converter will wait until the wake up period elapses before exe cuting the calibration If the wake up time has elapsed the converter will be in the standby mode waiting for instruction and will enter the calibration cycle immediately if CAL and CONV become ac tive The calibration lasts for 3246 clock cycles Calibration coefficients are then retained in the SRAM static RAM for use during conversion The state of BP UP is ignored during calibration but should remain stable throughout the calibration period to minimize noise When conversions are performed in unipolar mode or in bipolar mode the converter uses the same cal ibration factors to compute the digital output code The only difference is that in bipolar mode the on chip microcontroller offsets the computed output word by a code value of 8000H This means that the bipolar measurement range is not calibrated from full scale positive to full scale negative Instead it is calibrated from the bipolar zero scale point to full scale positive The slope factor is then extended be low bipolar zero to accommodate the negative in DS125F2 CS5509 put signals The converter can be used to convert both unipolar and bipolar signals by changing the BP UP pin Recalibration is not required when switching between unipolar and
27. o End of Conversion Note 15 Leon 1624 foik S DS125F2 5 CS5509 E XIN EI XIN 2 i Z CAL ER E 4 CONV j ANM AAA tscl S A teal gt STATE Standby 7 Calibration Standby Figure 1 Calibration Timing Not to Scale 4 XIN 2 E XIN 2 7 CONV 7 DRDY cpw 7 2 7 rT Ty 7 Z BP UP l j 7 N tbus gt tbuh t t 2 u scn gt lt con Zx gt STATE Standby Conversion 7 Standby Figure 2 Conversion Timing Not to Scale 6 DS125F2 CS5509 5V SWITCHING CHARACTERISTICS 1 25 C VA VD 5V 10 Input Levels Logic 0 OV Logic 1 VD C 50 pF Note 2 Parameter Symbol Min Typ Max Unit Serial Clock fscik 0 2 5 MHz Serial Clock Pulse Width High Ton 200 e ns Pulse Width Low tpi 200 ns Access Time CS Low to data valid Note 16 tesa 60 200 ns Maximum Delay Time Note 17 SCLK falling to new SDATA bit tad 150 310 ns Output Float Delay cs High to output Hi Z Note 18 rai 60 150 ns SCLK falling to Hi Z bus 160 300 ns Notes 16 If CS is activated asynchronously to DRDY CS will not be recognized if it occurs when DRDY is high for 2 clock cycles The propagation delay time may be as great as 2 f cycles plus 200 ns To guarantee proper clocking of SDATA when using asyn
28. pin determines the output rate of the data from the SDATA pin This pin must not be allowed to float DS125F2 19 Control Input Pins CAL Calibrate Pin 3 When taken high the same time that the CONV pin is taken high the converter will perform a self calibration which includes calibration of the offset and gain scale factors in the converter CONV Convert Pin 2 The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is high or it initiates a conversion if it is taken from low to high with the CAL pin low If CONV is held high CAL low the converter will do continuous conversions BP UP Bipolar Unipolar Pin 6 The BP UP pin selects the conversion mode of the converter When high the converter will convert bipolar input signals when low it will convert unipolar input signals Measurement and Reference Inputs AIN AIN Differential Analog Inputs Pins 7 8 Analog differential inputs to the delta sigma modulator VREF VREF Differential Voltage Reference Inputs Pins 9 10 A differential voltage reference on these pins operates as the voltage reference for the converter The voltage between these pins can be any voltage between 1 0 and 3 6 volts Power Supply Connections VA Positive Analog Power Pin 11 Positive analog supply voltage Nominally 5 volts VD Positive Digital Power Pin 13 Positive digital supply voltage Nominally 5 volts or 3 3 volts GND
29. r on reset delay of about 10 ms resets all of the logic in the device The oscillator must then begin oscillating before the device can be considered functional After the power on reset is applied the device enters the wake up period for 1800 clock cycles after clock is present This allows the delta sigma modulator and other circuitry which are op erating with very low currents to reach a stable bias condition prior to entering into either the cali bration or conversion states During the 1800 cycle wake up period the device can accept an input command Execution of this command will not oc cur until the complete wake up period elapses If no command is given the device enters the standby state 10 Calibration After the initial application of power the CS5509 must enter the calibration state prior to performing accurate conversions During calibration the chip executes a two step process The device first per forms an offset calibration and then follows this with a gain calibration The two calibration steps determine the zero reference point and the full scale reference point of the converter s transfer function From these points it calibrates the zero point and a gain slope to be used to properly scale the output digital codes when doing conversions The calibration state is entered whenever the CAL and CONV pins are high at the same time The state of the CAL and CONV pins at power on are recog nized as commands but w
30. s the maximum sig nal magnitude stays within the supply voltages The A D converter is intended to measure dc or low frequency inputs It is designed to yield accurate conversions even with noise exceeding the input voltage range as long as the spectral components of this noise will be filtered out by the digital filter For example with a 3 0 volt reference in unipolar mode the converter will accurately convert an in put dc signal up to 3 0volts with up to 15 over range for 60Hz noise A 3 0volt dc signal could have a 60Hz component which is 0 5volts above the maximum input of 3 0 3 5 volts peak 3 0 volts dc plus 0 5 volts peak noise and still accurately convert the input signal XIN 32 768 kHz This assumes that the signal plus noise amplitude stays within the supply voltages The CS5509 converters output data in binary for mat when converting unipolar signals and in offset binary format when converting bipolar signals Ta ble 1 outlines the output coding for both unipolar and bipolar measurement modes Converter Performance The CS5509 A D converter has excellent linearity performance Calibration minimizes the errors in 12 CS5509 Unipolar Input Output Bipolar Input Voltage Codes Voltage gt VREF 1 5 LSB FEEF gt VREF 1 5 LSB VREF 1 5 LSB FFFF VREF 1 5 LSB FFFE VREF 2 0 5 LSB 8000 0 5 LSB 7FFF 0 5 LSB 0001 VREF 0 5 LSB 0000 lt 0 5 LSB 0000 lt VREF 0 5 LS
31. source 13 The wake up period begins once the oscillator starts or when using an external fy after the power on reset time elapses 14 Calibration can also be initiated by pulsing CAL high while CONV 1 15 Conversion time will be 1622 f if CONV remains high continuously 4 DS125F2 CS5509 3 3V SWITCHING CHARACTERISTICS 1 25 C VA 5V 10 VD 3 3V 5 Input Levels Logic 0 OV Logic 1 VD C 50 pF Note 2 Parameter Symbol Min Typ Max Unit Master Clock Frequency Internal Oscillator XIN 30 0 32 768 53 0 kHz External Clock Jo 30 330 kHz Master Clock Duty Cycle 40 60 96 Rise Times Any Digital Input Note 10 1 0 us Any Digital Output trise 50 ns Fall Time Any Digital Input Note 10 1 0 US Any Digital Output kat 20 ns Start Up Power On Reset Period Note 11 tres 10 ms Oscillator Start up Time XTAL 32 768 kHz Note 12 tosu 500 ms Wake up Period Note13 twp 180fk s Calibration CONV Pulse Width CAL 1 Note 14 Leon 100 ns CONV and CAL High to Start of Calibration ll 2f 200 ms Start of Calibration to End of Calibration teal 3246 fox S Conversion CONV Pulse Width Low 100 ns CONV High to Start of Conversion Lon 2lfak 200 ns Set Up Time BP UP stable prior to DRDY falling tbus Dia s Hold Time BP UP stable after DRDY falls tbuh 0 ns Start of Conversion t
32. tep ts out s 5V DIGITAL CHARACTERISTICS 1 25 C VA VD 5V 10 GND 0 Notes 2 and 8 Parameter Symbol Min Typ Max Unit High Level Input Voltage XIN 3 5 V All Pins Except SIN Vin 2 0 V Low Level Input Voltage XIN 1 5 V All Pins Except SIN Mu 0 8 V High Level Output Voltage Note 9 Vou VD 1 0 V Low Level Output Voiltage lout 1 6 MA Vo i 0 4 V Input Leakage Current lin 1 10 HA 3 State Leakage Current loz 7 10 HA Digital Output Pin Capacitance Cout 9 pF Notes 8 All measurements are performed under static conditions 9 lout 100 uA This guarantees the ability to drive one TTL load Voy 2 4 V at lout 40 pA 3 3V DIGITAL CHARACTERISTICS T 25 C VA 5V 10 VD 3 3V 5 GND 0 Notes 2 and 8 Parameter Symbol Min Typ Max Unit High Level Input Voltage XIN 0 7 VD V All Pins Except XIN Vin 0 6 VD V Low Level Input Voltage XIN 0 3 VD V All Pins Except SINT Mu 0 16 VD V High Level Output Voltage Note 9 Vou VD 0 3 V Low Level Output Voiltage lout 1 6 MA VoL 0 3 V Input Leakage Current lin s 1 10 HA 3 State Leakage Current loz 10 HA Digital Output Pin Capacitance Cout 9 pF Specifications are subject to change without notice DS125F2 3 CS5509 5V SWITCHING CHARACTERISTICS T 25 C VA VD

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