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zilog Z86D990/Z86D991 OTP Z86L99X ROM Low-Voltage Microcontrollers with ADC Manual

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1. PS003807 1002 OSC p x2 Internal clock TMR Ds 1 4 gt PRE1 Ti Le 5 IRQ5 Edge m trigger V Tin jj P5 _ D D Le vy Le trigger A TMR Ds D4 11 p IRQO Figure 32 Triggered Clock Mode Retriggerable Input Mode The Tin Retriggerable Input mode TMR bits Ds and D both set to 1 causes T4 to load and start counting on every occurrence of a High to Low transition on Tiy see Figure 32 Interrupt request IRQs is generated if the programmed time inter val determined by T4 prescaler and counter timer register initial values has elapsed since the last High to Low transition on Tiy In single pass mode the end of count resets the Enable Count bit Subsequent Tin transitions do not cause T to load and start counting until software sets the Enable Count bit again In continuous mode counting continues when T is triggered until software resets the Enable Count bit When enabled each High to Low Tj transition causes T4 to P R EL IM INAR Y 44 PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z ZiLOG reload and restart counting Interrupt request IRQs is generated on every end of count T8 and T16 Timer Operation The T8 timer is a programmable 8 bit counter timer with two 8 bit capture regis ters and two 8 bit load registers The T16 timer is a programmable 16 bi
2. Bit 7 6 5 4 3 2 1 0 Bit Field T8 Capture LO R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Tg Capture R Data Captured Data Low Value W No Effect PRELIMINARY T8 High Load Register TC8H The T8 High Load Register as described in Table 43 is loaded with the counter value necessary to keep the T8 Out signal in the high state for the required time Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Table 43 TC8H Register Group Bank ODh Register 5 Li ZiLOG Bit 7 6 5 4 3 2 1 0 Bit Field T8 Level HI R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Tg Level R W Data Duration that T8_Out remains High High Value T8 Low Load Register TC8L The T8 Low Load Register as described in Table 44 is loaded with the counter value necessary to keep the T8 Out signal in the low state for the required time PS003807 1002 Table 44 TC8L Register Group Bank ODh Register 4 Bit 7 6 5 4 3 2 1 0 Bit Field T8_Level_LO R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Tg Level R W Data Duration that
3. 67 P3M Register Group Bank FOh Register 7 R247 68 P2 Register Group Bank 00h Register 2 R2 68 P2M Register Group Bank FOh Register 6 R246 68 P4 Register Group Bank 00h Register 4 R4 69 P4M Register Group Bank OFh Register 2 69 P5 Register Group Bank 00h Register 5 R5 70 P5M Register Group Bank OFh Register 4 70 P6 Register Group Bank 00h Register 6 R6 71 P R E LIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAR ZiLOG Table 33 P6M Register Group Bank OFh Register 6 71 Table 34 T1 Register Group Bank FOh Register 2 R242 72 Table 35 TMR Register Group Bank FOh Register 1 R241 72 Table 36 PRE1 Register Group Bank FOh Register 3 R243 73 Table 37 CTR1 Register In Transmit Mode Group Bank ODh Register 1 nnna annaa 74 Table 38 CTR1 Register in Demodulation Mode Group Bank ODh Register 1 anaana annaa 75 Table 39 CTR3 Register Group Bank ODh Register 3 76 Table 40 CTRO Register Group Bank ODh Register 0 77 Table 41 HI8 Register Group Bank ODh Register B 78 Table 42 LO8 Register Group Bank ODh Register A 78 Table 43 TC8H Register Group Bank ODh Register
4. Continued 2 TiLoad R W 1 Load T 0 No effect 10 Reserved R 1 Always reads 11 W X No effect T1 Prescale Register PRE1 The T1 prescaler consists of an 8 bit register and a 6 bit down counter The six most significant bits D2 D7 of PRE1 hold the prescaler s count modulo a value from 1 to 64 decimal as shown in Table 36 The prescale register also contains control bits that specify the counting mode and clock source for T1 Table 36 PRE1 Register Group Bank FOh Register 3 R243 Bit 7 6 5 4 3 2 1 0 Clock Count Bit Field Prescaler_Modulo Source Mode R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 765432 Prescaler Modulo R W Data Range 1 to 64 Decimal 1 Clock Source R W 1 T4 Internal 0 T External Tiny on P52 0 Count Mode R W 1 T4 Modulo n 0 T Single Pass Timer Control Registers T8 and T16 Timers One of the unique features of the Z86D99 Z86L99 family is a special timer archi tecture to automate the generation and reception of complex pulses or signals This timer architecture consists of one programmable 8 bit counter timer with two capture registers and two load registers and a programmable 16 bit counter timer with one 16 bit capture register pair and one 16 bit load register pair and their associated control registers These counter timers can work independently
5. T16 MS Byte Capture Register H116 The T16 MS Byte Capture Register as described in Table 46 holds the captured data from the output of the T g counter timer This register holds the most signifi cant byte of the data Table 46 HI16 Register Group Bank ODh Register 9 Bit 7 6 5 4 3 2 1 0 Bit Field T16_Capture_HI R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 T4 Capture HI R Data MS Byte of Captured Data W No Effect T16 LS Byte Capture Register LO16 The T16 LS Byte Capture Register as described in Table 47 holds the captured data from the output of the T4 counter timer This register holds the least signifi cant byte of the data Table 47 LO16 Register Group Bank ODh Register 8 Bit 7 6 5 4 3 2 1 0 Bit Field T16 Capture LO R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 TygCaptureLO R Data LS Byte of Captured Data W No Effect P R E LIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 82 ZiLOG T16 MS Byte Load Register TC16H The T16 MS Byte Load Register as described in Table 48 is loaded with the most significant byte of the Tig counter value Table 48 TC16H Register
6. and an interrupt can be generated if enabled CTRO D1 and T8 continues counting from FFh see Figure 35 P R E LIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC 50 ZiLOG T8 8 Bit Demodulation Mode T8 Enable CTRO D7 FFh 5 TC8 First Edge Present No Enable TC8 Disable TC8 T8 Enable Bit Set No No Edge Present T8 Time Out Set Edge Present Status Bit and Trigger Data Capture Int if Enabled Set Time out Status Bit and Trigger Time Out Int if Enabled Continue Counting Figure 35 Demodulation Mode Flowchart PS003807 1002 P R E LIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 51 ZiLOG T16 Transit Mode In normal or ping pong mode the output of T16 when not enabled is dependent on CTR1 DO If CTR1 DO is a0 T16_OUT is a 1 if CTR1 DO isa 1 T16_OUT is 0 The user can force the output of T16 to either a O or 1 whether it is enabled or not by programming CTR1 D3 D2 to a 10 or 11 When T16 is enabled TC16H 256 TC16L is loaded and T16 OUT is switched to its initial value CTR1 d0 When T16 counts down to 0 T16 OUT is toggled in normal or ping pong mode an interrupt is generated if enabled CTR2 D1 and a status bit CTR2 D5 is set If it is in modulo N mode it is loaded with TC16H 256 TC16L and the counting continues The user can modify t
7. 096 B 0 36 0 46 014 018 c 0 23 0 30 009 012 D 17 78 18 00 700 10 po E 7 40 7 60 291 299 TX yr G 1 27 BSC 050 BSC H 10 00 10 65 394 419 H H h 0 30 0 71 012 028 1 14 L 0 61 1 00 024 039 OPTIONAL Q1 0 97 1 09 038 043 P1 IDENTIFIER 5 E ry iii H Cc gt jj i CONTROLLING DIMENSIONS MM i A1 LEADS ARE COPLANAR WITHIN 004 INCH B Seating plane U DETAIL A Figure 40 28 Pin SOIC PS003807 1002 P R E LIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 94 ZiLOG Design Considerations The Z8 uses a Pierce oscillator with an internal feedback circuit The advantages of this circuit are low cost large output signal low power level in the crystal stabil ity with respect to Voc and temperature and low impedances not disturbed by stray effects One drawback is the requirement for high gain in the amplifier to compensate for feedback path losses Traces connecting crystal capacitors and the Z8 oscillator pins must be as short and wide as possible Short and wide traces reduce para sitic inductance and resistance The components capacitors crystal and resis tors must be placed as close as possible to the oscillator pins of the Z8 The traces from the oscillator pins of the integrated circuit IC and the ground side of the lead capacitors must be guarded from all other traces clock Voc and system ground to reduce cross talk and noise injection
8. 2 1 0 Bit Field Port 2 Data R W R W R W R W R W R W R W R W R W Reset X X X X X X X X R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Port 2 Data R W Data Port 2 Input Output Register Bit 7 6 5 4 3 2 1 0 Bit Field P27M P26M P25M P24M P23M P22M P21M_ P20M R W W W W W W W W W Reset 1 1 1 1 1 1 1 1 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Port 2 Mode R 1 Always reads 11111111 by bit Select W 1 Input W 0 Output P R ELI I N A RY PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 69 ZiLOG A bit set to 1 in the P2M Register configures the corresponding bit in Port 2 as an input while a bit set to 0 configures an output line Port 4 Control and Mode Registers P4 and P4M Port 4 is a general purpose 8 bit bidirectional I O port as shown in Table 28 Each of the eight Port 4 I O lines can be independently programmed as either input or output using the Port 4 Mode Register see Table 29 Table 28 P4 Register Group Bank 00h Register 4 R4 Bit 7 6 5 4 3 2 1 0 Bit Field Port 4 Data R W R W R W R W R W R W R W R W R W Reset X X X X X X X X R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Port 4 Data R W Data Port 4 Input Output Register Table 29 P4M Regist
9. 41 Timer Mode Register Ty Operation 00 00 0048 42 Prescaler 1 Tjy Operation 0 0 00 e eee 42 External Clock Input Mode 00 cece eee eee ee 43 Gated Clock Input Mode 0 000 c eee eee 43 Triggered Clock Mode 2 0 5 ccc i Kaha KET enoweanedaees tox 44 Counter Timer Architecture 0 a 46 Transmit Mode Flowchart 0 48 PS003807 1002 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC ZiLOG Demodulation Mode Flowchart a 50 Test Load Diagram 22 weak wa bs ees oo tes ged sudsdeiaee gos 86 48 Pin S5OP at seaweed eee oo kang ee NG ee eee te ee 91 40 Pin PDIP 1 ee ees 92 28 PIm PDIP 4 e256 Band coded ba Pad l tha dea eth dh ee hoe 92 20 PIN SOIG 2773223 eet eee ee ee eee a ee Be Se eS Na 93 P R E LIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC List of Tables PS003807 1002 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 ZiLOG Z86L99 Z86D99 Feature Comparison eee eee 1 Pin Descriptions paaa daa wea Dao Pans a oes eae
10. 5 79 Table 44 TC8L Register Group Bank ODh Register 4 79 Table 45 CTR2 Register Group Bank ODh Register 2 80 Table 46 HI16 Register Group Bank ODh Register 9 81 Table 47 LO16 Register Group Bank ODh Register 8 81 Table 48 TC16H Register Group Bank ODh Register 7 82 Table 49 TC16L Register Group Bank ODh Register 6 82 Table 50 SMR Register Group Bank OFh Register B 83 Table 51 P2SMR Register Group Bank OFh Register 1 84 Table 52 P5SMR Register Group Bank OFh Register 5 84 Table 53 Absolute Maximum Ratings 0000 c eee eee 85 Table 54 DC Characteristics for the Z86D99X OTP Only 87 Table 55 DC Characteristics for the Z86L99X Mask Only 88 Table 56 Analog to Digital Converter Characteristics 89 Table 57 AC Characteristics c eee eens 90 PS003807 1002 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 1 ZiLOG Architectural Overview The Z86D99 is a low voltage general purpose one time programmable OTP z8 microcontroller with an integrated four channel 8 bit sigma delta analog to digital converter The Z86L99 is the read only memory ROM version of this controller The Z86D99 Z86L99 family is designed to be used in
11. 5 V 0 8 V V Voie High Drive Pins P54 P55 P56 P57 2 3 V 0 4 V V 4mA 5 5 V 0 4 V V 2 3 V 0 8 V V 7 mA 5 5 V 0 8 V V leco Controlled Current Output P43 2 3V 70 120 mA Vout 1 2 V to VDD at room 5 5V 70 120 mA temperature see Figure 17 TE Input Leakage 23V i 1 pA uA Vin 0 V Vdd 5 5V 1 1 uA uA Vin 0 V Vdd lec Supply Current 2 3 V 3 mA at 8 MHz 5 5 V 8 mA at 8 MHz 2 3 V 250 uA at 32 KHz 5 5 V 850 uA at 32 KHz ADC is off loc Standby Current Halt Mode 2 3V 2 mA Vin 0 V Vdd 5 5 V 5 mA at 8 MHz loco Standby Current STOP Mode 2 3 V 8 uA Vin 0 V Vdd ADC is off 55V 25 0 uA WDT Comparators Low Voltage Detection and ADC if applicable are disabled The IC might draw more current if any of the above peripherals is enabled loce Standby Current STOP Mode 5 5 V 15 HA at 30 C ly Standby Current Low Voltage 20 uA Measured at VppzVj y 0 2 V lapc Current with A D Running 2 3 V 500 uA 5 5 V 900 uA Viv Vdd Low Voltage Protection 2 2 V Low voltage protection is also known as brownout Typical is around 1 7 V at room temperature VLB Low Battery Detection 3 0 V Typical is around 2 4 V at room temperature PS003807 1002 P R ELIM I N A R Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC ZiLOG Analog to Digital Converter Characteristics Table 56 lists the analog to digital converter characteristics Table 56 Analog to Digital Converter Character
12. 518 286D 990H Z008SC EM PG Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Micro controllers with ADC Preliminary Product Specification PS003807 1002 ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 3432 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com ZiLOG This publication is subject to replacement by a later edition To determine whether a later edition exists or to request copies of publications contact ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 3432 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com ZiLOG is a registered trademark of ZiLOG Inc in the United States and in other countries All other products and or service names mentioned herein may be trademarks of the companies with which they are associated Document Disclaimer 2002 by ZiLOG Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE Except with the express written approval ZiLOG use of information devices or technology as critical comp
13. Bank OFh Register 4 Bit 7 6 5 4 3 2 1 0 Bit Field P57M P56M P55M P54M P53M P52M P51M P50M R W R W R W R W R W R W R W R W R W Reset 1 1 1 1 1 1 1 1 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7654 10 Port 5 Mode R W 1 Input by bit Select 0 Output 32 P53 P52 R W 1 Input Mode Select Regardless of what is written to this pin P53 and P52 are always in input mode A bit set to a 1 in the P5M Register configures the corresponding bit in Port 5 as an input while a bit set to O configures an output line Note Regardless of how P5M bits 2 and 3 are set P52 and P53 are always in input mode P R ELIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 71 ZiLOG Port 6 Control and Mode Registers P6 and P6M Port 6 is a general purpose 8 bit bidirectional I O port as shown in Table 32 Each of the eight Port 6 I O lines can be independently programmed as either input or output using the Port 6 Mode Register see Table 33 Table 32 P6 Register Group Bank 00h Register 6 R6 Bit 7 6 5 4 3 2 1 0 Bit Field Port 6 Data R W R W R W R W R W R W R W R W R W Reset X X X X X X X X R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Port 6 Data R W Data Port 6 Input Output Register Table 33 P6M Register Group Bank OF
14. Comparator 1 reference P51 CIN1 11 17 20 O Port 5 Bit 1 Capture timer input IRQs P52 CIN2 12 18 21 Input Port 5 Bit 2 Timer 1 timer input IRQg P53 CREF2 13 19 22 Input Port 5 Bit 3 Comparator 2 reference IRQ P54 14 20 23 O Port 5 Bit 4 High drive output P55 15 25 28 O Port 5 Bit 5 High drive output P56 17 27 32 O Port 5 Bit 6 Timer 1 output High drive output P57 16 26 29 O Port 5 Bit 7 High drive output P60 39 47 O Port 6 Bit 0 P61 40 48 O Port 6 Bit 1 P62 1 1 O Port 6 Bit 2 P63 2 2 O Port 6 Bit 3 P64 21 24 O Port 6 Bit 4 P65 22 25 O Port 6 Bit 5 P66 23 26 O Port 6 Bit 6 P67 24 27 O Port 6 Bit 7 XTAL1 10 16 18 Input Crystal Oscillator clock XTAL2 9 15 17 Output Crystal Oscillator clock AVpp 13 14 Analog power supply VDD CORE 13 15 Z8 core power supply AVss 6 7 Analog ground VRet 7 8 Input A D converter lower reference VRet 12 13 Input A D converter upper reference VDD padring 8 14 16 Power supply pad ring Vss 22 32 37 38 Ground Notes A D converter is not available in the 28 pin configuration PS003807 1002 In the 28 pin configuration all three core pad ring and analog powers are tied together P REL I N A RY Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 9 ZiLOG Operational Description Central Processing Unit CPU Description The Z8 architecture is characterized by a flexible I O scheme an efficient register and address space structure
15. Gated Clock PRE1 Tl T1 Triggered Clock Initial Value Initial Value Current Value Register Register Register er Write Write Read l IN 31 Internal Data Bus Figure 18 T4 Counter Timer Block Diagram PS003807 1002 P R E LIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 36 ZiLOG The counter timer prescaler and associated mode registers are mapped into the register file as shown in Figure 19 The software uses the counter timer as a gen eral purpose register which eliminates the need for special instructions DEC Hex identifiers 243 T1 prescaler F3 PRE1 242 Timer counter 1 F2 T1 241 Timer mode F1 TMR Figure 19 Register File Prescaler and Counter Timer The prescaler PRE F3h consists of an 8 bit register and a 6 bit down counter as shown in Figure 18 on page 35 The prescaler register is a read write register Figure 20 shows the prescaler register R243 PRE1 Prescaler 1 Register F3h Read Write D7 Dg Ds D4 D3 Do Dy Do Count mode 1 T4 modulo N 0 T4 single pass Clock source 1 T4 internal 0 T4 external Tiy Prescaler modulo range 1 64 decimal 01h 00h Figure 20 Prescaler 1 Register P R ELIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 37 ZiLOG The six most significant bits D D7 of PRE hold the prescale
16. Guarding the traces is usually accomplished by keeping other traces and system ground trace planes away from the oscillator circuit and by placing a Z8 device Vgg ground ring around the traces components The ground side of the oscillator lead capacitors must be connected to a single trace to the Z8 Vss GND pin It must not be shared with any other system ground trace or components except at the Z8 device Vss pin Not sharing the ground side of the oscillator lead capacitors is to prevent differen tial system ground noise injection into the oscillator PS003807 1002 P R E LIM INAR Y Ordering Information Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAP ZiLOG Part PSI Description Z86D99 OTP Z86D990PZ008SC 40 pin PDIP Z86D990HZ008SC 48 pin SSOP Z86D991PZ008SC 28 pin PDIP Z86D991SZ008SC 28 pin SOIC Z86L99 Mask ROM Z86L990PZ008SC 40 pin PDIP Z86L990HZ008SC 48 pin SSOP Z86L991PZ008SC 28 pin PDIP Z86L991SZ008SC 28 pin SOIC Z86L996PZ008SC 28 pin PDIP Z86L996SZ008SC 28 pin SOIC Z86L997PZ008SC 28 pin PDIP Z86L997SZ008SC 28 pin SOIC Emulator Z86L9900100ZEM Emulator Programmer Adapter Z86D9900100ZDH 48 SSOP Adapter Evaluation Board Z86L9900100ZCO Evaluation Board For fast results contact your local ZiLOG sale offices for assistance in ordering part s Updated information can be found on the ZiLOG website HTTP WWW ZILOG COM Precharacterization Product The product represented by this
17. IRQ The IRQ is read by specifying it as the source register of an instruction and the IRQ is written by specifying it as the destination register Interrupt Initialization After RESET all interrupts are disabled and must be re initialized before vectored or polled interrupt processing can begin The Interrupt Priority Register Interrupt Mask Register and Interrupt Request Register must be initialized in that order to Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 19 ZiLOG start the interrupt process However the IPR does not have to be initialized for polled processing Interrupts must be globally enabled using the El instruction Setting bit 7 of the IMR is not sufficient Subsequent to this El instruction interrupts can be enabled either by IMR manipulation or by use of the El instruction with equivalent effects Additionally interrupts must be disabled by executing a DI instruction before the IPRs or IMRs can be modified Interrupts can then be enabled by executing an El instruction IRQ Software Interrupt Generation IRQ can be used to generate software interrupts by specifying IRQ as the destina tion of any instruction referencing the Z8 Standard Register File These Software Interrupts SWIs are controlled in the same manner as hardware generated requests the IPR and the IMR control the priority and enabling of each SWI level To generate a SWI the request bit in the IRQ is set as fo
18. In the mask part the P43 output is disabled until it is configured as output Power On Reset A POR cold start always resets the Z8 control and status registers to their default conditions A POR sets bit 7 of the Stop Mode Recovery register to O to indicate that a cold start has occurred A timer circuit clocked by a dedicated on board RC oscillator is used for the Power On Reset Timer TPOR function The POR time is specified as Tpop Tpep time allows Vcc and the oscillator circuit to stabilize before instruction exe cution begins The POR delay timer circuit is a one shot timer triggered by one of three condi tions e Power Fail to Power OK status including recovery from Low Voltage Vj y Standby mode e STOP Mode Recovery when bit 5 of the SMR register 1 e WDT time out Under normal operating conditions a stop mode recovery event always triggers the POR delay timer This delay is necessary to allow the external oscillator time to stabilize When using an RC or LC oscillator with a low Q factor the shorter wake up time means the delay can be eliminated Bit 5 of the SMR register selects whether the POR timer delay is used after Stop Mode Recovery or is bypassed If bit 5 1 then the POR timer delay is used If bit 5 0 then the POR timer delay is bypassed In this case the SMR source must be held in the recovery state for 5 TpC to pass the Reset signal internally Watch Dog Timer WDT The WDT is a retriggerab
19. OFh r6 Port 6 Mode P6M page 71 OFh r8 ADC Control ADCCTRL page 61 OFh rll Stop Mode Recovery SMR page 83 FOh rl R241 T1 Timer Mode TMR page 72 FOh r2 R242 T1 Timer Data T1 page 72 FOh r3 R243 T1 Timer Prescale PRE1 page 73 FOh r6 R246 Port 2 Mode P2M page 68 FOh r7 R247 Port Configuration B P3M page 67 FOh r9 R249 Interrupt Priority IPR page 64 FOh r10 R250 Interrupt Request IRQ page 65 FOh r11 R251 Interrupt Mask IMR page 63 FOh r12 R252 Program Control Flags Flags page 57 FOh r13 R253 Register Pointer RP page 58 FOh r15 R255 Stack Pointer SP page 59 Note This register is not reset following Stop Mode Recovery SMR Flags and Pointer Registers In addition to the three standard Z8 flag and pointer registers Program Control Register Pointer and Stack Pointer the Z86D99 Z86L99 family includes a Low Battery Detect Flag register P R EL IM N A R Y PS003807 1002 Program Control Flag Register Flags Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAP ZiLOG The Program Control Flag register see Table 15 reflects the current status of the Z8 as shown in Table 15 The FLAGS register contains six bits of status informa tion that are set or cleared by CPU operations Four of the bits C V Z and S can be tested for use with conditional jump instructions Two flags H and D cannot be tested and are used for BCD arithmetic The two remaining flags in the r
20. Register IMR and Interrupt Priority Register IPR Figure 8 When more than one interrupt is pending priorities are resolved by a priority encoder con trolled by the IPR P R EL IM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z ZiLOG EI Instruction E S Interrupt Request Register IRQ FAH q R PAT Reset Power On Reset POR j Figure 8 Interrupt Block Diagram Interrupt requests are stored in the Interrupt Request Register IRQ which can also be used for polling When an interrupt request is granted the Z8 enters an interrupt machine cycle that globally disables all other interrupts saves the pro gram counter the address of the next instruction to be executed and status flags and finally branches to the vector location for the interrupt granted Itis only at this point that control passes to the interrupt service routine for the specific interrupt All six interrupts can be globally disabled by resetting the master Interrupt Enable bit 7 of the IMR with a Disable Interrupts DI instruction Interrupts are globally enabled by setting the same bit with an Enable Interrupts E1 instruction Descriptions of three interrupt control registers the Interrupt Request Register the Interrupt Mask Register and the Interrupt Priority Register are provided in Register Summary on page 52 The Z8 family supports both vectored and
21. Vcc is at the required level for correct operation of the device When voltage begins to approach the Vp point an on chip low battery detection circuit is tripped which in turn sets a user read able flag The LB register as described in Table 18 is used to set and reset the an interrupt request LB flag Table 18 LB Register Group Bank ODh Register C Bit 7 6 5 4 3 2 1 0 Pad LVD_ LVD_ Bit Field Reserved LVD Flag Enable R W W W W W W R W R W R W Reset 1 1 1 1 1 X 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7654373 Reserved R 1 Always reads 11111 W X No Effect 2 PadLVD R 1 Pad is not regulated when P43 0 Vpaa lt Vmin see page 33 R 0 Pad is regulating the current when P43 0 Vpad Vmin See page 33 W X Reset Pad LB flag 1_ LVD Flag R 1 LB Flag Set if Vpp lt VLv R 0 LB Flag Reset W X No Effect 0 LVD Enable R W 1 Enable LB 0 Disable LB Note When LVD is enabled IRQ5 is set only for low voltage detection Timer 1 will not generate Note The LB flag will be valid after enabling the detection for 20 uS design estimation not tested in production LB does not work at STOP mode It must be disabled during STOP mode in order to reduce current P R EL IM I N A RY PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 61 ZiLOG Analog to Digital Converter Control Registers The Z86D
22. W X Identifies 1 of 16 possible WR Group Pointer Groups each containing 16 Working Registers 5m 3210 Expanded R W X Identifies 1 of 16 possible ERF Register File Banks only Banks 0 D and F are Bank Pointer valid for the Z86D99 Z86L99 family PS003807 1002 P R EL IM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 59 ZiLOG Stack Pointer SP The Z86D99 Z86L99 family of products is configured for an internal stack The size of the stack is limited only by the available memory space or general purpose RAM registers dedicated to this task An 8 bit stack pointer as described in Table 17 is used for all stack operations Table 17 SP Register Group Bank FOh Register F R255 Bit 7 6 5 4 3 2 1 0 Bit Field Stack Pointer R W R W R W R W R W R W R W R W R W Reset X X X X X X X X R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Stack Pointer R W X Points to the data stored on the top of the stack an overflow or underflow can occur if the stack address is incremented or decremented during normal stack operations P R E LIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Low Battery Detect Flag LB Li ZiLOG When the Z86D99 Z86L99 is used in a battery operated application one of the on chip comparators can be used to check that the
23. and IRQ2 The comparators are turned off in STOP mode P51 RQ2 P51 Data Latch CIN1 o P50 P456CON CREF1 Bit5 1 comparator 0 digital Comparator 1 P52 Se RQ0 P52 Data Latch HING P456CON P53 Bit4 1 comparator CREF2 0 digital Comparator 2 Figure 13 Analog Comparators Analog Digital Converter ADC The Z86D99 Z86L99 family incorporates an 8 bit ADC that uses a sigma delta architecture Figure 14 comprised of a modulator and a digital filter The input is selected bit 3 2 from ADCCTRL with an analog mux from 4 P47 P44 pins that can be configured as analog inputs bit 7 4 from ADCCTRL Note Whenever an input pin has an analog value the digital input buffer has to be disabled in order to reduce the current through the device P R ELIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC ZiLOG Analog Mux 1 if YA Modulator P45 Digital LPF Figure 14 ADC Block Diagram The low pass filter transfer function is presented in Figure 15 with the 3 dB fre quency given by the formula where fapc is the sampling frequency of the modulator PS003807 1002 P R E LIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Li ZiLOG Filter response T T T T T T l 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 log10 f Figure 15 Low Pass Filter with 8 MHz Crystal The sampling frequency o
24. gt 4 11 4 5 P50 CREF1 P52 CIN2 T1 Timer Input H 12 4 P56 T1 Timer Output P53 CREF2 13 gt P57 P54 COUT1 GP dJ 14 P55 COUT2 Notes 1 P43 is a controlled current output 2 P54 P55 P56 and P57 are high drive outputs Vpp Vop_core VDD padring AVpp Figure 4 28 Pin SOIC DIP Pin Assignment User Mode Pins Configuration Table 2 describes the pins Table 2 Pin Descriptions Pin 28 40 48 Symbol PDIP SOIC PDIP SSOP Direction Description P20 24 34 40 O Port 2 Bit 0 P21 25 35 41 O Port 2 Bit 1 P22 26 36 44 O Port 2 Bit 2 P23 27 37 45 O Port 2 Bit 3 P24 28 38 46 O Port 2 Bit 4 P25 1 3 3 O Port 2 Bit 5 P26 2 4 4 O Port 2 Bit 6 P27 3 5 5 O Port 2 Bit 7 P40 19 29 34 O Port 4 Bit O T8 Output PS003807 1002 P R ELIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z ZiLOG Table 2 Pin Descriptions Continued Pin 28 40 48 Symbol PDIP SOIC PDIP SSOP Direction Description P41 20 30 35 O Port 4 Bit 1 T16 Output P42 21 31 36 O Port 4 Bit 2 P43 23 33 39 Output T8 T16 Output Controlled current output P44 4 8 9 O Port 4 Bit 4 A D Channel 0 P45 5 9 10 O Port 4 Bit 5 A D Channel 1 P46 6 10 11 O Port 4 Bit 6 A D Channel 2 P47 7 11 12 O Port 4 Bit 7 A D Channel 3 P50 CREF1 18 28 33 O Port 5 Bit O
25. instruction turns off both the internal CPU clock SCLK and internal Timer clock TCLK and reduces the standby current to the minimum The STOP mode is terminated by a POR or SMR source Terminating the STOP mode causes the processor to restart the application program at address 000ch Note When the STOP instruction is executed the microcontroller goes into the STOP mode despite any state change of the state of the port The ports need to be checked immediately before the NOP and STOP instructions to ensure the right input logic before waiting for the change of the ports Stop Mode Recovery Sources Exiting STOP mode using an SMR source is greatly simplified in the Z86D99 Z86L99 family The Z86D99 Z86L99 family of products allows 16 individual I O P R EL tM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 24 ZiLOG pins Ports 2 and 5 to be used as stop mode recovery sources The STOP mode is exited when one of these SMR sources is toggled A transition from either low to high or high to low on any pin of Port 2 or Port 5 if the pin is identified as an SMR source will effect an SMR There are three registers that control STOP mode recovery Stop Mode Recovery e Port 2 Stop Mode Recovery P2SMR e Port 5 Stop Mode Recovery P5SMR The functions and applications of these registers are explained in Stop Mode Recovery Control Registers on page 82 Low Voltage Standby An on chip v
26. of sixteen 8 bit registers known as Working Register WR groups Working Register Group F contains various control and status registers The lower half of Working Register Group O consists of I O port registers RO to R7 the upper eight registers are available for use as general purpose RAM registers Working Register Group 1 through Group E of the standard register file are avail able to be used as general purpose RAM registers The user can use 233 bytes of general purpose RAM registers in the standard Z8 register file Bank 0 PS003807 1002 P R EL IM INAR Y PS003807 1002 Grp Bnk Reg FOh r0 to 15 EOh r0 to 15 DOh r0 to 15 COh r0 to 15 BOh r0 to 15 A0h r0 to 15 90h r0 to 15 80h r0 to 15 70h rO to 15 60h rO to 15 50h r0 to 15 40h r0 to 15 30h ro to 15 20h r0 to 15 10h r0 to 15 r8 to 15 00h ro to 7 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 13 ZiLOG Working Register Group Function Control and Status Registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM registers General purpose RAM reg
27. polled interrupt handling External Interrupt Sources External sources involve interrupt request lines P51 P52 and P53 IRQ IRQp and IRQ respectively IRQo IRQ and IRQs are generated by a transition on the corresponding port pin As shown in Figure 9 when the appropriate port pin P51 P52 or P53 transitions the first flip flop is set The next two flip flops syn chronize the request to the internal clock and delay it by two internal clock peri ods The output of the most recent flip flop IRQp IRQ or IRQ sets the corresponding Interrupt Request Register bit P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Muliple Input and Signal Conditioning Circuitry System Clock Internal Figure 9 External Interrupt Sources IRQ IRQ Block Diagram The programming bits for the Interrupt Edge Select function are located in the IRQ register bits 6 and 7 The configuration of these bits and the resulting interrupt edge is shown in Table 4 Table 4 Interrupt Edge Select for External Interrupts Interrupt Request Register Interrupt Edge Bit 7 Bit 6 IRQ P51 IRQ P52 0 0 Falling Falling 0 1 Falling Rising 1 0 Rising Falling 1 1 Rising Falling Rising Falling p Note Although interrupts are edge triggered minimum interrupt request Low and High times must be observed for proper operation See Electrical Characteristics on page 85 for exact ti
28. rC Low Battery Detect Flag LB ODh rB T16 MS Byte Capture Register HI8 ODh rA T16 LS Byte Capture Register LO8 ODh 19 T8 High Capture Register HI16 ODh r8 T8 Low Capture Register LO16 ODh 17 T16 MS Byte Hold Register TC16H ODh r6 T16 LS Byte Hold Register TC16L ODh r5 T8 High Hold Register TC8H ODh 14 T8 Low Hold Register TC8L ODh 13 T8 T16 Control Register B CTR3 ODh 12 T16 Control Register CTR2 ODh rl T8 T16 Control Register A CTR1 ODh 10 T8 Control Register CTRO P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 54 ZiLOG Table 13 SMR and Port Mode Registers Group 0 Bank F Registers 0 F Grp Bnk Reg Register Function Identifier OFh rF Reserved OFh rE Reserved OFh rD Reserved OFh rC Reserved OFh rB Stop Mode Recovery Register SMR OFh rA Reserved OFh 19 Reserved OFh r8 ADC Control Register ADCCTRL OFh 17 Reserved OFh r6 Port 6 Mode P6M OFh r5 Port 5 Stop Mode Recovery P5SMR OFh r4 Port 5 Mode Register P5M OFh 13 Reserved OFh 12 Port 4 Mode Register P4M OFh rl Port 2 Stop Mode Recovery P2SMR OFh r0 Port Configuration Register P456CON Register Error Conditions PS003807 1002 Registers in the Z8 Standard Register File must be used correctly because certain conditions produce inconsistent results and must be avoided e Registers F5h F 9h are write only register
29. see yeh ka Kag 7 Interrupt Types Sources and Vectors 15 Interrupt Edge Select for External Interrupts 17 Control and Status Register Reset Conditions 20 Clock Status in Operating Modes eee eae 22 Special Port Pin Functions saaana Giaad jiu PERA 27 Active Glitch Filter Specifications Preliminary 32 Current Sink Pad P43 Specifications Preliminary 33 I O Port Registers Group 0 Bank 0 Registers O F 52 Timer Control Registers Group 0 Bank D Registers O F 53 Control and Status Registers Group F Bank 0 Registers QSF u cia sus dhnenetes die ada kiari tee EDNA Ada 53 SMR and Port Mode Registers Group 0 Bank F Registers QF imaga a aida NAGING hd dee es Reteerese 54 Register Description Locations 020000085 55 FLAGS Register Group Bank FOh Register C R252 57 RP Register Group Bank FOh Register D R253 58 SP Register Group Bank FOh Register F R255 59 LB Register Group Bank ODh Register C 60 ADCCTRL Register Group Bank OFh Register 8 61 ADCDATA Register Group Bank 00h Register 7 62 IMR Group Bank OFh Register B 0 0a 63 IPR Group Bank OFh Register 9 0 0a 64 IRQ Group Bank OFh Register A 0a 65 P456CON Register Group Bank OFh Register 0
30. the prescaler is set to divide by three the count sequence is as follows 3 2 1 3 2 1 3 2 PS003807 1002 P R E LIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 39 ZiLOG R243 PRE1 Prescaler 1 Register F3h Read Write Do Count mode 1 T4 modulo N 0 Ty single pass Figure 24 Counting Modes When the PRE register is loaded with 000000 in the six most significant bits the prescaler divides by 64 If that number is 000001 the prescaler does not divide and passes its clock on to T4 Each time the prescaler reaches its end of count a carry is generated which allows the counter timer to decrement by one on the next timer clock input When T4 and PRE both reach their end of count an interrupt request is generated IRQ for T4 Depending on the counting mode selected the counter timer either comes to rest with its value at 00h single pass mode or the initial value is auto matically reloaded and counting continues continuous mode In single pass mode the prescaler still continues to decrement when the timer T has reached its end of count The prescaler always starts from its programmed value upon restarting the counter The counting modes are controlled by bit Dy of PRE with Dg cleared to o for sin gle pass counting mode or set to 1 for continuous mode The counter timer can be stopped at any time by setting the Enable Count bit to 0 and restarted b
31. 003807 1002 P R E LIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 67 ZiLOG Port Configuration Registers P456CON and P3M The port configuration register described in Table 24 switches the comparator inputs from digital to analog and allows Ports 4 5 and or 6 to be switched from push pull active outputs to open drain outputs In ZILOG Test Mode bit 3 of this register is used to enable the Address Strobe Data Strobe Bit 3 is not available in User Mode Table 24 P456CON Register Group Bank OFh Register 0 Bit 7 6 5 4 3 2 1 0 P51 P52 P6 P5 p4 Bit Field Not Used Mode Mode Reserved Output Output Output R W R W R W R W R W R W W W W Reset 0 0 0 0 0 1 1 1t R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76 Not Used R W These bits exist but do not have any function assigned to them they are reserved for future extensions and must not be used 9 Comparator 1 RW 1 Analog P50 P51 as Inputs Mode 0 Digital inputs 4 Comparator2 R W 1 Analog comparator inputs P52 P53 Mode 0 configured as Inputs Digital inputs 3 Reserved 2 Port 6 Output W 1 Push Pull Active Configuration 0 Open Drain Outputs Always reads back 1 1 Port 5 Output W 1 Push Pull Active Configuration 0 Open Drain Outputs Always reads back 1 0 Port 4 Output W 1 Push Pull Active Configuration 0 Open Drain Outpu
32. 635 BSC 0 025 BSC neon H 10 16 10 44 0 400 0 410 L 0 51 1 016 0 020 0 040 CONTROLLING DIMENSIONS MM LEADS ARE COPLANAR WITHIN 004 INCH Detail A Figure 37 48 Pin SSOP PS003807 1002 P R E LIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC 92 ZiLOG 40 21 La A mm PS eam ms Fm vce Tro HA ce om CS MA pes coms IA see cH a ee WE nee SYMBOL MILLIMETER INCH MIN MAX MIN MAX D 2 A1 0 51 1 02 020 040 bog A2 3 18 3 94 125 A55 B 0 38 0 53 015 021 B1 1 02 1 52 040 060 j Si Yu ta TG fa aC AK GA Se NA ET CD YY Oy GU GA Cc 0 23 0 38 009 015 1 20 52 07 52 58 2 050 2 070 be D E 15 24 15 75 600 620 E1 13 59 14 22 535 560 fe 2 54 TYP 100 TYP eA 15 49 16 76 610 660 L 3 05 3 81 120 A50 5 EF Q1 1 40 1 91 055 075 5 1 52 2 29 060 090 ET Jo LIL JH CONTROLLING DIMENSIONS INCH VW PU VU U E T U Al Be ahl AM S B tl B1 Figure 38 40 Pin PDIP oi i YMBOL OPT MILLIMETER INCH
33. 99 Z86L99 family features an 8 bit analog to digital converter with external voltage references The output of the ADC is stored in the ADC Data Register as shown in Table 20 The ADC is configured using the ADC Control Register as shown in Table 19 Table 19 ADCCTRL Register Group Bank OFh Register 8 Bit 7 6 5 4 3 2 1 0 ADC p47 P46 p45 P44 Channel A D Pwr Clock Bit Field A D A D A D A D Selection On Select R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7 P47_A D R W 1 P47 configured as A D Input 0 P47 configured as digital input 6 P46_A D R W 1 P46 configured as A D Input 0 P46 configured as digital input _ 5 P45 A D R W 1 P45 configured as A D Input 0 P45 configured as digital input 4 P44 A D R W 1 P44 configured as A D Input 0 P44 configured as digital input 32 Chamael R W 11 Channel 3 P47 Selection 10 Channel 2 P46 01 Channel 1 P45 00 Channel 0 P44 1 A D_PowerON R W 1 ON 0 OFF 0 ADC Clock Select R W 1 SCLK 2 0 SCLK ADC Control Register ADCCTRL The ADCCTRL register controls the operation of the analog to digital converter Bits 2 and 3 of the ADCCTRL register determine which of the four analog input channels feeds into the ADC at any given time Bits 4 through 7 enable or disable the digital input buffer When configured as an ADC input channel the port ha
34. CTRO D5 and Generate Timeout Int if Enabled Single Pass 0 V Load E Load TC8H E T8 OUT Set T8 OUT Enable T8 Set Time out Status Bit CTRO D5 and Generate Timeout Int if Enabled T8 Timeout Yes Disable T8 Figure 34 Transmit Mode Flowchart PS003807 1002 P R EL IM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 49 ZiLOG Note Do not use the same instructions for stopping the counter timers and setting the status bits Two successive commands are necessary the first command for stopping counter timers and the second command for resetting the status bits because one counter timer clock interval must complete for the initiated event to actually occur T8 Demodulation Mode Program TC8L and TC8H to FFn After T8 is enabled when the first edge rising falling or both depending on CTR1 D5 D4 is detected it starts to count down When a subsequent edge rising falling or both depending on CTR1 D5 D4 is detected during counting the current value of T8 is one s complemented and put into one of the capture registers If T8 is a positive edge data is placed in LO8 If T8 is a negative edge data is placed in H18 One of the edge detect status bits CTR1 D1 DO is set and an interrupt can be generated if enabled CTRO D2 Meanwhile T8 is loaded with TC8H and starts counting again If T8 reaches O the time out status bit CTRO D5 is set
35. ELIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC ZiLOG P24 pH lt gt Pol P63 4 gt q2 gt P60 P25 4 gt qd 3 lt gt P24 as gt i Z86D990 lt gt P23 gt gt P22 AV ss 6 Z86L990 gui VRef gd 7 lt gt P20 P44 ADCO lt gt cI 8 gt P43 Combined T8 T16 Output P4S ADCI 4 gt d 9 Vss P46 ADC2 lt gt di 10 gt PA P47 ADC3 gt 11 lt gt P41 T16 Output lt gt P40 T8 Output lt gt P50 CREF1 VRef _ gt AVDD Vpp coRE Vpp_padring lt lt P56 T1 Timer Output XTAL2 gt P57 XTALI lt P55 COUT2 P51 CIN1 Captive Timer Input 4 gt lt gt P67 P52 CIN2 T1 Timer Input TIN gt gt P66 P53 CREF2 gt gt P65 P54 COUT 4 35 lt gt P64 Notes 1 AVpp must be connected to Vpp core and a 10 uF capacitor for good A D conversion 2 Power must be connected to Vpp padring Current passes to Vpp core through the internal power filter Figure 3 40 Pin DIP Pin Assignment PS003807 1002 P R ELIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z ZiLOG P25 4 gt gi 4 P4 P26 4 gt qd2 4 P23 P27 4 gt A3 4 P22 P44 ADCO 4 4 786D991 gt P21 P45 ADC1 O5 71861991 lt gt P20 P46 ADC2 P6 P43 Combined T8 T16 Output P47 ADC3 GP F7 Vss Vpp 8 gt P42 XTAL2 4 9 GP P41 T16 Output XTALI P 110 lt gt P40 T8 Output P51 CIN1 Capture Timer Input lt
36. Figure 25 is used in conjunction with the Port 5 Mode register P5M to configure P5 for Toyz operation In order for Tour to function P5g must be defined as an output line by setting P5M bit Dg to 0 Output is controlled by one of the counter timers Tg or T4 or the internal clock R241 TMR Timer Mode Register F1h Read Write D7 Dg Do 0 No function 1 Load Ty Tour modes Tout off 00 Reserved 01 T4 out 10 Internal clock out 11 Figure 25 Timer Mode Register Toyr Operation The P5 output is selected by TMR bits D7 and Dg T4 is selected by setting D7 and Dg to 1 and 0 respectively The counter timer Toyz mode is turned off by set ting TMR bits D7 and Dg both to o freeing P3 to be a data output line Tour is initialized to a logic 1 whenever the TMR Load bit D5 is set to 1 At end of count the interrupt request line IRQs clocks a toggle flip flop The out put of this flip flop drives the Tour line P5 In all cases when the counter timer reaches its end of count Toyz toggles to its opposite state see Figure 26 If for example the counter timer is in continuous counting mode Tour has a 50 duty cycle output You can control the duty cycle by varying the initial values after each end of count P R EL IM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAF ZiLOG 2 ib P5 gt Tout IRQ5 T1 end of count Figu
37. Group Bank ODh Register 7 Bit 7 6 5 4 3 2 1 0 Bit Field T16 Data HI R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Tig Data HI R W Data MS Byte of the T g Counter T16 LS Byte Load Register TC16L The T16 LS Byte Load Register as described in Table 49 is loaded with the least significant byte of the T4 counter value Table 49 TC16L Register Group Bank ODh Register 6 Bit 7 6 5 4 3 2 1 0 Bit Field T16_Data_LO R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Tg Data LO R W Data LS Byte of the T g Counter Stop Mode Recovery Control Registers The Z86D99 Z86L99 family of products allows 16 individual I O pins Ports 2 and 5 to be used as a stop mode recovery sources The STOP mode is exited when one of these SMR sources is toggled P R EL IM INAR Y PS003807 1002 Stop Mode Recovery Register Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAF ZiLOG The SMR register serves two functions Bit D7 of the SMR register as shown in Table 50 is the Stop Mode Flag that is set upon entering stop mode A 0 in this bit indicates that the device has been reset by a POR or WDT Reset A POR or WDT Reset is sometimes
38. PR 00h rB General Purpose RAM Register GPR 00h rA General Purpose RAM Register GPR 00h 19 General Purpose RAM Register GPR 00h r8 General Purpose RAM Register GPR 00h r7 Analog Digital Converted Data ADCDATA 00h 16 Port 6 Control Register P6 00h r5 Port 5 Control Register P5 00h r4 Port 4 Control Register P4 00h r3 Reserved 00h r2 Port 2 Control Register P2 00h rl Reserved 00h rO Reserved PS003807 1002 P R E LIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAF ZiLOG Table 11 Control and Status Registers Group F Bank 0 Registers 0 F Grp Bnk Reg Register Function Identifier FOh rF Stack Pointer SP FOh rE General purpose RAM Register GPR FOh rD Register Pointer RP FOh rC Program Control Flag Register Flags FOh rB Interrupt Mask Register IMR FOh rA Interrupt Request Register IRQ FOh r9 Interrupt Priority Register IPR FOh r8 Reserved FOh r7 Port 3 Mode Register P3M FOh 16 Port 2 Mode Register P2M FOh r5 Reserved FOh r4 Reserved FOh 13 T1 Prescale Register PRE1 FOh 12 T1 Data Register T1 FOh rl T1 Mode Register TMR FOh r0 Reserved Table 12 Timer Control Registers Group 0 Bank D Registers 0 F Grp Bnk Reg Register Function Identifier ODh rF Reserved ODh rE Reserved ODh rD Reserved ODh
39. R 1 Counter Timeout Occurred R 0 No Counter Timeout W 1 Reset Flag to 0 W 0 No Effect 43 TgeClock R W 11 SCLK 8 10 SCLK 4 01 SCLK 2 00 SCLK 2 Capture Interrupt R W 1 Enable Data Capture Interrupt Mask Disable Data Capture Interrupt 0 1_ Counter Interrupt R W 1 Enable Time Out Interrupt Mask 0 Disable Time Out Interrupt 1 0 0 P40 Out R W P40 configured as Tg Output P40 configured as I O PS003807 1002 P R EL IM INAR Y PS003807 1002 T8 High Capture Register HI8 The T8 High Capture Register as described in Table 41 holds the captured data from the output of the Tg counter timer This register is typically used to hold the number of counts when the input signal is high or 1 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Table 41 HI8 Register Group Bank ODh Register B Li ZiLOG Bit 7 6 5 4 3 2 1 0 Bit Field T8 Capture HI R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Tg Capture R Data Captured Data High Value W No Effect T8 Low Capture Register LO8 The T8 Low Capture Register as described in Table 42 holds the captured data from the output of the Tg counter timer This register is typically used to hold the number of counts when the input signal is low or 0 Table 42 LO8 Register Group Bank ODh Register A
40. T8 Out remains Low Low Value P R E LIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 80 ZiLOG T16 Control Register CTR2 The T16 Control Register known as CTR2 controls the operation of the 16 bit T46 timer see Table 45 Table 45 CTR2 Register Group Bank 0Dh Register 2 Bit 7 6 5 4 3 2 1 0 Single Capture Counter T16 Mod Time INT INT P41 Bit Field Enable julo n Out T16_Clock Mask Mask Out R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7 Tig Enable R 1 Counter Enabled R 0 Counter Disabled W 1 Enable Counter W 0 Stop Counter 6 Single R W In Transmit Mode Modulo n 1 Single Pass 0 Modulo n In Demodulation Mode Tag Does Not Recognize Edge T4g Recognizes Edge 1 0 1 Counter Timeout Occurred 0 1 5 Time Out R R No Counter Timeout W Reset Flag to 0 W 0 No Effect _ 43 TigClock R W 11 SCLK 8 10 SCLK 4 01 SCLK 2 00 SCLK 2 Capture Interrupt R W 1 Enable Data Capture Interrupt Mask Disable Data Capture Interrupt 0 1_ Counter Interrupt R W 1 Enable Time Out Interrupt Mask 0 Disable Time Out Interrupt 1 0 0 P41 Out R W P41 configured as T g Output P41 configured as I O PS003807 1002 P R EL IM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 81 ZiLOG
41. T8 Timer Counter CTRO HI8 LO8 TC8H and TC8L e T16 Timer Counter CTR2 H116 LO16 TC16H and TC16L e T8 T16 Control Registers CTR1and CTR3 In addition the four port registers are considered to be peripheral registers The following are port control registers e Port Configuration Registers P456CON and P3M e Port 2 Control and Mode Registers P2 and P2M e Port 4 Control and Mode Registers P4 and P4M e Port 5 Control and Mode Registers P5 and P5M e Port 6 Control and Mode Registers P6 and P6M The functions and applications of the control and peripheral registers are explained in Control and Status Registers on page 52 Memory ROM OTP and RAM There are four basic address spaces available to support a wide range of configu rations e Program memory on chip e Standard register file e Expanded register file e Executable RAM The Z8 standard register file totals up to 256 consecutive bytes organized as 16 groups of 16 eight bit registers These registers consist of I O port registers PS003807 1002 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 11 ZiLOG general purpose RAM registers and control and status registers Every RAM reg ister acts like an accumulator speeding instruction execution and maximizing cod ing efficiency Working register groups allow fast context switching The standard register file of the Z8 known as Bank 0 has been expande
42. The Timer Mode register bits Ds and D can then be used to select the Tin operation For T4 to start counting as a result of a Tiy input the Enable Count bit D3 in TMR must be set to 1 When using Tin as an external clock or a gate input the initial values must be loaded into the down counters by setting the Load bit D in TMR to 1 before counting begins Initial values are automatically loaded in Trigger and Retrigger modes so software loading is unnecessary Configure P5 as an input line by setting P5M bit D to 1 P R ELIM INAR Y TIN clock Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC ZiLOG Each High to Low transition on Tin generates interrupt request IRQp regardless of the selected Tj mode or the enabled disabled state of T4 IRQg must therefore be masked or enabled according to the needs of the application External Clock Input Mode The Tin External Clock Input mode TMR bits Ds and D both set to 0 supports the counting of external events where an event is considered to be a High to Low transition on Tin see Figure 30 occurrence single pass mode or on every nth occurrence continuous mode of that event TMR Dz D4 00 wel P5 pl D D PRE1 Ti IRQS t 4 A Internal clock p gt RQO Figure 30 External Clock Input Mode Gated Internal Clock Mode The Tj Gated Internal Clock mode TMR bits Ds and D set to 0
43. Voltage Microcontrollers with ADC Z 58 ZiLOG Table 15 FLAGS Register Group Bank FOh Register C R252 Continued 3__ Decimal Adjust R W 1 Used for BCD arithmetic after a Flag D 0 subtraction the flag is set to 1 following an addition it is cleared to 0 2 Half Carry R W 1 Set to 1 whenever an addition Flag H 0 generates a carry out of bit position 3 overflow of an accumulator or subtraction generates a borrow into bit 3 User definable 1 User Flag F2 R W 0 User Flag F1 R W User definable O O Register Pointer RP Z8 instructions can access registers directly or indirectly using either a 4 bit or 8 bit address field The upper nibble of the Register Pointer as described in Table 16 contains the base address of the active Working Register GROUP The lower nibble contains the base address of the Expanded Register File BANK When using 4 bit addressing the 4 bit address of the working register r0 to rF is combined with the upper nibble of the Register Pointer identifying the WR GROUP thus forming the 8 bit actual address Table 16 RP Register Group Bank FOh Register D R253 Bit 7 6 5 4 3 2 1 0 Bit Field Working Register Group Expanded Register File Bank R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7654 Working Register R
44. Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 85 ZiLOG Electrical Characteristics This section covers the absolute maximum ratings standard test conditions DC characteristics and AC characteristics Absolute Maximum Ratings Table 53 lists the absolute maximum ratings Table 53 Absolute Maximum Ratings Symbol Description Min Max Units VMAX Supply Voltage 0 3 7 0 V TsTG Storage Temp 65 150 C Ta Oper Ambient Temp t C VRAM Minimum RAM Voltage 1 0 V Note Voltage on all pins with respect to GND See Ordering Information on page 95 Estimated value not tested Stresses greater than those listed in the preceding table can cause permanent damage to the device This rating is a stress rating only Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied Exposure to absolute maximum rating condi tions for an extended period can affect device reliability Standard Test Conditions The characteristics listed below apply for standard test conditions as noted All voltages are referenced to GND Positive current flows into the referenced pin see Figure 36 PS003807 1002 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 86 ZiLOG From Output O Under Test Figure 36 Test Load Diagram DC Characteristics Ta
45. Z86L99X ROM Low Voltage Microcontrollers with ADC Z 76 ZiLOG Table 39 CTR3 Register Group Bank ODh Register 3 Bit 7 6 5 4 3 2 1 0 T16_ T8 Sync Bit Field Enable Enable Mode Reserved R W R W R W R W R W R W R W R W R W Reset 0 0 0 x X X X X R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7 T46 Enable R 1 Counter Enabled R 0 Counter Disabled W 1 Enable Counter W 0 Stop Counter 6 Tg Enable R 1 Counter Enabled R 0 Counter Disabled W 1 Enable Counter W 0 Stop Counter _ 5 Sync Mode R W 1 Enable Sync Mode 0 Diable Sync Mode 43210 Reserved R 1 Always reads 11111 W X No Effect P R ELIM I N ARY Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 77 ZiLOG T8 Control Register CTRO As shown in Table 40 the T8 Control Register Known as CTRO controls the oper ation of the 8 bit Tg timer Table 40 CTRO Register Group Bank ODh Register 0 Bit 7 6 5 4 3 2 1 0 Single Capture Counter T8 Mod Time INT INT P40_ Bit Field Enable julo n Out T8 Clock Mask Mask Out R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7 Tg Enable R 1 Counter Enabled R 0 Counter Disabled WwW 1 Enable Counter W 0 Stop Counter 6 Single R W 1 Single Pass Modulo n 0 Modulo n 5 Time Out
46. a oe ee ee MIN MAX MIN MAX A1 0 38 1 02 015 040 A2 3 18 4 19 125 165 B 0 38 0 53 015 021 D E1 BI 01 1 40 1 65 1055 065 02 1 14 1 40 1045 1055 c 0 23 0 38 009 015 D 01 36 58 37 34 1 440 1 470 1 14 02 35 31 35 94 1 390 1 415 D E 15 24 15 75 500 620 A 01 13 59 14 10 535 555 02 12 83 13 08 505 515 gt A 2 54 TYP 100 BSC ai eA 1549 16 76 610 660 i Ag L 3 05 3 81 120 150 A2 al 01 140 1 91 1055 075 02 1 40 1 78 055 070 L H C 01 1 52 2 29 060 090 to TT Al i 02 102 1 52 040 060 s jao Ja Jl B1 eA CONTROLLING DIMENSIONS INCH OPTION TABLE OPTION PACKAGE 01 STANDARD 02 IDF Note ZiLOG supplies both options for production Component layout PCB design should cover bigger option 01 Figure 39 28 Pin PDIP PS003807 1002 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC 93 ZiLOG ka D j C MILLIMETER INCH 28 15 SYMBOL MIN MAX MIN MAX H H A 2 40 2 64 094 104 Al 0 10 0 30 004 012 A2 2 24 2 44 088
47. a wide variety of embedded control applications including battery chargers home appliances infrared IR remote controls security systems and wireless keyboards It has three counter timers a general purpose 8 bit counter timer with a 6 bit pres caler and an 8 bit 16 bit counter timer pair that can be used individually for gen eral purpose timing or as a pair to automate the generation and reception of complex pulses or signals Unique features of the Z86D99 Z86L99 family of prod ucts include 489 bytes of general purpose random access memory RAM 256 bytes of which are mapped into the program memory space and can be used to store data variables or as executable RAM a low battery detection flag anda controlled current output pin which is a regulated current source that sinks a pre defined current Icco Table 1 highlights the basic product features of these microcontrollers Table 1 Z86L99 Z86D99 Feature Comparison Memory Operating Watch Dog Pins 1 0 Bytes Voltage V ADC Timers Timer Z86D990 40 48 32 32K OTP 3 0 5 5 4 channel 3 Yes Z86D991 28 24 32K OTP 3 0 5 5 3 Yes Z86L990 40 48 32 16K ROM 2 3 5 5 4 channel 3 Yes Z86L991 28 24 16K ROM 2 3 5 5 3 Yes Z86L996 28 24 4K ROM 2 3 5 5 3 Yes Z86L997 28 24 8K ROM 2 3 5 5 3 Yes The Z8 microcontroller core offers more flexibility and performance than accumu lator based microcontrollers All 256 general purpose registers including dedi cated input out
48. able 5 Control and Status Register Reset Conditions VAF ZiLOG Address Reset Value Register Function Grp Bnk Register Symbol RW 7 6 5 4 3 2 1 0 Register Pointer FOh r13 R253 RP R W 0 10 O 0 JO 0 0 0 Stack Pointer FOh r15 R255 SP R W X X X X X X X X Program Control Flags FOh r12 R252 Flags RAW X X X X X X X X Low Battery Detect ODh r12 LB RAW 1 11 11 11 11 X 0 0 ADC Control OFh r8 ADCCTRL RW 0O 0 0 0 0 0 O O ADC Data 00h r7 R7 ADCDATA R 0 0 00 0 0 0 O O Interrupt Mask FOh r11 R251 IMR R W 0 10 O 0 JO O 0 0 Interrupt Priority FOh r9 R249 IPR W 0 0 10 0 0 0 O O Interrupt Request FOh r10 R250 IRQ R W 0 10 0 O 0 O0 O O Port Configuration A OFh r0 P456CON R W 0O 0 0 0 0 1 1 11 Port Configuration B FOh r7 R247 P3M W 1 1 1 1 1 1 01 1 Port 2 Data 00h r2 R2 P2 RW X X X X X X X X Port 2 Mode FOh r6 R246 P2M W 1 1 1 1 1 1 1 1 Port 4 Data 00h r4 R4 P4 RW X X X X X X X X Port 4 Mode OFh r2 P4M RW 1 1 1 14 1141 1 1 Port 5 Data 00h r5 R5 P5 RW X X X X X X X X Port 5 Mode OFh r4 P5M RW 1 1 1 1 1 1 01 1 Port 6 Data 00h r6 R6 P6 RW X X X X X X X X Port 6 Mode OFh r6 P6M RW 1 1 1 1 1 1 01 T1 Timer Data FOh r2 R242 T1 R W 0 10 O 0 JO O0 0 0 T1 Timer Mode FOh rl R241 TMR R W 0 0 O O 0 0 1 11 T1 Timer Pr
49. able 8 Active Glitch Filter Specifications Preliminary Parameter Max Min Condition Diff stage gain 75 dB Diff stage bandwidth 15 MHz Rise time 255 ns 50 mV pulse Fall time 214 ns 50 mV pulse Rgson 100 On the wafer level all three power buses are available Depending on the number of pins of the package one or more power buses are connected together The active glitch power filter effectively increases the noise immunity for battery operated designs where the controller is driving high current loads for example IR LED P R ELIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 33 ZiLOG Controlled Current Output P43 is an open drain output only pin on the Z86D990 D991 but it can be config ured as output or Tristate High Impedance on the Z86L990 L991 To function properly Bit 3 of P4M must be set to zero to configure the pin as an open drain output For the Z86L990 L991 after reset P43 defaults to Tristate High Impedance while the Z86D990 D991 P43 is always configured as output The data at Port 4 must be initialized as it is undefined at power on reset The current output is a controlled current source that is controlled by the output of the value of P43 see Table 9 P43 cannot be configured as input and if P43 is read P43 always returns the state of the output value 1 for no sink and 0 for sink P43 uses internal current reference and will dra
50. ain somewhere between a logic 1 and 0 General Port I O The eight I O lines of each port except P43 P52 and P53 can be configured under software control to be either input or output independently Bits pro grammed as outputs can be globally programmed as either push pull or open drain See Figure 12 PS003807 1002 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAP ZiLOG OTP Mask Vec T Pate T VO i o Pad Note Pull up resistance is ae about 200 KQ at 2 3 V and In 75 KQ at 5 0 V with 50 tolerance Figure 12 General Input Output Pin Read Write Operations The ports are accessed as general purpose registers Port registers are written by specifying the port register as an instruction s destination register Writing to a port causes data to be stored in the output register of the port and reflected externally on any bit configured as an output Ports are read by specifying the port register as the source register of an instruc tion When an output bit is read data on the external pin is returned Under normal loading conditions returning data on the external pin is equivalent to reading the output register However if a bit is defined as an open drain output the data returned is the value forced on the output pin by the external system This value might not be the same as the data in the output regis
51. an be used as data RAM or executable RAM e 32 Kbytes of OTP memory Z86D99X e 16 Kbytes of ROM Z86L99X Counter Timers e Special architecture to automate generation and reception of complex pulses or signals Programmable 8 bit counter timer T8 with two 8 bit capture registers and two 8 bit load registers Programmable 16 bit counter timer T16 with one 16 bit capture register pair and one 16 bit load register pair Programmable input glitch filter for pulse reception e One general purpose 8 bit counter timer T1 with 6 bit prescaler Input Output and Interrupts PS003807 1002 e Thirty two I Os twenty nine of which are bidirectional I Os with programmable resistive pull up transistors 24 I Os are available in the 28 pin configuration e Sixteen I Os are selectable as stop mode recovery sources e Six interrupt vectors with nine interrupt sources Three external sources Two comparator interrupts P R EL tM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 3 ZiLOG Three timer interrupts One low battery detector flag Operating Characteristics e 8 MHZz operation e 3 0 V to 5 5 V operating voltage Z86D990 Z86D991 e 2 3 V to 5 5 V operating voltage Z86L990 Z86L991 e Low power consumption with three standby modes Stop Halt Low Voltage Standby e Low battery detection flag e Low voltage protection circuit also known as Vp or voltage bro
52. and 1 respec tively measures the duration of an external event In this mode the T prescaler is driven by the internal timer clock gated by a High level on Tin see Figure 31 T4 counts while Tin is High and stops counting when Tin is Low Interrupt request IRQg is generated on the High to Low transition of Tiy signaling the end of the gate input Interrupt request IRQ is generated if T reaches its end of count O SC py 2 pe Internal clock 4 yy PRET T1 p RQ5 TIN gate P59 D D pm IRQ0 PS003807 1002 Figure 31 Gated Clock Input Mode P R EL tM INAR Y 43 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC ZiLOG Triggered Input Mode The Tin Triggered Input mode TMR bits Ds and D set to 1 and 0 respectively causes T to start counting as the result of an external event see Figure 32 T4 is then loaded and clocked by the internal timer clock following the first High to Low transition on the Tin input Subsequent Tin transitions do not affect T4 In the sin gle pass mode the Enable bit is reset whenever T reaches its end of count Fur ther Tin transitions have no effect on T4 until software sets the Enable Count bit again In continuous mode when T4 is triggered counting continues until software resets the Enable Count bit Interrupt request IRQs is generated when T4 reaches its end of count
53. and a number of ancillary features for cost sensitive high volume embedded control applications ROM based products are geared for high volume production where the software is stable and one time programma ble equivalents for prototyping as well as volume production where time to market or code flexibility is critical Architecture Type The Z8 register oriented architecture centers around an internal register file com posed of 256 consecutive bytes known as the standard register file The standard register file consists of 4 I O port registers R2 R4 R5 and R6 12 control and status registers 233 general purpose registers and 7 registers reserved for future expansion In addition to the standard register file the Z86D99 Z86L99 family uses 21 control and status registers located in the Z8 expanded register file Any general purpose register can be used as an accumulator and address pointer or an index data or stack register All active registers can be referenced or modified by any instruction that accesses an 8 bit register without the requirement for special instructions Registers accessed as 16 bits are treated as even odd register pairs In this case the data s most significant byte MSB is stored in the even numbered register while the least significant byte LSB goes into the next higher odd numbered register The Z8 CPU has an instruction set designed for the large register file The instruc tion set provides a full co
54. ble 54 lists the DC characteristics for the Z86D99X OTP only Table 55 lists the DC characteristics for the Z86L99X mask only P R E LIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Table 54 DC Characteristics for the Z86D99X OTP Only ZiLOG Symbol Parameter VDD Min Max Units Comments Vop Power Supply Voltage 3 5 5 Vou Clock Input High Voltage 3 0 V 0 8Vdd Vdd 0 3 V Driven by Ext clock 5 5 V 0 8Vdd Vdd 0 3 V generator VeL Clock Input Low Voltage 3 0 V Vss 0 3 0 2Vdd Driven by Ext clock 5 5 V Vss 0 3 0 2Vdd generator Vin Input High Voltage 3 0 V 0 7Vdd Vdd 0 3 V 5 5 V 0 7Vdd Vdd 0 3 V VIL Input Low Voltage 3 0 V Vss 0 3 0 2Vdd V 5 5 V Vss 0 3 0 2Vdd V Vout Output High Voltage 3 0V Vpp 0 8 V 1 2 mA Regular I O 5 5V Vpp 0 8 V VoH2 High Drive Pins P54 P55 P56 3 0 V Vpp 0 8 V 5 0 mA P57 5 5 V Vpp 0 8 V Vout Regular I O 3 0 V 0 4 V 2 mA Output low voltage 5 5 V 0 8 V 4 0 mA VoL2 High Drive Pins P54 P55 P56 3 0 V 0 4 V 4mA P57 5 5 V 0 8 V 7 0 mA loco Controlled Current Output P43 3 0V 70 120 mA Vout 1 2 V to VDD 5 5 V 70 120 mA see Figure 17 lit Input Leakage 3 0 V 1 1 uA uA Vin 0 V Vdd 55V 1 1 uA uA Vin 0 V Vdd lcc Supply Current 3 0 V 10 mA at 8 MHz 5 5 V 15 mA at 8 MHz 3 0 V 250 uA at 32 KHz 5 5 V 850 uA at 32 KHz ADC is off lect Standby Current Halt Mode 3 0 V 3 mA Vin 0 V Vdd 5 5 V 5
55. ble sources The six interrupts are assigned as fol lows e Three edge triggered external interrupts P51 P52 and P53 two of which are shared with the two analog comparators e One internal interrupt assigned to the T8 Timer e One internal interrupt assigned to the T16 Timer e One internal interrupt shared between the Low Battery Detect flag and the T1 Timer Table 3 presents the interrupt types the interrupt sources and the location of the specific interrupt vectors Table 3 Interrupt Types Sources and Vectors Vector Name Source Location Comments IRQo P52 F R Comparator 2 0 1 External interrupt P52 is triggered by either rising or falling edge internal interrupt generated by Comparator 2 is mapped into IRQ IRQ P53 F 2 3 External interrupt P53 is triggered by a falling edge IRQ P51 R F Comparator 1 4 5 External interrupt P51 is triggered by either a rising or falling edge internal interrupt generated by Comparator 1 is mapped into IRQ IRQ3 T16 Timer 6 7 Internal interrupt IRQ T8 Timer 8 9 Internal interrupt IRQs LVD T1 Timer 10 11 Internal interrupt LVD flag is multiplexed with T1 Timer End of Count interrupt Notes F Falling edge triggered R Rising edge triggered When LVD is enabled IRQS is triggered only by low voltage detection Timer 1 does not generate an interrupt These interrupts can be masked and their priorities set by using the Interrupt Mask
56. cece eee eee 52 Register Summary 2 za pha BT ABRA ES betes kB DIANA YRS Senses 52 Register Error Conditions 22 icc0 scnsei aes ne eo eewetder bene ease 54 Registers Grouped by Function 0 000 e eee eee eee 55 Electrical Characteristics 2a Nah Saka ee elses eae Gee NULAYAA ANA 85 Absolute Maximum Ratings 0 000 eee eee eee 85 Standard Test Conditions isos aah ect aebebee ba od ieee ba wet nneass 85 DC Characteristics 2 5 2 KANE BAG RA ned wet hewk Lae hee ee bee KGG 86 Analog to Digital Converter Characteristics 89 AG Characteristics a 222444205 4 e 35 Sa DB DAA Pirika dii LBG BID LABAG 90 PACKAGING ei esisel a enw envied HE KALA pA KENNEDY GA Na TAB GA KA pA NE 91 Design Considerations 0 000 c ee eee 94 Ordering Information 2 2g Bass Km ee pb hon RSS baw hohe Ss Bet eee ede kse 95 Precharacterizalion Product a a nanakawan PALAKA ed heeds wate etna ea e 95 PS003807 1002 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC List of Figures PS003807 1002 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Fig
57. ctive Glitch Filter The Z86D99 Z86L99 family incorporates an active power glitch filter that can be used to improve the quality of the power supply when the device is operating in noisy environments The chips use three separate power buses pad ring power bus all the output drivers plus the crystal RC oscillator called VDD padring core power bus all digital circuitry called Vp core analog power bus all analog circuitry called AVpp Depending on the pin availability one or more of the power buses are connected together The active power filter can be used in the packages that have the Vpp separate Figure 16 shows the internal schematic P R E LIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAP ZiLOG To Power Supply z 2 O External Cap E Z a a a gt L gt Chip Switch To Pad Ring E To Core ae Comp Figure 16 Active Glitch Power Filter When the internal power glitch filter is not used both Vpp padring ANA VDD CORE must be connected together externally to the power supply When the internal circuitry is used the Vpp paaring has to be connected to the power supply and the Vpp core has to be connected to an external energy stor age capacitor 1 10 uF range The core is connected only to this capacitor during power supply glitches Table 8 describes the active glitch filter specifications T
58. cy system clock divided by 1 option f ADC 4 MHz The step response 238 uS AC Characteristics PS003807 1002 Table 57 lists the AC characteristics Table 57 AC Characteristics No Symbol Parameter VDD Min Max Units 1 TpC Input Clock Period 23V 120 DC ns 55V 120 DC 2 TrCe TIC Clock Input Rise and Fall Times 2 3 V 25 ns 5 5 V 25 ns 3 TwC Input Clock Width 23V 50 ns 55V 50 ns 4 TwTinL Timer Input Low Width 23V 2TPC 55V 2TPC ns 5 TwTinH Timer Input High Width 23V 2 TpC 55V 2 TpC 6 TpTiin Timer 1 Input Period 23V 8 TpC 55V 8 TpC 7 TrTin TfTin Timer Input Rise and Fall Time 2 3 V 100 ns 5 5 V 100 ns 8 TwiIL Interrupt Request Low Time 23V 100 ns 5 5V 70 ns 9 TwIH Interrupt Request Input High Time 2 3V 5 TpC 55V 5 TpC 10 Twsm Stop Mode Recovery Width Spec 2 3V 12 ns 55V 12 ns 12 Twat Watch Dog Timer Time Out 23V 25 ms 55V 10 ms P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 91 ZiLOG Packaging Figure 37 through Figure 40 show the available packages 48 25 se MILLIMETER INCH AAAAARARAAAAARRRRARARARA SYMBOL an wx un WA A 2 41 2 79 0 095 0 110 Ai 0 23 0 38 0 009 0 015 n H A2 2 18 2 39 0 086 0 094 b 0 20 0 34 0 008 0 0135 O c 0 13 0 25 0 005 0 010 D 15 75 16 00 0 620 0 630 i il i i i i i i EREHE il il E 7 39 7 59 0 291 0 299 1 da 0
59. d to form 16 expanded register file ERF banks The expanded register file allows for addi tional system control registers and for the mapping of additional peripheral devices into the register area Each ERF bank can potentially consist of up to 256 registers the same amount as in the standard register file that can then be divided into 16 working register groups Currently only Group 0 of ERF Banks F and D oFh and oph has been implemented In addition to the standard program memory and the RAM register files the Z86D99 Z86L99 family also has 256 bytes of executable RAM that has been mapped into the upper 256 bytes of the program memory address space FF00h FFFFh Data can be written to the executable RAM by using the LDC instruction Program Memory Structure The first 12 bytes of program memory are reserved for the interrupt vectors These locations contain six 16 bit vectors that correspond to the six available interrupts IRQp through IRQs Address 12 ocn up to 32 767 7FFFh consists of on chip one time programmable memory The Z86L99X only has the 4K 8K 16K ROM size After any reset operation power on reset watch dog timer time out and stop mode recovery program execution resumes with the initial instruction fetch from location 000ch After a reset the first routine executed must be one that initializes the control registers to the required system configuration A unique feature of the Z86D99 Z86L99 family is the presenc
60. dent of the processor instruction sequence which relieves software from time critical opera tions such as interval timing and event counting The T counter timer operates in either single pass or continuous mode At the end of count counting either stops or the initial value is reloaded and counting continues Under software control new values are loaded immediately or when the end of count is reached Software also controls the counting mode how the counter timer is started or stopped and the counter timer s use of I O lines Both the counter and prescaler registers can be altered while the counter timer is run ning P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 35 ZiLOG Counter timer 1 is driven by a timer clock generated by dividing the internal clock by four The divide by four stage the 6 bit prescaler and the 8 bit counter timer form a synchronous 16 bit divide chain Counter timer T4 can also be driven by an external input Tj using Port P52 Port P5 can serve as a timer output Tour through which T or the internal clock can be output The timer output toggles at the end of count Figure 18 is a block diagram of the counter timer OSC 2 Internal Clock 2 elouT P56 External Clock Clock Logic 6 Bit 8 Bit IRQS he 44 Down Counter Down Counter Internal Clock
61. document is newly introduced and ZiLOG has not completed the full characterization of the product The document states what ZiLOG knows about this product at this time but additional features or nonconfor mance with some aspects of the document might be found either by ZiLOG or its customers in the course of further application and characterization work In addi tion ZiLOG cautions that delivery might be uncertain at times due to start up yield issues ZiLOG Inc 532 Race Street San Jose CA 95126 3432 Telephone 408 558 8500 FAX 408 558 8300 Internet HTTP WWww ZILOG com PS003807 1002 P REL M N A R Y
62. e IRQ as described in Table 23 is a read write register that stores the interrupt requests for both vectored and polled interrupts When an interrupt request is made by any of the six interrupts the corresponding bit in the IRQ is set to 1 Table 23 IRQ Group Bank OFh Register A PS003807 1002 Bit 7 6 5 4 3 2 1 0 Set Set Set Set Set Set Bit Field Interrupt Edge IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQO R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76 Interrupt Edge R W 11 P51 Rise FallingP52 Rise Falling Trigger 10 P51 Rising P52 Falling 01 P51 FallingP52 Rising 00 P51 FallingP52 Falling _5 Set IRQs R 1 IRQs Inactive R 0 IRQs Active W 1 Set IRQs W 0 Reset IRQs _ 4 Set IRQ R 1 IRQ Inactive R 0 IRQ Active W 1 Set IRQ W 0 Reset IRQ 3 Set IRQ3 R 1 IRQ3 Inactive R 0 IRQ3 Active W 1 Set IRQ3 W 0 Reset IRQ3 2 SetIRQ R 1 IRQ Inactive R 0 IRQ Active W 1 Set IRQ W 0 Reset IRQ 1 SetIRQ R 1 IRQ Inactive R 0 IRQ Active W 1 Set IRQ W 0 Reset IRQ 0 SetIRQo R 1 IRQg Inactive R 0 IRQ Active W 1 Set IRQ W 0 Reset IRQo P R E LIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 66 ZiLOG Whenever a power on reset is executed the IRQ is reset to 00h and disabled Before the IRQ accepts requests it must be enabled by executing an enable in
63. e of 256 bytes of on chip executable RAM This random access memory is in addition to the standard Z8 register file memory available on all Z8 microcontrollers As illustrated in Figure 5 the executable RAM is mapped into the upper 256 bytes of the 64K pro gram memory address space FFO0h FFFFh Data can be written to the execut able RAM by using the LDC instruction Memory locations between 8000h and FEFFh have not been implemented on the Z86D99X microcontrollers The Z86D99 Z86L99 family does not have the capability of accessing external memory PS003807 1002 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC 4 ZiLOG Location Hex FFFF 256 bytes Executable RAM FFOO Not Implemented 3FFF 7FFF ROM OTP PROGRAM MEMORY 000C Location of the first byte of the initial instruction executed after RESET 000B IRQs lower byte 000A IRQs upper byte 0009 IRQ lower byte 0008 IRQ upper byte 0007 IRQ lower byte 0006 IRQ3 upper byte 0005 IRQ lower byte 0004 IRQ upper byte 0003 IRQ lower byte 0002 IRQ upper byte 0001 IRQg lower byte 0000 IRQ upper byte Figure 5 Program Memory Map Z8 Standard Register File Bank 0 Bank 0 of the Z8 expanded register file architecture is known as the standard reg ister file of the Z8 As shown in Figure 6 the Z8 standard register file consists of 16 groups
64. e the counters timers are running can cause intermittent counter timer function Disable the counters timers then reset the status flags before starting the ping pong mode PS003807 1002 P R E LIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 52 ZiLOG Control and Status Registers The Z86D99 Z86L99 family has 4 I O port registers 33 status and control regis ters and 233 general purpose RAM registers The I O port and control registers are included in the general purpose register memory to allow any Z8 instruction to process I O or control information directly thus eliminating the requirement for special I O or control instructions The Z8 instruction set permits direct access to any of these 37 registers In addition each of the 233 general purpose registers can also function as an accumulator an address pointer or an index register Registers identified as Reserved do not exist or have not been implemented in this design Register Summary Table 10 through Table 13 summarize the name and location of all registers The register by register descriptions follow this section Table 10 1 O Port Registers Group O Bank O Registers 0 F Grp Bnk Reg Register Function Identifier 00h rF General Purpose RAM Register GPR 00h rE General Purpose RAM Register GPR 00h rD General Purpose RAM Register GPR 00h rC General Purpose RAM Register G
65. egister F1 and F2 are available to the user but they must be set or cleared by instruc tions and are not usable with conditional jumps Table 15 FLAGS Register Group Bank FOh Register C R252 Bit 7 6 Bit Field C Z R W R W R W R W R W R W Reset X X R Read W Write X Indeterminate Bit Position Bit Field R W Description 7 Carry Flag C R W Indicates the carry out of bit 7 position of a register being used as an accumulator on Rotate and Shift instructions this bit contains the most recent value shifted out of the specified register Zero Flag Z R W Indicates that the contents of an accumulator register is zero following an arithmetic or logical operation Sign Flag S R W Stores the value of the most significant bit of a result following an arithmetic logical Rotate or Shift operation in arithmetic operations on signed numbers a positive number is identified by a 0 and a negative number is identified by a 1 Overflow Flag V R W For signed arithmetic Rotate and Shift operations the flag is set to 1 when the result is greater than the maximum possible number gt 127 or less than the minimum possible number lt 128 that can be represented in two s complement form following logical operations this flag is set to 0 P R ELI M I N A RY Z86D990 Z86D991 OTP and Z86L99X ROM Low
66. er Group Bank OFh Register 2 Bit 7 6 5 4 3 2 1 0 Bit Field P47M P46M P45M P44M P43M P42M P41M P40M R W R W R W R W R W R W R W R W R W Reset 1 1 1 1 1 1 1 1 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7654 210 Port 4 Mode R W 1 Input by bit Select 0 Output 3 P48 R W 0 Output Mode Select 1 Tristate High Impedance available on Z86L990 L991 only A bit set to 1 in the P4M Register configures the corresponding bit in Port 4 as an input while a bit set to O configures an output line Note P43 the controlled current output pad cannot be configured as an input P43 read P43 out P R EL IM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 70 ZiLOG Port 5 Control and Mode Registers P5 and P5M Port 5 is a general purpose 8 bit bidirectional I O port as shown in Table 30 Each of the eight Port 5 I O lines can be independently programmed as either input or output using the Port 5 Mode Register see Table 31 Table 30 P5 Register Group Bank 00h Register 5 R5 Bit 7 6 5 4 3 2 1 0 Bit Field Port 5 Data R W R W R W R W R W R W R W R W R W Reset X X X X X X X X R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Port 5 Data R W Data Port 5 Input Output Register Table 31 P5M Register Group
67. escale FOh r3 R243 PRE1 R W 0 10 O 0 JO O0 0 0 T8 T16 Control A ODh rl CTR1 R W 0 O 0 0 O O O 0 T8 T16 Control B ODh r3 CTR3 R W 0 0 O X X X X X T8 Timer Control ODh r0 CTRO R W 0 O 0 0 0 j0 j0 O T8 High Capture ODh_ rll Hist RW lo lo jo jo jo jo jo jo T8 Low Capture ODh r10 Lost R W 0 0 O O O O 0 0 T8 High Load ODh r5 TC8Ht R W 0 0 O O O O 0 0 T8 Low Load ODh r4 TC8L R W 0 0 0 00 00 0 0 0 T16 Timer Control ODh r2 CTR2 R W 0 0 O O O O 0 0 T16 High Capture ODh r9 HI16T R W 0 0 O O O O 0 0 T16 Low Capture ODh r8 LO161 R W 0 0 O O 00 O 0 0 T16 High Load ODh r7 TC16Ht R W 0 0 0 O 00 O 0 0 T16 Low Load ODh r6 TC16LT R W 0 0 O O O O 0 0 PS003807 1002 P R ELIM I A R Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC LZ ZiLOG Table 5 Control and Status Register Reset Conditions Continued Address Reset Value Register Function Grp Bnk Register Symbol RW 7 6 5 4 13 2 1 0 Stop Mode Recovery OFh rll SMR R W 0 0O 11 10 0 O 0 40 Port 2 SMR Source OFh rl P2SMR R W 0 O 0 O O 0 JO 0 Port 5 SMR Source OFh r5 P5SMR R W 0 0 O O O O 0 0 Notes TThis register is not reset following Stop Mode Recovery SMR This bit is not reset following SMR X means this bit is undefined at POR and is not reset following SMR In OTP the default for P43 is open drain output at power up you need to initialize the P43 data
68. f the modulator f apc can be selected between fscj x and fsc_K 2 bit1 from ADCCTRL Reducing the clock frequency lowers the power dissipated in the ADC block The ADC can be enabled or disabled When enabled the YA converter tracks the input voltage When switching between the channels step response the required time to reach the final value is given by the time constant of the low pass filter EE ee 2 _ 952 Maclay fin 0 002Ifin fipo 3db ADC ADC When available the reference for the ADC is set externally with the Vief and Vref pins The output code represents the following ratio Vin 7 V ref x 256 Vreft Vref out PS003807 1002 P R EL IM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAF ZiLOG Though the ADC functions for smaller input voltage range Vpet VRet the noise and offsets remain constant over the specified electrical range The errors of the converter increase due to small input signals For fast access to the output of the ADC the current data is available in the ADC result register r8 bank00 To reduce the interference between the digital part and the analog part separate AVss and AVpp pins are available on the packages where the ADC can be used Note In the smaller packages which do not support the ADC the user must keep the converter not active in order to not have power dissipated in the ADC block By default ADC is off A
69. h Register 6 Bit 7 6 5 4 3 2 1 0 Bit Field P67M P66M P65M P64M P63M P62M P61M P60M R W R W R W R W R W R W R W R W R W Reset 1 1 1 1 1 1 1 1 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Port 6 Mode R W 1 Input by bit Select 0 Output A bit set to 1 in the P6M Register configures the corresponding bit in Port 6 as an input while a bit set to O configures an output line Timer Control Registers General Purpose Timer T1 The Z86D99 Z86L99 family provides one standard 8 bit Z8 counter timer T1 driven by its own 6 bit prescaler PRE1 T1 is independent of the processor instruction sequence relieving software from time critical operations such as interval timing or event counting There are three registers that control the opera tion of T1 T1 Data Register T1 T1 Mode Register TMR and T1 Prescale Reg ister PRE1 Because the timer prescaler and mode register are mapped into the standard Z8 register file the software can treat the counter timer as a general purpose register thus eliminating the requirement for special instructions PS003807 1002 P R EL IM INAR Y PS003807 1002 T1 Data Register T1 The counter timer register T1 consists of an 8 bit down counter a write only reg ister that holds the initial count value and a read only register that holds the cur rent count value The initial value of T1 can range fro
70. he values in TC16H and TC16L at any time The new values take effect when they are loaded Do not load these registers at the time the val ues are to be loaded into the counter timer An initial count of 1 is not allowed An initial count of O causes T16 to count from O to FFFFh to FFFEh Transition from 0 to FFFFh is not a time out condition T16 Demodulation Mode Program TC16L and TC16H to FFh After T16 is enabled when the first edge ris ing falling or both depending on CTR1 D5 D4 is detected T16 captures HI16 and LO16 reloads and begins counting Ping Pong Mode This operation mode is only valid in transmit mode T8 and T16 must be pro grammed in single pass mode CTRO D6 CTR2 D6 and ping pong mode must be programmed in CTR1 D3 D2 The user can begin the operation by enabling either T8 or T16 CTRO D7 or CTR2 D7 For example if T8 is enabled T8 OUT is set to this initial value CTR1 D1 According to T8_OUT s level TC8H or TC8L is loaded into T8 After the terminal count is reached T8 is disabled and T16 is enabled T16 OUT switches to its initial value CTR1 DO data from TC16H and TC16L is loaded and T16 starts to count After T16 reaches the terminal count it stops T8 is enabled again and the whole cycle repeats Interrupts can be allowed when T8 or T16 reaches terminal control CTRO D1 CTR2 D1 To stop the ping pong operation write 00 to bits D3 and D2 or CTR1 p Note Enabling ping pong operation whil
71. isters O Port Registers Figure 6 Standard Z8 Register File Working Reg Groups 0 F Bank 0 Z8 Expanded Register File In addition to the Standard Z8 Register File Bank 0 Expanded Register File Banks F and D of Working Register Group 0 have been implemented on the Z86D99 Z86L99 Figure 7 illustrates the Z8 Expanded Register File architecture These two expanded register file banks of Working Register Group 0 provide a total of 32 additional RAM control and status registers The Z86D99 Z86L99 fam ily has implemented 21 of the 32 available registers P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAR ZiLOG Z8 Standard Register File Z8 Expanded Register Files Group 0 Bank F Control and Status Reg Stop Mode Recovery and Port Mode Registers General Purpose RAM Registers Working Register Groups Bank F Group 0 Bank D Timer Control Registers N 7 Banks 2 through C are T O Port Registers Reserved Not Implemented Bank E is also reserved SHRWEURUNUATNSP HOOD HY Bank 0 Figure 7 Z8 Expanded Register File Architecture Clock Circuit Description PS003807 1002 The Z8 derives its timing from on board clock circuitry connected to pins XTAL1 and XTAL2 The clock circui
72. istics Parameter Minimum Typical Maximum Units _ Resolution 8 bits Integral Nonlinearity 0 5 1 LSB Differential Nonlinearity 0 5 1 LSB Zero Error at 25 C 7 8 mv Supply Voltage Range OTP 3 0 5 5 V Supply Voltage Range ROM 2 3 5 5 V Power Dissipation No Load 1 2 mw Clock Frequency f ADC 4 MHz Input Voltage Range VRet VRef V Step Response 2 0 0021 X f ADC s ADC Input Capacitance 25 40 pF Vref Input Capacitance 25 40 pF VRet Range VRef_t 2 0 AVpp V VRet Range AGND VRet 2 0 V VRet VRet 2 0 AVpp V Temperature Range 0 70 C 3 db Frequency 0 0021 X f ADC Hz Signal to Noise 47 db ADC Output Code Dout Vref Input Source Impedance 1 0 kOhms ADC Input Source Impedance 1 0 kOhms PS003807 1002 Notes Dout Vin VRe_ VReti VRet X 256 f ADC set in ADCCTRL configuration register Step Response is the time to track the input if a step from VRet t0 VRef is applied The ADC input is a switching capacitor that charges up to the applied input volt age whenever it is configured as an ADC input If you switch it from digital mode to P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 90 ZiLOG the ADC input mode the switching capacitor starts to charge up from 0 V For the maximum swing Dout 0 to FF it takes 2 0 0021x f ADC For an 8 MHz MCU crystal with clock divide by two mode the internal system clock is 4 MHz In ADCCTRL if you select the ADC frequen
73. le one shot timer that resets the Z8 if it reaches its terminal count When operating in the RUN modes a WDT reset is functionally PS003807 1002 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 22 ZiLOG equivalent to a hardware POR reset If the mask option of the permanently enabled watch dog timer is selected it runs when power up If the option is not selected the WDT is initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction The WDT instruction does not affect the Zero Z Sign S and Overflow V flags Permanently enabled WDTs are always enabled and the WDT instruction is used to refresh it The WDT cannot be disabled after it has been initially enabled The WDT is off during both HALT and STOP modes The WDT circuit is driven by an on board RC oscillator The time out period for the WDT is fixed to a typical value see Table 57 on page 90 Power Management PS003807 1002 In addition to the standard RUN mode the Z8 supports three power down modes to minimize device current consumption The following three modes are sup ported e HALT e STOP e Low Voltage Standby Table 6 shows the status of the internal CPU clock SCLK the internal Timer clock TCLK the external oscillator and the Watch Dog Timer during the RUN mode and three low power modes Table 6 Clock Status in Operating Modes Opera
74. llows OR IRQ NUMBER where the immediate data NUMBER has a 1 in the bit position corresponding to the appropriate level of the SWI For example for an SWI on IRQ5 NUMBER has a 1 in bit 5 With this instruction if the interrupt system is globally enabled IRQ5 is enabled and there are no higher priority pending requests control is transferred to the service routine pointed to by the IRQ5 vector Reset Conditions A system reset overrides all other operating conditions and puts the Z8 into a known state The control and status registers are reset to their default conditions after a power on reset POR or a Watch Dog Timer WDT time out while in RUN mode The control and status registers are not reset to their default conditions after Stop Mode Recovery SMR while in HALT or STOP mode General purpose registers are undefined after the device is powered up Reset ting the Z8 does not affect the contents of the general purpose registers The reg isters keep their most recent value after any reset as long as the reset occurs in the specified Voc operating range Registers do not keep their most recent state from a Vy reset if Vcc drops below Vray see Table 54 on page 87 Following a reset see Table 5 the first routine executed must be one that initial izes the control registers to the required system configuration PS003807 1002 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC T
75. lve simultaneous interrupt requests There are 48 sequence possibilities for interrupts The six interrupts IRQ to IRQs are divided into three groups of two interrupt requests each as follows e Group A consists of IRQ3 and IRQ e Group B consists of IRQ and IRQ e Group C consists of IRQ and IRQ Table 22 IPR Group Bank OFh Register 9 Bit 7 6 5 4 3 2 1 0 Grp A GrpB GrpC Int Bit Field Reserved IRQ3_5 Int Group IRQO 2 IRQ1 4 Group R W W W W W W W W W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76 Reserved W X No Effect 5 Grp A Priority W 1 IRQ3 gt IRQ Group A IRQ3 and IRQs 0 IRQ55IRQ3 43 0 Interrupt Grow W 111 Reserved Priority 110 B gt A gt C 101 C gt B gt A 100 B gt C gt A 011 A gt C gt B 010 A gt B gt C 001 C gt A gt B 000 Reserved 2 GrpB Priority W 1 IRQg5IRQ Group B IRQg and IRQs 0 IRQ 5IRQg 1_ Grp C Priority W 1 IRQ4 gt IRQ Group C IRQ and IRQ 0 IRQ45IRQ Priorities can be set both within and between groups using the IPR Bits 1 2 and 5 of the IPR define the priority of individual members within the groups Bits 0 3 and 4 are encoded to define six priority orders between the three groups Bits 6 and 7 are reserved PS003807 1002 P R ELIM INAR Y Interrupt Request Register Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z ZiLOG Th
76. m 1 to 255 O represents 256 see Table 34 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAP ZiLOG Table 34 T1 Register Group Bank FOh Register 2 R242 Bit 7 6 5 4 3 2 1 0 Bit Field T1 Value R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 T Value R Data Current Value W Data Initial Value Range 1 to 256 Decimal T1 Mode Register TMR Under software control T1 counter timer is started and stopped using the T1 Mode Register as shown in Table 35 Table 35 TMR Register Group Bank FOh Register 1 R241 Bit 7 6 5 4 3 2 1 0 T1 T1_ Bit Field TOUT_Mode TIN_Mode Count Load Reserved R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 1 1 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76 Tour Mode R W 11 Internal Clock OUT on P56 10 T OUT on P56 01 Reserved 00 Not used P56 configured as I O __ 54 Tin Mode R W 11 Trigger Input Retriggerable 10 Trigger Input Not retriggerable 01 Gate Input 00 External Clock Input T n on P52 3 T4 Count R W 1 Enable T4 Count 0 Disable T4 Count P R ELIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC 4 ZiLOG Table 35 TMR Register Group Bank FOh Register 1 R241
77. mA at 8 MHz 3 0 V 2 mA Clock divided by 16 5 5 V 4 mA XTAL running ADC is off loce Standby Current STOP Mode 3 0 V 20 uA Vin 0 V Vdd ADC is off 5 5 V 30 E a Voltage Detection and ADC if applicable are disabled The IC might draw more current if any of the above peripherals is enabled lape Current with A D Running 3 0 V 500 HA 5 5 V 900 uA Viv Vdd Low Voltage Protection 2 90 V Low voltage protection is also known as brownout Typical is 2 6 V VLB Low Battery Detection VLV V 0 5 V PS003807 1002 P R ELIM INAR Y 87 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC 88 ZiLOG Table 55 DC Characteristics for the Z86L99X Mask Only Symbol Parameter Vpp Min Max Units Comments Vpp Power Supply Voltage 2 3 5 5 Vou Clock Input High Voltage 2 3V 0 8Vdd Vdd 0 3 V Driven by Ext clock generator 5 5V 0 8Vdd Vdd 0 3 V VeL Clock Input Low Voltage 2 3 V Vss 0 3 0 2Vdd Driven by Ext clock generator 5 5 V Vss 0 3 0 2Vdd Vin Input High Voltage 23V 0 7Vdd Vdd 0 3 V 5 5V 0 7Vdd Vdd 0 3 V Vit Input Low Voltage 2 3V Vss 0 3 0 2Vdd V 5 5V Vss 0 3 0 2Vdd V Vout Output High Voltage 2 3V 2 0 V 0 5 mA Regular I O 5 5V 5 0 V 2 3V 1 9 V 1 2 mA 5 5V 5 0 V Von High Drive Pins P54 P55 P56 P57 2 3V 1 9 V 3 mA 5 5V 5 1 V 23V 1 7 V 5 mA 5 5V 4 7 V Vout Regular I O 2 3V 0 4 V V 2mA Output low voltage 5 5 V 0 4V V 2 3 V 0 8 V V 4mA 5
78. ming requirements TwIL TwIH on external interrupt requests Internal Interrupt Sources Internal sources are ORed with the external sources so that either an internal or external source can trigger the interrupt Interrupt Request Register Logic and Timing Figure 10 shows the logic diagram for the Interrupt Request Register The leading edge of an interrupt request sets the first flip flop It remains set until the interrupt requests are sampled PS003807 1002 P R E LIM INAR Y IRQg IRQs PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC To Mask and Priority Logic From Priority Logic Figure 10 IRQ Logic Internal interrupt requests are sampled during the most recent clock cycle before an Op Code fetch see Figure 11 External interrupt requests are sampled two internal clocks earlier than internal interrupt requests because of the synchroniz ing flip flops shown in Figure 9 ul m m 1 m ra frs r1 r2 1a m r2 fr Interrupt Request Sampled Internally External Interrupt Request Sample Figure 11 Interrupt Request Timing At sample time the interrupt request is transferred to the second flip flop shown in Figure 10 which drives the interrupt mask and priority logic When an interrupt cycle occurs this flip flop is reset only for the highest priority level that is enabled The user has direct access to the second flip flop by reading and writing to the
79. mpliment of 8 bit arithmetic and logical operations BCD operations are supported using a decimal adjustment of binary values and 16 bit quantities for addresses and counters can be incremented and decremented Bit manipulation and Rotate and Shift instructions complete the data manipulation capabilities of the Z8 CPU No special I O instructions are necessary because the I O is mapped into the register file CPU Control Registers The standard Z8 control registers govern the operation of the CPU Any instruc tion which references the register file can access these control registers The fol lowing are available control registers e Register Pointer RP e Stack Pointer SP e Program Control Flags FLAGS PS003807 1002 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 10 ZiLOG e Interrupt Control IPR IMR and IRQ e Stop Mode Recovery SMR P2SMR and P5SMR e Low Battery Detect LB Flag The Z8 uses a 16 bit Program Counter PC to determine the sequence of current program instructions The PC is not an addressable register Peripheral registers are used to transfer data configure the operating mode and control the operation of the on chip peripherals Any instruction that references the register file can access the peripheral registers The following are peripheral control registers e Analog Digital Converter ADCCTRL and ADCDATA e T1 Timer Counter TMR T1 and PRE1 e
80. olled Current Output P6 is only in the Z86L990 Z86D990 8 Bit A DT VRef MUX VRef Z ZiLOG Vpp padring t Vpp CORE lt XTAL 1 3 XTAL 2 P43 Lk ADCO P44 ADC1 P45 O ADC2 P46 ADC3 P47 TADC is only in the Z86L990 Z86D990 ttProgram memory is as follows In the 28 pin package VDD padring and Vpp CORE are bonded together Figure 1 Functional Block Diagram PS003807 1002 P R E L IM INA Z86D990 Z86D991 Z86L990 Z86L991 R Y 32K OTP 32K OTP 16K ROM 16K ROM Pin Descriptions Notes Figure 2 through Figure 4 show the pin names and locations P62 P63 P25 P26 P27 NC AVss VREF P44 P45 P46 P47 VREF AVpp VDD coRE VDD padring XTAL2 XTAL1 NC P51 P52 P53 P54 P64 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC CAD MW PWN H 9 10 Z86D990 11 i2 Z86L990 villtyy IH a Hk a T tili al 1 Both Vgs pins must be connected to ground NC is no connection to the die P61 P60 P24 P23 P22 NC NC P21 P20 p43 VSS VSS P42 P41 P40 P50 P56 NC NC P57 P55 P67 P66 P65 Z ZiLOG 2 3 AVpp must be connected to Vpp core and a 10 uF capacitor for good A D conversion 4 Power must be connected to VDD padring Current passes to Vpp core through the internal power filter PS003807 1002 Figure 2 48 Pin SSOP Pin Assignments P R
81. oltage comparator checks that the Vcc level is at the required level for correct operation of the Z8 When Vec falls below the low voltage trip voltage Viv reset is globally driven and then the device is put in a low current standby mode with the external oscillator stopped If the Voc remains above Vppw the RAM content is preserved When the power level rises above the V y level the device performs a POR and functions normally The minimum operating voltage varies with temperature and operating frequency while Vjy varies with temperature only O Ports The Z86D99 Z86L99 family has up to 32 lines dedicated to input and output in the 40 pin configuration These lines are grouped into four 8 bit ports known as Port 2 Port 4 Port 5 and Port 6 All four ports are bit programmable as either inputs or outputs with the exception of P52 P53 and P43 P52 and P53 are input only as they are used in OTP programming P43 is the controlled current output and is therefore output only All ports have push pull CMOS outputs In addition the push pull outputs can be turned off for open drain operation using the P456CON register Internal resistive pull up transistors are available as a user defined OTP mask option on all ports For Ports 4 5 and 6 the pull ups are nibble selectable For Port 2 the pull up option applies to all eight I O lines gt Note Internal pull ups are disabled on any given pin or group of port pins when those pins a
82. onents of life support systems is not authorized No licenses or other rights are conveyed implicitly or otherwise by this document under any intellectual property rights P RELIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC ZiLOG Architectural Overview p0h setae lade Gee OS eed ee NG 1 Features 32 5 2508 ye 2 Rk KER ed GRAY EDR AA HEHE Re Heed EE KG KAMANG 2 Counter TiMmers aaa nah NG cees TANGAN daa ha ANNA AETA ANG 2 Input Output and Interrupts 22 122 si4052i6acgei desdsdasusiae HIGA 2 Operating Characteristics c eee 3 User Programmable Option Bits 0 0 0 0 eee eee ee 3 Functional Block Diagram 2cace AR PARAK veh eee s a8 Gees eG Sse bak eee 4 Pin Descriptions 24 156 ABA pouint uaa ae i aR OME EEREYSERELE PEERS Sees 5 Pins Configuration icaessdeGbneehadeatae seed Shere sei AGE hhaha ay 7 Operational Description cs secdse ended Seeds edo ea seeds ELELEDN GG ses 9 Central Processing Unit CPU Description aaa 9 Memory ROM OTP and RAM 0ccc0 0 5 cee ea dieeeteeea viens 10 Clock Circuit Description 343 35728i eee eho dees CEA ee ewes 14 MCN UPIS 53 oso Spake dod a oraa aa AA head AA 15 Reset Conditions 2 2253 02c0te0s66easees seated DOTA AANI 32 19 Power Management 2 0 e ee ee 22 VO PONS oreari ara nde AA 24 PenpheralS sesosaarsnisrde Una bg a aaga peaa ie KG KNA Sewer aad 28 Control and Status Registers 0 0 0
83. onment AN Caution Do not attempt to use these bits as the results are PS003807 1002 unpredictable and meaningless Table 14 Register Description Locations Address Grp Bnk Register Register Function Symbol Location 00h r2 R2 Port 2 Data P2 page 68 00h r4 R4 Port 4 Data p4 page 69 00h r5 R5 Port 5 Data P5 page 70 00h r6 R6 Port 6 Data P6 page 71 00h r7 R7 ADC Data ADCDATA page 62 ODh ro T8 Timer Control CTRO page 77 ODh rl T8 T16 Control A CTR1 page 74 ODh r2 T16 Timer Control CTR2 page 80 ODh r3 T8 T16 Control B CTR3 page 76 ODh r4 T8 Low Load TC8L page 79 0Dh r5 T8 High Load TC8Ht page 79 ODh r T16 Low Load TC16LT page 82 ODh 17 T16 High Load TC16H1 page 82 ODh r8 T16 Low Capture LO161 page 81 ODh 19 T16 High Capture HI16T page 81 0Dh r10 T8 Low Capture Lost page 78 P R E LIM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Table 14 Register Description Locations Continued VAP ZiLOG Address Grp Bnk Register Register Function Symbol Location Oph rll T8 High Capture HI8T page 78 ODh r12 Low Battery Detect LB page 60 OFh r0 Port Configuration A P456CON page 67 OFh rl Port 2 SMR Source P2SMR page 84 OFh r2 Port 4 Mode P4M page 69 OFh r4 Port 5 Mode P5M page 70 OFh r5 Port 5 SMR Source P5SMR page 84
84. or can be combined together using a number of user selectable modes governed by the T8 T16 control registers P R EL IM N A R Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z PS003807 1002 T8 T16 Control Register A CTR1 ZiLOG The T8 T16 Control Register A controls the functions in common with both the Tg and T46 counter timers The Tg and T46 counter timers have two primary modes of operation Transmit Mode and Demodulation Mode Transmit Mode is used for generating complex waveforms The Transmit Mode has two submodes Normal Mode and Ping Pong Mode The settings for CTR1 in Transmit Mode are given in Table 37 Table 37 CTR1 Register In Transmit Mode Group Bank ODh Register 1 Bit 7 6 5 4 3 2 1 0 Initial_ P43 Transmit_ Initial T16 Bit Field Mode Out T8 T16_Logic Submode T8 Out Out R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7 Mode R W 1 Demodulation 0 Transmit 6 P43 Out R W 1 P43 configured as T8 T16 Output 0 P43 configured as I O _ 54 3 3 Te T4g Logic R W 11 NAND 10 NOR 01 OR 00 AND 82 Transmit R W 11 T16_Out 1 Submode 10 T16 Out 0 01 Ping Pong Mode 00 Normal Operation 1 lnitial T8 Out R W 1 T8 Out set to 1 initially 0 T8 Out set to 0 initially 0 Initial T16 Out R W 1 T16 Out set to 1 initially 0 T16 Out set to 0 ini
85. put I O port registers can be used as accumulators This unique register to register architecture avoids accumulator bottlenecks for high code effi ciency The registers can be used as address pointers for indirect addressing as index registers or for implementing an on chip stack The Z8 has a sophisticated interrupt structure and automatically saves the pro gram counter and status flags on the stack for fast context switching Speed of execution and smooth programming are also supported by a working register area with short 4 bit register addresses PS003807 1002 P R EL tM INAR Y Features Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 2 ZiLOG The Z8 instruction set consisting of 43 basic instructions is optimized for high code density and reduced execution time It is similar in form to the ZILOG Z80 instruction set The eight instruction types and six addressing modes together with the ability to operate on bits 4 bit nibbles or binary coded decimal BCD dig its 8 bit bytes and 16 bit words make for a code efficient flexible microcontroller e Four channel 8 bit sigma delta analog to digital A D converter with external voltage references not available in the 28 pin configuration e Two independent analog comparators e Controlled current output e 489 bytes of RAM 233 bytes of general purpose register based RAM 256 bytes of RAM mapped into the program memory space that c
86. r count modulo a value from 11 to 64 decimal The prescaler register also contains control bits that specify T counting modes These bits also indicate whether the clock source for T4 is internal or external The counter timer T4 F2h consists of an 8 bit down counter a write only register that holds the initial count value and a read only register that holds the current count value see Figure 18 on page 35 The initial value can range from 1 to 256 decimal 01h 02h 00h Figure 21 illustrates the counter timer register R242 T1 Counter Timer 1 Register F2h Read Write er 8e es Ps 85 01 05 Initial value when written range 1 256 decimal 01h 00h Current value when read Figure 21 Counter Timer 1 Register Counter Timer Operation Under software control T is started and stopped using the Timer Mode register F1h bits Do D3 a Load bit and an Enable Count bit See Figure 22 R241 TMR Timer Mode Register F1h Read Write D3 Do Dy Do Reserved 0 No function 1 Load Ty 0 Disable T count 1 Enable T4 count Figure 22 Timer Mode Register Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 38 ZiLOG Load and Enable Count Bits Setting the Load bit D to 1 transfers the initial values in the prescaler and the counter timer registers into their respective down counters The next internal clock resets bit D to 0 readying the Load bit fo
87. r the next load operation The initial val ues can be loaded into the down counters at any time If the counter timer is run ning the counter timer continues to run and starts the count over with the initial value Therefore the Load bit actually functions as a software re trigger The T4 counter timer remains at rest as long as the Enable Count bit D5 is 0 To enable counting the Enable Count bit D3 must be set to 1 Counting actually starts when the Enable Count bit is written by an instruction The first decrement occurs four internal clock periods after the Enable Count bit has been set The Load and Enable Count bits can be set at the same time For example using the instruction oR TMR 0c sets both D and D3 of TMR to 1 The initial values of PRE and T4 are loaded into their respective counters and the count is started after the M2T2 machine state after the operand is fetched as shown in Figure 23 03 is fetched TMR is written first decrement counter timers occurs four are loaded clocks later Figure 23 Starting the Count Prescaler Operations During counting the programmed clock source drives the prescaler 6 bit counter The counter is counted down from the value specified by bits Do D7 of the corre sponding prescaler register PRE or PRE Figure 24 When the prescaler counter reaches its end of count the initial value is reloaded and counting contin ues The prescaler never actually reaches zero For example if
88. re 26 Counter Timer Output Using Tour The internal clock can be selected as output instead of T4 by setting TMR bits D7 and Dg both to 1 The internal clock XTAL frequency 2 is then directly output on P5 Figure 27 Internal clock OSC pp 2 o Z em P5 Tout Figure 27 Internal Clock Output Using TouT While programmed as Tout P5g cannot be modified by a write to port register P5 However the Z8 software can examine P5 s current output by reading the port register T n Modes The Timer Mode register TMR F1h Figure 28 is used in conjunction with the Prescaler register PRE F3n Figure 29 to configure P5 as Tin Tin is used in conjunction with T4 in one of four modes e External clock input e Gated internal clock e Triggered internal clock e Retriggerable internal clock P R EL IM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC 1 42 ZiLOG R241 TMR Timer Mode Register F1h Read Write Tin Modes External clock input 00 Gate input 01 Trigger input 10 non retriggerable Trigger input 11 retriggerable Figure 28 Timer Mode Register Tj Operation R243 PRE1 Prescaler 1 Register F3h Write Only Clock source 1 T4 internal 0 Ty external Tiy Figure 29 Prescaler 1 Tj Operation The T4 counter timer clock source must be configured for external by setting PRE bit D to 0
89. re programmed as outputs PS003807 1002 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 25 ZiLOG Mode Registers Each port has an associated Mode Register that determines the port s functions and allows dynamic change in port functions during program execution Port and Mode Registers are mapped into the Standard Register File Because of their close association Port and Mode Registers are treated like any other general pur pose register There are no special instructions for port manipulation Any instruc tion that addresses a register can address the ports Data can be directly accessed in the Port Register with no extra moves Input and Output Registers Each of the four ports Ports 2 4 5 and 6 has an input register an output regis ter and associated buffer and control logic Because there are separate input and output registers associated with each port writing bits defined as inputs store the data in the output register This data cannot be read as long as the bits are defined as inputs However if the bits are reconfigured as output the data stored in the output register is reflected on the output pins and can then be read This mecha nism allows the user to initialize the outputs before driving their loads Because port inputs are asynchronous to the Z8 internal clock a READ operation could occur during an input transition In this case the logic level might be uncer t
90. referred to as a cold start A 1 in bit D7 indicates that the device was awakened by a SMR source Waking a device with a SMR source is sometimes referred to as a warm start The Stop Mode Recovery source can be selected by any combination of P2 and P5 by P2SMR and P5SMR respectively If the pin is selected as the SMR source its logic level is latched into a register A wait up signal is generated if its logic level changes This applies to all selected pins for the SMR source The comparators of P5 cannot be used as an SMR source The comparator is turned off in STOP mode Table 50 SMR Register Group Bank OFh Register B Bit 7 6 5 4 3 2 1 0 Stop Re Stop Bit Field Flag served Delay Reserved SCLK Select R W R R W W R W R W R W W W Reset 0 0 1 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7 Stop Mode Flag R 1 Stop Recovery warm start R 0 POR WDT Reset cold start W X No Effect 6 Reserved R 1 Always reads 1 W X No Effect 5 Stop Delay R 1 Always reads 1 W 1 Enable 5ms Reset delay W 0 Disable Reset delay after SMR 432 Reserved R 1 Always reads 111 W X No Effect 10 System Clock R 11 Always reads 11 Select W 11 SCLK TCLK XTAL 16 W 10 SCLK TCLK XTAL W 01 SCLK TCLK XTAL 32 W 00 SCLK TCLK XTAL 2 The second function of the SMR register is the selection of the external clock divide value The purpose of this con
91. s If an attempt is made to read these registers FFh is returned Reading any write only register returns FFh e When the Register Pointer register FDH is read the least significant four bits lower nibble indicate the current Expanded Register File Bank For example 0000 indicates the Standard Register File while 1010 indicates Expanded Register File Bank A e Writing to bits that are selected as timer outputs changes the I O register but has no effect on the pin signal e The Z8 instruction DJNZ uses any general purpose working register as a counter e Logical instructions such as OR and AND require that the current contents of the operand be read They do not function properly on write only registers P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAF ZiLOG Registers Grouped by Function The following is a summary of the 37 special purpose registers of the Z86D99 Z86L99 family grouped by function The following are the functional groups Flags and Pointers Analog to Digital Converter Control Interrupt Control I O Port Control Timer Control General Purpose Timer T1 Timer Control T8 and T16 Timers Stop Mode Recovery Control For any of the registers described in this section see Table 14 bits identified as Reserved either do not exist meaning they have not been implemented in this design or have a special purpose in a ZiLOG engineering or test envir
92. s mode CTRO D6 T8 counts down to 0 and stops T8_OUT toggles the time out status bit CTRO D5 is set and a time out interrupt can be generated if it is enabled CTRO D1 In modulo N mode upon reaching terminal count T8 OUT is toggled but no interrupt is generated Then T8 loads a new count if T8 OUT level is 0 TC8L is loaded if T8 OUT is 1 TC8H is loaded P REL M Divider T8 Clock Divider N A R Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 47 ZiLOG T8 counts down to O toggles T8 OUT sets the time out status bit CTRO D5 and generates an interrupt if enabled CTRO D1 This completes one cycle T8 then loads from TC8H or TC8L according to the T8 OUT level and repeats the cycle The user can modify the values in TC8H or TC8L at any time The new values take effect when they are loaded Do not write these registers at the time the values are to be loaded into the counter timer An initial count of 1 is not allowed An ini tial count of O causes TC8 to count from O to FFh to FEh Transition from 0 to FFh is not a time out condition see Figure 34 PS003807 1002 P R E LIM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC 48 ZiLOG T8 8 Bit Transmit Mode T8_Enable Bit Set Reset T8 Enable Bit CTR1 D1 Y Value Load TC8L Load TC8H Reset 18 OUT Set T8 OUT Set Time out Status Bit
93. s to be configured in Input Mode and with the digital input buffer disabled P R EL IM INAR Y PS003807 1002 ADC Data Register ADCDATA Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC 4 ZiLOG The ADCDATA register is a read only register that contains the digital output of the analog to digital converter See Table 20 Table 20 ADCDATA Register Group Bank 00h Register 7 Bit 7 6 5 4 3 2 0 Bit Field ADC Data R W R R R R R R R Reset 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 ADC Data R Data Output of the ADC W X No Effect Interrupt Control Registers The Z8 allows up to six different interrupts from a variety of sources These inter rupts can be masked and their priorities set by using the Interrupt Mask Register and Interrupt Priority Register The Interrupt Request Register stores the interrupt requests for both vectored and polled interrupts P REL M N A R Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 63 ZiLOG Interrupt Mask Register The IMR as described in Table 21 individually or globally enables the six interrupt requests Bit 7 of the IMR is the master enable and must be set before any of the individual interrupt requests can be recognized Bit 7 must be set and reset by the enable interrupts and disable interrupts instr
94. t counter timer with one 16 bit capture register pair and one 16 bit load register pair See Figure 33 The T8 and T16 counters timers have two modes of operation The transmit mode is used to generate complex waveforms There are two submodes The normal mode can be used in single pass or modulo N repeating mode The ping pong mode is used when the T8 timer counts down enables the T16 timer that counts down enabling T8 and so on until the mode is disabled The demodulation mode is used to capture and demodulate complex waveforms P R E LIM INAR Y H116 LO16 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z ZiLOG 16 Bit Timer 16 T16 1248 Input t t f t SCLK Clock s Divider Glitch T16 Clocked And Or TC16H TC16L HI8 LO8 Edge z Detect f X8 X8 meee Bi Circuit a gt Timer 8 i 1248 8 TC8H TC8L l l SCLK Clock PS003807 1002 Figure 33 Counter Timer Architecture T8 Transmit Mode Before T8 is enabled the output of T8 depends on CTR1 D1 If CTR1 D1 is 0 T8_OUT is 1 If CTR1 D1 is 1 T8_OUT is O When T8 is enabled the output T8 OUT switches to the initial value CTR1 D1 If the initial value CTR1 D1 is 0 TC8L is loaded otherwise TC8H is loaded into the counter In single pas
95. ter rupts instruction p Note IRQ is always cleared to 00h and is in read only mode until the first El instruction that enables the IRQ to be read write Setting the Global Interrupt Enable bit in the Interrupt Mask Register IMR bit 7 does not enable the IRQ Execution of an El instruction is required For polled processing IRQ must be initialized by an El instruction To properly ini tialize the IRQ the following code is provided CLR IMR make sure vectored interrupts are disabled EI enable IRQ otherwise it is read only not necessary if interrupts were previously enabled DI disable interrupt handling IMR is cleared before the IRQ enabling sequence to ensure no unexpected inter rupts occur when El is executed This code sequence must be executed before programming the application required values for IPR and IMR O Port Control Registers Each of the four ports Ports 2 4 5 and 6 has an input register an output regis ter and an associated buffer and control logic Because there are separate input and output registers associated with each port writing bits defined as inputs stores the data in the output register This data cannot be read as long as the bits are defined as inputs However if the bits are reconfigured as output the data stored in the output register is reflected on the output pins and can then be read This mechanism allows the user to initialize the outputs before driving their loads PS
96. ter Reading input bits also returns data on the external pins PS003807 1002 P R EL IM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC LZ ZiLOG Special Functions Table 7 defines the special functions of Ports 4 and 5 Table 7 Special Port Pin Functions Function Pin Signal Configuration Register Analog Comparator Inputs P51 CIN1 P456CON P52 CIN2 P456CON Analog Comparator P50 CREF1 References P53 CREF2 Analog Comparator Outputs P54 COUT1 P55 COUT2 ADC Channels P44 ADCO ADCCTRL P45 ADC1 ADCCTRL P46 ADC2 ADCCTRL P47 ADC3 ADCCTRL External Interrupts P52 IRQo IMR and IRQ P53 IRQ IMR and IRQ P51 IRQ IMR and IRQ Tin External Clock Input P52 TIN TMR and PRE1 Capture Timer Input P51 Demodulator_Input CTR1 T1 Timer Output P56 T1OUT TMR T8 Output P40 P40_Out CTRO T16 Output P41 P41 Out CTR2 Combined T8 T16 Output P43 P43 Out CTR1 Controlled Current Output ZiLOG Test Mode P41 DSn Enable P456CON P42 ASn Enable P456CON P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC VAP ZiLOG Peripherals PS003807 1002 Analog Comparators The Z86D99 Z86L99 family includes two independent on chip general purpose analog comparators as shown in Figure 13 The comparators are multiplexed with a digital input signal by the P456CON register They can also be used to generate interrupts IRQO
97. tially P R ELIM N A R Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 75 ZiLOG In Demodulation Mode the T8 and T16 counter timers are used to capture and demodulate complex waveforms The settings for CTR1 in Demodulation Mode are given in Table 38 Table 38 CTR1 Register in Demodulation Mode Group Bank ODh Register 1 Bit 7 6 5 4 3 2 1 0 Demod Rising Falling Bit Field Mode Input Edge Detect Glitch Filter Edge Edge R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7 Mode R W 1 Demodulation 0 Transmit 6 Demodulator _ R W 1 P20 as Demodulator Input Input 0 P51 as Demodulator Input 54 Edge Detect R W 11 Reserved 10 Both Edges 01 Rising Edge 00 Falling Edge 32 Glitch Filter R W 11 16 SCLK Cycles 10 8 SCLK Cycles 01 4 SCLK Cycles 00 No Filter 1_ Rising Edge R 1 Rising Edge Detected R 0 No Rising Edge W 1 Reset Flag to 0 W 0 No Effect 0 Falling Edge R 1 Falling Edge Detected R 0 No Falling Edge W 1 Reset Flag to 0 W 0 No Effect PS003807 1002 P R ELIM INAR Y PS003807 1002 T8 T16 Control Register B CTR3 The T8 T16 Control Register B known as CTR3 is a new register to the Z86D99 Z86L99 family This register allows the Tg and T g counters to be synchronized The settings of CTR3 are described in Table 39 Z86D990 Z86D991 OTP and
98. ting Mode SCLK TCLK External OSC WDT RUN On On On On HALT Off On On Off STOP Off Off Off Off Low Voltage Standby Off Off Off Off Note When WDT is enabled by the mask option bit Using the Power Down Modes In order to enter HALT or STOP mode it is necessary to first flush the instruction pipeline to avoid suspending execution in mid instruction You can flush the P R EL IM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 23 ZiLOG instruction pipeline by executing a NOP Op Code FFh immediately before the appropriate sleep instruction For example Mnemonic Comment Op Code NOP clear the pipeline FFh STOP enter STOP mode 6Fh or Mnemonic Comment Op Code NOP clear the pipeline FFh HALT enter HALT mode 7Fh HALT HALT mode suspends instruction execution and turns off the internal CPU clock SCLK The on chip oscillator circuit remains active so the internal Timer clock TCLK continues to run and is applied to the counter timers and interrupt logic An interrupt request either internally or externally generated must be executed enabled to exit HALT mode After the interrupt service routine the program con tinues from the instruction immediately following the HALT The HALT mode can also be exited by a POR In this case the program execution restarts at the reset address 000ch STOP STOP mode provides the lowest possible device standby current This
99. trol is to selectively reduce device power P R EL IM I N A RY PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z ZiLOG consumption during normal processor execution SCLK control and or HALT mode where TCLK sources counter timers and interrupt logic Port 2 Stop Mode Recovery P2SMR The P2SMR register as described in Table 51 defines which I O lines in Port 2 are to be used as stop mode recovery sources Table 51 P2SMR Register Group Bank OFh Register 1 Bit 7 6 5 4 3 2 1 0 Bit Field P27RS P26RS P25RS P24RS P23RS P22RS P21RS P20RS R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Port 2 Stop Mode R W 1 Recovery Source by bit Recovery 0 Not Port 5 Stop Mode Recovery P5SMR The P5SMR register as described in Table 52 defines which I O lines in Port 5 are to be used as stop mode recovery sources Table 52 P5SMR Register Group Bank OFh Register 5 Bit 7 6 5 4 3 2 1 0 Bit Field P57RS P56RS P55RS P54RS P53RS P52RS P51RS P50RS R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 76543210 Port5 Stop Mode R W 1 Recovery Source by bit Recovery 0 Not P R EL IM I N A RY Z86D990
100. try consists of an oscillator a divide by two shaping circuit and a clock buffer The oscillator s input is XTAL1 and the oscillator s out put is XTAL2 The clock can be driven by a crystal a ceramic resonator LC clock RC or an external clock source Clock Control The Z8 offers software control of the internal system clock using programming register bits in the SMR register This register selects the clock divide value and determines the mode of STOP Mode Recovery The default setting is external clock divide by two When bits 1 and 0 of the SMR register are set to O the System Clock SCLK and Timer Clock TCLK are equal to the external clock frequency divided by two When bit 1 of the SMR register is set to 1 then SCLK and TCLK equal the exter nal clock frequency Refer to Table 53 on page 85 for the maximum clock fre quency A divide by 16 prescaler of SCLK and TCLK allows the user to selectively reduce device power consumption during normal processor execution under SCLK con trol and or HALT mode where TCLK sources counter timers and interrupt logic Combining the divide by two circuitry with the divide by 16 prescaler allows the external clock to be divided by 32 P R E LIM INAR Y Interrupts PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z ZiLOG The Z86D99 Z86L99 family allows up to six different interrupts three external and three internal from nine possi
101. ts Always reads back 1 t Note Do not use the read modify write instructions for example OR and AND with this register Bits 0 1 and 2 always read back 1 Note For Z86L990 L991 P43 can never be configured as push pull After any reset P43 is configured as tristate high impedance Port 2 outputs are configured using the P3M Register shown in Table 25 Bit O of the P3M Register switches Port 2 from push pull active to open drain outputs No other bits in this register are implemented P R EL tM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Port 2 Control and Mode Registers P2 and P2M Port 2 is a general purpose 8 bit bidirectional I O port as shown in Table 26 Each of the eight Port 2 I O lines can be independently programmed as either input or output using the Port 2 Mode Register see Table 27 Table 26 P2 Register Group Bank 00h Register 2 R2 ZiLOG Table 25 P3M Register Group Bank FOh Register 7 R247 Bit 7 6 5 4 3 2 1 0 P2_ Bit Field Reserved Output R W W W W W W W W W Reset 1 1 1 1 1 1 1 1 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7654321 Reserved R 1 Always reads 1111111 W X No Effect 0 Port 2 Output W 1 Push Pull Active Configuration 0 Open Drain Outputs Table 27 P2M Register Group Bank FOh Register 6 R246 Bit 7 6 5 4 3
102. uctions only The IMR is automatically reset during an interrupt service routine and set following the execution of an Interrupt Return IRET instruction Table 21 IMR Group Bank OFh Register B Bit 7 6 5 4 3 2 1 0 Re Bit Field Master served IRQ5 IRQ4 IR 3 IRQ2 IRQ1 IRQO R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate Bit Position Bit Field R W Value Description 7 Master R W 1 Enable Master Interrupt 0 Disable Master Interrupt 6 Reserved R 1 Always reads 1 W X No Effect _ 5 IRQs R W 1 Enable IRQs 0 Disable IRQs _ 4 IRQ R W 1 Enable IRQ 0 Disable IRQ 3 IRQs R W 1 Enable IRQ 0 Disable IRQ3 2_ IRQ R W 1 Enable IRQ5 0 Disable IRQ 1_ IRQ R W 1 Enable IRQ 0 Disable IRQ 0 IRQ R W 1 Enable IRQg 0 Disable IRQg Note Bit 7 must be reset by the DI instruction before the contents of the Interrupt Mask Register or the Interrupt Priority Register are changed except in the following situations Immediately after a hardware reset Immediately after executing an interrupt service routine and before IMR bit 7 has been set by any instruction P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 64 ZiLOG Interrupt Priority Register IPR The IPR as described in Table 22 is a write only register that sets priorities for the vectored interrupts in order to reso
103. ure 34 ZiLOG Functional Block Diagram 9 22 7403 apa sa 02000045 eadee vues 4 48 Pin SSOP Pin Assignments 0 00 cee eee ee eee 5 40 Pin DIP Pin Assignment 0002 e eee eee ee 6 28 Pin SOIC DIP Pin Assignment User Mode 7 Program Memory Map cccscspieasdesg KAANAK Wa AL 12 Standard Z8 Register File Working Reg Groups 0 F Bank 0 13 Z8 Expanded Register File Architecture 14 Interrupt Block Diagram 22k paawa a Ka DRAG KARLA KI WAG AGA 16 External Interrupt Sources IRQO IRQ2 Block Diagram 17 IRO LOJI APA 18 Interrupt Request Timing nananana 18 General Input Output PIN nnana aana aa 26 Analog Comparators 66 24 ssas aaaeeeaa 28 ADC Block Diagram na nnana 29 Low Pass Filter with 8 MHz Crystal aa 30 Active Glitch Power Filter 00 00 e eee eee 32 I V Characteristics for the Current Sink Pad P43 34 T4 Counter Timer Block Diagram a 35 Register Pile wapka pah K ABRA WA seed See Geueeuteadeass 36 Prescaler 1 Register 0 36 Counter Timer 1 Register a 37 Timer Mode Register 0c cece eee eee 37 Starting the Count 4 44 kaka eke ees bad ves be Peed a KAKA 38 Counting Modes i1iG5ntiaedeta KAU KAG dans Gatdeiadeotanes 39 Timer Mode Register Toyz Operation 40 Counter Timer Output Using Thy ee eee ee 41 Internal Clock Output Using Touf eee eee eee
104. w current if it outputs a low logic even without external connection This applies to both Run mode and Stop mode Table 9 Current Sink Pad P43 Specifications Preliminary Parameter Min Max Conditions Rise time 0 4 u LED load Fall time 0 02 u LED load Voutmin 0 54 V 27C Comparator response 0 2 u Regulated current 80 mA 120 mA Internal resistance 80 Q The pad driver can function in two modes e controlled current output when the voltage on the pad is over a minimum value V pad gt Voutmin e resistive pull down when the driver cannot regulate the current in this mode the gate of the NMOS pull down is raised to the power rail The I V characteristics of the pad are presented in Figure 17 P R EL IM INAR Y Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC 25C Current mA PS003807 1002 Voltage Figure 17 I V Characteristics for the Current Sink Pad P43 The CPU reads the mode of the pad driver by reading bit number 2 from the LB register This bit is the output of a Set Reset flip flop that sets whenever the volt age on the pad is lower than Voutmin and is reset by a CPU write to the respective register T1 Timer The Z86D99 Z86L99 family provides one general purpose 8 bit counter timer T4 driven by its own 6 bit prescaler PRE The T counter timer is indepen
105. wnout circuit e Watch dog timer and power on reset circuits User Programmable Option Bits e Clock source RC other LC resonator or crystal e Watch dog timer permanently enable e 32 kHz crystal e Port 20 27 pull up resistive transistor e Port 40 42 pull up resistive transistor e Port 44 47 pull up resistive transistor e Port 50 51 pull up resistive transistor e Port 54 57 pull up resistive transistor e Port 60 63 pull up resistive transistor not available in Z86D991 Z86L991 e Port 64 67 pull up resistive transistor not available in Z86D991 Z86L991 e P43 high impedance in STOP mode available in OTP only Force P43 to output a 1 in the open drain configuration PS003807 1002 P R EL IM INAR Y Functional Block Diagram Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Figure 1 shows the functional block diagram for the microcontrollers Register File 256 x 8 bit Expanded Register File Program Memory a tt Port 2 256 Bytes P52 P53 CIN2 CREF2 Port 4 Two Analog Comparators CIN1 CREF1 P51 P50 Power Filter Z8 Core Machine Timing Instruction Control and Controlled Current Output Port 5 8 Bit C T Carrier v 16 Bit C T Modulation 8 Bit C T General Contr
106. y setting the Enable Count bit back to 1 The T counter timer con tinues its count value at the time it was stopped The current value in the T4 counter timer can be read at any time without affecting the counting operation New initial values can be written to the prescaler or the counter timer registers at any time These values are transferred to their respective down counters on the next load operation If the counter timer mode is continuous the next load occurs on the timer clock following an end of count New initial values must be written before the load operation because the prescaler always effectively operates in continuous count mode If the value loaded in the T register is 01h the timer is actually not timing or counting at all the timer is passing the prescaler end of count through Because the prescaler is continuously running regardless of the single pass continuous mode operation the 8 bit timer continuously times out at the rate of the prescaler end of count if the T4 timer value is programmed to 01h P R EL tM INAR Y PS003807 1002 Z86D990 Z86D991 OTP and Z86L99X ROM Low Voltage Microcontrollers with ADC Z 40 ZiLOG The time interval i until end of count is given by i txpxv where t is 8 divided by XTAL frequency p is the prescaler value 1 64 and v is the counter timer value 1 256 The prescaler and counter timer are true divide by n counters Tout Modes The Timer Mode register TMR F1h

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