ST M29W160ET M29W160EB 16 Mbit (2Mb x8 or 1Mb x16 Boot Block) 3V Supply Flash Memory handbook
Contents
1. 39 4 40 M29W160ET M29W160EB SUMMARY DESCRIPTION The M29W160E is a 16 Mbit 2Mb x8 or 1Mb x16 non volatile memory that can be read erased and reprogrammed These operations can be per formed using a single low voltage 2 7 to 3 6V supply On power up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory Program and Erase commands are writ ten to the Command Interface of the memory An on chip Program Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents The end of a program or erase operation can be detected and any error conditions identified The Figure 2 Logic Diagram Voc 15 CL DQ0 DQ14 DQ15A 1 M29W160ET M29W160EB Vss 1068498 command set required to control the memory is consistent with JEDEC standards The blocks in the memory are asymmetrically ar ranged see Figures 5 and 6 Block Addresses The first or last 64 KBytes have been divided into four additional blocks The 16 KByte Boot Block can be used for small initialization code to2. retento Fem Te Chip Enable Output Enable or Address Transition to Output Transition ELFL Enable to BYTE Low or High tELBH tELFH 107 BYTE Low to Output Hi Z BYTE High to Output Valid Note 1 Sampled only not 10095 tested taLQv tenaz taHaz 22 40 57 M29W160ET M29W160EB Figure 12 Write AC Waveforms Write Enable Controlled ju VALID 000 007 008 0015 tVCHEL Al02923 M29W160E Parameter f 9 ox _ o oueon 9 Program Erase Valid to Low Voc High to Chip Enable Low Note 1 Sampled only not 100 tested 53 IBN BC 23 40 M29W160ET M29W160EB Figure 13 Write AC Waveforms Chip Enable Controlled jd jan VALID 000 007 008 0015 tVCHWL Al02924 M29W160E Parameter NC 53 IBN BC ww 9 ww T tVCHWL Vcc High to Write Enable Low Note 1 Sampled only not 10095 tested 24 40 M29W160ET M29W160EB Figure 14 Reset Block Temporary Unprotect AC Waveforms tRHWL tRHEL tRHGL tPHPHH Al02931B Table 15 Reset Block Temporary Unprotect AC Characteristics Parameter RP High to Write Enable Low
3. o9 ener Symbol 27 40 M29W160ET M29W160EB PART NUMBERING Table 18 Ordering Information Scheme Example M29W160EB 90 N 6 T Device Type M29 Operating Voltage W Vcc 2 7 to 3 6V Device Function 160E 16 Mbit x8 x16 Boot Block Array Matrix T Top Boot B Bottom Boot Speed 70 70 ns 90 90 ns Package N TSOP48 12 x 20 mm ZA TFBGA48 6x8 mm 0 80mm pitch Temperature Range 6 40 to 85 Option Blank Standard Packing T Tape and Reel Packing E Lead free Package Standard Packing F Lead free Package Tape amp Reel Packing Devices are shipped from the factory with the memory content bits erased to 1 For alist of available options Speed Package etc or for further information on any aspect of this device please contact the ST Sales Office nearest to you 28 40 M29W160ET M29W160EB APPENDIX A BLOCK ADDRESS TABLE Table 19 Top Boot Block Addresses Table 20 Bottom Boot Block Addresses M29W160ET M29W160EB IE ED TE eo KBytes x8 x16 KBytes x8 x16 ss s racoon Fare Ce aoooonazeren 25000 e sr coooon aeren 64
4. 2 sesonvoprrrrr _ eoooconcorrren ooooon o7eren 16 oooon o7FFFh 29 40 M29W160ET M29W160EB APPENDIX B COMMON FLASH INTERFACE CFI The Common Flash Interface is a JEDEC ap proved standardized data structure that can be read from the Flash memory device It allows a System software to query the device to determine various electrical and timing parameters density information and functions supported by the mem ory The system can interface easily with the de vice enabling the software to upgrade itself when necessary When the CFI Query Command is issued the de vice enters CFI Query mode and the data structure is read from the memory Tables 21 22 23 24 25 Table 21 Query Structure Overview M S and 26 show the addresses used to retrieve the data The CFI data structure also contains a security area where a 64 bit unique security number is writ ten see Table 26 Security Code area This area can be accessed only in Read mode by the final user It is impossible to change the security num ber after it has been written by ST Issue a Read command to return to Read mode Note The Common Flash Interface is only avail able for Temperature range 6 40 to 85 C M S CFI Query Identification String Command set ID and algorithm data offset System Interface Information Device timing amp voltage infor
5. Bus Read Bus Write ViL Standby Read Manufacturer Output Disable A0 A19 DQ15A 1 DQ14 DQO 1 9 Vip Code Vi Vi Others Vi or dd A V 1 9 Read Device Code ViL ViL redi Vin Note X or COMMAND INTERFACE All Bus Write operations to the memory are inter preted by the Command Interface Commands consist of one or more sequential Bus Write oper ations Failure to observe a valid sequence of Bus Write operations will result in the memory return ing to Read mode The long command sequences are imposed to maximize data security The address used for the commands changes de pending on whether the memory is in 16 bit or 8 bit mode See either Table 4 or 5 depending on the configuration that is being used for a summary of the commands Read Reset Command The Read Reset com mand returns the memory to its Read mode where it behaves like a ROM or EPROM unless other wise stated It also resets the errors in the Status Register Either one or three Bus Write operations can be used to issue the Read Reset command The Read Reset Command can be issued be tween Bus Write cycles before the start of a pro gram or erase operation to return the device to read mode Once the program or erase operation has started the Read Reset command is no longer accepted The Read Reset command will not abort an Erase operation when
6. ANY ADDRESS WITH A1 A6 Wait 10ms WRITE 40h ADDRESS CURRENT BLOCK ADDRESS A0 VIL A1 Vip A6 INCREMENT CURRENT BLOCK READ DATA ADDRESS CURRENT BLOCK ADDRESS AO A1 Vip YES 00h ISSUE READ RESET ISSUE READ RESET COMMAND COMMAND A103472 38 40 M29W160ET M29W160EB REVISION HISTORY Table 28 Document Revision History 06 Aug 2002 First Issue originates from M29W160D datasheet dated 24 Jun 2002 9x8mm FBGA48 package replaced by 6x8mm VDD min reduced for 70ns speed class 27 Nov 2002 1 1 Erase Suspend Latency Time typical and maximum added to Program Erase Times and Program Erase Endurance Cycles table Logic Diagram corrected 03 Dec 2002 Package information corrected in ordering information table 21 Mar 2003 20 Document promoted to full Datasheet status Block Protect and Chip Unprotect algorithms specified in Appendix BLOCK PROTECTION 27 Jun 2003 TSOP48 package information updated see Figure 15 and Table 16 26 Jan 2004 Block Erase Command clarified 39 40 M29W160ET M29W160EB Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherw
7. Bottom Boot Block Addresses M29W160EB 29 APPENDIX B COMMON FLASH INTERFACE CFl 0000 e eee e eee eee nnn 30 Table 21 Query Structure 30 Table 22 CFI Query Identification String 0 30 Table 23 CFI Query System Interface 31 Table 24 Device Geometry Definition 32 Table 25 Primary Algorithm Specific Extended Query 33 Table 26 Security Code Area eh a eee eee 33 APPENDIX C BLOCK 2 34 Programmer Technique 34 In System Technique ie ie eee ee E EX eee wees 34 Table 27 Programmer Technique Bus Operations BYTE VH Ofr VIL 34 Figure 17 Programmer Equipment Block Protect Flowchart 35 Figure 18 Programmer Equipment Chip Unprotect Flowchart 36 Figure 19 In System Equipment Block Protect 37 Figure 20 In System Equipment Chip Unprotect Flowchart 38 REVISION HISTORY es QE WE 39 Table 28 Document Revision
8. MWET M29W160EB 16 Mbit 2Mb x8 or 1Mb x16 Boot Block 3V Supply Flash Memory FEATURES SUMMARY m SUPPLY VOLTAGE Figure 1 Packages Vcc 2 7V to 3 6V for Program Erase and Read m ACCESS TIMES 70 90ns PROGRAMMING TIME 10us per Byte Word typical 35 MEMORY BLOCKS 1 Boot Block Top or Bottom Location 2 Parameter and 32 Main Blocks m PROGRAM ERASE CONTROLLER Embedded Byte Word Program C _ algorithms m ERASE SUSPEND and RESUME MODES TSOP48 N 12 x 20mm Read and Program another Block during Erase Suspend m UNLOCK BYPASS PROGRAM COMMAND Faster Production Batch Programming m TEMPORARY BLOCK UNPROTECTION FBGA MODE E m COMMON FLASH INTERFACE S 64 bit Security Code TFBGA48 ZA 6 x 8mm m LOW POWER CONSUMPTION Standby and Automatic Standby m 100 000 PROGRAM ERASE CYCLES BLOCK m ELECTRONIC SIGNATURE Manufacturer Code 0020h Device Code M29W160ET 22C4h Bottom Device Code M29W160EB 2249h January 2004 1 40 M29W160ET M29W160EB TABLE OF CONTENTS FEATURES SUMMARY eat Eaters el aed ee 1 Figure T Packages tee Ree Oe Feed aoe 1 SUMMARY DESCRIPTION 0000 cece eee eee 5 Figure 2 Logic eee 5 Table 1 Signal Names essc uc Sie earn gud as heaped a ERA ERU d 5 Figure 3 TSOP Connections lh rn 6 F
9. Chip Enable Low Output Enable Low RB High to Write Enable Low Chip Enable Low Output Enable Low Note 1 Sampled only not 100 tested MWe o M29W160ET M29W160EB PACKAGE MECHANICAL Figure 15 TSOP48 48 lead Plastic Thin Small Outline 12 x 20mm Package Outline Note Drawing is not to scale Table 16 TSOP48 48 lead Plastic Thin Small Outline 12 x 20mm Package Mechanical Data Lo pom sw _ sem BL 12 000 11 900 12 100 0 4724 0 4685 0 4764 20 000 19 800 20 200 0 7874 0 7795 0 7953 18 400 18 300 18 500 0 7244 0 7205 0 7283 Lo 0 600 0 500 0 700 0 0236 0 0197 0 0276 26 40 M29W160ET M29W160EB Figure 16 TFBGA48 6x8mm 6x8 ball array 0 80 mm pitch Package Outline BALL Ai 732 Table 17 TFBGA48 6x8mm 6x8 array 0 80 pitch Package Mechanical Data m m Tow Lo 9 om 1 99 ew sme ow amo f ees o Ce f i os m om T o om
10. an address pin DQ15A 1 Low will select the LSB of the Word on the other addresses DQ15A 1 High will select the MSB Throughout the text consider references to the Data Input Output to include this pin when BYTE is High and references to the Address In puts to include this pin when BYTE is Low except when stated explicitly otherwise Chip Enable E The Chip Enable E activates the memory allowing Bus Read and Bus Write op erations to be performed When Chip Enable is High Vin all other pins are ignored Output Enable G The Output Enable G con trols the Bus Read operation of the memory Write Enable W The Write Enable W controls the Bus Write operation of the memory s Com mand Interface Reset Block Temporary Unprotect RP The Reset Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected A Hardware Reset is achieved by holding Reset Block Temporary Unprotect Low for at least After Reset Block Temporary Unprotect goes High Viu the memory will be ready for Bus 10 40 Read and Bus Write operations after tpHeL or tRHEL whichever occurs last See the Ready Busy Output section Table 15 and Figure 14 Reset Temporary Unprotect AC Characteristics for more details Holding RP at Vip will temporarily unprotect the protected Blocks in the memory Program and Erase operations on all blo
11. issued while in Erase Suspend Auto Select Command The Auto Select com mand is used to read the Manufacturer Code the Device Code and the Block Protection Status Three consecutive Bus Write operations are re quired to issue the Auto Select command Once the Auto Select command is issued the memory remains in Auto Select mode until a Read Reset command is issued Read CFI Query and Read Reset commands are accepted in Auto Select mode all other commands are ignored 12 40 22C4h M29W160ET 2249h M29W160EB From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with AO and A1 The other address bits may be set to either The Manufacturer Code for STMicroelectronics is 0020h The Device Code can be read using a Bus Read operation with AO and A1 The other address bits may be set to either or The Device Code for the M29W160ET is 22C4h and for the M29W160EB is 2249h The Block Protection Status of each block can be read using a Bus Read operation with AO A1 and A12 A19 specifying the address of the block The other address bits may be to ei ther Vi or Vip If the addressed block is protected then is output on Data Inputs Outputs DQO 007 otherwise 001 is output Program Command The Program command can be used to program a value to one address in the memory array at a time The command re quires four Bus Write ope
12. x16 FFFFFh 32 KWord F8000h F7FFFh F0000h Total of 31 32 KWord Blocks Total of 31 32 KWord Blocks 32 KWord 00000h Al06852 Note Also see Appendix A Tables 19 and 20 for a full listing of the Block Addresses 9 40 M29W160ET M29W160EB SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram and Table 1 Signal Names for a brief overview of the signals connect ed to this device Address Inputs A0 A19 The Address Inputs select the cells in the memory array to access dur ing Bus Read operations During Bus Write opera tions they control the commands sent to the Command Interface of the Program Erase Con troller Data Inputs Outputs DQ0 DQ7 The Data In puts Outputs output the data stored at the selected address during a Bus Read operation During Bus Write operations they represent the commands sent to the Command Interface of the Program Erase Controller Data Inputs Outputs DQ8 DQ14 The Data In puts Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High When BYTE is Low these pins are not used and are high impedance During Bus Write operations the Command Register does not use these bits When reading the Status Register these bits should be ignored Data Input Output or Address Input DQ15A 1 When BYTE is High this pin behaves as Data Input Output as 008 0014 When BYTE is Low this pin behaves as
13. ENS tbe e Ne be Ree ARN ER n 11 Standby d peu x es PD UDIN VENUS EX e 11 Automatic Standby eye ded ce Robe e den d e Eon eR e dn de e yd 11 Special B s Operatlons 5 PR RERO bod x eins RC OC RC EOS UR I EGRE 11 Electronic Signature RE 0 11 Block Protection and Blocks 11 Table 2 Bus Operations BYTE tees 11 Table 3 Bus Operations BYTE 2 12 COMMAND INTERFACE 000 2 eee eee 12 Read Reset eee eee 12 Auto Select Command e ee b RR don E EUR ROC ROS RR 12 Program Command neci tala murem a IRR a POM iR Pd 12 Unlock Bypass Command hm 13 Unlock Bypass Program 13 Unlock Bypass Reset Command ee 13 2 40 57 M29W160ET M29W160EB Chip Erase Command x ynn ah Od ee ge 13 Block Erase Gommlard age ahead ddd ARES ed 13 Erase Suspend Command a ss cs seraa 0 13 Erase Resume Command E Y 14 Read CFI Query Command ts saraat ioaad tee ae 14 Table 4 Commands 16 bit mo
14. Each additional block must therefore be selected within 5Ops of the last block The 50us timer restarts when an additional block is selected The Status Register can be read after the sixth Bus Write operation See the Status Register sec tion for details on how to identify if the Program Erase Controller has started the Block Erase oper ation If any selected blocks are protected then these are ignored and all the other selected blocks are erased If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 1005 leaving the data un changed No error condition is given when protect ed blocks are ignored During the Block Erase operation the memory will ignore all commands except the Erase Suspend command Typical block erase times are given in Table 6 All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs Outputs See the section on the Status Register for more details After the Block Erase operation has completed the memory will return to the Read Mode unless an error has occurred When an error occurs the memory will continue to output the Status Regis ter A Read Reset command must be issued to re set the error condition and return to Read mode The Block Erase Command sets all of the bits in the unprotected selected blocks to 1 All previous data in the selected blocks is lost Erase Suspend Command The Erase
15. Erase operation ap pears to start but will terminate within about 100us leaving the data unchanged No error condition is given when protected blocks are ignored During the erase operation the memory will ignore all commands It is not possible to issue any com mand to abort the operation Typical chip erase y M29W160ET M29W160EB times are given in Table 6 All Bus Read opera tions during the Chip Erase operation will output the Status Register on the Data Inputs Outputs See the section on the Status Register for more details After the Chip Erase operation has completed the memory will return to the Read Mode unless an error has occurred When an error occurs the memory will continue to output the Status Regis ter A Read Reset command must be issued to re set the error condition and return to Read Mode The Chip Erase Command sets all of the bits in un protected blocks of the memory to 1 All previous data is lost Block Erase Command The Block Erase com mand can be used to erase a list of one or more blocks Six Bus Write operations are required to select the first block in the list Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block The Block Erase operation starts the Program Erase Controller about 50us after the last Bus Write operation Once the Program Erase Controller starts it is not possible to select any more blocks
16. Read Reset command read the memory as normal until another command is issued Auto Select After an Auto Select command read Manufacturer ID Device ID or Block Protection Status Program Unlock Bypass Program Chip Erase Block Erase After these commands read the Status Register until the Program Erase Controller completes and the memory returns to Read Mode Add additional Blocks during Block Erase Command with additional Bus Write Operations until Timeout Bit is set Unlock Bypass After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands Unlock Bypass Reset After the Unlock Bypass Reset command read the memory as normal until another command is issued Erase Suspend After the Erase Suspend command read non erasing memory blocks as normal issue Auto Select and Program com mands on non erasing blocks as normal Erase Resume After the Erase Resume command the suspended Erase operation resumes read the Status Register until the Pro gram Erase Controller completes and the memory returns to Read Mode Query Command is valid when device is ready to read array data or when device is in Auto Select mode 15 40 M29W160ET M29W160EB Table 5 Commands 8 bit mode BYTE Vit Unlock Bypass Program Note X Don t Care PA Program Address PD Program Data BA Any address in the Block All values in the table are in hexadecimal The Command Interface only uses 1 A0 A10 and DQO DQ7 to v
17. Suspend Command may be used to temporarily suspend a 13 40 M29W160ET M29W160EB Block Erase operation and return the memory to Read mode The command requires one Bus Write operation The Program Erase Controller will suspend within the Erase Suspend Latency Time refer to Table 6 for value of the Erase Suspend Command being issued Once the Program Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended If the Erase Suspend command is issued during the period when the memory is waiting for an additional block before the Program Erase Controller starts then the Erase is suspended immediately and will start im mediately when the Erase Resume Command is issued It is not possible to select any further blocks to erase after the Erase Resume During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased both Read and Program operations behave as normal on these blocks If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged The Status Register is not read and no error condition is given Read ing from blocks that are being erased will output the Status Register It is also possible to issue the Auto Select Read CFI Query and Unlock Bypass commands during 14 40 an Erase Suspend The Read Reset command must be issued to return the device to Read Array mode
18. Vip Data Inputs Outputs DQ15A 1 DQ14 DQ0 A0 A19 Others X Others X Pass XX01h Others X Retry XX00h Retry XX01h Others X Pass M29W160ET M29W160EB Figure 17 Programmer Equipment Block Protect Flowchart AI03469b Note 1 Address Inputs A19 A12 give the address of the block that is to be protected It is imperative that they remain stable during the operation 6 2 During the Protect and Verify phases of the algorithm Chip Enable E must be kept Low Vi 35 40 M29W160ET M29W160EB Figure 18 Programmer Equipment Chip Unprotect Flowchart START PROTECT ALL BLOCKS n 0 CURRENT BLOCK 0 Unprotect INCREMENT CURRENT BLOCK AI03470 36 40 M29W160ET M29W160EB Figure 19 In System Equipment Block Protect Flowchart WRITE 60h ADDRESS BLOCK ADDRESS Vj A1 A6 VIL WRITE 60h ADDRESS BLOCK ADDRESS A1 Vip VIL Wait 100 5 WRITE 40h ADDRESS BLOCK ADDRESS Vj A1 VIL Wait 4 5 READ DATA ADDRESS BLOCK ADDRESS Vj A1 Vip A6 VIL ISSUE READ RESET COMMAND ISSUE READ RESET COMMAND A103471 37 40 M29W160ET M29W160EB Figure 20 In System Equipment Chip Unprotect Flowchart START PROTECT ALL BLOCKS n CURRENT BLOCK 0 WRITE 60h ANY ADDRESS WITH A0 VIL A1 Vip A6 WRITE 60h
19. before the Resume command will be ac cepted Erase Resume Command The Erase Resume command must be used to restart the Program Erase Controller from Erase Suspend An erase can be suspended and resumed more than once Read CFI Query Command The Read CFI Query Command is used to read data from the Common Flash Interface Memory Area This command is valid when the device is in the Read Array mode or when the device is in Auto Select mode One Bus Write cycle is required to issue the Read CFI Query Command Once the command is is sued subsequent Bus Read operations read from the Common Flash Interface Memory Area The Read Reset command must be issued to re turn the device to the previous mode the Read Ar ray mode or Auto Select mode A second Read Reset command would be needed if the device is to be put in the Read Array mode from Auto Select mode See Appendix B Tables 21 22 23 24 25 and 26 for details on the information contained in the Common Flash Interface CFI memory area M29W160ET M29W160EB Table 4 Commands 16 bit mode BYTE Unlock Bypass Program Note X Don t Care PA Program Address PD Program Data BA Any address in the Block All values in the table are in hexadecimal The Command Interface only uses 1 A0 A10 and 200 007 to verify the commands A11 A19 DQ8 DQ14 and DQ15 Don t Care DQ15A 1 is A 1 when BYTE is or DQ15 when BYTE is Read Reset After a
20. cks will be possible The transition from to Vip must be slower than Ready Busy Output The Ready Busy is an open drain output that can be used to identify when the device is performing a Program or Erase operation During Program or Erase operations Ready Busy is Low Voi Ready Busy is high im pedance during Read mode Auto Select mode and Erase Suspend mode After a Hardware Reset Bus Read and Bus Write operations cannot begin until Ready Busy be comes high impedance See Table 15 and Figure 14 Reset Temporary Unprotect AC Characteris tics The use of an open drain output allows the Ready Busy pins from several memories to be connected to a single pull up resistor A Low will then indicate that one or more of the memories is busy Byte Word Organization Select BYTE The Byte Word Organization Select pin is used to switch between the 8 bit and 16 bit Bus modes of the memory When Byte Word Organization Se lect is Low the memory is in 8 bit mode when itis High the memory is in 16 bit mode Vcc Supply Voltage The Vcc Supply Voltage supplies the power for all operations Read Pro gram Erase etc The Command Interface is disabled when the Vcc Supply Voltage is less than the Lockout Voltage Vi xo This prevents Bus Write operations from ac cidentally damaging the data during power up power down and power surges If the Program Erase Controller is programming or erasi
21. de BYTE 15 Table 5 Commands 8 bit mode BYTE 16 Table 6 Program Erase Times and Program Erase Endurance 5 17 STATUS REGISTER gun TI ELIT IRE eae bate 17 Data Polling Bit DQ7 ehem Re etm E Germ Ron ese n E deg 17 Toggle Bit xol asse todos AU 17 Error Bit DOS tem eS ev Ne lesen s 17 Erase Timer Bit 003 a 18 Alternative Toggle Bit 002 2 RR Rh 18 Table 7 Status Register lt 18 Figure 7 Data Polling Flowchart 19 Figure 8 Data Toggle 0 19 MAXIMUM RATING ERR Ere Ae ee 19 Table 8 Absolute Maximum Ratings lise n 19 AC PARAMETERS ey teed RR E er ETE 20 Table 9 Operating and AC Measurement 5 20 Figure 9 AC Measurement I O 20 Figure 10 AC Measurement Load Circuit 20 Table 10 Device 2 2 a e i aea EEEE hr rn 20 Table 11 DC Characteristics 2 0 0 0c ttt eee 21 Figu
22. e Suspend Latency Time Program Byte or Word Chip Program Byte by Byte Chip Program Word by Word Program Erase Cycles per Block Data Retention Note 1 Typical values measured at room temperature and nominal voltages 2 Sampled but not 100 tested 3 Maximum value measured at worst case conditions for both temperature and Vcc after 100 000 program erase cycles 4 Maximum value measured at worst case conditions for both temperature and Vcc STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations It is also read during Erase Sus pend when an address within a block being erased is accessed The bits in the Status Register are summarized in Table 7 Status Register Bits Data Polling Bit DQ7 The Data Polling Bit can be used to identify whether the Program Erase Controller has successfully completed its opera tion or if it has responded to an Erase Suspend The Data Polling Bit is output on DQ7 when the Status Register is read During Program operations the Data Polling Bit outputs the complement of the bit being pro grammed to 007 After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the ad dress just programmed output DQ7 not its com plement During Erase operations the Data Polling Bit out puts 0 the complement of the erased state of 007 After successful completion o
23. erify the commands 11 19 DQ8 DQ14 and DQ15 are Don t Care DQ15A 1 is 1 when BYTE is DQ15 when BYTE is Read Reset After a Read Reset command read the memory as normal until another command is issued Auto Select After an Auto Select command read Manufacturer ID Device ID or Block Protection Status Program Unlock Bypass Program Chip Erase Block Erase After these commands read the Status Register until the Program Erase Controller completes and the memory returns to Read Mode Add additional Blocks during Block Erase Command with additional Bus Write Operations until Timeout Bit is set Unlock Bypass After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands Unlock Bypass Reset After the Unlock Bypass Reset command read the memory as normal until another command is issued Erase Suspend After the Erase Suspend command read non erasing memory blocks as normal issue Auto Select and Program com mands on non erasing blocks as normal Erase Resume After the Erase Resume command the suspended Erase operation resumes read the Status Register until the Pro gram Erase Controller completes and the memory returns to Read Mode Query Command is valid when device is ready to read array data or when device is in Auto Select mode 16 40 M29W160ET M29W160EB Table 6 Program Erase Times and Program Erase Endurance Cycles Chip Erase Block Erase 64 KBytes Eras
24. f the Erase op eration the memory returns to Read Mode In Erase Suspend mode the Data Polling Bit will output 1 during a Bus Read operation within a block being erased The Data Polling Bit will change from a 0 to a 1 when the Program Erase Controller has suspended the Erase operation Figure 7 Data Polling Flowchart gives an exam ple of how to use the Data Polling Bit A Valid Ad dress is the address being programmed or an address within the block being erased Toggle Bit 006 The Toggle Bit be used identify whether the Program Erase Controller has successfully completed its operation or if it has re sponded to an Erase Suspend The Toggle Bit is output on DQ6 when the Status Register is read During Program and Erase operations the Toggle Bit changes from 0 to 1 to 0 etc with succes sive Bus Read operations at any address After successful completion of the operation the memo ry returns to Read mode During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased The Toggle Bit will stop toggling when the Program Erase Controller has suspended the Erase operation If any attempt is made to erase a protected block the operation is aborted no error is signalled and DQ6 toggles for approximately 100 5 If any tempt is made to program a protected block or a suspended block the operation is aborted no er ror is signalled and DQ6 to
25. ggles for approximately ius Figure 8 Data Toggle Flowchart gives an exam ple of how to use the Data Toggle Bit Error Bit 005 The Error Bit can be used to identify errors detected by the Program Erase Controller The Error Bit is set to 1 when a gram Block Erase or Chip Erase operation fails to write the correct data to the memory If the Error Bit is set a Read Reset command must be issued before other commands are issued The Error bit is output on DQ5 when the Status Register is read 17 40 M29W160ET M29W160EB Note that the Program command cannot change a bit set to 0 back to 1 and attempting to do so will set DQ5 to 1 A Bus Read operation to that ad dress will show the bit is still 0 One of the Erase commands must be used to set all the bits in a block or in the whole memory from 0 to 1 Erase Timer Bit DQ3 The Erase Timer Bit can be used to identify the start of Program Erase Controller operation during a Block Erase com mand Once the Program Erase Controller starts erasing the Erase Timer Bitis set to 1 Before the Program Erase Controller starts the Erase Timer Bit is set to 0 and additional blocks to be erased may be written to the Command Interface The Erase Timer Bit is output on DQ3 when the Status Register is read Alternative Toggle Bit DQ2 The Alternative Toggle Bit can be used to monitor the Program Erase controller during Erase operations The Al ternative Togg
26. igure 4 TFBGA Connections Top view through package 7 Figure 5 Block Addresses 8 lisse nen 8 Figure 6 Block Addresses 16 cee te 9 SIGNAL DESCRIPTIONS han tnnt 10 Address Inputs A0 A19 e a dunk e e dg 10 Data Inputs Outputs DQ0 DQ7 tees 10 Data Inputs Outputs DQ8 DQ14 III 10 Data Input Output or Address Input 1 10 Ghip Enable E eria 10 O tput Ense tele tse eae bct ies ete das 10 Write Enable WT 44 s ttl e S ME ee tuam S d nee 10 Reset Block Temporary Unprotect 10 Ready Busy E iss utl MA s o 10 Byte Word Organization Select 10 Supply Voltage EIE tines 10 Ground urea tee eee ecc kta ale wing dec ue as dels i 10 BUS OPERATIONS eae eas aie ee sce eee ae ee ee Sete 11 Bus Read caws eae eth 11 BUS Write e E EE p gc an e a pd m Pee dp e gues 11 OUTPUT Disable sede S R
27. ise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2004 STMicroelectronics All rights reserved STMicroelectronics GROUP OF COMPANIES Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www st com 40 40
28. le Bit is output on DQ2 when the Status Register is read Table 7 Status Register Bits During Chip Erase and Block Erase operations the Toggle Bit changes from 0 to 1 to 0 etc with successive Bus Read operations from addresses within the blocks being erased A protected block is treated the same as a block not being erased Once the operation completes the memory returns to Read mode During Erase Suspend the Alternative Toggle Bit changes from 0 to 1 to 0 etc with successive Bus Read operations from addresses within the blocks being erased Bus Read operations to ad dresses within blocks not being erased will output the memory cell data as if in Read mode After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the er ror The Alternative Toggle Bit changes from 0 to 1 to 0 etc with successive Bus Read Opera tions from addresses within blocks that have not erased correctly The Alternative Toggle Bit does not change if the addressed block has erased cor rectly Ames 5 995 L NENNT 5 Program During Erase Program Error Error Any Address Address ee 9 MEC timeout 5 ee Non Erasing Block Block Erase E
29. ll output data if a Bus Read operation is in progress Special Bus Operations Additional bus opera tions can be performed to read the Electronic Sig nature and also to apply and remove Block Protection These bus operations are intended for use by programming equipment and are not usu ally used in applications They require Vip to be applied to some pins Electronic Signature The memory has two codes the manufacturer code and the device code that can be read to identify the memory These codes can be read by applying the signals listed in Tables 2 and 3 Bus Operations Block Protection and Blocks Unprotection Each block can be separately protected against accidental Program or Erase Protected blocks can be unprotected to allow data to be changed There are two methods available for protecting and unprotecting the blocks one for use on pro gramming equipment and the other for in system use Block Protect and Blocks Unprotect opera tions are described in Appendix C DIE Address Inputs Data Inputs Outputs DQ15A 1 A0 A19 0014 008 007 000 Bus Write VIL Output Disable Read Manufacturer Standby Vi A1 Vii A9 Vit Vit Others or ie 20h AO A1 A9 Read Device Code VIL ViL A MS ID Hi Z Note X or C4h M29W160ET 49h M29W160EB 11 40 M29W160ET M29W160EB Table 3 Bus Operations BYTE Operation
30. mand Once the Unlock Bypass command has been is sued the memory will only accept the Unlock By pass Program command and the Unlock Bypass Reset command The memory can be read as if in Read mode Unlock Bypass Program Command The Un lock Bypass Program command can be used to program one address in memory at a time The command requires two Bus Write operations the final write operation latches the address and data and starts the Program Erase Controller The Program operation using the Unlock Bypass Program command behaves identically to the Pro gram operation using the Program command A protected block cannot be programmed the oper ation cannot be aborted and the Status Register is read Errors must be reset using the Read Reset command which leaves the device in Unlock By pass Mode See the Program command for details on the behavior Unlock Bypass Reset Command The Unlock Bypass Reset command can be used to return to Read Reset mode from Unlock Bypass Mode Two Bus Write operations are required to issue the Unlock Bypass Reset command Read Reset command does not exit from Unlock Bypass Mode Chip Erase Command The Chip Erase com mand can be used to erase the entire chip Six Bus Write operations are required to issue the Chip Erase Command and start the Program Erase Controller If any blocks are protected then these are ignored and all the other blocks are erased all of the blocks are protected the Chip
31. marized in Table 9 Operating and ment conditions and the DC and AC characteris AC Measurement Conditions Designers should tics of the device The parameters in the DC and check that the operating conditions in their circuit AC characteristics Tables that follow are derived match the operating conditions when relying on from tests performed under the Measurement the quoted parameters Table 9 Operating and AC Measurement Conditions M29W160E 9 Parameter Load Capacitance CL Figure 9 AC Measurement I O Waveform Figure 10 AC Measurement Load Circuit Voc 2 DEVICE 104498 UNDER TEST C includes JIG capacitance A104499 Table 10 Device Capacitance Note Sampled only not 100 tested 20 40 M29W160ET M29W160EB Table 11 DC Characteristics lo Output Leakage Current Leakage Current OV lt Vout lt Vcc Vcc 0 2 Supply Current Program Erase Program Erase Controller active So a me _____ een ee fomne meme xew We memes 8 __ 5 Y e Supply Voltage Note 1 Sampled only not 100 tested 21 40 M29W160ET M29W160EB Figure 11 Read Mode AC Waveforms A0 A19 1 tEHQZ gt 000 007 008 0015 tELBL tELBH tBLQZ 102922 Table 12 Read AC Characteristics
32. mation 4Eh _ Device Device Geometry Definition Flash device layout Algorithm specific Extended Additional information specific to the Primary Query table Algorithm optional 64 bit unique device number Note Query data are always presented on the lowest order data outputs Table 22 CFI Query Identification String Address Description Value Query Unique ASCII String QRY 13h 0002h Primary Algorithm Command Set and Control Interface ID code 16 bit AMD 14h 0000 code defining a specific algorithm Compatible 15h 0040h Address for Primary Algorithm extended Query table see Table 24 P 40h 16h 2Ch 0000h 17h 2Eh 0000h Alternate Vendor Command Set and Control Interface ID Code second NA 18h 0000 Vendor specified algorithm supported 19h 0000h Address for Alternate Algorithm extended Query table 1Ah 0000h Note Query data are always presented on the lowest order data outputs DQ7 DQ0 only DQ8 DQ15 are 0 30 40 M29W160ET M29W160EB Table 23 CFI Query System Interface Information Address Description E mE Logic Supply Minimum Program Erase voltage 1Bh 36h 0027h bit 7 to 4BCD value in volts bit 3 to OBCD value in 100 mV Vcc Logic Supply Maximum Program Erase voltage 1Ch 38h 0036h bit 7 to 4BCD value in volts bit 3 to OBCD value in 100 mV aor evar Sosy nan Pavan as ter o
33. ng during this time then the operation aborts and the memo ry contents being altered will be invalid capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply The PCB track widths must be sufficient to carry the currents required during program and erase operations Vss Ground The Vss Ground is the reference for all voltage measurements The two Vss pins of the device must be connected to the system ground BUS OPERATIONS There are five standard bus operations that control the device These are Bus Read Bus Write Out put Disable Standby and Automatic Standby See Tables 2 and 3 Bus Operations for a summary Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations Bus Read Bus Read operations read from the memory cells or specific registers in the Com mand Interface A valid Bus Read operation in volves setting the desired address on the Address Inputs applying a Low signal to Chip Enable and Output Enable and keeping Write Enable High The Data Inputs Outputs will output the value see Figure 11 Read Mode AC Waveforms and Table 12 Read AC Characteristics for details of when the output becomes valid Bus Write Bus Write operations write to the Command Interface A valid Bus Write operation begins by setting the desired add
34. r evar mum Posters om wsaiesapesseme enne ra _ 31 40 M29W160ET M29W160EB Table 24 Device Geometry Definition Description EINE 0015h Device Size 2 in number of Bytes 28h 50h 0002h 5 0000h Flash Device Interface Code description 2Ah 4h h UR Maximum number of Bytes in multi Byte program or page 2 Number of Erase Block Regions within the device 2Ch 58h 0004h It specifies the number of regions within the device containing contiguous Erase Blocks of the same size 2Dh 5Ah 0000h Region 1 Information 2Eh 5Ch 0000h Number of identical size erase block 0000h 1 2Fh 5Eh 0040h Region 1 Information 16 KByte 30h 60h 0000h Block size in Region 1 0040h 256 Byte y 31h 62h 0001h Region 2 Information 2 64h 0000h Number of identical size erase block 0001h 1 33h 66h 0020h Region 2 Information 34h 68h 0000h Block size in Region 2 0020h 256 Byte 35h 6Ah 0000h Region 3 Information 1 36h 6Ch 0000h Number of identical size erase block 0000h 1 37h 6Eh 0080h Region 3 Information 32 KByte 38h 70h 0000h Block size in Region 3 0080h 256 Byte 39h 72h 001Eh Region 4 Information 31 3Ah 74h 0000h Number of identical size erase block 001Eh 1 3Bh 76h 0000h Region 4 Information 64 KByte 3Ch 78h 0001h Block size in Region 4 0100h 256 Byte 32 40 M29W160ET M29W160EB Table 25 Primary Algorithm Specific Extended Query Table x T Description Value HH Primary Algorithm ex
35. rations the final write op eration latches the address and data and starts the Program Erase Controller If the address falls in a protected block then the Program command is ignored the data remains unchanged The Status Register is never read and no error condition is given During the program operation the memory will ig nore all commands It is not possible to issue any command to abort or pause the operation Typical program times are given in Table 6 Bus Read op erations during the program operation will output the Status Register on the Data Inputs Outputs See the section on the Status Register for more details After the program operation has completed the memory returns to the Read mode unless an error 1577 has occurred When an error occurs the memory continues to output the Status Register A Read Reset command must be issued to reset the error condition and return to Read mode Note that the Program command cannot change a bit set at 0 back to 1 One of the Erase Com mands must be used to set all the bits in a block or in the whole memory from 0 to 1 Unlock Bypass Command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memo ry When the access time to the device is long as with some EPROM programmers considerable time saving can be made by using these com mands Three Bus Write operations are required to issue the Unlock Bypass com
36. re 11 Read Mode AC Waveforms 00 00 en 22 Table 12 Read AC 5 22 Figure 12 Write AC Waveforms Write Enable 23 Table 13 Write AC Characteristics Write Enable Controlled 23 Figure 13 Write AC Waveforms Chip Enable Controlled 24 Table 14 Write AC Characteristics Chip Enable 24 Figure 14 Reset Block Temporary Unprotect 25 Table 15 Reset Block Temporary Unprotect AC Characteristics 25 PACKAGE hm ham rnm hn nnn 26 Figure 15 TSOP48 48 lead Plastic Thin Small Outline 12 x 20mm Package Outline 26 Table 16 TSOP48 48 lead Plastic Thin Small Outline 12 x 20mm Package Mechanical Data 26 Figure 16 TFBGA48 6x8mm 6x8 ball array 0 80 mm pitch Package Outline 27 Table 17 TFBGA48 6x8mm 6x8 ball array 0 80 mm pitch Package Mechanical Data 27 PART NUMBERING gt nm 28 Table 18 Ordering Information Scheme 2 28 3 40 M29W160ET M29W160EB APPENDIX A BLOCK ADDRESS TABLE 00 eee eee eee eee eee 29 Table 19 Top Boot Block Addresses 2 160 29 Table 20
37. ress on the Ad dress Inputs The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable whichever occurs last The Data Inputs Outputs are latched by the Com mand Interface on the rising edge of Chip Enable or Write Enable whichever occurs first Output En able must remain High during the whole Bus Write operation See Figures 12 and 13 Write AC Waveforms and Tables 13 and 14 Write AC Characteristics for details of the timing require ments Output Disable The Data Inputs Outputs are in the high impedance state when Output Enable is High Standby When Chip Enable is High the memory enters Standby mode and the Data In puts Outputs pins are placed in the high imped Table 2 Bus Operations BYTE Vii M29W160ET M29W160EB ance state To reduce the Supply Current to the Standby Supply Current 2 Chip Enable should be held within Vcc 0 2V For the Standby current level see Table 11 DC Characteristics During program or erase operations the memory will continue to use the Program Erase Supply Current for Program or Erase operations un til the operation completes Automatic Standby If CMOS levels 0 2V are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is re duced to the Standby Supply Current 2 The Data Inputs Outputs will sti
38. rror Note Unspecified data bits should be ignored 18 40 Data read as normal WEN uses wee Fumo asses v Toone 1 Tone Figure 7 Data Polling Flowchart M29W160ET M29W160EB Figure 8 Data Toggle Flowchart READ DQ5 amp DQ7 at VALID ADDRESS READ DQ7 at VALID ADDRESS PASS AI03598 READ DQ6 READ DQ5 amp DQ6 DQ6 TOGGLE YES READ DQ6 TWICE Al01370C MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per manent damage to the device Exposure to Abso lute Maximum Rating conditions for extended periods may affect device reliability These are stress ratings only and operation of the device at Table 8 Absolute Maximum Ratings these or any other conditions above those indicat ed in the Operating sections of this specification is not implied Refer also to the STMicroelectronics SURE Program and other relevant quality docu ments Temperature Under Bias Storage Temperature Input or Output Voltage 1 2 Identification Voltage Note 1 Minimum voltage may undershoot to 2V during transition and for less than 20ns during transitions 2 Maximum voltage may overshoot to Vcc 2 during transition and for less than 20ns during transitions 19 40 M29W160ET M29W160EB DC AND AC PARAMETERS This section summarizes the operating measure Conditions sum
39. scribed in the Signal De scriptions section Unlike the Command Interface of the Program Erase Controller the techniques for protecting and unprotecting blocks could change between differ ent Flash memory suppliers Programmer Technique The Programmer technique uses high volt age levels on some of the bus pins These cannot be achieved using a standard microprocessor bus therefore the technique is recommended only for use in Programming Equipment To protect a block follow the flowchart in Figure 17 Programmer Equipment Block Protect Flowchart During the Block Protect algorithm the A19 A12 Address Inputs indicate the address of the block to be protected The block will be correctly protected only if A19 A12 remain valid and stable and if Chip Enable is kept Low Vj all along the Protect and Verify phases The Chip Unprotect algorithm is used to unprotect all the memory blocks at the same time This algo rithm can only be used if all of the blocks are pro tected first To unprotect the chip follow Figure 18 Programmer Equipment Chip Unprotect Flow chart Table 27 Programmer Technique Bus Op erations gives a Summary of each operation The timing on these flowcharts is critical Care should be taken to ensure that where a pause is specified it is followed as closely as possible Do not abort the procedure before reaching the end Chip Unprotect can take several seconds and a user message should be provided
40. start the microprocessor the two 8 KByte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the ap plication may be stored Chip Enable Output Enable and Write Enable sig nals control the bus operation of the memory They allow simple connection to most micropro cessors often without additional logic The memory is offered TSOP48 12 x 20mm and TFBGA48 0 8mm pitch packages The memory is supplied with all the bits erased set to 1 Table 1 Signal Names es romrom 5 40 M29W160ET M29W160EB Figure 3 TSOP Connections Al06850 6 40 M29W160ET M29W160EB Figure 4 TFBGA Connections Top view through package CAM A PLN PLEN 0010 Seer emt 1009 part Al02985B 7 40 M29W160ET M29W160EB Figure 5 Block Addresses x8 M29W160ET Top Boot Block Addresses x8 16 KByte 32 KByte 1EFFFFh 64 KByte 1E0000h 64 KByte 64 KByte 000000h 64 KByte Blocks M29W160EB Bottom Boot Block Addresses x8 64 KByte 64 KByte 1E0000h Total of 31 64 KByte Blocks 64 KByte 32 KByte 16 KByte 106851 Note Also see Appendix A Tables 19 and 20 for full listing of the Block Addresses 8 40 M29W160ET M29W160EB Figure 6 Block Addresses x16 M29W160ET M29W160EB Top Boot Block Addresses x16 Bottom Boot Block Addresses
41. tended Query table unique ASCII string PRI Lm sm Lm oem Dum proren s 0000h Address Sensitive Unlock bits 1 to 0 00 required 01 2 not required Silicon Revision Number bits 7 to 2 0002h Erase Suspend 00 not supported 01 Read only 02 Read and Write 47h 8bh 0001h Block Protection 1 00 not supported x number of blocks in per group 48h 90h 0001h Temporary Block Unprotect Yes 00 not supported 01 supported 49h 92h 0004h Block Protect Unprotect 4 04 M29W400B 4 0000h Simultaneous Operations 00 not supported No 0000h Burst Mode 00 not supported 01 supported No 0000h Page Mode 00 not supported 01 4 page Word 02 8 page Word Table 26 Security Code Area Address a ge Description C3h C5h C7h C6h C9h C8h 64 bit unique device number 33 40 M29W160ET M29W160EB APPENDIX C BLOCK PROTECTION Block protection can be used to prevent any oper ation from modifying the data stored in the Flash memory Each Block can be protected individually Once protected Program and Erase operations on the block fail to change the data There are three techniques that can be used to control Block Protection these are the Program mer technique the In System technique and Tem porary Unprotection Temporary Unprotection is controlled by the Reset Block Temporary Unpro tection pin RP this is de
42. to show that the operation is progressing In System Technique The In System technique requires a high voltage level on the Reset Blocks Temporary Unprotect pin RP This can be achieved without violating the maximum ratings of the components on the micro processor bus therefore this technique is suitable for use after the Flash memory has been fitted to the system To protect a block follow the flowchart in Figure 19 In System Block Protect Flowchart To unprotect the whole chip it is necessary to protect all of the blocks first then all the blocks can be unprotected at the same time To unprotect the chip follow Fig ure 20 In System Chip Unprotect Flowchart The timing on these flowcharts is critical Care should be taken to ensure that where a pause is specified it is followed as closely as possible Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the pro cedure before reaching the end Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing Table 27 Programmer Technique Bus Operations BYTE or Vit Block Protect Block Protection Verify Block Unprotection Verify 34 40 Address Inputs A12 A19 Block Address A9 A12 A15 Vin Vii A1 Vin A6 A9 Vip A12 A19 Block Address A12 A19 Block Address Vit A1 Vin Vin A9
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ST M29W160ET M29W160EB 16 Mbit (2Mb x8 or 1Mb x16 Boot Block) 3V Supply Flash Memory handbook