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RENESAS Regarding the change of names mentioned in the document such as Mitsubishi Electric Mitsubishi XX to Renesas Technology Corp. handbook

1. 144P6Q A MMP Plastic 144pin 20X20mm body LQFP EIAJ Package Code JEDEC Code Weight g Lead Material LQFP144 P 2020 0 50 1 23 Cu Alloy HD D AAARARAARARARRRAARAAAAARARARARRARARA d Os O O o Recommended Mount Pad E E Symbol Dimension in Millimeters r y Min Nom Max E A 17 A1 0 05 0 125 0 2 E ud A2 14 E b 0 17 022 027 c 0 105 0 125 0 175 D 199 20 0 20 1 E 199 200 201 e 0 5 eO 3 Ho 218 220 222 EEEEEREEREEELTECEEEEEEEEEEEEGTEGTT A IR HE 218 22 0 22 2 6 A L 0 35 0 5 0 65 Kap Li L1 1 0 F m Lp 0 45 0 6 0 75 e A3 0 25 a El x E 0 08 Ju woh e y i 0 1 i Lu Ted 8 0 8 b z ule b2 0225 J y gt lt x l2 0 95 Detail F Lp MD E 204 E ME 20 4 322 24 NE SAS Renesas Technology Corp Revision history Mitsubishi Microcomputers M16C 80 group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Revision History Version Contents for change Page 1 line 5 1 M byte gt 16 M bytes Page 1 line 15 10 MHz with software one wait gt 10 MHz under planning Page 1 line 16 35 mW f XIN 220MHz without software wait Vcc 5V M30800MC XXXFP target value gt 45 mA M30800MC XXXFP Page 1 X Y converter 1 circuit Addition Page 4 line 28 35 mA gt 45 mA Page 6 figure 1 1 4 Page 18 figure 1 5 4 and corresponding pages 106 Peri
2. A D control register 0 address 039616 Addresses 038116 038016 038316 038216 ET A D register 0 A D register 1 038516 038416 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F 16 038E16 A D register 3 A D register 4 16 16 A D register 2 16 16 16 Decoder A D register 5 16 A D register 6 16 16 A D register 7 AAAAAAA AA Comparator Data bus high order Data bus low order YYYvYvvv CH2CHi CH0 000 Oo Qc Q8 D e p oS ow CH2 CH1 CH0 001 CH2 CH1 CH0 010 CH2 CH1 CH0 01 1 OPA1 0PA0 0 0 O0 76 4 CH2 CH1 CH0 100 CH2 CH1 CH0 101 CH2 CH1 CH0 110 CH2 CH1 CHO 111 OOO00 0 0 O OPA1 OPAO 0 0 Normal operation 0 1 ANEXO 1 0 ANEX1 1 1 External op amp mode OPA1 OPA0 1 1 RS NI OPA1 0PA0 0 1 Figure 1 21 1 Block diagram of A D converter 24 NESAS Renesas Technology Corp 166 Mitsubishi Microcomputers M16C 80 group A D Converter SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D control register O Note 1 57 ARG bo A04 SDO t02 Bibo Symbol Address When reset ADCONO 039616 00000XXX2 p mA 0 cC OE ANo is selected
3. BCLK Address bus RD signal WR signal Br X Source Y source X Destination X CPU use 3 When one wait is inserted into the source read under the conditions in 1 Address bus CPU use Source X Destination CPU use RD signal WR signal Data e bus CPU use X Source X Destination y 4 When one wait is inserted into the source read under the conditions in 2 When 16 bit data is transferred and the width of data but at the destination is 8 bit there are two destination write cycles BCLK Address Source Source 1 Destination CPU use bus WR signal Data bus CPU use Source Source 1 Destination CPU use Note The same timing changes occur with the respective conditions at the destination as at the source Figure 1 11 6 Example of the transfer cycles for a source read 434 N SAS 87 Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group DMAC SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 2 DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible Table 1 11 2 shows the number of DMAC transfer cycles The number of DMAC transfer cycles can be calculated as follows No of transfer cycles per transfer unit No of read cycles x j No o
4. Measuring condition Standard i Symbol Parameter g Min Typ Max Unit HIGH output POo P07 P10 P17 P20 P27 voltage P30 P37 P40 P47 P50 P57 Xen P60 P67 P72 P77 P80 P84 as oe d P86 P87 P90 P97 P100 P107 P110 P114 P120 P127 P130 P137 P140 P146 P150 P157 Note 1 HIGHPOWER loH2 0 1 mA 2 5 jeu output XOUT v Vou voltage LOWPOWER loH 50 pA 2 5 HIGH output Xcour HIGHPOWER With no load applied 3 0 v voltage LOWPOWER With no load applied 1 6 LOW output P0Oo P07 P10 P17 P20 P27 voltage P30 P37 P40 P47 P50 P57 u vo P60 P67 P70 P77 P80 P84 locedmA 0 5 V P86 P87 P90 P97 P100 P107 P110 P114 P120 P127 P130 P137 P140 P146 P150 P157 Note 1 loL20 1mA 0 5 VoL LOW output Xour HIGHPOWER y voltage LOWPOWER loL 50pA 0 5 LOW output xcour HIGHPOWER With no load applied o v voltage LOWPOWER With no load applied 0 Hysteresis HOLD RDY TAOIN TA4IN V VI TBOiN TB2IN INTo INT5 ADTRG dr CTSo CTS4 CLKo CLK4 TA20uT TA40uT 0 2 1 0 V NMI Klo Kls RxDO RxD4 SCL2 SCL4 SDA2 SDA4 VT VT Hysteresis RESET 0 2 1 8 V HIGH input POo PO7 P 10 P17 P20 P27 current P30 P37 P40 P47 P50 P57 lid P60 P67 P70 P77 P80 P87 Vi 3V 4 0 UA P9o P97 P100 P107 P110 P114 P120 P127 P130 P137 P140 P 146 P150 P157 Note 1 XIN RESET CNVss BYTE LOW input POo PO7 P10 P17 P20 P27 current P30 P37 P40 P47 P50 P57 li P60 P67 P70 P77 P80 P87 Vi20V 4 0 A P9o P97 P100 P107 P110 P114 H P120 P127 P130 P137 P140 P14
5. ar CTS RTS disabled CTS RTS selected RTSO CTS0 RTS0 O oo Vcc b CTS RTS disabled 0 0 i CTS RTS separated CTSo CTSO from UART1 UART1 RxD1 UART reception 5 Receive i Clock source selection o Reception clock Transmit control circuit receive f o Bit rate Clock synchronous type 9 unit ts Internal generator EE bs UART transmission ee i UA Mates lias 5 ransmit N Transmission clock 9 0n Le control circuit External Clock synchronous type r9 Clock synchronous type when internal clock is selected S ol o Clock synchronous type Clock synchronous type when internal clock is selected when external clock is selected 1 2 CLK CLK1 OQ Polarity reversing circuit CTS RTS disabled _CTS1 RTS1 o N EN EL eadeni 4 ate OTSO DERS Clock output pin Vcc select switch CTS RTS disabled o o CTSo CTS1 CTSO to UARTO UART2 RxD polarity TxD ane eran reversing circuit reversing UART reception s Receive circuit Clock source selection Reception clock Transmit Bit rate Clock synchronous type o control circuit receive Internal unit T enerator fe we ee UART transmission Transmit 1 16 ce d 241 Q Transmission clock x H Clock synchronous type o control circuit Clock synchronous type when internal clock is selected
6. td BCLK HLDA HLDA output delay time Note Calculated according to the BCLK frequency as follows Note that inserting wait or using lower operation frequency f BCLK is needed when calculated value is negative 10 tact RD DB Feo X2 42 jns 10 tact AD DB Tey 55 ns 10 X tac2 RD DB wee 42 ns m 3 5 and 7 when 1 wait 2 wait and 3 wait respectively 9 tac2 AD DB BRE UNS 55 ns n 2 3 and 4 when 1 wait 2 wait and 3 wait respectively f BCLK 10 X tac3 RD DB dT 55 ns m 3 and 5 when 2 wait and 3 wait respectively 9 tac3 AD DB EOE 55 ns n 5 and 7 when 2 wait and 3 wait respectively 10 X m tac4 RAS DB decugX2 55 ns m 3 and 5 when 1 wait and 2 wait respectively 10 Xn tac4 CAS DB Teco X2 55 ns n 1 and 3 when 1 wait and 2 wait respectively 10 X tac4 CAD DB EO 55 ns l 1 and 2 when 1 wait and 2 wait respectively 246 24 NE SAS Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Timing Vcc 3V SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Vcc 3V Timing requirements referenced to Vcc 3V Vss OV at Topr 25 C unless otherwise specified Table 1 28 28 Timer A input counter input in event counter mode Standard Min Max Parameter TAiiN input cycle time TAiIN input HIGH pulse width TAiiN input LOW pulse width Table 1 28 29 Timer
7. 10 f BCLK X 2 ns 10 h WR AD zi IN f BCLK X 2 n ns 10 th RD CS f BCLK X2 10 ns 10 th WR CS i f BCLK X 2 i ns td DB WR _10 Xm__ 25 i ae f BCLK X 2 i ns m 3 and 5 when 2 wait and 3 wait respectively 10 th WR DB 4 f BCLK X 2 9 ns 10 FRA BEE S fBclX2 29 ns 10 Dec f amp Bc X2 19 ns 228 24 NE SAS Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Timing Vcc 5V SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Vcc 5V Switching characteristics referenced to Vcc 5V Vss OV at Topr 25 C unless otherwise specified Table 1 28 22 Memory expansion mode and microprocessor mode BCLK RAD Parameter Row address output delay tine BCLK RAD Row address output hold time BCLK standard BCLK CAD String address output delay time BCLK CAD String address output hold time BCLK standard RAS RAD Row address output hold time after RAS output BCLK RAS RAS output delay time BCLK standard BCLK RAS RAS output hold time BCLK standard P RAS H hold time BCLK CAS CAS output delay time BCLK standard BCLK CAS CAS output hold time BCLK standard BCLK DW Data output delay time BCLK standard BCLK DW Data output hold time BCLK standard su DB CAS CAS after DB output setup time h
8. A D control register O Note b7 b6 b5 b4 b3 b2 bi bO iT 4 Symbol Address When reset ADCONO 039616 00000XXX2 i symbol Analog input pin Invalid in repeat sweep mode 0 select bit A D operation mode Pi PA select bit O Repeat sweep mode 0 x A D conversion disabled 1 A D conversion started O fAD 4 is selected 1 fAD 2 is selected Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate A D control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi bO PLETE Toh ty Beon baare 0018 Bit symbol Bit name Function i A D sweep pin select bit When single sweep and repeat sweep mode 0 SCANO are selected b1 bO 00 ANO AN1 2 pins 0 1 ANo to AN8 4 pins 1 2 ANo to AN5 6 pins ANo to AN7 8 pins W Ud ta E A D operation mode 0 An mode other than repeat sweep mode 1 select bit 1 8 10 bit mode select bit p rE bit mode Frequency select bit 1 0 fAD 2 or fAD 4 is selected Note 3 fAD is selected Vref connect bit Vref connected External op am ende ee ANEXO and ANEX1 are not used Note 4 ANEXO input is A D converted Note 5 i bit Note 2 ANEX1 input is A D converted Note 6 External op amp connection mode Note 7 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Neither 01 nor 10 can be selected with the external op amp con
9. Timer B3 register TB3 Timer B5 register TB5 The blank area is reserved and cannot be used by user Figure 1 5 2 Location of peripheral unit control registers 2 24 NE SAS 23 Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group SFR SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 034016 Count start flag TABSR 038016 A D regi D register 0 ADO 034116 Clock prescaler reset flag CPSRF 038116 9 ADO 034216 One shot start flag ONSF 038216 A D register 1 AD1 034316 Trigger select register TRGSR 038316 034416 Up down flag UDF 038416 034516 pansies A D register 2 AD2 034616 038616 034716 Timer AO register TAO 038716 034816 A 038816 034916 mer A1 register TA1 038916 034A16 __ A 038A16 034Bie Timer A2 register TA2 038B16 034Ci6 _ 038C16 034Die Timer A3 register TA3 038D 6 034E16 038E16 034r Timer A4 register TA4 038F 16 035016 039016 035116 Timer BO register TBO 039116 035216 039216 035316 Timer B1 register TB1 039316 En Timer B2 register TB2 in A D control register 2 ADCON2 035616 Timer AO mode register TAOMR 039616 A D contro
10. LSB first When transfer format select bit 1 CLKi TXDi X D7 X De X Ds X Da X Ds X D2 X D1 X Do RXDi X pz X De X D5 X D4 X Da X D2 X Di X Do MSB first Note This applies when the CLK polarity select bit 0 Figure 1 17 4 Transfer format 434 NE SAS 141 Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Clock synchronous serial I O mode SINGLE CHIP 16 BIT CMOS MICROCOMPUTER c Transfer clock output from multiple pins function UART1 This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the port function select register bits of related to P64 and P65 See Figure 1 17 5 The multiple pins function is valid only when the internal clock is selected for UART1 Note that when this function is selected UART1 CTS RTS function cannot be used Microcomputer TxD1 P67 CLKSi P64 CLK1 P65 Note This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I O mode Figure 1 17 5 The transfer clock output from the multiple pins function usage d Continuous receive mode If the continuous receive mode enable bit bits 2 and 3 at address 037016 bit 5 at address 033D16 032D16 02FD16 is set to 1 the unit is placed in continuous receive mode In th
11. 0 2 2 X cycle Sample amp hold bit is enabled 24 NE SAS 211 Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Usage precaution SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts 1 Setting the stack pointer The value of the stack pointer is initialized to 00000016 immediately after reset Accepting an interrupt before setting a value in the stack pointer may cause runaway Be sure to set a value in the stack pointer before accepting an interrupt When using the NMI interrupt initialize the stack pointer at the beginning of a program Regard ing the first instruction immediately after reset generating any interrupts including the NMI inter rupt is prohibited Set an even address to the stack pointer so that operating efficiency is increased 2 The NMI interrupt As for the NMI interrupt pin an interrupt cannot be prohibited Connect it to the VCC pin via a resistance pulled up if unused The NMI pin also serves as P85 which is exclusively input Reading the contents of the P8 register allows reading the pin value Use the reading of this pin only for establishing the pin level at the time when the NMI interrupt is input Signal of L level width more than 1 clock of CPU operation clock BCLK is necessary for NMI pin 3 Address match interrupt Do not set the following addresses to the address match interrupt register 1
12. CTS3 RTS3 O o Vcc g CSTs disabled o CTS3 UART4 RxD polarity Clock source selection Transmit receive unit UART reception 1 16 Bit rate Clock synchronous type o R Receive S eception clock 6 control circuit Transmit receive TxD polarity reversing circuit TxD polarity reversing circuit Internal unit fg 9 x o Transmit clock generator uu 2 170241 241 UART transmission o Ner rye Qi Transmission Clock synchronous type o control circuit External Clock synchronous type when internal clock is selected Q o Clock synchronous type when external clock is selected Clock synchronous type when internal clock is selected lt CTS RTS CTS RTS disabled selected o CLK polarity reversing circuit CLKAO RTS4 CTS4 RTS4O Vcc 4 Cr e disabled o n3 Values set to UARTS bit rate generator BRG3 n4 Values set to UARTA bit rate generator BRG4 Figure 1 16 2 Block diagram of UARTI i 3 4 RENESAS 125 Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Serial I O SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock synchronous type UART 7 bits Clock UART 8 bits PAR synchronous UART 7 bits UARTi receive register disabled Lo O PAR enabled Clock synchron
13. m a m EN e ER oo N P96 ANEX1 TxD4 SDA4 SRxD4 P95 ANEX0 CLK4 ro P94 DA1 TB4IN CTS4 RTS4 SS4 9 o P93 DAo TBSIN CTSs RTS3 SS3 lt a P92 TB2IN TxD3 SDA3 SRxD3 a o P91 TB1IN RxD3 SCL3 STxD3 gt o P90 TBOIN CLK3 a P87 XCIN lt i P8e Xcour lt P85 NMI 3 P84 INT2 cA P83 INT1 cA P82 INTo t S P81 TA4INU lt P80 TA4ouT U c9 P77 TASIN 8 P7e TA3our c9 F P7s TA2IN N c P74 TA2oUT W s S P7a CLKe TA1our V 1 gt S P73 CTS2 RTS2 TAIINV c P71 RxD2 SCL2 TAOIN TBSIN Note c S P7o TxD2 SDA2 TAOOUT Note lt 8 a P54 HLDA ALE e P55 HOLD gt P5e ALE RAS V P57 RDY a P60 CTSo RTSo a P61 CLKo c P62 RxDo CA PosTxDo O OO V 9 P64 CTS1 RTS1 CTSo CLKS1 lt P65 CLK1 P66 RxD1 lt p67 TxD1 Note This port is N channel open drain output Package 100P6S A Figure 1 1 1 Pin configuration for 100 pin version top view 1 434 NE SAS Renesas Technology Corp Description Mitsubishi Microcomputers M16C 80 group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER PIN CONFIGURATION top view P12 Di0 lt 2 P11 Do lt gt P10 Ds lt gt P07 D7 lt P0c De t P0s D5 lt gt P04 D4 ct P03 D3 83 P02 D2 P01 D1 lt gt P00 Do am 4 D5 D
14. td BCLK CAD i td BCLK RAD _ th BCLK RAD ae 25ns max i th BCLK CAD 25ns max 1 Ons min i o Ons min Row address j String address B L th RAS RAD 2 i gt i th BCLK RAS td BCLK RAS td BCLK CAS Ons min 4 gt 25ns max 1 gt 25ns max 1 i tac4 CAS DB 2 1 4 tac4 CAD DB 2 tac4 RAS DB 2 tsu 40ns min 1 1 It is a guarantee value with being alone 55ns max garantees as follows td BCLK RAS tsu DB BCLK td BCLK CAS tsu DB BCLK td BCLK CAD tsu DB BCLK 2 It depends on operation frequency tac4 RAS DB tcyc 2 x m 55 ns max m 3 and 5 when 1 wait and 2 wait respectively tac4 CAS DB tcyc 2 x n 55 ns max n 1 and 3 when 1 wait and 2 wait respectively tac4 CAD DB tcyc x I 55 ns max I21 and 2 when 1 wait and 2 wait respectively th RAS RAD tcyc 2 25 ns min tRP tcyc 2 x 3 40 ns min Measuring conditions e Vec 3V 10 Input timing voltage Determined with VIH 1 5V ViL 0 5V Output timing voltage Determined with VoHz21 5V VOL 1 5V Figure 1 28 23 Vcc 3V timing diagram 9 24 NE SAS 261 Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Timing Vcc 3V SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Memory expansion Mode and Microprocessor Mode When accessing DRAM area with 2 wait Write Timing BCLK i tcyc i td BCLK RAD 25ns max 4 gt th B
15. Interrupt request generation timing When measurement pulse s effective edge is input Note 1 When an overflow occurs Simultaneously the timer Bi overflow flag changes to 1 The timer Bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer Bi mode register TBiIN pin function Measurement pulse input Set the corresponding function select register A to I O port Read from timer When timer Bi register is read it indicates the reload register s content measurement result Note 2 Write to timer Cannot be written to Note 1 An interrupt request is not generated when the first effective edge is input after the timer has started counting Note 2 The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer Timer Bi mode register b7 b6 b5 b4 b3 b2 bi b0 HIEEBEBUU Bremo Biramo TMODO TMOD1 When reset 00XX00002 00XX00002 Symbol Address TBiMR i 0 to 5 035Bt6 to 035D16 031B16 to 031D16 b1 b0 1 0 Pulse period pulse width measurement mode Operation mode select bit b3 b2 0 0 Pulse period measurement Interval between measurement pulse s falling edge to falling edge 0 1 Pulse period measurement Interval between measurement pulse s rising edge to rising edge 10 Pulse width measurement Interval between measurement pulse s falling edge to rising edge
16. The blank area is reserved and cannot be used by user Mitsubishi Microcomputers M16C 80 group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 144 pin version 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03FC16 03FD16 O3FE16 03FF16 Port P6 P6 Port P7 P7 Port P6 direction register PD6 Port P7 direction register PD7 Port P8 P8 Port P9 P9 Port P8 direction register PD8 Port P9 direction register PD9 Port P10 P10 Port P11 P11 Port P10 direction register PD10 Port P11 direction register PD11 Port P12 P12 Port P13 P13 Port P12 direction register PD12 Port P13 direction register PD13 Port P14 P14 Port P15 P15 Port P14 direction register PD14 Port P15 direction register PD15 Pull up control register 2 PUR2 Pull up control register 3 PUR3 Pull up control register 4 PUR4 Port PO P0 Port P1 P1 Port PO direction register PDO Port P1 direction register PD1 Port P2 P2 Port P3 P3 Port P2 direction register
17. 1 It depends on operation frequency td AD ALE tcyc 2 27 ns min gt AE th BCLK RD th RD AD 3ns min T th ALE AD tcyc 2 20 ns min th RD AD tcyc 2 20 ns min th RD CS tcyc 2 20 ns min tac3 RD DB tcyc 2 x m 55 ns max m 3 and 5 when 2 wait and 3 wait respectively tac3 AD DB tcyc 2 x n 55 ns max n 5 and 7 when 2 wait and 3 wait respectively Write Timing th BCLK ALE gt 2ns min td BCLK ALE 25ns max th BCLK cs eats CS td AD PC th ALE AD 2 Address Ons min th BCLK DB Ons min Address Data output td BCLK AD 25ns max td BCLK WR lt gt 25ns max 2 It depends on operation frequency td AD ALE tcyc 2 27 ns min th ALE AD tcyc 2 20 ns min th WR AD tcyc 2 20 ns min th WR CS tcyc 2 20 ns min th WR DB tcyc 2 20 ns min td DB wR tcyc 2 x m 40 ns min m 3 and 5 when 2 wait and 3 wait respectively Figure 1 28 19 Vcc 3V timing diagram 5 td DB wR 2 gt lt ig 1 th WR DB th BCLK AD i i0ns min th BCLK WR th WR AD Ons min gt Measuring conditions Vcc23Vt1096 Input timing voltage Determined with VIH 1 5V ViIL 0 5V Output timing voltage Determined with VOH 1 5V VOL 1 5V 24 NE SAS 257 Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Timing Vcc 3V SINGLE CHIP 16 BIT CMOS MICROCOMPUTE
18. 24 NE SAS Renesas Technology Corp 35 Bus Control Mitsubishi Microcomputers M16C 80 group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 4 ALE signal The ALE signal latches the address when accessing the multiplex bus space Latch the address when the ALE signal falls The ALE output pin is selected using bits 4 and 5 of the processor mode register 1 address 000516 The ALE signal is occurred regardless of internal area and external area When BYTE pin H ALE Do Ao to D7 A7 Address Data Note 1 A8 to A15 Address A16 to A19 Address Note 2 A20 to A22 A23 y Address or CS Note 1 Floating when reading When BYTE pin L ALE Do Ao to D15 A15 Address Data Note 1 A16 to A19 Address Note 2 A20 to A22 A23 y Address or CS Note 2 When full space multiplexed bus is selected these are I O ports Figure 1 7 3 ALE signal and address data bus 5 Ready signal The ready signal facilitates access of external devices that require a long time for access As shown in Figure 1 7 2 inputting L to the RDY pin at the falling edge of BCLK causes the microcomputer to enter the ready state Inputting H to the RDY pin at the falling edge of BCLK cancels the ready state Table 1 7 7 shows the microcomputer status in the ready state Figure 1 7 4 shows the example of the RD signal being extended using the RDY signal Re
19. Nothing but 0 may be written Set CLKi and TxDi both for output using the CLKi and TxDi function select register A Set the RxDi function select register A for input output port and the port direction register to O Set STxDi for output using the STxDi function select registers A and B Set the CLKi and SRxDi function select register A for input output port and the port direction register to O Figure 1 16 12 Serial l O related registers 8 434 NE SAS 135 Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Clock synchronous serial I O mode SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 1 Clock synchronous serial I O mode The clock synchronous serial I O mode uses a transfer clock to transmit and receive data Tables 1 17 1 and 1 17 2 list the specifications of the clock synchronous serial I O mode Figure 1 17 1 shows the UARTI transmit receive mode register Table 1 17 1 Specifications of clock synchronous serial I O mode 1 Transfer data format Transfer data length 8 bits Transfer clock When internal clock is selected bit 3 at addresses 036016 036816 033816 032816 02F816 0 fi 2 n 1 Note fi f1 f8 f32 CLK is selected by the corresponding port function select register periph eral function select register and peripheral subfunction select register When external clock is selected bit 3 at addresses 036016 036816 033816 032816 02F816 1 Input from CLKi pin
20. When this bit is 1 Xour is H Also the internal feedback resistance remains ON so XIN is pulled up to Xour H level via the feedback resistance When the main clock is stopped the main clock division register address 000C16 is set to the division by 8 mode When 1 has been set once 0 cannot be written by software To set CMO7 1 from 0 first set CM04 to 1 and an oscillation of sub clock is stable Then set CM07 Do not set CM04 and CMO7 simultaneously Also to set CMO7 0 from 1 first set CMO5 to 1 and an oscillation of main clock is stable Then set CMO7 Note 10 fc32 is not included Note 11 When XcIN XcOUT is used set port P86 and P87 to no pull up resistance with the input port System clock control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi b0 ofo efefefo our O07 BOI CM10 All clock stop control bit 0 Clock on Note 3 1 All clocks off stop mode Note 4 Reserved bit Always set to 0 loo CM15 XIN XOUT drive capacity 0 LOW select bit Note 2 1 HIGH Reserved bit Always set to 0 loo Set bit O of the protect register address 000A16 to 1 before writing to this register Changes to 1 when shifting from high speed or middle speed mode to stop mode or reset This bit is remained in low speed or low power dissipation mode When this bit is 1 Xour is H and the internal feedback resistance is disabled XCIN and XCOUT are high inpedance
21. td BCLK ALE th BCLK ALE lt gt gt 4 2ns min td BCLK CS i i th BCLK cs 18ns max 1 u 3ns min tcyc gt re th RD cS i E Ons min ti BCLK AD i th BCLK AD 4 18ns max i i lt gt 3ns min tdlBCLK RD je th RD AD 10ns max gt i Ons min T th BCLK RD tac2 RD DB 2 bns min tac2 AD DB 2 tsu DB BCLK gt m i th RD DB 26ns min 1 C Ons min 1 It is a guarantee value with being alone 35ns max garantees as td BCLK AD tsu DB BCLK 2 It depends on operation frequency tac2 RD DB tcyc 2 x m 35 ns max m 3 5 and 7 when 1 wait 2 wait and 3 wait respectively tac2 AD DB tcyc x n 35 ns max n 2 3 and 4 when 1 wait 2 wait and 3 wait respectively Write Timing BCLK Jem 4 X d d BCLK ALE 3 1 th BCLK ALE d y T Y 2ns min td BCLK CS i i th BCLK CS mn 18ns max Dig 3ns min Dh WR CS 3 M td BCLK AD La th BCLK AD i 18ns max 1 E dns min td BCLK WR T 18ns max gt i o ou y A th BCLK WR gt hs 3ns min pig th WR DB S 1 1 D Sesca sees ioecsssezseesxs iizzcasesezus emus 1 1 1 3 It depends on operation frequency Measuring conditions i ta DB WR tcyc x n 20 ns min Vcc 5V 1096 n 1 2 and 3 when 1 wait 2 wait and 3 wait respectively Input timing voltage th WR DB tcyc 2 10 ns min Determined with ViIH 2 5V Vi
22. Bit Function Function symbol Bit name During clock synchronous During UART mode serial I O mode e Receive data Receive data Nothing is assigned When write set 0 When read the value of these bits is 0 Arbitration lost detecting Not detected Invalid flag Note 2 Detected Overrun error flag Note 1 No overrun error 0 No overrun error Overrun error found 1 Overrun error found Framing error flag Note 1 Invalid 0 No framing error 1 Framing error found Parity error flag Note 1 Invalid 0 No parity error 1 Parity error found Error sum flag Note 1 Invalid 0 No error 1 Error found Note 1 Bits 15 through 12 are set to 0 when the serial I O mode select bit bits 2 to 0 at addresses 036016 036816 033816 032816 and 02F816 are set to 0002 or the receive enable bit is set to Bit 15 is set to 0 when bits 14 to 12 all are set to 0 Bits 14 and 13 are also set to 0 when the lower byte of the UARTi receive buffer register addresses 036616 036E16 033E16 032E16 and O2FE 6 is read out Note 2 Arbitration lost detecting flag is allocated to U2RB USRB and U4RB and nothing but 0 may be written Nothing is assigned in bit 11 of UORB and U1RB When write set 0 When read the value of this bit is 0 UARTI bit rate generator Note 1 2 ERIS gr on bo U1BRG 036916 Indeterminate U2BRG 033916 Indeterminate USBRG 032916 Indeterminate U4BRG 02F
23. Signal wave Timer B2 Timber B2 interrupt occurres Rewriting timer A4 and timer A4 1 Y Possible to set the number of overflows to generate an V Trigger signal for interrupt by use of the interrupt occurrences frequency timer Ai start Pod set circuit timer B2 overflow l signal tot i The three phase shift register shifts in synchronization qi je i E with the falling Control signal for H do EH edge of the A4 timer A4 reload 4 i output Timer A4 output U phase output signal U phase output signal U phase Note 1 U phase gt Dead time gt ee O gt i4 gt ia Dead time INV13 Triangular wave gee o eee F modulation detect flag d i 1 1 i Note 3 Note 1 When INV14 0 output wave Low active Note 2 When INV14 1 output wave High active Note 3 Set to triangular wave modulation mode and to three phase mode 1 Figure 1 15 6 Timing chart of operation 1 118 24 NE SAS Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Three phase motor control timers functions SINGLESGEIP Te BIT CMOS MICROCOMPUTER Assigning certain values to DUO bit 0 at 030A16 and DUBO bit 1 at 030A16 and to DU1 bit O at 030B16 and DUB1 bit 1 at 030B16 allows you to output the waveforms as shown in Figure 1 15 7 that is to output the U phase alone to fix U phase to H to fix the U phase to
24. BRK instruction Cannot be masked flag Software interrupt number 8 32 to 35 Note 1 DMAO Software interrupt number 9 36 to 39 Note 1 DMA1 Software interrupt number 10 40 to 43 Note 1 DMA2 Software interrupt number 11 44 to 47 Note 1 DMA3 Software interrupt number 12 48 to 51 Note 1 Timer AO Software interrupt number 13 52 to 55 Note 1 Timer A1 Software interrupt number 14 56 to 59 Note 1 Timer A2 Software interrupt number 15 60 to 63 Note 1 Timer A3 Software interrupt number 16 64 to 67 Note 1 Timer A4 Software interrupt number 17 UARTO transmit Software interrupt number 18 UARTO receive Software interrupt number 19 76 to 79 Note 1 UART1 transmit Software interrupt number 20 80 to 83 Note 1 UART1 receive 468 to 471 Note 1 72 to 75 Note 1 1 Software interrupt number 21 84 to 87 Note 1 Timer BO Software interrupt number 22 88 to 91 Note 1 Timer B1 Software interrupt number 23 92 to 95 Note 1 Timer B2 Software interrupt number 24 96 to 99 Note 1 Timer B3 Software interrupt number 25 100 to 103 Note Timer B4 Software interrupt number 26 104 to 107 Note 1 INT5 Software interrupt number 27 108 to 111 Note 1 INT4 Software interrupt number 28 112 to 115 Note 1 INT3 Software interrupt number 29 116 to 119 Note 1
25. H or to output the U phase alone A carrier wave of triangular waveform Carrier wave Signal wave Timer B2 Rewriting timer A4 every timer B2 interrupt occurres Po Timer B2 interrupt occurres Trigger signal for Rewriting three phase buffer register timer Ai start pod eoo oF Por od timer B2 overflow signal Timer A4 output Control signal for timer A4 reload U phase output signal U phase output signal U phase U phase Po LL e Dead time Note Set to triangular wave modulation mode and to three phase mode 1 Figure 1 15 7 Timing chart of operation 2 24 NE SAS 119 Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Three phase motor control timers functions SINGLE CHIP Te BIT CMOS MICROCOMPUTER Sawtooth modulation To generate a PWM waveform of sawtooth wave modulation set 1 in the modulation mode select bit bit 6 at 030816 Also set 0 in the timers A4 A1 and A2 1 control bit bit 1 at 030916 In this mode the timer registers of timers A4 A1 and of A2 comprise conventional timers A4 A1 and A2 alone and reload the corresponding timer register s content to the counter every time the timer B2 counter s content be comes 000016 The effective interrupt output specification bit bit 1 at 030816 and the effective interrupt output polarity select bit bit O at 030816 go nullified An example of U phase waveform is
26. Note 4 Use the control program except in the internal flash memory for write to this bit Flash memory control register 1 b7 b6 b5 b4 b3 b2 bi bO fofofofo ooo Purr aree 000000 Must always be set to 0 FMR13 Flash memory power 0 Flash memory power supply is supply OF F bit Note connected 1 Flash memory power supply off Reserved bit Must always be set to 0 For this bit to be set to 1 the user needs to write a 0 and then a 1 to it in succession When it is not this procedure it is not enacted in 1 This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval Use the control program except in the internal flash memory for write to this bit During parallel I O mode programming erase or read of flash memory is not controlled by this bit only by external pins Figure 1 30 1 Flash memory control registers 21 NE S AS 271 RenesasTechnology Corp Mitsubishi Microcomputers M16C 80 group CPU Rewrite Mode Flash Memory Version SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Program in ROM Program in RAM Single chip mode memory expansion Boot mode only mode or boot mode Set user ROM area select bit to 1 Set CPU rewrite mode select bit to 1 by writing 0 and then 1 in succession Note 2 Transfer CPU rewrite mode control Using software command execute erase program to internal RAM program or other operation Set lock bit disable bit as r
27. Ons min 1 It is a guarantee value with being alone 35ns max garantees as td BCLK AD tsu DB BCLK 2 It depends on operation frequency tac2 RD DB tcyc 2 x m 35 ns max m 3 5 and 7 when 1 wait 2 wait and 3 wait respectively tac2 AD DB tcyc x n 35 ns max n 2 3 and 4 when 1 wait 2 wait and 3 wait respectively Timing E 18ns max j r td BCLK ALE gt 2 ie th BCLK ALE 2ns min 5 Ee td BCLK CS 18ns max td BCLK AD M 18ns max td BCLK WR tw WR 3 18ns max teo i th BCLK CS gt 3ns min i tn wR cs 3 Ah BCLK AD 3ns min an i th BCLK WR gt 3ns min td DB wr 3 ba th WR DB 3 3 lt depends on operation frequency Measuring conditions ta DB WR tcyc x n 20 ns min n 1 2 and 3 when 1 wait 2 wait and 3 wait respectively th WR DB tcyc 2 10 ns min th WR AD tcyc 2 10 ns min th wR CS tcyc 2 10 ns min e Vcc 5V 1096 Input timing voltage Determined with ViIH 2 5V ViL 0 8V Output timing voltage Determined with VOH 2 0V VoL 0 8V tw WR tcyc 2 x n 15 ns min n 1 3 and 5 when 1 wait 2 wait and 3 wait respectively Figure 1 28 3 Vccz5V timing diagram 2 232 434 NE SAS Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Timing Vcc 5V SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Memory expansion Mode and Microprocessor Mode with 2 wait Read Timing BCLK 18ns max
28. Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group CPU Rewrite Mode Flash Memory Version SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Program in ROM Program in RAM Transfer the program to be executed in the Set flash memory power supply OFF bit to 1 low speed mode to the internal RAM by writing 0 and then 1 in succession Note 1 Jump to transferred control program in RAM Switch the count source of BCLK Subsequent operations are executed by control XIN stop Note 2 program in this RAM fi Process of low speed mode a XIN oscillating gt Wait until the XIN has stabilized Switch the count source of BCLK Note 2 Set flash memory power supply OFF bit to O Wait time until the internal circuit stabilizes Set NOP instruction about twice Note 1 For flash memory power supply OFF bit to be set to 1 the user needs to write a 0 and then a 1 to it in succession When it is not this procedure it is not enacted in 1 This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval Note 2 Before the count source for BCLK can be changed from XIN to XCIN or vice versa the clock to which the count source is going to be switched must be oscillating stably Figure 1 30 3 Shifting to the low speed mode flowchart 24 NE SAS 273 Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group CPU Rewrite Mode Flash Memory V
29. Start and stop condition detection timing characteristics are shown in Figure 1 20 4 Always set bit 7 start stop condition control bit to 1 Bit 1 is the clock synchronization bit When this bit is set to 1 if the rise edge is detected at pin SCL2 while the internal SCL is H level the internal SCL is changed to L level the baud rate generator value is reloaded and the L sector count starts Also while the SCL2 pin is L level if the internal SCL changes from L level to H baud rate generator stops counting If the SCL2 pin is H level counting restarts Because of this function the UART2 transmission reception clock takes the AND condition for the internal SCL and SCL2 pin signals This function operates from the clock half period before the 1st rise of the UART2 clock to the 9th rise To use this function select the internal clock as the transfer clock Bit 2 is the SCL wait output bit When this bit is set to 1 output from the SCL2 pin is fixed to L level at the clock s 9th rise When set to 0 the L output lock is released Bit 3 is the SDA output stop bit When this bit is set to 1 an arbitration lost is generated If the arbitration lost detection flag is 1 the SDA2 pin simultaneously becomes high impedance Bit 4 is the UART2 initialize bit While this bit is set to 1 the following operations are performed when the start condition is detected 1 The transmission shift register is initialized an
30. aa 20 id ia f BCLK X 2 Ins Standard Max Note Note Note 24 NE SAS Renesas Technology Corp 249 Timing Vcc 3V Mitsubishi Microcomputers M16C 80 group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Vcc 3V Switching characteristics referenced to Vcc 3V Vss OV at Topr 25 C unless otherwise specified Table 1 28 40 Memory expansion and microprocessor modes td BCLK AD with wait accessing external memory Parameter Address output delay time Address output hold time BCLK standard th BCLK AD th RD AD Address output hold time RD standard th WR AD Address output hold time WR standard td BCLK CS Chip select output delay time th BCLK CS Chip select output hold time BCLK standard th RD CS Chip select output hold time RD standard th WR CS Chip select output hold time WR standard td BCLK ALE ALE signal output delay time th BCLK ALE ALE signal output hold time td BCLK RD RD signal output delay time RD signal output hold time td BCLK WR WR signal output delay time th BCLK WR WR signal output hold time td DB WR Data output delay time WR standard th BCLK RD th WR DB Data output hold time WR standard tw WR WR signal width Measuring condi
31. current P4o P47 P5o P57 P60 P67 P72 P77 P80 P84 P86 P87 P90 P97 P100 P107 P110 P114 P120 P127 P130 P137 P140 P 146 P150 P157 Note 5 1 OL peak LOW peak output P0o P07 P10 P17 P20 P27 P3o P37 current P40 P47 P50 P57 P60 P67 P70 P77 P80 P84 P86 P87 P90 P97 P100 P107 P110 P114 P120 P127 P130 P137 P140 P 146 P150 P157 Note 5 LOW average POo P07 P10 P17 P20 P27 P30 P37 output current P40 P47 P50 P57 P60 P67 P70 P77 P80 P84 P86 P87 P90 P97 P100 P107 P110 P114 P120 P127 P130 P137 P140 P 146 P150 P157 Note 5 Main clock input oscillation frequency No wait Vcc 4 2V to 5 5V Vcc 2 7V to 4 2V Subclock oscillation frequency Note 1 The mean output current is the mean value within 100ms Note 2 The total loL peak for ports PO P1 P2 P86 P87 P9 P10 P11 P14 and P15 must be 80mA max The total IOH peak for ports PO P1 P2 P86 P87 P9 P10 P11 P14 and P15 must be 80mA max The total loL peak for ports P3 P4 P5 P6 P7 P80 to P84 P12 and P13 must be 80mA max The total loH peak for ports P3 P4 P5 P6 P72 to P77 P80 to P84 P12 and P13 must be 80mA max Note 3 Specify a product of 40 to 85 C to use it Note 4 The specification of ViH and VIL of P87 is not when using as XCIN but when using programmable input port Note 5 Port P11 to P15 exist in 144 pin version 220 24 NE SAS Renesas Technology Corp
32. Address Data input Not Page program 4116 middle high input input input to 259th acceptable byte Block Address Address D016 Not ock erase 2016 middle high acceptable Erase all unlocked blocks A716 oar ae Read status register 7016 DOES Not Clear status register 5016 acceptable Address Address Not Read lock bit status 7116 middle high acceptable Lock bit Address Address D016 Not ock bit program 7716 middle high acceptable Not Lock bit enable 7A16 acceptable Lock bit disable 7516 MUT Address Address Address Code processing function F516 low middle high ID size ID1 To ID7 Acceptable D load functi Size Check To Not ownload function FA16 Size low high sum Data required acceptable input number of times Version data output function Acceptable Address Not Boot ROM area output middle acceptable function Not Read check data acceptable Note 1 Shading indicates transfer from flash memory microcomputer to peripheral unit All other data is trans ferred from the peripheral unit to the flash memory microcomputer Note 2 SRD refers to status register data SRD1 refers to status register data1 Note 3 All commands can be accepted when the flash memory is totally blank 292 24 NE SAS Renesas Technology Corp Mitsubishi Microcomputers M16C 80 group Appendix Standard
33. Any of the timers for setting dead time takes the value of the reload register into its counter if a start trigger comes from its corresponding timer and performs a down count in line with the clock source selected by the dead time timer count source select bit bit 2 at 030916 The timer can receive another trigger again before the workings due to the previous trigger are completed In this instance the timer performs a down count from the reload register s content after its transfer provoked by the trigger to the timer for setting dead time Since the timer for setting dead time works as a one shot timer it starts outputting pulses if a trigger comes it