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FREESCALE MC68HC908AS32A Data Sheet Manual

1. Effect o o 2 5 ob Operation Description 5 9 S 33 8 6 DIR BC 2 JMP opr EXT hhll 3 JMP opr X Jump PC lt Jump Address x2 DC 4 JMP opr X EC ff 3 JMP X IX FC 2 ISR opr Pe LPO alo tor Ext mi 5 us JSR opr X Jump to Subroutine Push PCH SP lt SP 1 Ei pD e ff 2 JSR X PC lt Unconditional Address IX FD 4 LDA opr IMM iii 2 LDA opr DIR B6 dd 3 LDA opr EXT C6 4 LDA opr X 1 2 06 4 LDA Load A from M A lt M i t1 ti E6 8 3 LDA X IX F6 2 LDA opr SP SP1 9EE6 ff 4 LDA opr SP SP2 9ED6 5 LDHX opr EE _ 45 lij 3 LDHX opr Load H X from M H X lt 1 1 1 DIR 55 Idd 4 LDX opr IMM AE 2 LDX opr DIR dd 3 LDX opr EXT 4 LDX IX2 DE 4 LDX Load X from M X lt M l t ti X1 EE 3 LDX X IX FE 2 LDX SP SP1 ff 4 LDX opr SP SP2 9EDE 5 LSL opr DIR 38 4 LSLA INH 48 1 LSLX Logical Shift Left Cle PET 58 1 LSL Same as ASL b7 IX1 68 4 LSL X IX 78 3 LSL opr SP SP1 9 68 ff 5 LSR opr DIR 34 dd 4 LSRA gt INH 44 1 LSH Logical Shift Right 0 EHE 3 LSR X b7 bo IX 74 3 LSR oprSP SP1 9 64 ff 5 MON iKa
2. 159 13 7 1 Pon F ds bee Peers Fe eat 159 13 7 2 pala Direction Register 160 Chapter 14 Serial Communications Interface SCI DARE 0 vmm 163 p AE 00 163 5523 X433 Ped d aA OEC Robe dol CA Y SERO UR I 164 144 OFulecusnal DOSCUBDOD io dde hg E ORC Re CLR 165 14 4 1 DNO FOIE ie Od 166 14 4 2 lii uc Tr 166 14 4 2 1 qoe 0i 7 succeed ears 167 14 4 2 2 RSCG Mir s ni ci ERO T RTI T Qi TOI tL T 167 14 4 2 3 cri df 2 T M 167 14 4 2 4 dle Lex 168 14 4 2 5 Inversion of Transmitted Output 168 14 4 2 6 168 14 4 3 168 14 4 3 1 daccorgb ETE 169 14 4 3 2 Recepto PPP eS 170 14 4 3 3 3 99 3 CEDAR OR Ee RS PAGE ER 170 14 4 3 4 Framing EITODS asser PEE RR 5006594054640 190185 171 14 4 3 5 Baud Raie A dog
3. 40 EEPROM Programming and 40 Program Erase Using ALTO 41 MC68HC908AS32A Data Sheet Rev 1 Freescale Semiconductor 7 Table of Contents 2 8 1 7 EEPROM 41 2 8 1 8 EEPROM o3 Mew 42 2 8 2 EEPROM Register Descriptions 43 2 8 2 1 EEPROM Control Register 9 43 25 22 EEPROM Array Configuration 5 44 2 8 2 3 EEPROM Nonvolatile 5 46 2 8 2 4 EEPROM Timebase Divider Register 46 2 8 2 5 EEPROM Timebase Divider Nonvolatile Register 47 2 8 3 Low Power MOES aid dedo dox dede dca UR C OUR RR 48 2 8 3 1 rere 48 2 8 3 2 Tcr 48 2 9 FLASH Memory FLASH 222222242 525452024425 III S eR Pe heated des 48 2 9 1 FLASH Control and Block Protect 5 49 2 9 1 1 FLASH 49 2 9 1 2 FLASH Block Protect 50 2 9 2 FLASH d2 o015 oorr 51 2 0 9 FLASH Page Erase Operation 52 2 9 4 FLASH Mass Erase Operation AERE EORR GR ACE beard 53 2
4. 19 Chapter sad dasad RA ARA RAAdAaUA RA RAR ARRR A RAE d 27 Chapter Analog to Digital Converter 57 Chapter 4 Byte Data Link Controller 65 Chapter 5 Clock Generator Module 95 Chapter 6 Configuration Register CONFIG1 113 Chapter 7 Configuration Register CONFIG2 115 Chapter 8 Computer Operating Properly 117 Chapter 9 Central Processor Unit 121 Chapter 10 External Interrupt Module 133 Chapter 11 Low Voltage Inhibit 139 Chapter 12 Programmable Interrupt Timer 143 Chapter 13 Input Output 149 Chapter 14 Serial Communications Interface 5 163 Chapter 15 System Integration Module 51 187 Chapter 16 Serial Peripheral Interface 203 Chapter 17 Timer Interface Module 225 Chapter 18 Development 243 Chapter 19 Electrical
5. 75 4 4 5 i ccce Fono EM cT 78 4 5 EORR CA ROCA OR Ede De Od OORT Rope aa Ec Rd 79 4 5 1 80 4 5 2 Rz and TX SNM EU CROIRE eoe disci 80 4 5 3 Rx and Tx Shadow Regist fS a CR OR 80 4 5 4 Digital Loopback dea m 81 4 5 5 81 4 5 5 1 258 05 rn 81 4 5 5 2 Receiving a Message Block 81 4 5 5 8 Transmitting a Message in Block 81 4 5 5 4 Jeo Ble A CPC C 81 4 5 5 5 SUIDAS EROR ACE ERR 82 4 6 BELLE DPI TRIS xd 83 4 6 1 BDLC Analog and Roundtrip Delay 5 83 4 6 2 BBLC ERU ER o ERR ERA HR 84 4 6 3 BDLC Control Register 2 TIMOR Lm 86 4 6 4 BDLC State Vector Register La EROR EE CERE SEES 90 4 6 5 BDLC Data Register cob LI error 92 4 7 E 22 48 rrr e 92 4 7 1 TOU ROI aa e ao PRU Ede o OLOR ER md d 92 4 7 2 WOP MOTE CC UST 93 Chapter 5 Clock Generator Module CGM 5 1 duis
6. Vector Priority Address Vector Lowest FFDA PIT Vector High FFDB PIT Vector Low A FFDC BDLC Vector High FFDD BDLC Vector Low FFDE ADC Vector High FFDF ADC Vector Low FFEO SCI Transmit Vector High FFE1 SCI Transmit Vector Low FFE2 SCI Receive Vector High FFE3 SCI Receive Vector Low FFE4 SCI Error Vector High FFE5 SCI Error Vector Low FFE6 SPI Transmit Vector High FFE7 SPI Transmit Vector Low FFE8 SPI Receive Vector High FFE9 SPI Receive Vector Low FFEA TIM Overflow Vector High FFEB TIM Overflow Vector Low FFEC TIM Channel 5 Vector High FFED TIM Channel 5 Vector Low FFEE TIM Channel 4 Vector High FFEF TIM Channel 4 Vector Low FFFO TIM Channel 3 Vector High FFF1 TIM Channel 3 Vector Low FFF2 TIM Channel 2 Vector High FFF3 TIM Channel 2 Vector Low FFF4 TIM Channel 1 Vector High FFF5 TIM Channel 1 Vector Low FFF6 TIM Channel 0 Vector High FFF7 TIM Channel 0 Vector Low FFF8 PLL Vector High FFF9 PLL Vector Low FFFA IRQ1 Vector High FFFB IRQ1 Vector Low FFFC SWI Vector High FFFD SWI Vector Low Y FFFE Reset Vector High Highest FFFF Reset Vector Low MC68HC908AS32A Data Sheet Rev 1 37 Memory 2 7 Random Access Memory RAM The 1024 bytes of random access memory RAM are located at address 0050 044F is the RAM location The 16 bit stack pointer allows the stack RAM to be anywhere i
7. gt E KC 7 REGISTERS UNIT ALU a MODULE ea PTB7 ATD7 CONTROL AND STATUS REGISTERS gt PTBO ATDO lt BREAK MODULE lt lt gt PTC4 ER FLASH 32 256 BYTE USER FLASH 32 256 BYTES Ke LOW VOLTAGE INHIBIT Gb M PTC2 MCLK USER RAM 1024 BYTES ee PTCI PTCO COMPUTER OPERATING lt PTDG ATD14 TCLK USER EEPROM 512 BYTES lt PROPERLY MODULE c ala lt gt PTD5 ATD13 T E 4 12 MONITOR ROM 256 BYTES s 6 CHANNEL TIMER PTD3 ATD11 INTERFACE MODULE PTDO ATD8 lt gt PTE7 SPSCK USER FLASH VECTOR SPACE 52BYTES KD PROGRAMMABLE INTERRUPT ese OSC1 PTES MISO CLOCK GENERATOR fu lt PTEA SS OSC2 lt KONE CGMXFC gt MODULE SERIAL COMMUNICATIONS gt PTESITCH INTERFACE MODULE lt lt 2 b l lt gt PTE1 RxD SERIAL PERIPHERAL zu SYSTEM INTEGRATION RST MODULE INTERFACE MODULE Gu PTF3 TCH5 PTFO TCH2 IRQ MODULE BYTE DATA LINK CONTROLLER D POWER ON RESET MODULE BDRxD BDTxD Vss Vpp lt AVssVnerk POWER Figure 16 1 Block Diagram Highlighting SPI Block and Pins The generic names of the SPI I O registers are e SPI control register SPCR e SPI status and control register SPSCR
8. 225 17 3 1 TIM Counter PEESORIBE OH ACCRUE RC 225 17 3 2 ul sid aded abb o rbd OQ MORE Rd 228 17 3 3 E LITERE 228 17 3 3 1 Unbuffered Output Compare 228 17 3 3 2 B ff red COMPS oa Eg E Rees od adde EC ScEERIGebEPEOqIS Sd QE 229 17 3 4 Pulse Width Modulation 230 17 3 4 1 Unbuffered PWM Signal Generation 230 17 3 4 2 Buffered PWM Signal Generation 231 17 3 4 3 ll Ei pcm rr 232 bb ee 233 17 5 Low Power ModS ideas a REOR GREC OR IR 233 17 5 1 so f She CEA eR ORR 233 17 52 eo tre Pac eee eee d eer ee aes 233 176 TIM Dn Brea iaceo le dse OE E REED C EY b EIC EL EE ETE EG HR 233 234 17 7 1 TIM Clock Pin A PTDOIATD PETUGLM 234 17 7 2 TIM Channel I O Pins PTF3 TCH5 PTFO TCH2 and PTES TCH1 PTE2 TCHO 234 158 barge EG KO CK S 04 Kcd oda edo Joc eee E CR CICERO 234 17 8 1 TIM Status Control Register uode TERT EA d 234 17 8 2 IARE ERR REAPER RR ER RES 236 MC68HC908AS32A Data Sheet Rev 1
9. 5 257 Chapter 20 Ordering Information and Mechanical Specifications 269 MC68HC908AS32A Data Sheet Rev 1 Freescale Semiconductor 5 P List of Chapters MC68HC908AS32A Data Sheet Rev 1 6 Freescale Semiconductor Table of Contents 1 1 7 2 1 3 1 4 1 4 1 1 4 2 1 4 8 1 4 4 1 4 5 1 4 6 1 4 7 1 4 8 1 4 9 1 4 10 1 4 11 1 4 12 1 4 13 1 4 14 1 4 15 1 4 16 2 1 22 2 3 2 4 2 5 2 6 2 7 2 8 2 8 1 2 8 1 1 2 8 1 2 2 8 1 3 2 8 1 4 2 8 1 5 2 8 1 6 1 General Description 19 19 a dcos dor Tape q PH Eb aep qoe arb ORE HORROR 20 22 Power Supply Fins Vig and PST ER 22 Dsellater Pins 5071 and 5 ER ERERAL RS EFE RR ERE RRERRE EE 23 External Reset Pin 5 23 Exterial Interrupt Pin IRQ ewe rre 23 External Filter Capacitor Pin RR aes 23 Analog Power Supply Re 23 Analog Ground Pin Vase 52556458 doa a RR 24 ADC Reference High Voltage Pin Vpepy e Rr Reed 24 Port A Input Output I O Pins 7 24 B EC Pins PIS AICP TBDIATLIUDS y dew be de RR RO e 24 Font t ID Fine
10. RT3 RT5 and RT7 Start Bit Noise Flag Samples Verification 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 MC68HC908AS32A Data Sheet Rev 1 170 Freescale Semiconductor Functional Description Start bit verification is not successful if any two of the three verification samples are 1s If start bit verification is not successful the RT clock is reset and a new search for a start bit begins To determine the value of a data bit and to detect noise recovery logic takes samples RT8 and RT10 Table 14 3 summarizes the results of the data bit samples Table 14 3 Data Bit Recovery RT8 RT9 and 10 Data Bit Noise Flag Samples Determination 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8 RT9 and RT10 samples do not affect start bit verification If any or all of the RT8 RT9 and RT10 start bit samples are 1s following a successful start bit verification the noise flag NF is set and the receiver assumes that the bit is a start bit To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 14 4 summarizes the results of the stop bit samples Table 14 4 Stop Bit Recovery RT8 RT9 and 10 Framing Noise Flag Samples Error Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
11. Bit 7 6 5 4 3 2 1 Bit 0 Read UNUSED UNUSED UNUSED EEBP2 EEBP1 EEBPO Write Reset Contents of EENVR FE1C Unimplemented Figure 2 5 EEPROM Array Configuration Register EEACR Bit 7 5 Unused Bits These read write bits are software programmable but have no functionality MC68HC908AS32A Data Sheet Rev 1 44 Freescale Semiconductor EEPRTCT EEPROM Protection Bit The bit is used to enable the security feature in the EEPROM see 2 8 1 3 EEPROM Program Erase Protection 1 EEPROM security disabled 0 EEPROM security enabled Electrically Erasable Programmable Read Only Memory EEPROM NOTE This feature is a write once feature Once the protection is enabled it may not be disabled EEBP 3 0 EEPROM Block Protection Bits These bits prevent blocks of EEPROM array from being programmed or erased 1 EEPROM array block is protected 0 EEPROM array block is unprotected Block Number EEBPx Address Range EEBPO 0800 087F EEBP1 0880 08FF EEBP2 0900 097F EEBP3 0980 09FF Table 2 5 EEPROM Block Protect and Security Summary Address Range EEBPx EEPRTCT 1 0 Byte programming available 0 bulk Dock Bind byte Byte programming available 0800 087F erasing available only byte erasing available 1 Protected P
12. 1 1 048576 or 1 0 MHz Vpp 5 0 10 Vss 0V 2 The receiver symbol timing boundaries are subject to an uncertainty of 1 tgp c uis due to sampling considerations 3 See Figure 19 3 Freescale Semiconductor MC68HC908AS32A Data Sheet Rev 1 267 Electrical Specifications BRK Figure 19 3 BDLC Variable Pulse Width Modulation VPW Symbol Timing 19 12 3 BDLC Transmitter DC Electrical Characteristics Characteristic Symbol Min Max Unit BDTxD output low voltage V __ IBDTxD 1 6 mA OLTX 0 4 V BDTxD output high voltage V Van s IBDTx 800 uA OHTX pp 99 V 1 Vpp 5 0 10 Vss 0 T4 40 C to 125 C unless otherwise noted 19 12 4 BDLC Receiver DC Electrical Characteristics Characteristic Symbol Min Max Unit BDRxD input low voltage Vi Rx Vas 0 3 x Vpp V input high voltage 0 7 Vpp V BDRxD input low current 1 1 1 input high current IugpRX 1 1 1 Vpp 5 0 10 Vas 0 T4 40 C to 125 C unless otherwise noted MC68HC908AS32A Data Sheet Rev 1 268 Freescale Semiconductor Chapter 20 Ordering Information and Mechanical Specifications 20 1 Introduction This section provides ordering information for the MC68HC908AS32A along with the dimensions for the 52 pin plastic lea
13. 103 5 4 7 Base Clock Output CGMOUT 103 5 4 8 COM GPU Interrupt CGMINT 66445545 64506546 44995446446 Rd F445 103 5 5 LO aud a A ded acad ok d a fe FR 104 5 5 1 PLE Control PGHISIDE Ea CORR Rd 104 5 5 2 PLL Bandwidth Control Registe rers kara vend eeu Ry RAS 105 5 5 8 E 106 5 6 j v nme 107 5 7 R 108 5 7 1 Wat MOdE 108 9 7 2 DID NIB qo E bob EHE 108 5 8 During Break Infer pts 22056850 108 29 Acquisition Lock Time 5 5 108 5 9 1 Acquisition Lock Time Definitions 108 5 9 2 Parametric Influences on Reaction 109 5 9 3 Choosing a lad 0c jT ER 110 5 9 4 Time r saca ECCE E dr a 110 Chapter 6 Configuration Register CONFIG1 6 1 dod 113 6 2 F nctional ee 2 2 113 Chapter 7 Configuration Register CONFIG2 7 1 ice ers PT eee ee ee ee ee eee eee ee ry eee ee 11
14. 14 4 3 4 Framing Errors If the data recovery logic does not detect a 1 where the stop bit should be in an incoming character it sets the framing error bit FE in SCS1 A break character also sets the FE bit because a break character has no stop bit The FE bit is set at the same time that the SCRF bit is set MC68HC908AS32A Data Sheet Rev 1 Freescale Semiconductor 171 Serial Communications Interface SCI 14 4 3 5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit Then a noise error occurs If more than one of the samples is outside the stop bit a framing error occurs In most applications the baud rate tolerance is much more than the degree of misalignment that is likely to occur As the receiver samples an incoming character it resynchronizes the RT clock on any valid falling edge within the character Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times Slow Data Tolerance Figure 14 7 shows how much a slow received character can be misaligned without causing a noise error or a framing error The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8 RT9 and RT10 For an 8 bit character data sampling of the stop bit takes th
15. Ina PTFO TCH2 IRQ MODULE BYTE DATA LINK CONTROLLER POWER ON RESET MODULE ma BDRxD BDTxD Vas lt AVss Vnerk o cm POWER V Vesa DDAREF Figure 3 1 Block Diagram Highlighting ADC Block and Pins 3 3 2 Voltage Conversion When the input voltage to the ADC equals see 19 7 Analog to Digital Converter ADC Characteristics the ADC converts the signal to FF full scale If the input voltage equals the ADC converts it to 00 Input voltages between and are a Straight line linear conversion Conversion accuracy of all other input voltages is not guaranteed Avoid current injection on unused ADC inputs to prevent potential conversion error NOTE Input voltage should not exceed the analog supply voltages MC68HC908AS32A Data Sheet Rev 1 58 Freescale Semiconductor Functional Description INTERNAL DATA BUS ZN READ DDRB DDRB WRITE DDRB DDRD DISABLE RESET DDRBx DDRDx WRITE PTB PTD gl PTBuPTOx ADC CHANNEL x READ PTB PTD 4 2 DISABLE ADC DATA REGISTER 4 NZ CONVERSION ADC VOLTAGE IN INTERRUPT COMPLETE ADC LOGIC SELECT iei coco ADC CLOCK CGMXCLK gt CLOCK BUS CLOCK GENERATOR ADIV 2 0 ADICLK Figure 3 2 ADC Block D
16. Bit 7 6 5 4 3 2 1 Bit 0 Read LOCK PN 0 0 0 0 AUTO ACQ XLD Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 5 5 PLL Bandwidth Control Register PBWC AUTO Automatic Bandwidth Control Bit This read write bit selects automatic or manual bandwidth control When initializing the PLL for manual operation AUTO 0 clear the ACQ bit before turning on the PLL Reset clears the AUTO bit 1 Automatic bandwidth control 0 Manual bandwidth control LOCK Lock Indicator Bit When the AUTO bit is set LOCK is a read only bit that becomes set when the VCO clock CGMVCLK is locked running at the programmed frequency When the AUTO bit is clear LOCK reads as 0 and has no meaning Reset clears the LOCK bit 1 VCO frequency correct or locked 0 VCO frequency incorrect or unlocked Acquisition Mode Bit When the AUTO bit is set ACQ isa read only bit that indicates whether the PLL is in acquisition mode or tracking mode When the AUTO bit is clear ACQ is a read write bit that controls whether the PLL is in acquisition or tracking mode MC68HC908AS32A Data Sheet Rev 1 Freescale Semiconductor 105 Clock Generator Module CGM In automatic bandwidth control mode AUTO 1 the last written value from manual operation is stored in a temporary location and is recovered when manual operation resumes Reset clears this bit enabling acquisition mode 1 Tracking mode 0 Acquisition mode XLD
17. Description Write to last address accessed 1 Operand Single data byte Data Returned None Opcode 19 Command Sequence FROM HOST J IWRITE IWRITE DATA DATA ECHO A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64 Kbyte memory map Table 18 8 READSP Read Stack Pointer Command Description Reads stack pointer Operand Data Returned None Returns incremented stack pointer value SP 1 in high byte low byte order Opcode 0C ECHO Command Sequence FROM HOST READSP READSP RETURN Table 18 9 RUN Run User Program Command Description Executes PULH and instructions Operand None Data Returned None Opcode 28 The MCU executes the SWI and PSHH instructions when it enters monitor mode The RUN command tells the MCU to execute the PULH and RTI instructions Before sending the RUN command the host can 254 Command Sequence FROM HOST Com ECHO MC68HC908AS32A Data Sheet Rev 1 Freescale Semiconductor Monitor Module MON modify the stacked CPU registers to prepare to run the host program The READSP command returns the incremented stack pointer value SP 1 The high and low bytes of the program counter are at addresses SP 5 and SP 6 Figure 18 12 Stack Pointer at Monitor Mode Entry 18 3 2 Securit
18. 211 16 6 1 TIT ET 211 16 6 2 1 Hilo eT TP rrr 213 214 16 8 Queuing Transmission Dala 4249 a eV dr PEOR EI HE eR ed CER RR m Re d a s 215 289 SPI 595 deed eX Re D ee a eee ee 216 16 10 Low Power Moges She ode pipi EQUES paces seus E Sx pP EASQUE Puede E Rr 216 Tcro 216 bb Reb 216 SPI During 5 54 555 555 555555 54 216 TEASE aided idus eee CK RD Jd ODE CA CROP ees 217 18 121 MISU Master In Slave 217 18122 MOSI Master DUE I 217 10129 rer 218 16 124 GRISE ar uestis qd but aeque dames 218 030 219 ox MU ri d o PRETERITO eee 219 2a a kid 1d 9 343 E ACC 219 181328 Status and Control Register 220 16 133 PVA Regter woke RIES 223 17 Timer Interface Module TIM DAMES 0 Drop 225 Ir Pees 225 173 i esc add
19. X 2 don t care EELAT EEPROM Latch Control This read write bit latches the address and data buses for programming the EEPROM array EELAT cannot be cleared if EEPGM is still set Reset clears this bit 1 Buses configured for EEPROM programming or erase operation 0 Buses configured for normal operation AUTO Automatic Termination of Program Erase Cycle When AUTO is set EEPGM is cleared automatically after the program erase cycle is terminated by the internal timer See note D for 2 8 1 7 EEPROM Programming 2 8 1 8 EEPROM Erasing and 19 11 2 EEPROM Memory Characteristics 1 Automatic clear of EEPGM is enabled 0 Automatic clear of EEPGM is disabled EEPGM EEPROM Program Erase Enable This read write bit enables the internal charge pump and applies the programming erasing voltage to the EEPROM array if the EELAT bit is set and a write to a valid EEPROM location has occurred Reset clears the EEPGM bit 1 EEPROM programming erasing power switched on 0 EEPROM programming erasing power switched off NOTE Writing Os to both the EELAT and EEPGM bits with a single instruction will clear EEPGM only to allow time for the removal of high voltage 2 8 2 2 EEPROM Array Configuration Register The EEPROM array configuration register configures EEPROM security and EEPROM block protection This read only register is loaded with the contents of the EEPROM nonvolatile register EENVR after a reset Address FE1F
20. 5 STHX opr Store H X in M 1 lt H X 42 DIR 35 dd 4 Enable Interrupts Stop Processing 3 _ EE STOP Refer to MCU Documentation lt 0 Stop Processing 0 INH 8E 1 STX opr DIR BF dd 3 STX opr EXT CF 4 STX 1 2 DF 4 STX opr X Store X in M lt X 42 1 1 EF ff 3 STX X IX FF 2 STX oprSP SP1 9EEF ff 4 STX oprSP SP2 9EDF 5 SUB opr IMM AO iii 2 SUB opr DIR BO dd 3 SUB opr EXT CO hhll 4 SUB IX2 DO 4 SUB Subtract A lt A M t t EO f 3 SUB X IX FO 2 SUB opr SP SP1 9EEO ff 4 SUB opr SP SP2 9EDO ee ff 5 MC68HC908AS32A Data Sheet Rev 1 130 Freescale Semiconductor Table 9 1 Instruction Set Summary Sheet 6 of 6 Opcode Map Effect 2 o ul Operation Description 5 g 9 S gt 2 lt lt 6 6 PC lt 1 Push PCL SP lt SP 1 Push PCH SP lt SP 1 Push X SWI Software Interrupt gee ise 1 INH 83 9 SP lt SP 1 1 lt 1 lt Interrupt Vector High Byte PCL lt Interrupt Vector Low Byte TAP Transfer A to CCR lt sf INH 84 2 TAX Transfer A to X X A 7 97 1 TPA Transfer CCR to A A lt 7 85 1 TST opr DIR dd 3 TSTA INH 4D 1 131X i INH 5D 1 TST oprX Test for Negative o
21. 5 66 OD 5 67 OF 5 BRN rel Branch Never PC lt 2 REL 21 jrr 3 DIR 60 00 5 DIR 61 02 5 62 04 ddrr 5 BRSET n opr rel Branch if Bit n in M Set lt 3 rel Mn 1 t DiR b4 05 dim e 65 5 DIR 66 5 DIR b7 OE 5 DIR 60 10 dd 4 DIR b1 12 dd 4 DIR b2 14 dd 4 b3 16 dd 4 n opr Set Bit nin M Mn lt 1 DIR 18 Jad 4 65 1A dd 4 b6 1 dd 4 67 4 PC lt 2 push PCL BSR rel Branch to Subroutine Si REL AD 4 PC lt rel PC lt 3 rel 00 DIR 31 ddrr 5 CBEQA stopr rel PC lt PC 3 rel A M 30 IMM 41 4 CBEQX stopr rel lt 3 rel X 00 51 4 and Branch if Equal lt PC 3 rel A M 00 1 1 61 5 CBEQ lt PC 2 rel A 00 1 71 i 4 CBEQ PC lt 4 rel M 00 SP1 9E61 ff rr 6 CLC Clear Carry Bit 0 INH 98 1 CLI Clear Interrupt Mask 1 0 0 9A 2 MC68HC908AS32A Data Sheet Rev
22. for block erase for bulk erase Clear EEPGM bit Wait for a time tggepy for the erasing voltage to fall Go to Step 8 Poll the EEPGM bit until it is cleared by the internal timer D Clear EELAT bits ES A Setting the EELAT bit configures the address and data buses to latch data for erasing the array Only valid EEPROM adaresses will be latched If EELAT is set other writes to the EECH will be allowed after a valid EEPROM write B If more than one valid EEPROM write occurs the last address and data Will be latched overriding the previous address and data Once data is written to the desired address do not read EEPROM locations other than MC68HC908AS32A Data Sheet Rev 1 42 Freescale Semiconductor Electrically Erasable Programmable Read Only Memory EEPROM the written location Reading an EEPROM location returns the latched data and causes the read address to be latched C The EEPGM bit cannot be set if the EELAT bit is cleared or a non valid EEPROM address is latched This is to ensure proper programming sequence Once EEPGM is set do not read any EEPROM locations otherwise the current program cycle will be unsuccessful When EEPGM is set the on board programming sequence will be activated D The delay time for the EEPGM bit to be cleared in AUTO mode is less than However on other MCUS this delay time may be different F
23. MC68HC908AS32A Data Sheet Rev 1 Freescale Semiconductor 187 D System Integration Module SIM M68HC08 CPU gt lt lt CPU ARITHMETIC LOGIC gt PTA7 PTAO REGISTERS UNIT ALU a MODULE PTB7 ATD7 CONTROL AND STATUS REGISTERS P KI PTBO ATDO BREAK MODULE USER FLASH 32 256 BYTES gt ds e 2 LOW VOLTAGE INHIBIT GE b gt PTC2IMCLK USER RAM 1024 BYTES MODULE gt PTCI PTOO de COMPUTER OPERATING lt gt PTDG ATD14 TCLK USER EEPROM 512 BYTES gt PROPERLY MODULE lt gt T E lt gt 2 MONITOR ROM 256 BYTES gt 6 CHANNEL TIMER KS PTD3 ATD11 INTERFACE MODULE PTDO ATD8 l PTE7 SPSCK USER FLASH VECTOR SPACE 52 BYTES KD PROGRAMMABLE INTERRUPT TIMER MODULE 7 lt gt PTES MISO CLOCK GENERATOR w u lt gt 4 66 lt lt MODULE KS gt CGMXFC gt SERIAL COMMUNICATIONS PTE3 TCH1 INTERFACE MODULE lt lt lt gt PTE1 RxD lt gt PTEO TxD SERIAL PERIPHERAL SYSTEM INTEGRATION RST MODULE C INTERFACE MODULE He 5 C8 7 S PTFO TCH2 IRQ gt IRQ MODULE gt BYTE DATA LINK CONTRO
24. Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 MCLKEN DDRC4 DDRC3 DDRC2 DDRC1 DDRCO rite Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 8 Data Direction Register C DDRC MCLKEN MCLK Enable Bit This read write bit enables MCLK to be an output signal on PTC2 MCLK is the same frquency as the bus clock If MCLK is enabled DDRC2 has no effect Reset clears this bit 1 MCLK output enabled 0 MCLK output disabled DDRC 4 0 Data Direction Register C Bits These read write bits control port C data direction Reset clears DDRC 4 0 configuring all port C pins as inputs 1 Corresponding port C pin configured as output 0 Corresponding port C pin configured as input NOTE Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1 MC68HC908AS32A Data Sheet Rev 1 Freescale Semiconductor 153 Input Output Ports Figure 13 9 shows the port C logic ZN READ DDRC 0006 WRITE DDRC 0006 e 2 5 WRITE 0002 lt 2 z READ PTC 0002 Figure 13 9 Port Circuit When bit DDRCx is 1 reading address 0002 reads the PTCx data latch When bit DDRCx is a 0 reading address 0002 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 13 3 summarizes the operation of the port C
25. 5o CGMXCLK o Jk JS can be 0 shorted when used with higher frequency crystals Refer to manufacturer s data Figure 5 3 CGM External Connections MC68HC908AS32A Data Sheet Rev 1 102 Freescale Semiconductor Signals 5 4 Signals The following paragraphs describe the CGM input output I O signals 5 4 1 Crystal Amplifier Input Pin OSC1 The OSC1 pin is an input to the crystal oscillator amplifier 5 4 2 Crystal Amplifier Output Pin OSC2 The OSC2 pin is the output of the crystal oscillator inverting amplifier 5 4 3 External Filter Capacitor Pin CGMXFC The CGMXFC pin is required by the loop filter to filter out phase corrections A small external capacitor is connected to this pin NOTE To prevent noise problems should be placed as close to the CGMXFC pin as possible with minimum routing distances and no routing of other signals across the Cp connection 5 4 4 Analog Power Pin VppA is a power pin used by the analog portions of the PLL Connect the pin to the same voltage potential as the Vpp pin NOTE Route VppA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package 5 4 5 Oscillator Enable Signal SIMOSCEN The SIMOSCEN signal enables the oscillator and PLL 5 4 6 Crystal Output Frequency Signal CGMXCLK CGMXCLK is the crystal oscillator output signal It
26. By recording the times for successive edges on an incoming signal software can determine the period and or pulse width of the signal To measure a period two successive edges of the same polarity are captured To measure a pulse width two alternate polarity edges are captured Software should track the overflows at the 16 bit module counter to extend its range Another use for the input capture function is to establish a time reference In this case an input capture function is used in conjunction with an output compare function For example to activate an output signal a specified number of clock cycles after detecting an input event edge use the input capture function to record the time at which the edge occurred A number corresponding to the desired delay is added to this captured value and stored to an output compare register see 17 8 5 TIM Channel Registers Because both input captures and output compares are referenced to the same 16 bit modulo counter the delay can be controlled to the resolution of the counter independent of software latencies Reset does not affect the contents of the TIM channel registers 17 3 3 Output Compare With the output compare function the TIM can generate a periodic pulse with a programmable polarity duration and frequency When the counter reaches the value in the registers of an output compare channel the TIM can set clear or toggle the channel pin Output compares can generate TIM CPU interru
27. TOE 5 52 51 50 Write 0 TRST Reset 0 0 1 0 0 0 0 0 Unimplemented Figure 17 4 TIM Status and Control Register TSC TOF TIM Overflow Flag Bit This read write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers Clear TOF by reading the TIM status and control register when TOF is set and then writing a O to TOF If another TIM overflow occurs before the clearing sequence is complete then writing O to TOF has no effect Therefore a TOF interrupt request cannot be lost due to inadvertent clearing of TOF Reset clears the TOF bit Writing a 1 to TOF has no effect 1 TIM counter has reached modulo value 0 TIM counter has not reached modulo value TOIE TIM Overflow Interrupt Enable Bit This read write bit enables TIM overflow interrupts when the TOF bit becomes set Reset clears the TOIE bit 1 TIM overflow interrupts enabled 0 TIM overflow interrupts disabled TSTOP TIM Stop Bit This read write bit stops the TIM counter Counting resumes when TSTOP is cleared Reset sets the TSTOP bit stopping the TIM counter until software clears the TSTOP bit 1 TIM counter stopped 0 TIM counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode Also when the TSTOP bit is set and input capture mode is enabled input captures are inhibited until TSTOP is cleared When using TSTOP to stop th
28. 252 18 3 2 i ol sf CT Mn EPPT 255 Chapter 19 Electrical Specifications 191 257 M 257 19 3 Functional Operating Range 258 Thermal CharactensSiits isa s 40406 OSHS EOS o ab EG 258 195 50 Volt DU Electrical Characteristi S cs sioe ska Re KR Kobie FACE ra 259 IB Conto 260 19 7 Analog to Digital Converter ADC Characteristics 260 19 8 5 0 0 5 V Serial Peripheral Interface SPI 0 261 19 9 Clock Generator Module CGM 5 264 19 9 1 CGM Op rating Conditions aoa dp o Or edo a poe ROI eee LR CR e KIC Red 264 19 9 2 CGM Component ERROR Pom ac E 264 19 9 3 Acquisition Lock Time Information 265 19 10 Timer Module Characteristics asses 265 19 4 265 19 11 1 RAM Memory Characteristics be RII 265 S112 EEPROM Memory Characteristics 266 19752 FLASH Memory 266 MC68HC908AS32A Data Sheet Rev 1 16 Fre
29. 52 K gt PROGRAMMABLE INTERRUPT PES SEE TIMER MODULE CLOCK GENERATOR I CGMXFC gt MODULE SERIAL COMMUNICATIONS lt gt INTERFACE MODULE lt gt lt gt lt gt SERIAL PERIPHERAL SYSTEM INTEGRATION cs MODULE a INTERFACE MODULE ES LL tC LL gt gt IRQ IRQ MODULE gt BYTE DATA LINK CONTROLLER POWER ON RESET MODULE BDRxD BDTxD Vss gt SONER AVgo VREFK Vppa lt lt V Vesa 3 DDAREF Figure 18 1 Block Diagram Highlighting BRK and MON Blocks IAB 15 8 BREAK ADDRESS REGISTER HIGH 8 BIT COMPARATOR IAB 15 0 8 BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB 7 0 Figure 18 2 Break Module Block Diagram MC68HC908AS32A Data Sheet Rev 1 CONTROL BREAK Freescale Semiconductor PTA7 PTAO PTB7 ATD7 PTBO ATDO PTC4 PTC3 PTC2 MCLK PTC1 PTCO PTD6 ATD14 TCLK PTDS ATD13 PTA4 ATD12 PTD3 ATD11 PTDO ATD8 7 5 5 PTE6 MOSI PTES MISO PTE4 SS PTE2 TCHO PTE1 RxD PTEO TxD PTFS TCH5 PTFO TCH2 Break Module BRK When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register the CPU starts a break interrupt by e Loading the instruction register with the SWI instruction e Loading the
30. Crystal Loss Detect Bit When the VCO output CGMVCLK is driving CGMOUT this read write bit can indicate whether the crystal reference frequency is active or not 1 Crystal reference not active 0 Crystal reference active To check the status of the crystal reference do the following 1 Write a 1 to XLD 2 Wait N x 4 cycles N is the VCO frequency multiplier 3 Read XLD The crystal loss detect function works only when the BCS bit is set selecting CGMVCLK to drive CGMOUT When BCS is clear XLD always reads as 0 Bits 3 0 Reserved for Test These bits enable test functions not available in user mode To ensure software portability from development systems to user applications software should write Os to bits 3 0 when writing to PBWC 5 5 3 PLL Programming Register The PLL programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the VCO Address 001 Bit 7 6 5 4 3 2 1 Bit 0 Read MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 rite Reset 0 1 1 0 0 1 1 0 Figure 5 6 PLL Programming Register PPG MUL7 MULA Multiplier Select Bits These read write bits control the modulo feedback divider that selects the VCO frequency multiplier N See 5 3 2 1 Circuits and 5 3 2 4 Programming the PLL A value of 0 in the multiplier select bits configures the modulo feedback divider the same as
31. MC68HC908AS32A Data Sheet Rev 1 Freescale Semiconductor 35 Memory Addr FE1C FE1D FE1F FF80 FF88 FFFF 36 Register Name EEPROM Nonvolatile Register EENVR See page 46 EEPROM Control Register EECR See page 43 EEPROM Array Configuration Register EEACR See page 44 FLASH Block Protect Register FLBPR See page 50 FLASH Control Register FLCR See page 49 COP Control Register COPCTL See page 119 Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Bit 7 6 5 4 3 2 1 Bit 0 EEPRTCT EEBP3 EEBP2 EEBP1 EEBPO Programmed value or 1 in the erased state 0 EEOFF EERAS1 EERASO EELAT AUTO EEPGM 0 0 0 0 0 0 0 0 EEPRTCT