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ANALOG DEVICES -AD8061/AD8062/AD8063 handbook

1. 10 100 1k 10k 100k 1M 10M FREQUENCY Hz TPC 20 Voltage Noise vs Frequency Vg 5V 10 HHH HH 10 100 1k 10k 100k 1M 10M FREQUENCY Hz TPC 21 Current Noise vs Frequency REV C Vg 2 5V G 1 Vin 1k 2 5V 1 Vi 1 OUT i gt J 0 0V 1 500mV DIV 1 80 100 120 140 160 TIME ns TPC 22 Input Overload Recovery Input Step 0 Vto2V 0 20 40 180 200 2 5V VOLTS 1 0V 0 0V 0 20 40 60 80 100 120 140 160 180 200 TIME ns TPC 23 Output Overload Recovery Input Step 0 V to 1 0 2V p p SIDE 2 SIDE 1 80 200mV p p 0 01 0 1 1 10 FREQUENCY MHz TPC 24 CMRR vs Frequency AD8061 AD8062 AD8063
2. 0 7 AVs 0 2V p p E 10 F Ry 1ko Vg 5V 6 Vo 5V 20 I PSRR 30 5 8 40 E 4 f 50 gt PSRR Eg 2 _60 E 70 2 80 1 90 100 0 0 01 0 1 1 10 100 500 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 FREQUENCY MHz DISABLE VOLTAGE TPC 25 PSRR vs Frequency Delta TPC 28 DISABLE Voltage vs Supply Current 20 Vs 5V m 30 G 2 m VpISABLE 4 fiy 10MHz x 40 a x z 50 gt amp 60 o E 70 o E INPUT SIDE 1 2 3 80 2 E 2 5 90 Vg 5V o Vin 400mV rms 100 n 5 1kO 9 110 G 2 120 001 0 1 1 10 100 500 0 0 4 0 8 1 2 1 6 2 0 FREQUENCY MHz TIME us TPC 26 AD8062 Crosstalk Vour 2 0 V p p 1 TPC 29 DISABLE Function Voltage 0Vto5V G 2 Vs 5 V 1000 Vs 25V Vo 0 2V p p 1kOQ Veias 1V IMPEDANCE DISABLED ISOLATION dB 1 10 100 1000 0 1 FREQUENCY MHz FREQUENCY MHz TPC 27 Disabled Output Isolation Frequency Response TPC 30 Output Impedance vs Frequency Vour 0 2 V 1
3. S1 3RD HARMONIC SINGLE 5V SUPPLY TPC 14 Harmonic Distortion vs Frequency 1 0 0 9 OUTPUT VOLTAGE V o a 0 0 10 0 20 0 30 0 40 0 50 TIME ps TPC 15 400 mV Pulse Response 0 01 0 00 0 01 0 02 0 04 0 06 DIFFERENTIAL GAIN 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 0 02 0 00 0 02 Degrees 0 04 0 06 DIFFERENTIAL PHASE TPC 16 Differential Gain and Phase Error G 2 NTSC Input Signal 1 Vs 5 DIFFERENTIAL GAIN 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH Degrees DIFFERENTIAL PHASE 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH TPC 17 Differential Gain and Phase Error G 2 NTSC Input Signal 150 0 Vs 5 FALLING EDGE RISING EDG SLEW V us 1 0 1 5 2 0 2 5 3 0 OUTPUT STEP AMPLITUDE V TPC 18 Slew Rate vs Output Step Amplitude REV C AD8061 AD8062 AD8063 1400 FALLING EDGE 1200 Ve 4V get 1000 I FALLING EDGE 2 Vg 45V gt 1 800 u amp 600 E o 400 RISING Vg 200 0 0 05 10 15 20 2 TPC 19 Slew Rate vs Output Step Amplitude G 2 RISING EDGE Vg 4V EDGE 5V 1 Vs 5V 100 10 CURRENT NOISE pA Hz 5 3 0 3 5 OUTPUT STEP V 4 0
4. o o 2 o LOAD CURRENT mA SINGLE POWER SUPPLY Voltage TPC 2 lIsuppLy VS VsurPLv 1 10 100 1000 FREQUENCY MHz TPC 3 Small Signal Response 0 O 50 Gz1 0 m 3 4 G 2 a ul N a 6 z 5 G 5 z 9 Vo 0 2V p p 1 0 Veias 1V 12 1 10 100 1000 FREQUENCY MHz TPC 4 Small Signal Frequency Response Vo 1 0V p p RL 1kQ VBiAs 1V NORMALIZED GAIN dB 1 10 100 1000 FREQUENCY MHz TPC 5 Large Signal Frequency Response NORMALIZED GAIN dB 1 10 100 1000 FREQUENCY MHz TPC 6 Small Signal Frequency Response REV C AD8061 AD8062 AD8063 Vs 5V Vo 1V p p RL 1kQ VBiAs 1V G 1 NORMALIZED GAIN dB 100 FREQUENCY MHz TPC 7 Large Signal Frequency Response NORMALIZED GAIN dB FREQUENCY MHz TPC 8 0 1 dB Flatness OPEN LOOP GAIN dB FREQUENCY MHz TPC 9 AD8062 Open Loop Gain
5. into a 150 Q load along with 0 1 dB flatness out to 30 MHz Additionally they offer wide bandwidth to 300 MHz along with 800 V us slew rate REV C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices CONNECTION DIAGRAMS Top Views SOIC 8 R SOT 23 6 RT AD8061 Nc 1 ADs063 s DISABLE AD8063 ONLY NC NO CONNECT SOIC 8 R and pSOIC RM Not to Scale The AD8061 AD8062 and AD8063 offer a typical low power of 6 8 mA amplifier while being capable of delivering up to 50 mA of load current The AD8063 has a power down disable feature that reduces the supply current to 400 uA These features make the AD8063 ideal for portable and battery powered applications where size and power are critical Re 500 Vo 0 2V p p Rf 00 3 6 NORMALIZED GAIN dB 9 1 10 100 1000 FREQUENCY MHz Figure 1 Small Signal Response Rr 0 50 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2001 AD8061 AD8062 AD8063 SPECIFICATION T 25 C 1 5 V
6. 5 10 REV C AD8061 AD8062 AD8063 SETTLING TIME TO 0 1 SETTLING TIME ns REV C 0 1 0 1 20ns DIV TPC 31 Output Settling Time to 0 1 RISING EDGE 0 5 1 1 5 2 2 5 OUTPUT VOLTAGE STEP TPC 32 Settling Time vs Vout 4 86 7 7 2 43 0 0V TPC 33 Output Swing 11 3 5V 2 5V 1 5V 500mV DI 0 10 20 30 40 50 60 70 80 90 100 TIME ns TPC 34 1 V Step Response 2 6V 2 5V 2 4V 20mV DIV 0 10 20 30 40 50 60 70 80 90 100 TIME ns TPC 35 100 mV Step Response Vs 5V G 2 Rp R 1kO Vin 4V p p 0 0V TPC 36 Output Rail to Rail Swing AD8061 AD8062 AD8063 2 6V 2 5V 2 4V 50mV DIV 0 5 10 15 20 25 30 35 40 45 50 TIME ns TPC 37 200 mV Step Response Vg 25V G 2 Rp 1k Vin 2V p p 4 5V 2 5V 0 5V 1V DIV 0 5 10 15 20 25 30 35 40 45 50 TIME ns TPC 38 2 V Step Response CIRCUIT DESCRIPTION The AD8061 AD8062 AD8063 family are very high speed volt age feedback op amps The high slew rate inp
7. 0 25 PLANE 0 003 0 08 0 014 0 35 AD8061 AD8062 AD8063 Revision History Location Data Sheet changed from REV B to REV C Replaced PPG 9 with ew gtapli oet o ae a e ete UR EY EU Cea T evden Reese eran es Geena dao de Whaat S meg C01065 0 5 01 C PRINTED IN U S A
8. DC PERFORMANCE Input Offset Voltage 1 6 mV Tyan to Tmax 2 6 mV Input Offset Voltage Drift 3 5 uV C Input Bias Current 3 5 8 5 uA Tmn to Tmax 4 8 5 uA Input Offset Current 0 3 4 5 uA Open Loop Gain Vo 0 5 V to 2 5 V R 150 Q 66 70 dB Vo 0 5 V to 2 5 V Rp 2 KQ 74 90 dB INPUT CHARACTERISTICS Input Resistance 13 MQ Input Capacitance 1 pF Input Common Mode Voltage Range 0 2 to 1 2 V Common Mode Rejection Ratio Vom 0 2V to 1 2 V 80 dB OUTPUT CHARACTERISTICS Output Voltage Swing 1509 0 3 0 1 to 2 87 2 85 V Ry 2 0 3 0 1 to 2 9 2 90 V Output Current Vo 0 5 V to 2 5 V 25 mA Capacitive Load Drive Voy 0 8 V 30 Overshoot G 1 Rs 0 Q 25 pF G 2 Rs 4 7Q 300 pF POWER DOWN DISABLE Turn On Time 40 ns Turn Off Time 300 ns DISABLE Voltage Off 0 8 V DISABLE Voltage On 1 2 V POWER SUPPLY Operating Range 2 7 3 V Quiescent Current per Amplifier 6 8 9 mA Supply Current when Disabled 0 4 mA AD8063 Only Power Supply Rejection Ratio 72 80 dB Specifications subject to change without notice REV C 3 AD8061 AD8062 AD8063 SPECIFICATIONS 2 552 7 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G 1 Vo 0 2 V p p 150 300 MHz G 1 2 Vo 0 2 V p p 60 115 MHz G 1 Vo 1 V p p 230 MHz Bandwidth for 0 1 dB Flatness G 1 Vo 0 2 V p p Vp DC 1 V 30 MHz Slew Rate G 1 Vo 0 7 V Step Ri 2 110 150 V us G 2 Vo
9. and more importantly creates a zero in the feedback path that compensates for the pole created by the output capacitance Figure 8 Series Resistor Isolating Capacitive Load Voltage feedback amplifiers like those in AD806x family will be able to drive more capacitive load without excessive peaking when used in higher gain configurations This is because the increased noise gain reduces the bandwidth of the overall feed back loop Figure 9 plots the capacitance that produces 30 overshoot versus noise gain for a typical amplifier 10000 Rg 4 7 1000 100 CAPACITIVE LOAD pF 2 3 4 5 CLOSED LOOP GAIN Figure 9 Capacitive Load vs Closed Loop Gain DISABLE OPERATION The internal circuit for the AD8063 disable function is shown in Figure 10 When the DISABLE node is pulled below 2 V from the positive supply the supply current will decrease from typi cally 6 5 mA to under 400 uA and the AD8063 output will enter a high impedance state If the DISABLE node is not con nected and thus is allowed to float the AD8063 will stay biased at full power TO AMPLIFIER DISABLE BIAS Figure 10 Disable Circuit of the AD8063 TPC 28 shows AD8063 supply current versus DISABLE volt age TPC 29 plots the output seen when the AD8063 input is driven with a 10 MHz sine wave and the DISABLE is toggled from 0 V to 5 V illustrating the part s turn on and turn off tim
10. 1 5 V Step Ri 2 kQ 95 130 V us Settling Time to 0 196 G 2 Vo 1 V Step 40 ns NOISE DISTORTION PERFORMANCE Total Harmonic Distortion fc 5 MHz Vo 2 V p p Ry 1 kQ 60 dBc fc 20 MHz Vo 2 V p p Ry 1 KQ 44 dBc Crosstalk Output to Output f 5 MHz G 2 90 dBc Input Voltage Noise f 100 kHz 8 5 nV VHz Input Current Noise f 100 kHz 1 2 DC PERFORMANCE Input Offset Voltage 1 6 mV Tam to Tmax 2 6 mV Input Offset Voltage Drift 3 5 Input Bias Current 3 5 uA TMN to Tax 4 8 5 uA Input Offset Current 0 3 4 5 uA Open Loop Gain Vo 0 5 V to 2 2 V Ry 150 Q 63 70 dB Vo 0 5 V to 2 2 V Rp 2 KQ 74 90 dB INPUT CHARACTERISTICS Input Resistance 13 MQ Input Capacitance 1 pF Input Common Mode Voltage Range 0 2 to 0 9 V Common Mode Rejection Ratio Vem 0 2 V to 40 9 V 80 dB OUTPUT CHARACTERISTICS Output Voltage Swing 150 Q 0 3 0 1 to 2 55 2 55 V RL 2 0 25 0 1 to 2 6 2 6 V Output Current Vo 0 5 V to 2 2 V 25 mA Capacitive Load Drive Voy 0 8 V 30 Overshoot G 1 Rs 0 Q 25 pF G 2 Rs 4 70 300 pF POWER DOWN DISABLE Turn On Time 40 ns Turn Off Time 300 ns DISABLE Voltage Off 0 5 V DISABLE Voltage On 0 9 V POWER SUPPLY Operating Range 2 7 8 V Quiescent Current per Amplifier 6 8 8 5 mA Supply Current when Disabled 0 4 mA AD8063 Only Power Supply Rejection Ratio 80 dB Specifications subject to change without notice Ls REV C AD8061 AD8062 AD8063 ABSOLUTE MA
11. R 1 Vo 1 V unless otherwise noted Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G 1 Vo 0 2 V p p 150 320 MHz G 1 2 Vo 0 2 V p p 60 115 MHz 3 dB Large Signal Bandwidth G 1 Vo 1 V p p 280 MHz Bandwidth for 0 1 dB Flatness G 1 Vo 0 2 V p p 30 MHz Slew Rate G 1 Vo 2 V Step Ri 2 500 650 V us G 2 Vo 2 V Step 2 kQ 300 500 V us Settling Time to 0 196 G 2 Vo 2 V Step 35 ns NOISE DISTORTION PERFORMANCE Total Harmonic Distortion fc 5 MHz Vo 2 V p p 1 KQ 77 dBc fc 20 MHz Vo 2 V p p Ry 1 kQ 50 dBc Crosstalk Output to Output f 5 MHz G 2 AD8062 90 dBc Input Voltage Noise f 100 kHz 8 5 nV VHz Input Current Noise f 100 kHz 1 2 pA VHz Differential Gain Error NTSC G 2 R 150 9 0 01 Differential Phase Error NTSC G 2 1502 0 04 Degree Third Order Intercept f 10 MHz 28 dBc SFDR f 5 MHz 62 dB DC PERFORMANCE Input Offset Voltage 1 6 mV Twin to Tmax 2 6 mV Input Offset Voltage Drift 3 5 uV C Input Bias Current 3 5 9 uA Tmn to Tmax 4 9 uA Input Offset Current 0 3 4 5 uA Open Loop Gain Vo 0 5 V to 4 5 V R 150 Q 68 70 dB Vo 0 5 V to 4 5 V Rp 2 KQ 74 90 dB INPUT CHARACTERISTICS Input Resistance 13 MQ Input Capacitance 1 pF Input Common Mode Voltage Range 0 2 to 3 2 V Common Mode Rejection Ratio Vem 0 2 V to 3 2 V 62 80 dB OUTPUT CHARACTERISTICS Output Volta
12. and Phase vs Frequency Vs 5 V 1 kQ REV C PHASE Degrees 2ND 1MHz 3RD 10MHz HARMONIC DISTORTION dBc 2ND 10MHz 3RD 1MHz 0 5 1 0 1 5 2 0 2 5 3 0 3 5 INPUT SIGNAL BIAS V TPC 10 Harmonic Distortion for a 1 V p p Signal vs Input Signal DC Bias gt 1M2 INPUT 2ND H DISTORTION dB 3RDH 0 01 0 1 1 10 50 FREQUENCY MHz START 10kHz STOP 30MHz TPC 11 Harmonic Distortion for a 1 V p p Output Signal vs Input Signal DC Bias Vg 5V oF BL Vo 1V 50 2ND 3RD 10MHz 60 1 wm a 70 80 e A 90 2ND 3RD 5MHz 100 1MHz 110 2ND 3RD 120 1 2 3 4 5 OUTPUT SIGNAL DC BIAS V TPC 12 Harmonic Distortion vs Output Signal DC Bias AD8061 AD8062 AD8063 40 Vg 5V Rp 10 50 FG 2 2ND 10MHz j a 1 z 2ND 2MHz o E a e 80 2ND 500kHz 7 o a 90 3RD e 2MHz 100 3RD 500kHz 110 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 RTO OUTPUT V p p TPC 13 Harmonic Distortion vs Output Signal Amplitude 1 1 2ND HARMONI DUAL 2 5V SUPPLY 1 D HARMONIC E 45V SUPPLY IL 0 01 0 1 1 10 FREQUENCY MHz START 10kHz STOP 30MHz DISTORTION dB
13. not at ground but at some positive voltage The circuit can be modified to provide the sync stripping function for such a waveform Instead of connecting RG to ground it should be connected to a dc voltage that is two times the black level of the input signal The gain from the input to the output is two which means that the black level will be amplified by two to the output However the gain through RG is unity to the output It will take a dc level of twice the input black level to shift the black level to ground at the output When this occurs the sync will be stripped and the active video will be passed as in the ground referenced case MONITOR 1 MONITOR 2 Figure 13 RGB Cable Driver Using AD8061 and AD8062 REV C RGB Amplifier Most RGB graphics signals are created by video DAC outputs that drive a current through a resistor to ground At the video black level the current goes to zero and thus the voltage of the video is also zero Before the availability of high speed rail to rail op amps it was essential that an amplifier have a negative supply to amplify such a signal Such an amplifier is necessary if one wants to drive a second monitor with from the same DAC outputs However high speed rail to rail output amplifiers like the AD8061 and AD8062 can accept ground level input signals and output ground level signals and thus be used as RGB signal amplifiers A combination of the AD8061 single and AD806
14. 2 dual can amplify the three video channels of an RGB system Figure 13 shows a circuit that performs this function Multiplexer The AD8063 has a disable pin that can be used to power down the amplifier to save power or can be used to create a mux circuit If two or more AD8063 outputs are connected together and only one is enabled then only the signal of the enabled amplifier will appear at the output This configuration can be used to select from various input signal sources Additionally the same input signal can be applied to different gain stages or differently tuned filters to make a gain step amplifier or a selectable frequency amplifier Figure 14 shows a schematic of two AD8063s used to create a mux that selects between two inputs One of these is a 1 V p p 3 MHz sine wave and the other is a 2 V p p 1 MHz sine wave SELECT Figure 14 Two to One Multiplexer Using Two AD8063s 15 AD8061 AD8062 AD8063 The SELECT signal and the output waveforms are shown in Figure 15 For synchronization clarity two differ ent frequency synthesizers whose time bases are other generate the signals for this circuit locked to each OUTPUT SELECT Figure 15 AD8063 Mux Output OUTLINE DIMENSIONS Dimensio
15. 2AR 40 C to 85 C 8 Lead SOIC SO 8 AD8062AR REEL 40 C to 85 C 8 Lead SOIC 13 Inch Tape and Reel AD8062AR REEL7 40 C to 85 C 8 Lead SOIC 7 Inch Tape and Reel AD8062ARM 40 C to 85 C 8 Lead uSOIC RM 8 HCA AD8062ARM REEL 40 C to 85 C 8 Lead ui SOIC 13 Inch Tape and Reel HCA AD8062ARM REEL7 40 C to 85 C 8 Lead uSOIC 7 Inch Tape and Reel HCA AD8063AR 40 C to 85 C 8 Lead SOIC SO 8 AD8063AR REEL 40 C to 85 C 8 Lead SOIC 13 Inch Tape and Reel AD8063AR REEL7 40 C to 85 C 8 Lead SOIC 7 Inch Tape and Reel AD8063ART REEL 40 C to 85 C 6 Lead SOT 23 RT 6 13 Inch Tape and Reel HHA AD8063ART REEL7 40 C to 85 C 6 Lead SOT 23 RT 6 7 Inch Tape and Reel HHA CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8061 AD8062 AD8063 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality REV C 5 WT ESD SENSITIVE DEVICE WARNING WA AD8061 AD8062 AD8063 Typical Performance Characteristics VOLTAGE DIFFERENTIAL FROM Vg TPC 1 Output Saturation Voltage vs Load Current POWER SUPPLY CURRENT mA NORMALIZED GAIN dB 12 E eo
16. 4V TO 3 8V 4V AND 5V 7 2 3 24 0 100 200 300 400 500 600 TIME ns Figure 6 Pulse Response for G 1 Follower Input Step Overloading the Input Stage Output Output overload recovery is typically within 40 ns after the amplifier s input is brought to a nonoverloading value Figure 7 shows output recovery transients for the amplifier recovering from a saturated output from the top and bottom supplies to a point at midsupply 5 0 4 6 42 OUTPUT VOLTAGE 5V TO 2 5V 3 8 34 x OUTPUT VOLTAGE OV TO 2 5V 3 0 2 6 2 2 1 8 1 4 1 0 INPUT AND OUTPUT VOLTAGE V o 0 10 20 30 40 50 60 70 TIME ns Figure 7 Overload Recovery G 1 V 5 V CAPACITIVE LOAD DRIVE The AD806x family is optimized for bandwidth and speed not for driving capacitive loads Output capacitance will create a pole in the amplifier s feedback path leading to excessive peaking and potential oscillation If dealing with load capaci tance is a requirement of the application the two strategies to consider are 1 using a small resistor in series with the amplifier s output and the load capacitance and 2 reducing the bandwidth of the amplifier s feedback loop by increasing the overall noise gain 13 AD8061 AD8062 AD8063 Figure 8 shows a unity gain follower using the series resistor strategy The resistor isolates the output from the capacitance
17. ANALOG DEVICES Low Cost 300 MHz Rail to Rail Amplifiers AD8061 AD8062 AD8063 FEATURES Low Cost Single AD8061 Dual AD8062 Single with Disable AD8063 Rail to Rail Output Swing 6 mV Vos High Speed 300 MHz 3 dB Bandwidth G 1 800 V ps Slew Rate 8 5 nV VHz 5 V 35 ns Settling Time to 0 1 with 1 V Step Operates on 2 7 V to 8 V Supplies Input Voltage Range 0 2 V to 43 2 V with Vs 5 Excellent Video Specs R 150 G 2 Gain Flatness 0 1 dB to 30 MHz 0 01 Differential Gain Error 0 04 Differential Phase Error 35 ns Overload Recovery Low Power 6 8 mA Amplifier Typical Supply Current AD8063 400 pA when Disabled Small Packaging AD8061 Available in SOIC 8 and SOT 23 5 AD8062 Available in SOIC 8 and pSOIC AD8063 Available in SOIC 8 and SOT 23 6 APPLICATIONS Imaging Photodiode Preamp Professional Video and Cameras Hand Sets DVD CD Base Stations Filters A to D Driver PRODUCT DESCRIPTION The AD8061 AD8062 and AD8063 are rail to rail output volt age feedback amplifiers offering ease of use and low cost They have bandwidth and slew rate typically found in current feed back amplifiers All have a wide input common mode voltage range and output voltage swing making them easy to use on single supplies as low as 2 7 V Despite being low cost the AD8061 AD8062 and AD8063 provide excellent overall performance For video applications their differential gain and phase errors are 0 01 and 0 04
18. XIMUM RATINGS Supply Voltage eeii edere ip a eee ee eee 8V Internal Power Dissipation Plastic Package 1 3 W Small Outline Package R 0 8 W SOT 23 5 Package 0 5 W SOT 23 6 Package oes eee nn 0 5 W USOIC Package 0 6 W Input Voltage Common Mode Vs 0 2 V to Vs 1 8 V Differential Input Voltage tVs Output Short Circuit Duration enne Bro bed Observe Power Derating Curves Storage Temperature Range R RM SOT 23 5 SOT223 0 lucere E qe RE 65 C to 125 C Operating Temperature Range 40 C to 85 C Lead Temperature Range Soldering 10 sec 300 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specification is for device in free air 8 Lead SOIC Package y 160 C W 56 C W 5 Lead SOT 23 5 Package 0 240 C W 92 C W 6 Lead SOT 23 6 Package 0j 230 C W 92 C W 8 Lead USOIC Package 054 200 C W 44 C W MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipate
19. d by the AD806x is limited by the associated rise in junction temperature The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic approximately 150 C Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package Exceeding a junction temperature of 175 C for an extended period can result in device failure While the AD806x is internally short circuit protected this may not be sufficient to guarantee that the maximum junction temperature 150 C is not exceeded under all conditions To ensure proper operation it is necessary to observe the maximum power derating curves 2 0 1 5 1 0 0 5 MAXIMUM POWER DISSIPATION Watts 0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE C Figure 2 Plot of Maximum Power Dissipation vs Temperature for AD8061 AD8062 AD8063 ORDERING GUIDE Temperature Package Package Branding Model Range Description Option Information AD8061AR 40 C to 85 C 8 Lead SOIC SO 8 AD8061AR REEL 40 C to 85 C 8 Lead SOIC 13 Inch Tape and Reel AD8061AR REEL7 40 C to 85 C 8 Lead SOIC 7 Inch Tape and Reel AD8061ART REEL 40 to 85 C 5 Lead SOT 23 RT 5 13 Inch Tape and Reel HGA AD8061ART REEL7 40 C to 85 C 5 Lead SOT 23 RT 5 7 Inch Tape and Reel HGA AD806
20. e TPC 27 shows the input output isolation response with the AD8063 shut off 14 BOARD LAYOUT CONSIDERATIONS Maintaining the high speed performance of the AD806x family requires the use of high speed board layout techniques and low parasitic components The PCB should have a ground plane covering unused portions of the component side of the board to provide a low impedance path The ground plane should be removed near the package to reduce parasitic capacitance Proper bypassing is critical A ceramic 0 1 chip capacitor should be used to bypass both supplies and be located within mm of each power pin An additional 4 7 uF to 10 uF tanta lum electrolytic capacitor should be connected in parallel to provide charge for fast large signal changes at the output Minimizing parasitic capacitance at the amplifier s inverting input pin is very important The feedback resistor should be located close to the inverting input pin The value of the feed back resistor may come into play for instance 1 kQ interacting with 1 pF of parasitic capacitance creates a pole at 159 MHz Stripline design techniques should be used for signal traces longer than 25 mm These should be designed with either 50 Q or 75 Q characteristic impedance and be properly terminated at each end APPLICATIONS Single Supply Sync Stripper When a video signal contains synchronization pulses it is sometimes desirable to remove them prior to performing cer
21. e rising edge settling time for the amplifier configured as a unity gain follower stretches out as the top ofa 1 V step input approaches and exceeds the specified input common mode voltage limit REV C AD8061 AD8062 AD8063 For signals approaching the minus supply and inverting gain and high positive gain configurations the headroom limit will be the output stage The AD806x amplifiers use a common emitter style output stage This output stage maximizes the available output range limited by the saturation voltage of the output transistors The saturation voltage increases with the drive current the output transistor is required to supply due to the output transistors collector resistance The saturation voltage can be estimated using the equation Vs47 25 mV Ip x 8 Q where is the output current and 8 Q is a typical value for the output transistors collector resistance 3 6 34 3 2 gt 1 3 0 2V TO 3V STEP LE 1 D ace 2 1V TO 3 1V STEP gt 5 26 2 2V TO 3 2V STEP 2 T M Op 5 2 3V 3 3V STEP T 2 4 24V TO 3 4V STEP 2 2 2 0 0 4 8 12 16 20 24 28 32 TIME ns Figure 5 Output Rising Edge for 1 V Step at Input Head room Limits G 1 Vs 5V 0V As the saturation point of the output stage is approached the output signal will show increasing amounts of compres
22. ge Swing Load Resistance 1500 0 3 0 1 to 4 5 4 75 V Is Terminated at Midsupply Ry 2 0 25 0 1 to 4 9 4 85 V Output Current Vo 0 5 V to 4 5 V 25 50 mA Capacitive Load Drive Voy 0 8 V 30 Overshoot G 1 Rs 0 25 pF G 2 Rs 4 7Q 300 pF POWER DOWN DISABLE Turn On Time 40 ns Turn Off Time 300 ns DISABLE Voltage Off 2 8 V DISABLE Voltage On 3 2 V POWER SUPPLY Operating Range 2 1 5 8 V Quiescent Current per Amplifier 6 8 9 5 mA Supply Current when Disabled 0 4 mA AD8063 Only Power Supply Rejection Ratio AV 2 7Vto5 72 80 dB Specifications subject to change without notice c2 REV C AD8061 AD8062 AD8063 SPECIFICATIONS T 25 C Vs 3 V 1 V 1 V unless otherwise noted Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G 1 Vo 0 2 V p p 150 300 MHz G 1 2 Vo 0 2 V p p 60 115 MHz 3 dB Large Signal Bandwidth G 1 Vo 1 V p p 250 MHz Bandwidth for 0 1 dB Flatness G 1 Vo 0 2 V p p 30 MHz Slew Rate G 1 Vo 1 V Step Ry 2 KQ 190 280 V us G 2 Vo 1 5 V Step 2 kQ 180 230 V us Settling Time to 0 196 G 2 Vo 1 V Step 40 ns NOISE DISTORTION PERFORMANCE Total Harmonic Distortion fo 5 MHz Vo 2 V p p 1 KQ 60 dBc 20 MHz Vo 2 V p p 1 KQ 44 dBc Crosstalk Output to Output f 5 MHz G 2 90 dBc Input Voltage Noise f 100 kHz 8 5 nV VHz Input Current Noise f 100 kHz 1 2
23. ns shown in inches and mm 5 Lead SOT 23 5 8 Lead SOIC RT 5 SO 8 0 1220 3 100 _ 0 1968 5 00 0 1063 2 700 HEE Gm H HH 8 5 0 0709 1 800 3 0 1181 3 000 CHER 02084 0 0590 1 500 i 0 0984 2 500 5 0 i pn E EH Pwa t 0 0196 0 50 0 0500 1 27 A 0 0374 0 950 REF BSE 0099 0 25 45 0 0748 1 900 0 0688 1 75 REF 0 0098 0 25 v Y 0 0532 1 35 _ 0 0079 0 200 0 0040 0 10 a gt 8 gt 4 0 0512 1 300 4 C 0 0571 1 450 0 0035 0 090 seating 0 0192 0 49 0 0098 0 25 0 0 0500 1 27 0 0354 0 900 0 0354 0 900 m PLANE 0 0138 0 35 0 0075 0 19 9 0160 0 41 gt 10 gt Pay 0 0059 0 150 0 0197 0500 SEATING t D 0 0236 0 600 0 0000 0 000 0 0118 0 300 0 0039 0 100 6 Lead SOT 23 6 8 Lead pSOIC RT 6 RM 8 0 122 3 10 0 122 3 10 0 106 2 70 m em 0 071 1 80 5 0 118 3 00 0 122 3 10 0 193 oo59 150 1 0098 250 0 114 2 90 620 4 a i PIN 1 A 0 037 0 95 BSC PINI fe 0 037 0 95 0 0256 0 65 BSC 0 030 0 75 0 075 1 90 0 043 o BSC 0 006 0 15 4 1 10 0 051 1 30 0 057 1 45 0 002 0 05 E S D _ gt je 0 035 0 90 4 0 035 0 90 4 4 GU SEATING 0 099 0 23 0 0 028 0 70 ge MN 0 005 0 13 0 016 0 40 0 006 0 15 0 020 0 50 SEATING 9 999 0 23 0 0 022 0 55 0 000 0 00 0 010
24. ommon mode voltage for the AD806x amplifier on a 5 V supply Accurate dc performance is maintained from about 200 mV below the minus supply to within 1 8 V of the positive supply For high speed signals however there are other consid erations Figure 4 shows 3 dB bandwidth versus dc input 4 0 0 5 0 0 5 1 0 1 5 20 25 3 0 35 4 0 Vem 7 V Figure 3 Vos vs Common Mode Voltage Vs 5 V 2 GAIN dB 4 6 8 0 1 1 10 100 1000 10000 FREQUENCY MHz Figure 4 Unity Gain Follower Bandwidth vs Input Common Mode Vs 5 voltage for a unity gain follower As the common mode voltage approaches the positive supply the amplifier holds together well but the bandwidth begins to drop at 1 9 V within Vs This can manifest itself in increased distortion or settling time TPC 10 plots the distortion of a 1 V p p signal with the AD806x amplifier used as a follower on a 5 V supply versus signal common mode voltage Distortion performance is maintained until the input signal center voltage gets beyond 2 5 V as the peak of the input sine wave begins to run into the upper common mode voltage limit Higher frequency signals require more headroom than the lower frequencies to maintain distortion performance Figure 5 illustrates how th
25. sion and clipping As in the input headroom case the higher frequency signals require a bit more headroom than the lower frequency signals TPCs 11 12 and 13 illustrate the point plotting typical distortion versus output amplitude and bias for gains of 2 and 5 Overload Behavior and Recovery Input The specified input common mode voltage of the AD806x is 200 mV below the negative supply to within 1 8 V of the posi tive supply Exceeding the top limit results in lower bandwidth and increased settling time as seen in Figures 4 and 5 Push ing the input voltage of a unity gain follower beyond 1 6 V within the positive supply leads to the behavior shown in Figure 6 an increasing amount of output error as well as much increased settling time Recovery time from input voltages 1 6 V or closer to the positive supply is about 35 ns which is limited by the settling artifacts caused by transistors in the input stage com ing out of saturation The AD806x family does not exhibit phase reversal even for input voltages beyond the voltage supply rails Going more than 0 6 V beyond the power supplies will turn on protection diodes at the input stage which will greatly increase the device s current draw REV C 37 3 5 3 3 3 1 H VOLTAGE STEP 5 FROM 2 4V TO 3 4V 9 29 E VOLTAGE STEP a FROM 2 4V TO 3 6V 2 27 8 T VOLTAGE STEP FROM 2
26. tain operations In the case of A to D conversion the sync pulses will consume some of the dynamic range so removing them will increase the converter s available dynamic range for the video information Figure 11 shows a basic circuit for creating a sync stripper using the AD8061 powered by a single supply When the nega tive supply is at ground potential the lowest potential to which the output can go is ground This feature is exploited to create a waveform whose lowest amplitude is the black level of the video and does not include the sync level Rg PIN NUMBERS ARE 1kQ FOR 8 PIN PACKAGE Figure 11 Single 3 V Sync Stripper Using AD8061 In this case the input video signal has its black level at ground so it comes out at ground at the input Since the sync level is below the black level it will not show up at the output However all of the active video portion of the waveform will be amplified by a gain of two and then be normalized to unity gain by the back terminated transmission line Figure 12 is an oscilloscope plot of the input and output waveforms REV C AD8061 AD8062 AD8063 INPUT OUTPUT Figure 12 Input and Output Waveforms for a Single Supply Video Sync Stripper Using an AD8061 Some video signals with sync are derived from single supply devices such as video DACs These signals can contain sync but the whole waveform is positive and the black level is
27. ut stage is a true single supply topology capable of sensing signals at or below the minus supply rail The rail to rail output stage can pull within 30 mV of either supply rail when driving light loads and within 0 3 V when driving 150 Q High speed performance is maintained at supply voltages as low as 2 7 V Headroom Considerations These amplifiers are designed for use in low voltage systems To obtain optimum performance it is useful to understand the behavior of the amplifier as input and output signals approach the amplifier s headroom limits The AD806x s input common mode voltage range extends from the negative supply voltage actually 200 mV below this or ground for single supply operation to within 1 8 V of the positive supply voltage Thus at a gain of 2 the AD806x can provide full rail to rail output swing for supply voltage as low as 3 6 V assuming the input signal swing from or ground to V 2 At a gain of 3 the AD806x can provide a rail to rail output range down to 2 7 V total supply voltage Exceeding the headroom limit is not a concern for any inverting gain on any supply voltage as long as the reference voltage at the amplifier s positive input lies within the amplifier s input common mode range a 2 The input stage will be the headroom limit for signals when the amplifier is used in a gain of 1 for signals approaching the positive rail Figure 3 shows a typical offset voltage versus input c

ANALOG DEVICES -AD8061/AD8062/AD8063 handbook

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