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NATIONAL SEMICONDUCTOR ADC084S021 Manual(1)

1. 5 0 ANALOG INPUTS An equivalent circuit for one of the ADC084S021 s input channels is shown in Figure 5 Diodes D1 and D2 provide ESD protection for the analog inputs At no time should any input go beyond V 300 mV or GND 300 mV as these ESD diodes will begin conducting which could result in erratic operation The capacitor C1 in Figure 5 has a typical value of 3 pF and is mainly the package pin capacitance Resistor R1 is the on resistance of the multiplexer and track hold switch and is typically 500 ohms Capacitor C2 is the ADC0845021 sam pling capacitor and is typically 30 pF The ADC084S021 will deliver best performance when driven by a low impedance source to eliminate distortion caused by the charging of the sampling capacitance This is especially important when using the ADC084S021 to sample AC signals Also important when sampling dynamic signals is a band pass or low pass filter to reduce harmonics and noise improving dynamic performance Conversion Phase Switch Open Track Phase Switch Closed 20124514 FIGURE 5 Equivalent Input Circuit 6 0 DIGITAL INPUTS AND OUTPUTS The ADC084S021 s digital output DOUT is limited by and cannot exceed the supply voltage V The digital input pins are not prone to latch up and and although not recom mended SCLK CS and DIN may be asserted before Va without any latchup risk 7 0 POWER SUPPLY CONSIDERATIONS The ADC084S021 is fully powered up whenever CS
2. UW UW MHz min MHz max KSPS min kSPS max SCLK cycles min max SCLK cycles SCLK cycles ADC084S021 Timing Specifications The following specifications apply for Va 2 7V to 5 25V GND OV fscrg 0 8 MHz to 3 2 MHz fsampre DO kSPS to 200 kSPS C 50 pF Boldface limits apply for Ta Tmn to Tmax all other limits Ty 25 C tesu Setup Time SCLK High to CS Falling Edge lern Hold time SCLK Low to CS Falling Edge tx Delay from CS Until DOUT active tacc Data Access Time after SCLK Falling Edge tsu Data Setup Time Prior to SCLK Rising Edge ty Data Valid SCLK Hold Time toy SCLK High Pulse Width teL SCLK Low Pulse Width le CS Rising Edge to DOUT High Impedance O O Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditions Note 2 All voltages are measured with respect to GND OV unless otherwise specified Note 3 When the input voltage at any pin exceeds the power supply that is Vin lt GND or Viy gt Va the current at that pin should be limited to 10 mA
3. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two The Absolute Maximum Rating specification does not apply to the Va pin The current into the V4 pin is limited by the Analog Supply Voltage specification Note 4 The absolute maximum junction temperature T max for this device is 150 C The maximum allowable power dissipation is dictated by T max the junction to ambient thermal resistance 8j and the ambient temperature Ta and can be calculated using the formula PpMAX Tymax T Oya The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition e g when input or output pins are driven beyond the power supply voltages or the power supply polarity is reversed Obviously such conditions should always be avoided Note 5 Human body model is 100 pF capacitor discharged through a 1 5 kQ resistor Machine model is 220 pF discharged through zero ohms Note 6 Reflow temperature profiles are different for lead free and non lead free packages Note 7 Tested limits are guaranteed to National s AOQL Average Outgoing Quality Level Note 8 This is the frequency range over which the electrical performance is guaranteed The device is functional over a wider range which is specified under Operating Ratings Note 9 Datasheet min max specification limits are guaranteed by des
4. 25 C Limits Parameter Conditions Typical Parameter Conditions Typieal Note 7 Symbol ANALOG INPUT CHARACTERISTICS Vu input Range oo oov Iper Cina Track Mode 33 ERROR 3 DIGITAL INPUT CHARACTERISTICS Va 5 25V sere A Ooo S a i lin Input Current Vin OV or Va 0 DIGITAL OUTPUT CHARACTERISTICS Isource 200 pA Va 0 03 lispunoe TM wasot 200 HA 0 03 Mob PARLA Velde ione 008 04 is mi 01 Vor Output High Voltage lozH loz TRI STATE Output Capacitance Output Coding POWER SUPPLY CHARACTERISTICS C 10 pF Cour Supply Current Normal Mode saupre 200 kSPS fiy 40 kHz l Operational CS low Va 3 6V E SAMPLE 200 kSPS fin 40 kHz l Va 5 25V o Aa i fsampLe 0 KSPS Supply Current Shutdown CS high 7 TT A 0 200 fsampre 0 KSPS Power Consumption Normal Mode Va 5 25V p Operational CS low Va 3 6V i Power Consumption Shutdown CS Va 5 25V righ Va 1360 AC ELECTRICAL CHARACTERISTICS fscLK Clock Frequency Note 8 fs Sample Rate Note 8 a DC SCLK Duty Cycle fscrk 3 2 MHz taco Track Hold Acquisition Time Full Scale Step Input 525 89 29 e ST 08 82 50 200 OB so 38 16 Throughput Time Acquisition Time Conversion Time www national com 4 Units pF max Straight Natural Binary V min V max MA max MA max nA nA mW max mW max
5. Applications Information continued conversion it is necessary to clock in the data indicating the input that is selected for the conversion after the current one See Tables 1 2 and Table 3 If CS and SCLK go low simultaneously it is the following rising edge of SCLK that is considered the first rising edge for clocking data into DIN There are no power up delays or dummy conversions re quired with the ADC084S021 The ADC is able to sample and convert an input to full conversion immediately following power up The first conversion result after power up will be that of IN1 TABLE 1 Control Register Bits Bi 7 MSB DONTC DONTC ADD2 ADDI ADDO DONTC DONTC DONTC TABLE 2 Control Register Bit Descriptions 7 6 2 0 DONTC Don t care The value of these bits do not affect device operation ADD2 These three bits determine which input channel will be sampled and ADD1 converted in the next track hold cycle The mapping between codes and ADDO channels is shown in Table 3 TABLE 3 Input Channel Selection ADDO Input Channel IN1 Default www national com o o na Applications Information continued 3 0 ADC084S021 TRANSFER FUNCTION The output format of the ADC084S021 is straight binary Code transitions occur midway between successive integer LSB values The LSB width for the ADC084S021 is V 256 The ideal transfer characteristic is shown in Figure 3 The transition from an output code of 0000 0000 to a cod
6. initiated on the falling edge of CS and ends on the rising edge of CS Each frame must contain an integer multiple of 16 rising SCLK edges The ADC output data DOUT is in a high impedance state when CS is high and is active when CS is low Thus CS acts as an output enable Additionally the device goes into a power down state when CS is high and also between continuous conversion cycles 15 During the first 3 cycles of SCLK the ADC is in the track mode acquiring the input voltage For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out MSB first starting on the 5th clock If there is more than one conversion in a frame the ADC will re enter the track mode on the falling edge of SCLK after the N 16th rising edge of SCLK and re enter the hold convert mode on the N 16 4th falling edge of SCLK where N is an integer When CS is brought high SCLK is internally gated off If SCLK is stopped in the low state while CS is high the subsequent fall of CS will generate a falling edge of the internal version of SCLK putting the ADC into the track mode This is seen by the ADC as the first falling edge of SCLK If SCLK is stopped with SCLK high the ADC enters the track mode on the first falling edge of SCLK after the falling edge of CS During each conversion data is clocked into the DIN pin on the first 8 rising edges of SCLK after the fall of CS For each www national com Lc0S78000V ADC084S021
7. is low and fully powered down whenever CS is high with one exception the ADC084S021 automatically enters power down mode between the 16th falling edge of a conversion and the 1st falling edge of the subsequent conversion see Timing Diagrams The ADC084S021 can perform multiple conversions back to back each conversion requires 16 SCLK cycles The ADC084S021 will perform conversions continuously as long as CS is held low www national com The user may trade off throughput for power consumption by simply performing fewer conversions per unit time The Power Consumption vs Sample Rate curve in the Typical Performance Curves section shows the typical power con sumption of the ADC084S021 versus throughput To calcu late the power consumption simply multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power dissipation 7 1 Power Management When the ADC084S021 is operated continuously in normal mode the maximum throughput is fsc k 16 Throughput may be traded for power consumption by running fsc x at its maximum 3 2 MHz and performing fewer conversions per unit time putting the ADC084S021 into shutdown mode between conversions A plot of typical power consumption versus throughput is shown in the Typical Performance Curves section To calculate the power consumption for a given throughput multiply the fr
8. to the sampling capaci tor until the comparator is balanced When the comparator is balanced the digital word supplied to the DAC is the digital representation of the analog input voltage The ADC084S021 is in this state for the fourth through sixteenth SCLK cycles after CS is brought low The time when CS is low is considered a serial frame Each of these frames should contain an integer multiple of 16 SCLK cycles during which time a conversion is performed and clocked out at the DOUT pin and data is clocked into the DIN pin to indicate the multiplexer address for the next conversion CHARGE REDISTRIBUTION DAC CONTROL LOGIC 20124509 FIGURE 1 ADC084S021 in Track Mode SAMPLING INT IN4 SW1 CAPACITOR CHARGE REDISTRIBUTION DAC CONTROL LOGIC 20124510 FIGURE 2 ADC084S021 in Hold Mode 2 0 USING THE ADC084S021 An ADC084S021 timing diagram and a serial interface timing diagram for the ADC084S021 are shown in the Timing Dia grams section CS is chip select which initiates conversions and frames the serial data transfers SCLK serial clock controls both the conversion process and the timing of serial data DOUT is the serial data output pin where a conversion result is sent as a serial data stream MSB first Data to be written to the ADC084S021 s Control Register is placed on DIN the serial data input pin New data is written to DIN with each conversion A serial frame is
9. 00 KSPS fsck 0 8 MHz to 3 2 MHZ fin 39 9 kHz unless otherwise stated Continued 8 00 O NI ENOB BITS lt e 7 T dB www national com ENOB vs Temperature al FEE 7 50 0 50 100 TEMPERATURE C 20124556 Spectral Response 5V 200 ksps FREQUENCY kHz 20124560 Spectral Response 3V 200 ksps dB FREQUENCY kHz 20124559 Power Consumption vs Throughput 6 25 6 E4 A Yn 3 Z O O x 2 gt z a O 1 P AL 0 pui 0 50 100 150 200 THROUGHPUT KSPS 20124561 Applications Information 1 0 ADC084S021 OPERATION The ADC084S021 is a successive approximation analog to digital converter designed around a charge redistribution digital to analog converter Simplified schematics of the ADC084S021 in both track and hold modes are shown in Figures 1 2 respectively In Figure 1 the ADC084S021 is in track mode switch SW1 connects the sampling capacitor to one of four analog input channels through the multiplexer and SW2 balances the comparator inputs The ADC084S021 is in this state for the first three SCLK cycles after CS is brought low Figure 2 shows the ADC084S021 in hold mode switch SW1 connects the sampling capacitor to ground maintaining the INT SAMPLING IN4 CAPACITOR swt AGND VA sampled voltage and switch SW2 unbalances the compara tor The control logic then instructs the charge redistribution DAC to add fixed amounts of charge
10. National Semiconductor ADC084S021 April 2005 4 Channel 200 KSPS 8 Bit A D Converter General Description The ADC084S021 is a low power four channel CMOS 8 bit analog to digital converter with a high speed serial interface Unlike the conventional practice of specifying performance at a single sample rate only the ADC084S021 is fully speci fied over a sample rate range of 50 kSPS to 200 kSPS The converter is based on a successive approximation register architecture with an internal track and hold circuit It can be configured to accept up to four input signals at inputs IN1 through IN4 The output serial data is straight binary and is compatible with several standards such as SPI QSPI MICROW IRE and many common DSP serial interfaces The ADC084S021 operates with a single supply that can range from 2 7V to 5 25V Normal power consumption using a 3V or 5V supply is 1 6 mW and 5 8 mW respec tively The power down feature reduces the power consump tion to just 0 12 uW using a 3V supply or 0 35 uW using a 5V supply The ADC084S021 is packaged in a 10 lead MSOP package Operation over the industrial temperature range of 40 C to 85 C is guaranteed Features m Specified over a range of sample rates m Four input channels m Variable power management m Single power supply with 2 7V 5 25V range Key Specifications m DNL 0 04 LSB typ m INL 0 04 LSB typ m SNR 49 6 dB typ m Power Consumptio
11. YCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period The speci fication here refers to the SCLK EFFECTIVE NUMBER OF BITS ENOB or EFFECTIVE BITS is another method of specifying Signal to Noise and Distortion or SINAD ENOB is defined as SINAD 1 76 6 02 and says that the converter is equivalent to a perfect ADC of this ENOB number of bits FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input GAIN ERROR is the deviation of the last code transition 111 110 to 111 111 from the ideal Vpep 1 5 LSB after adjusting for offset error INTEGRAL NON LINEARITY INL is a measure of the deviation of each individual code from a line drawn from negative full scale 12 LSB below the first code transition through positive full scale 12 LSB above the last code transition The deviation of any given code from this straight lime is measured from the center of that code value INTERMODULATION DISTORTION IMD is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time It is defined as the ratio of the power in the second and third order intermodulation products to the sum of the power in both of the original frequencies IMD is usually expressed in dB MISSING CODES are those output codes
12. a 100 series resistor at the ADC output located as close to the ADC output pin as practical This will limit the charge and discharge current of the output Capacitance and improve noise performance Physical DIMENSIONS inches millimeters unless otherwise noted edo 189 4 8 10X 040 1 02 10X 012 ya ihi LL tax 0197 0 5 005 TYP R 005 TYP 043 MAX 034 0 13 a _ LA AT 004 10 11 A Io p 002 006 TYP 10X 0097 993 L 007 002 TYP 021 4 005 0 6 0 06 0 15 0038 00 0 180 051 0 530 121 SEATING PLANE TYP 002 0 05 M B Ic 0375 BIBS CO 0 953 CONTROLLING DIMENSION IS INCH VALUES IN ARE MILLIMETERS DIMENSIONS IN FOR REFERENCE ONLY MUB10A Rev B 10 Lead MSOP Order Number ADC084S021CIMM ADC084S021 CIMMX NS Package Number POMUB10A National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications For the most current product information visit us at www national com LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component is any
13. action of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption Generally the user will put the part into normal mode and then put the part back into shutdown mode Note that the curve of power consumption vs throughput is nearly linear This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes 7 2 Power Supply Noise Considerations The charging of any output load capacitance requires cur rent from the power supply Va The current pulses required from the supply to charge the output capacitance will cause voltage variations on the supply If these variations are large enough they could degrade SNR and SINAD performance of the ADC Furthermore discharging the output capaci tance when the digital output goes from a logic high to a logic low will dump current into the die substrate which is resis tive Load discharge currents will cause ground bounce noise in the substrate that will degrade noise performance if that current is large enough The larger is the output capaci tance the more current flows through the die substrate and the greater is the noise coupled into the analog channel degrading noise performance To keep noise out of the power supply keep the output load Capacitance as small as practical If the load capacitance is greater than 50 pF use
14. ce Characteristics T 25 C fsampre 50 KSPS to 200 KSPS fsck 0 8 MHz to 3 2 MHZ fin 39 9 kHz unless otherwise stated Continued SNR vs Supply THD vs Supply 60 50 ao 2 x 40 Z T 30 20 25 30 35 40 45 50 55 25 30 35 40 45 50 55 SUPPLY VOLTAGE V V SUPPLY VOLTAGE V V 20124530 20124535 SNR vs Clock Frequency THD vs Clock Frequency ao 2 na Z T CLOCK FREQUENCY MHz CLOCK FREQUENCY MHz 20124531 20124536 SNR vs Clock Duty Cycle THD vs Clock Duty Cycle ao 2 or Z T CLOCK DUTY CYCLE CLOCK DUTY CYCLE 20124532 20124537 www national com 10 Typical Performance Characteristics T 25 C feampre 50 KSPS to 200 kSPS fsck 0 8 MHz to 3 2 MHz fin 39 9 kHz unless otherwise stated Continued SNR dB SNR dB SFDR dB SNR vs Input Frequency INPUT FREQUENCY kHz 20124533 SNR vs Temperature V 3 0V to 5 0V TEMPERATURE C SFDR vs Supply 25 30 35 40 45 5 0 SUPPLY VOLTAGE V V 20124534 20124540 11 THD dB THD dB SINAD dB LcOS78000V THD vs Input Frequency INPUT FREQUENCY kHz 20124538 THD vs Temperature TEMPERATURE C 20124539 SINAD vs Supply 60 50 40 30 20 25 30 35 40 45 50 5 5 SUPPLY VOLTAGE V V 20124545 www national com ADC084S021 Typical Performance Characteristics T 25 C fsampLe 50 kSPS to 200 kSPS fsck 0 8 MHz to 3 2 MHZ fin 39 9 kHz u
15. component of a life support which a are intended for surgical implant into the body or device or system whose failure to perform can be reasonably b support or sustain life and whose failure to perform when expected to cause the failure of the life Support device or properly used in accordance with instructions for use system or to affect its safety or effectiveness provided in the labeling can be reasonably expected to result in a significant injury to the user BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification CSP 9 111C2 and the Banned Substances and Materials of Interest Specification CSP 9 111S2 and contain no Banned Substances as defined in CSP 9 111S2 National Semiconductor National Semiconductor National Semiconductor National Semiconductor Americas Customer Europe Customer Support Center Asia Pacific Customer Japan Customer Support Center Support Center Fax 49 0 180 530 85 86 Support Center Fax 81 3 5639 7507 Email new feedback nsc com Email europe support nsc com Email ap support nsc com Email jpn feedback nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 69 9508 6208 Tel 81 3 5639 7560 English Tel 44 0 870 24 0 2171 www national com Frangais Tel 33 0 1 41 91 8790 A9 9AUOI A V 119 8 SdSM 007 PUUEUI fr LZ0STY80ICAY
16. conversion It is the acquisition time plus the conversion time www national com Lc0S78000V ADC084S021 Typical Performance Characteristics 1 25 C fgampie 50 KSPS to 200 KSPS fsck 0 8 MHZ to 3 2 MHZ fin 39 9 KHz unless otherwise stated DNL V 3 0V INL V 3 0V 0 10 Fs 200 ksps 0 05 ao co A 0 00 Z f Z 0 05 0 10 20124520 20124521 0 10 0 05 ao A 0 00 Z 5 Z 0 05 0 10 20124562 20124563 0 10 0 05 ao a 0 00 z Z f Z 0 05 l 0 10 25 30 35 40 45 50 55 25 30 35 40 45 50 55 SUPPLY VOLTAGE V V SUPPLY VOLTAGE V V 20124522 20124523 www national com Typical Performance Characteristics T 25 C fsampre 50 KSPS to 200 KSPS fsck 0 8 MHz to 3 2 MHz fin 39 9 kHz unless otherwise stated Continued DNL vs Clock Frequency 0 10 0 05 DNL LSB 0 1 2 3 4 CLOCK FREQUENCY MHz 20124524 DNL vs Clock Duty Cycle 200 KSPS DNL LSB CLOCK DUTY CYCLE 20124526 DNL vs Temperature DNL LSB 50 0 50 100 TEMPERATURE C 20124528 LcOS78000V INL vs Clock Frequency 0 10 0 05 ao a 0 00 Z 0 05 0 10 0 1 2 3 4 CLOCK FREQUENCY MHz 20124525 INL vs Clock Duty Cycle 0 10 ne m 0 05 ku ao VW 0 00 0 05 0 10 CLOCK DUTY CYCLE 20124527 INL vs Temperature ao U l Z TEMPERATURE C 20124529 www national com ADC084S021 Typical Performan
17. e of 0000 0001 is at 1 2 LSB or a voltage of V 512 Other code transitions occur at steps of one LSB 4 0 TYPICAL APPLICATION CIRCUIT A typical application of the ADC084S021 is shown in Figure 4 Power is provided in this example by the National Semi conductor LP2950 low dropout voltage regulator available in a variety of fixed and adjustable output voltages The power supply pin is bypassed with a capacitor network located close to the ADC0845S021 Because the reference for the 111 000 ADC084S021 is the supply voltage any noise on the supply da will degrade device noise performance To keep noise off the sin ILSB V 256 supply use a dedicated linear regulator for this device or provide sufficient decoupling from other circuitry to keep noise off the ADC084S021 supply pin Because of the ADC084S021 s low power requirements it is also possible to 000 010 use a precision reference as a power supply to maximize 000 001 performance Because of the ADC084S021 s low power re 000 000 e a quirements it is also possible to use a precision reference as ov 1LSB V 1LSB a power supply to maximize performance The four wire ANALOG INPUT interface is also shown connected to a microprocessor or 20124511 DSP 111 111 111 110 ADC CODE FIGURE 3 Ideal Transfer Characteristic LP2950 20124513 FIGURE 4 Typical Application Circuit 17 www national com Lc0S78000V ADC084S021 Applications Information continued
18. ign test or statistical analysis Note 10 Clock may be in any state high or low when CS is asserted with the restrictions on setup and hold time given by tcsy and toy 5 www national com Lc0S78000V ADC084S021 Timing Diagrams Power Down una re i Power Up i Power Up I T __ 1MVWXl e I I i Track Hold i Track Hold im pig NOG _ o 0___ _o _ om _ _mua_6mu I pini a 20124551 ADC084S021 Operational Timing Diagram TO OUTPUT PIN 20124508 Timing Test Circuit Iacg _ o pag EN ui _ A A tacc E ri State D l N 252505 20124506 CSU SCLK CLH SCLK 20124550 SCLK and CS Timing Parameters www national com 6 Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage That is it is time required for the hold capacitor to charge up to the input voltage APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion CONVERSION TIME is the time required after the input voltage is acquired for the ADC to convert the input voltage to a digital word CROSSTALK is the coupling of energy from one channel into the other channel or the amount of signal energy from one analog input that appears at the measured analog input DIFFERENTIAL NON LINEARITY DNL is the measure of the maximum deviation from the ideal step size of 1 LSB DUTY C
19. must comply with National Semiconduc tors Reflow Temperature Profile specifications Refer to www national com packaging Note 6 ADC084S021 Converter Electrical Characteristics note 9 The following specifications apply for Va 2 7V to 5 25V GND OV fscrg 0 8 MHz to 3 2 MHz fsampre 00 kKSPS to 200 kSPS C 50 pF unless otherwise noted Boldface limits apply for Ta Tm to Tmax all other limits T 25 C Limits Symbol Parameter Conditions Typical Units Parameter Conditions Typieal Note 7 STATIC CONVERTER CHARACTERISTICS VoFF Offset Error sd Error LSB mag h h Offset E Channel to oie Ee ee annel Offset Error 0 01 LSB max Match Full Full Scale Error Error Gata LSB mad ae to Channel Full Scale Error DYNAMIC CONVERTER CHARACTERISTICS rt premete e SET a oe moons ities em ii Total Harmonic Distorion Ys _ a ui dBFS ve e eee TN em ce Channel to Channel Crosstalk Order Terms f 40 161 kHz f 41 015 kHz Order Terms f 40 161 kHz f 41 015 kHz Va 5V MHz Soe sue A e R E E Vasy S O ei ee www national com Lc0S78000V ADC084S021 ADC084S021 Converter Electrical Characteristics Note 9 Continued The following specifications apply for Va 2 7V to 5 25V GND OV fscrk 0 8 MHz to 3 2 MHz fsampre 50 KSPS to 200 kSPS C 50 pF unless otherwise noted Boldface limits apply for Ta Tmn to Tmax all other limits T
20. n 3V Supply 1 6 mW typ 5V Supply 5 8 mW typ Applications m Portable Systems m Remote Data Aquisitions m Instrumentation and Control Systems Pin Compatible Alternatives by Resolution and Speed All devices are fully pin and function compatible Specified for Sample Rate Range of 50 to 200 KSPS 200 to 500 kSPS 500 kSPS to 1 MSPS ADC 1248021 ADC124S051 ADC1248101 ADC1048021 ADC104S051 ADC104S101 ADC084S021 ADC084S051 ADC084S101 Connection Diagram CS 1 O SCLK V A 2 DOUT AD 4S021 GND 3 ere DIN IN4 4 IN1 IN3 5 IN2 20124505 TRI STATE is a trademark of National Semiconductor Corporation QSPI and SPI are trademarks of Motorola Inc 2005 National Semiconductor Corporation DS201245 www national com J9MBAUOD A V 119 8 SdS 007 euueyyd fr LZOSY809AV ADC084S021 Ordering Information ADC084S021CIMM 40 C to 85 C 10 Lead MSOP Package X19C ADC084S021CIMMX 40 C to 85 C 10 Lead MSOP Package Tape amp Reel X19C ADC084S021EVAL ai Evaluation Board Se Block Diagram INA 8 Bit Va SUCCESSIVE APPROXIMATION ADC GND IN4 SCLK CONTROL CS LOGIC DIN DOUT 20124507 Pin Descriptions and Equivalent Circuits Pin No Symbol Description ANALOG I O 4 7 IN1 to IN4 Analog inputs These signals can range from OV to Va DIGITAL I O 10 SCLK Digital clock input This clock directly controls the conversion and readout processes Digital data output The output samples are cl
21. nless otherwise stated Continued SFDR vs Clock Frequency SINAD vs Clock Frequency 60 50 T 3S or Q 40 n 2 T 7 30 20 CLOCK FREQUENCY MHz CLOCK FREQUENCY MHz 20124541 20124546 SFDR vs Clock Duty Cycle SINAD vs Clock Duty Cycle 80 60 Va 3 0V to 5 0V 70 T m x Q 40 a o Z 50 T TT 30 20 30 40 50 60 70 CLOCK DUTY CYCLE CLOCK DUTY CYCLE 20124542 20124547 SFDR vs Input Frequency SINAD vs Input Frequency 80 60 so TT m se 1 _ i ac Q 40 a o T Z 50 T MS 30 20 0 15 30 45 60 INPUT FREQUENCY kHz INPUT FREQUENCY kHz 20124543 20124548 www national com 12 Typical Performance Characteristics T 25 C fgampre 50 KSPS to 200 kSPS fsck 0 8 MHz to 3 2 MHz fin 39 9 kHz unless otherwise stated Continued SINAD vs Temperature SFDR vs Temperature Va 3 0V to 5 0V A o O a 2 To T TEMPERATURE C TEMPERATURE C 20124544 20124549 ENOB vs Supply ENOB vs Clock Frequency 8 1 8 1 8 0 8 0 an D a a m 7 9 m 7 9 O O 2 Z LL LU 7 8 7 8 it 7 7 25 30 35 40 45 50 5 5 SUPPLY VOLTAGE V V CLOCK FREQUENCY MHz 20124552 20124553 ENOB vs Clock Duty Cycle ENOB vs Input Frequency 8 1 8 0 D a ln ln a a co m 7 9 O O Z Z LL Lu 7 8 7 7 0 15 30 45 60 CLOCK DUTY CYCLE INPUT FREQUENCY kHz 20124554 20124555 LcOS78000V 13 www national com ADC084S021 Typical Performance Characteristics T 25 C fsampre 50 KSPS to 2
22. ocked out of this 9 DOUT l pin on falling edges of the SCLK pin Digital data input The ADC084S021 s Control Register is loaded through this pin on rising edges of the SCLK pin i CS Chip select On the falling edge of CS a conversion process begins Conversions continue as long as CS is held low POWER SUPPLY Positive supply pin This pin should be connected to a quiet 2 7V to 5 25V source and bypassed to GND with a 1 uF 2 V a capacitor and a 0 1 uF monolithic capacitor located within 1 cm of the power pin 3 GND The ground return for the analog supply and signals www national com 2 Absolute Maximum Ratings notes 1 2 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Va 0 3V to 6 5V Voltage on Any Pin to GND 0 3V to Va 0 3V Input Current at Any Pin Note 3 10 mA Package Input Current Note 3 20 mA Power Consumption at T 25 C See Note 4 ESD Susceptibility Note 5 Human Body Model 2500V Machine Model 250V Junction Temperature 150 C Storage Temperature 65 C to 150 C Operating Ratings notes 1 2 Operating Temperature Range 40 C lt Ta lt 85 C Va Supply Voltage 2 7V to 5 25V Digital Input Pins Voltage Range 0 3V to Va Clock Frequency 0 8 MHz to 3 2 MHz Analog Input Voltage OV to Va Package Thermal Resistance 10 lead MSOP 190 C W Soldering process
23. that will never appear at the ADC outputs The ADC084S021 is guaranteed not to have any missing codes OFFSET ERROR is the deviation of the first code transition 000 000 to 000 001 from the ideal i e GND 0 5 LSB SIGNAL TO NOISE RATIO SNR is the ratio expressed in dB of the rms value of the input signal to the rms value of the sum of all other spectral components below one half the sampling frequency not including harmonics or d c SIGNAL TO NOISE PLUS DISTORTION S N D or SINAD Is the ratio expressed in dB of the rms value of the input signal to the rms value of all of the other spectral compo nents below half the clock frequency including harmonics but excluding d c SPURIOUS FREE DYNAMIC RANGE SFDR is the differ ence expressed in dB between the rms values of the input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input excluding d c TOTAL HARMONIC DISTORTION THD is the ratio ex pressed in dB or dBc of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output THD is calcu lated as Ago Agee THD 20 l0g19 Aer where Af is the RMS power of the input frequency at the output and Af through Af are the RMS power in the first 5 harmonic frequencies THROUGHPUT TIME is the minimum time required between the start of two successive

NATIONAL SEMICONDUCTOR ADC084S021 Manual(1)

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