ST PSD3200 FAMILY handbook
Contents
1. UPSD3200 yr amp 503200 FAMILY Flash Programmable System Device FEATURES SUMMARY m The uPSD3200 Family combines a Flash PSD architecture with an 8032 microcontroller core The uPSD3200 Family of Flash PSDs features dual banks of Flash memory SRAM general purpose I O and programmable logic supervi sory functions and access via USB I C ADC DDC and PWM channels and an on board 8032 microcontroller core with two UARTs three 16 bit Timer Counters and one External Interrupt As with other Flash PSD families the uPSD3200 Family is also in system program mable ISP via a JTAG ISP interface Large 8 KByte SRAM with battery back up option Dual bank Flash memories 128 KByte or 256 KByte main Flash memory 32 KByte secondary Flash memory Content Security Block access to Flash memory Programmable Decode PLD for flexible address mapping of all memories High speed clock standard 8032 core 12 cycle USB Interface uPSD3234A 40U6 only C interface for peripheral connections Five Pulse Width Modulator PWM channels Standalone Display Data Channel DDC Six I O ports with up to 50 I O pins 3000 gate PLD with 16 macrocells Supervisor functions In System Programming ISP via JTAG Zero Power Technology Single Supply Voltage 4 5to 5 5 V 3 0 to 3 6 V June 2002 Complete data available on Data on Disc CD ROM or at www st com with 8032 Microcontroller Core DATA BRIEFING2. 2 VSYNC 30 P4 1 DDC SCL T P4 0 DDC SDA 33 ADO P0 0 36 L AD1 P0 1 37 AD2 P0 2 38 CL ADS P0 3 39 P3 4 TO 40 105791 Note 1 NC Not Connected 2 USB needs a pull up resistor see the description of the USB function 3 6 8 uPSD3200 FAMILY PART NUMBERING Table 2 Ordering Information Scheme Example uPSD 3 2 34 BV 244 U 6 T Device Type uPSD Microcontroller PSD Family 3 8032 core PLD Size 2 16 Macrocells 3 32 Macrocells SRAM Size 1 16 Kbit 3 64 Kbit 5 256 Kbit Main Flash Memory Size 3 1 Mbit 4 2 Mbit 5 4 Mbit IP Mix A USB PWM DDG ADC 2 UARTs Supervisor Reset Out Reset In LVD WD B PWM DDC ADC 2 UARTs Supervisor Reset Out Reset In LVD WD Operating Voltage blank Vcc 4 5 to 5 5V V Vcc 3 0 to 3 6V Speed 24 24 MHz 40 40 MHz Package T 52 pin TQFP U 80 pin TQFP Temperature Range 1 0 to 70 C commercial 6 40 to 85 C industrial Option T Tape amp Reel Packing For a list of available options speed package device please contact your nearest ST Sales Of etc or for further information on any aspect of this fice r uPSD3200 FAMILY Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of s
3. Figure 1 Packages TQFP80 U 1 8 uPSD3200 FAMILY SUMMARY DESCRIPTION Dual bank Flash memories One 16 bit PWM unit Concurrent operation read from memory one Standalone Display Data Channel DDC while erasing and writing the other In Appli For use in monitor projector and TV applica cation Programming IAP for remote updates tions Large 128 KByte or 256 KByte main Flash Compliant with VESA standards DDC1 and memory for application code operating sys DDC2B tems or bit maps for graphic user interfaces Eliminate external DDC PROM Large 32 KByte secondary Flash memory di Six I O ports with up to 501 0 pins vided in small sectors Eliminate external EE 2 PROM with software EEPROM emulation Multifunction I O GPIO DDC PWM PLD I O supervisor and JTAG Secondary Flash memory is large enough for Eliminates need for external latches and logic sophisticated communication protocol USB during IAP while continuing critical system 3000 gate PLD with 16 macrocells tasks Create glue logic state machines delays Large SRAM with battery back up option etc 8 KByte SRAM for RTOS high level languag Eliminate external PALs PLDs and 74HCxx es communication buffers and stacks Simple PSDsoft Express software Free Programmable Decode PLD for flexible address Supervisor functions mapping of all memories Generates reset upon low voltage
4. nels Four 8 bit PWM units 3 2 8 uPSD3200 FAMILY Figure 2 uPSD3200 Family Functional Modules Port UART n a oo o Pot3 Pott d aus MCU MODULE CPLD 16 MACROCELLS 106619 3 3 8 uPSD3200 FAMILY Table 1 80 Pin Package Pin Description ernate AD7 ADO Multiplexed Address Data bus RxD2 RxD1 UART Receive TxD2 TxD1 UART Transmit INT 1 INTO Interrupt inputs timer gate controls T2 TO Counter inputs SDA1 SDA2 2 Bus serial data DDC interface General I O port pins Bus clock O VSYNC input for DDC interface Timer 2 Trigger input ADC Channels input 8 bit Pulse Width Modulation outputs vo sere Amer mb we o mE mer T Xmz omron PLD Macro cell outputs PLD inputs PA7 PAO General I O port pins Latched Address Out A0 A7 Peripheral mode PLD Macro cell outputs PB7 PBO y o General I O port pins PLD inputs Latched Address Out A0 A7 PLD Macro cell outputs PLD inputs SRAM stand by voltage input VSTBY ere VO General I O port pins _ JTAG Interface TDI TDO TMS TCK TSTAT TERR 5 SRAM battery on indicator PC4 1 PLD I O PD2 PD1 General I O port pin 2 Clock input to PLD and APD 3 Chip select to PSD Module Note PSD Po
5. or watch Place individual Flash and SRAM sectors on dog time out Eliminate external supervisor any address boundary device Built in page register breaks restrictive 8032 Reset In pin limit of 64 KByte address space m In System Programming ISP via JTAG Program entire chip in 10 25 seconds with no involvement of 8032 Special register swaps Flash memory seg ments between 8032 program space and data space for efficient In Application Pro gramming m High speed clock standard 8032 core 12 cycle 40 MHz operation at 5 V 24 MHz at 3 3 V Two UARTs with independent baud rate three 16 bit Timer Counters and two External Allows efficient manufacturing easy product testing and Just In Time inventory Eliminate sockets and pre programmed parts Program with FlashLINK cable and any PC m Content Security Interrupts Programmable Security Bit blocks access of m USB Interface uPSD3234A 40U6 only device programmers and readers Supports USB 1 1 Slow Mode 1 5 Mbit s m Zero Power Technology Control endpoint 0 and interrupt endpoints 1 Memones PLD automatically raach and standby current between input changes m Packages 52 pin TQFP 80 pin TQFP allows access to 8032 address data control signals for connecting to external peripherals 2 interface for peripheral connections Capable of master or slave operation m Five Pulse Width Modulator PWM chan
6. rt A and MCU Address Data bus are added for 80 pin device 3 4 8 uPSD3200 FAMILY Figure 3 TOFP52 Connections 46 VREF 44 RST IN 41 ADC3 40 ADC2 39 P1 5 ADC1 38 P1 4 ADCO 37 P1 3 TXD1 36 P1 2 RXD1 35 P1 1 T2X 34 P1 0 T2 33 Voc 32 XTAL2 31 XTAL1 30 P3 7 SCL1 29 P3 6 SDA1 28 P3 5 T1 27 P3 4 TO P4 7 PWM4 14 P4 6 PWM3 15 4 5 PWM2 16 P4 4 PWM1 17 LL P4 3 PWMO 18 P4 2 DDC VSYNC 20 P4 1 DDC SCL 21 LL P4 0 DDC SDA 22 P3 0 RXD 23 P3 1 TXD 24 LL P3 2 EXINTO 25 P3 3 EXINT1 26 AI05790B Note NC Not Connected PU Pull up resistor required 2kQ for devices 7 5kQ for 5V devices 3 5 8 uPSD3200 FAMILY Figure 4 TQFP80 Connections CL 79 P3 2 EXINTO 77 P3 1 TXD C 75 P3 0 68 RESET IN 1 65 RD CNTL1 1 64 P1 7 ADC3 T 63 PSEN CNTL2 162 WR CNTLO 1 61 P1 6 ADC2 L 70 VREF PD2 P3 3 EXINT1 PD1 PDO ALE PC7 PC6 5 USB PC4 60 P1 5 ADC1 59 P1 4 ADCO 58 P1 3 TXD1 57 P2 3 A11 56 P1 2 RXD1 55 P2 2 A10 54 P1 1 T2X 53 P2 1 A9 52 P1 0 T2 ont WORD a USB 51 2 0 8 50 Vcc 49 XTAL2 13 48 XTAL1 47 P0 7 AD7 15 46 P3 7 SCL1 16 45 P0 6 AD6 NC 17 44 P3 6 SDA1 P4 7 PWM4 18 43 P0 5 ADS 4 6 PWM3 19 42 P3 5 1 20 41 P0 4 AD4 P4 5 PWM2 23 I P4 4 PWM1 25 P4 3 PWMO 27 CL P4
7. uch information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners 2002 STMicroelectronics All Rights Reserved STMicroelectronics group of companies Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www st com r 8 8
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ST PSD3200 FAMILY handbook