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TEXAS INSTRUMENTS TPS40075 Manual

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1. INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 GAIN PHASE vs vs FREQUENCY FREQUENCY 60 200 180 40 160 System Phase ESR 0 Q System Gain ESR 0 95 mo 130 7 20 d 120 d E M WM H I L 2 c 0 S 100 E N 9 N 80 N N 60 d al A0 d 40 System Gain ESR 0 Q 20 System Phase ESR 0 95 mQ 60 0 LL L L 111111 I 100 1k 10k 100 k 1M 100 1k 10k 100 k 1M Frequency Hz Frequency Hz Figure 34 Figure 35 ALTERNATE APPLICATIONS Some alternative applicaiton diagrams are shown in Figure 36 through Figure 38 34 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 d TEXAS INSTRUMENTS www ti com 2nF 10 KO 14kQ 75 pF Si7868DP COEV DXM1306 100 uF TDK C3225X5R0J107M x 3 TDK C4532X5R1C226M x 2 Dg 1 50 100 nF External Logic Supply TPS40075 Power Good 3 22uF 22uF 1 3 uH 2 UDG 04109 Figure 36 400 kHz 12 V to 1 2 V Converter with Powergood Indication Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 Submit Documentation Feedback
2. TEXAS INSTRUMENTS TPS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS continued DBP VOLTAGE BOOTSTRAP DIODE VOLTAGE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 4 50 2 0 Vpp 4 5 V 4 49 lLoap 25mA T 1 9 I 4 48 S 1 8 a 7 447 o 1 7 S S 446 S 16 2 gt 4 3 R 4 45 915 a 2 4 44 S 1 4 a t S 443 9 1 3 m 4 42 a 1 2 tc 4 41 14 4 40 1 0 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 Ty Junction Temperature C T Junction Temperature C Figure 3 Figure 4 CURRENT LIMIT OFFSET VOLTAGE CURRENT LIMIT SINK CURRENT vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 0 150 gt E I 145 10 435 lt 140 I lt 20 s Average 6 130 2 x 5 E 120 S 40 5 115 5 s VDD 35 O 28V L 110 ______ 12V 50 4 5 V z 108 gt 60 100 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 T Junction Temperature C Ty Junction Temperature C Figure 5 Figure 6 Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback T Product Folder Link s TPS40075 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A
3. www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS continued MAXIMUM DUTY CYCLE UNDERVOLTAGE LOCKOUT vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 93 4 35 9 gt 4 30 SES Sn 91 A Ee o 4 25 V 4 fgw 100 KHZ g 4125 VNB s 9 420 e bass E gt 89 a a e E 5 heess 4 15 88 m fsw 500 kHZ S 4410 x 87 S 4 05 M 2 2 V 85 fsw 1MHZ L 4 00 UVLO off l 84 E 3 95 83 3 90 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 T Junction Temperature C Ty Junction Temperature C Figure 11 Figure 12 PROGRAMMABLE UVLO THRESHOLD SOFTSTART CHARGING CURRENT vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 1 10 14 0 gt d d od 1 08 gt VuvLo ott 195 o E ZS 1 06 VuvLO on I 2 13 0 1 04 o I O 12 5 E 1 02 S 2 o 2 1 00 1 ji S 12 0 lt o S 0 98 Kap 2 9 C P 0 96 g o 11 0 094 A gt 105 0 92 i d 0 90 10 0 gt 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 T Junction Temperature C T Junction Temperature C Figure 13 Figure 14 Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link s TPS40075 TPS40075 SLUS676A MAY 2006 REVISED SEPTEMBER 2007 d TEXAS INSTRUMENTS www ti com TYPICAL CHARACTERISTICS continued ERROR AMPLIFIER INPUT BIAS CURRENT
4. 150 200 250 300 350 400 Ryrr Feedforward Impedance KQ Figure 19 UVLO THRESHOLD VOLTAGE vs FEEDFORWARD IMPEDANCE 20 450 T T few 750 kH mic s UVLOVoN UVLOVorr 40 60 80 100 120 140 160 Ryrr Feedforward Impedance KQ Figure 21 Copyright 2006 2007 Texas Instruments Incorporated 180 VuvLo Programmable UVLO Threshold V Duty Cycle UVLO THRESHOLD VOLTAGE vs FEEDFORWARD IMPEDANCE T fsw I 500 kHz UVLOVoN 100 90 120 150 180 210 240 Ryrr Feedforward Impedance kQ 270 Figure 20 TYPICAL MAXIMUM DUTY CYCLE vs INPUT VOLTAGE UVLO on 15 V UVLO on 4 8 Product Folder Link s TPS40075 12 16 20 24 28 Vin Input Voltage V Figure 22 Submit Documentation Feedback 11 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS continued INPUT VOLTAGE INPUT VOLTAGE vs vs DBP VOLTAGE LOW VOLTAGE BYPASS VOLTAGE 10 4 50 4 45 gt E 9 o 4 40 I S o S 9 4 35 s 2 m S 4 30 p gt s m 7 o 4 25 a S E S 420 a z 6 S 445 S I gt amp 4 10 5 gt 4 05 4 4 00 0 5 10 15 20 25 5 10 15 20 25 30 Vpp
5. Ta PACKAGE PART NUMBER TPS40075RHLT 40 C to 85 C Plastic QFN RHL TPS40075RHLR 2 1 The TPS40075 is available taped and reeled only Add an T suffix i e TPS40075RHLT to the orderable part number for quantities of 250 units per small reel 2 Add an R suffix i e TPS40075RHLR to the orderable part number for quantities of 3 000 units per large reel DEVICE RATINGS ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted TPS40075 UNIT VDD ILIM 30 FB KFF PGD SYNC 0 3 to 6 Vpp Input voltage range zd ei Y SA SA 0 3 to 11 SW transient 50 ns 2 5 SW transient 125 Vxns COMP RT SS 0 3 to 6 BOOST HDRV 50 Vout Output voltage range DBP SAO LDRV 105 V LVBP 6 lout Output current source LDRV HDRV 1 5 A LDRV HDRV 2 0 lout Output current sink KEE 40 RT 1 mA lout Output current source VBP ie Ty Operating junction temperature range 40 to 125 C Tstg Storage temperature 55 to 150 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability
6. THERMAL INFORMATION This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink The thermal pad must be soldered directly to the printed circuit board PCB After soldering the PCB can be used as a heatsink In addition through the use of thermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC For information on the Quad Flatpack No Lead QFN package and its advantages refer to Application Report Quad Flatpack No Lead Logic Packages Texas Instruments Literature No SCBAO17 This document is available at www ti com The exposed thermal pad dimensions for this package are shown in the following illustration 2 9 UUUUJUUU U Exposed Thermol Pad 1 1D f cuo 2 090 11 ho j f NS 205 5 An AAA A AIA 19 12 lt lt gt Bottom View NOTE All linear dimensions are in millimeters Exposed Thermal Pad Dimensions 4206363 2 E 03 08 LAND PATTERN RHL R PQFP N20 NOTES Example Stencil Design Example Board Layout 0 125mm Stencil Thickness Note E 14X0 5 EE 1 825 4 5 4 25 A ZEP 40 257 m LI Ies s
7. 3 1 5 Rectifier MOSFET QSR Similar criteria can be used for the rectifier MOSFET There is one significant difference Due to the body diode conducting the rectifier MOSFET switches with near zero voltage across its drain and source so effectively with near zero switching losses However there are some losses in the body diode These are minimized by reducing the delay time between the transition from the switching MOSFET turn off to rectifier MOSFET turn on and vice versa The TPS40075 incorporates TI s proprietary predictive gate drive which helps reduce this delay to between 10 ns and 20 ns Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Link s TPS40075 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 The calculations for the losses in the rectifier MOSFET are show in Equation 29 through Equation 32 Pasr Pasricony PpiopE PosR GATE 29 2 Vo 2 Al Paswcon Rps on X Ib Rpsion X Vin x U ET 30 Ppiope Vi X lioap X ty ta X fsw 81 Ko UVLO PWM 1V 32 where s Paonr body diode losses e t body diode conduction prior to turn on of channel 10 ns for predictive gate drive e ta body diode conduction after turn off of channel 10 ns for predictive gate drive e Vi body diode forward voltage Estimating the body diode losses based on a forward voltage of 1 2 V gives 0 142 W The gate losses are unk
8. Figure 33 Overall System Bode Plot Using these values and the equations above the resistors and capacitors around the compensation network can be calculated 1 Set Rz 10 kO 2 Calculate Rser using Equation 49 Rser 8750 Q Two resistors in parallel Bac and Rskr are used to make up Rset Harr 9 53 kO RsErT2 105 kO 3 Using Equation 54 and fz 3559 Hz Cpz can be calculated to be 4 47 nF Cpz 4 7 nF 4 Fp and Equation 52 yields Rp to be 677 Q Rp 680 Q 5 The required gain of 17 6 dB 7 586 and Equation 52 sets the value for Rpz Note actual gain used for this calculation was 20 dB 10 this ensures that the gain of the transfer function is high enough Rpz 6 2 kQ 6 Cz is calculated using Equation 55 and the desired frequency for the second zero Cz 6 8 nF 7 Opa is calculated using the second pole frequency and Equation 53 Cp 150 pF Using MathCAD the above values were used to draw the actual Bode plot for gain and phase From these plots the crossover frequency phase margin and gain margin can be recorded Table 3 Equivalent Series Resistance ESR CROSSOVER FREQUENCY PHASE MARGIN GAIN MARGIN Q kHz dB 0 23 1 72 gt 46 0 0095 98 6 78 8 gt 33 Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Link s TPS40075 35 TEXAS TPS40075
9. Input Voltage V Vpp Input Voltage V Figure 23 Figure 24 TERMINAL INFORMATION RHL PACKAGE BOTTOM VIEW l lt lt op Wa SYNC 20 1 SAO PGD GND LVBP SS RT FB KFF COMP ILIM PGND VDD LDRV HDRV N R DBP m z op op O m 12 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 K TEXAS INSTRUMENTS TPS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 Table 1 TERMINAL FUNCTIONS TERMINAL yo DESCRIPTION NAME NO The BOOST voltage is 8 V greater than the input voltage The peak voltage on BOOST is equal to the SW node BOOST 11 I voltage plus the voltage present at DBP less the bootstrap diode drop This drop can be 1 4 V for the internal bootstrap diode or 300 mV for an external schottkey diode The voltage differential between this pin and SW is the available drive voltage for the high side FET Output of the error amplifier input to the PWM comparator A feedback network is connected from this pin to the COMP 6 O FB pin to compensate the overall loop This pin is internally clamped to a 3 4 V maximum output drive capability for quicker recovery from a saturated feedback loop situation DBP 9 o 8 V regulator output used for the gate drive of the N channel synchronous rectifier and as the supply for charging the bootstrap capacitor This pin should be bypassed to ground with a 1 0 uF
10. 2 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 ki TEXAS INSTRUMENTS www ti com RECOMMENDED OPERATING CONDITIIONS TPS40075 SLUS676A MAY 2006 REVISED SEPTEMBER 2007 MIN NOM MAX UNIT Vpp Input voltage 4 5 28 V TA Operating free air temperature 40 85 G ELECTROSTATIC DISCHARGE ESD PROTECTION PARAMETER MIN TYP MAX UNIT Human body model 1500 V CDM 1500 PACKAGE DISSIPATION RATINGS AIRFLOW LFM THERMAL IMPEDANCE JUNCTION TO AMBIENT Ta 25 C POWER RATING W Ta 85 C POWER RATING W C W Natural Convection 42 2 38 0 95 200 35 2 85 1 14 400 31 3 22 1 29 1 For more information on the RHL package and the test method refer to TI technical brief literature number SZZA017 The ratings in this table are for the JEDEC High K board Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link s TPS40075 TPS40075 SLUS676A MAY 2006 REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS d TEXAS INSTRUMENTS T4 40 C to 85 C Vin 12 Vac Rr 90 9 kO Ikre 300 pA fsw 500 KHz all parameters at zero power dissipation unless otherwise noted www ti com
11. MINIMUM OUTPUT VOLTAGE vs vs JUNCTION TEMPERATURE FREQUENCY i ER Vin 28 V lt H INS 4 5 Vin lt 24 V S 20 gt 40 Vin 18 V a ViN 15 V g 30 3 5 Viu 12V m 5 VIN 10 V 40 3 0 amp Vi BN o 8 25 I Vin 5V E 60 5 20 WRC o S gt uw 70 1 5 2 a 80 1 0 90 0 5 50 25 0 25 50 75 100 125 100 200 300 400 500 600 700 800 900 1000 Ty Junction Temperature C fosc Oscillator Frequency kHz Figure 15 Figure 16 SWITCHING FREQUENCY TYPICAL SWITCHING FREQUENCY vs vs TIMING RESISTANCE INPUT VOLTAGE 600 520 515 500 510 i 400 9 Z 505 E o s a 2 300 g 500 c GC E 495 E 200 9 E 9 E 490 kd 100 485 480 0 200 400 600 800 1000 a js ei bs a S n Vpp Input Voltage V fsw Switching Frequency kHz Figure 17 Figure 18 10 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 ki TEXAS INSTRUMENTS Vuv_o Programmable UVLO Threshold V Vuv_o Programmable UVLO Threshold V www ti com TPS40075 SLUS676A MAY 2006 REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS continued UVLO THRESHOLD VOLTAGE vs FEEDFORWARD IMPEDANCE 20 fsw 300 kH alle ee S UVLOVoN
12. starts and sinks current when the soft start time has completed SHUTDOWN AND SEQUENCING The TPS40075 can be shut down by pulling the SS pin to a level below 250 mV Pulling the pin low resets the internal pre bias circuitry to ensure that the converter does not damage sensitive loads Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link s TPS40075 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 Automatic startup sequencing can be accomplished by connecting the PGD pin of a master supply based on the TPS40075 to the SS pin of a slave supply The master comes up first and release the salve SS pin to allow the slave to come up Controlled shutdown of sequenced supplies can be accomplished by either pulling the SS pin of the master below the shutdown threshold and letting the PGD pin pull the slave SS pin down or by pulling down the SS pins of all supplies simultaneously TPS40075 POWER DISSIPATION The power dissipation in the TPS40075 is largely dependent on the MOSFET driver currents and the input voltage The driver current is proportional to the total gate charge Qg of the external MOSFETSs Driver power neglecting external gate resistance can be calculated from Pp Qg X Vor x foy Watts driver 12 where e Vbr is the driver output voltage The total power dissipation in the TPS40075 assuming the same MOSFET is selected for both
13. MAY 2006 REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS continued FEEDBACK REGULATION VOLTAGE SENSE AMPLIFIER OUTPUT CURRENT vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 704 30 VDD 28 V za rE L 4 703 1 lt 4 5 V 1 12V 5 20 gt 702 5 o s 15 Si 5 Low Level Output Current o o 701 5 Z Ki o 10 S S 2 E 5 High Level Output Current 3 700 SCH a Q e EN E E I NN ke m 699 z 2 2 gt bh a Y E 5 a I ta aad P d H 698 eg Z ES D 697 15 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 T Junction Temperature C T Junction Temperature C Figure 7 Figure 8 CURRENT SENSE AMPLIFIER GAIN SWITCHING FREQUENCY vs vs JUNCTION TEMPERATURE INPUT VOLTAGE 1 0005 500 Rat 90 1kQ 499 gt 498 N H Z 497 5 0 9990 Mc esee ET P 496 23 a 3 g 0 9985 L 495 Vpp 1 25 V 2 DD 1 E 0 9980 5 494 a Vpp 20 5 V ZS 493 it 0 9975 I E 492 0 9970 e 491 0 9965 490 50 25 0 25 50 75 100 125 4 8 12 16 20 24 28 T Junction Temperature C Vvpp Input Voltage V Figure 9 Figure 10 8 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 K TEXAS INSTRUMENTS TPS40075
14. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY Vpp Input voltage range VIN 4 5 28 V OPERATING CURRENT Ipp Quiescent current Output drivers not switching 2 5 3 5 mA LVBP Vi vgp Output voltage TA Ty 25 C 3 9 4 2 4 5 V OSCILLATOR RAMP GENERATOR fosc Accuracy 450 500 550 kHz VRT RT voltage 223 240 2 58 V ton min Minimum output pulse time Cupry 0 nF 150 ns Vin High level input voltage SYNC 2 5 V Vit Low level input voltage SYNC 0 8 Isync Input current SYNC 5 10 pA Vrg 0 V 100 kHz lt fsw lt 500 kHz 8496 9596 Maximum duty cycle Vrg 0 V fsw 1 MHz 7696 9396 VkFF Feed forward voltage 0 35 0 40 0 45 V Iker Feed forward current operating range 20 1100 pA SOFT START Iss Charge current 9 5 12 145 pA tpscu Discharge time Css 3 9 nF 25 75 tss Soft start time m M LM ME M Ra Vsssp Shutdown threshold Vss falling 225 275 325 VssEN Enable threshold Vss rising 310 410 mV Vssspuvs Shutdown threshold hysteresis 35 130 DBP Vpp 10V 9 Vppp Output voltage V Vypp 4 5 V lout 25 mA 4 0 4 3 ERROR AMPLIFIER Ta Ty 25 C 0 698 0 700 0 704 VFB Feedback regulation voltage total variation 0 C lt TA Tj lt 85 C 0 690 0 700 0 707 v 40 C lt TA Ty lt 85 C 0 690 0 700 0 715 Vesiottset Soft start offset from VSS Offset from Vss to error amplifier 1 GBWP Gain bandwidth 5 10 MHz AvoL Open loop gain 50 dB ISRC Output source current 25 4 5 sier Isink Output sink current 2 5 6 IBAs Input bias current Vr
15. POWERGOOD OPERATION The PGD pin is an open drain output that actively pulls to GND if any of the following conditions are met assuming that the input voltage is above 4 5 V s Soft start is active Vyss lt 3 5 V e Vrp lt 0 63 V Vrp gt 0 77 V e Programmable UVLO condition not satisfied Viy below programmed level e Overcurrent condition exists Die temperature is greater than 165 C PRE BIASED OUTPUTS Some applications require that the converter not sink current during startup if a pre existing voltage exists at the output Since synchronous buck converters inherently sink current some method of overcoming this characteristic must be employed Applications that require this operation are typically power rails for a multi supply processor or ASIC The method used in this controller is to not allow the low side or rectifier FET to turn on until there the output voltage commanded by the start up ramp is higher than the pre existing output voltage This is detected by monitoring the internal pulse width modulator PWM for its first output pulse Since this controller uses a closed loop startup the first output pulse from the PWM does not occur until the output voltage is commanded to be higher than the pre existing voltage This effectively limits the controller to sourcing current only during the startup sequence If the pre existing voltage is higher that the intended regulation point for the output of the converter the converter
16. SLUS676A MAY 2006 REVISED SEPTEMBER 2007 35 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 From 3 3 V Logic Clock Source VDD 5Vto12V 22 uF 2 180uF 180 uF Si7868DP T L lt UDG 04110 Coiltronics HC2LP 2R2 or Vishay IHLP5050FDRZ2R2M01 Panasonic EEF SE0J181R x 2 TDK C4532X5R1C226M x2 Figure 37 300 kHz Intermediate Bus 5 V to 12 V to 3 3 V Converter 36 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 TPS40075 SLUS676A MAY 2006 REVISED SEPTEMBER 2007 INSTRUMENTS www ti com d TEXAS a LLe0 5an I Na9087Z S 4 aos d3ro8L lY O au 00L dGa898 S osi O o _ T Se nt x a 00L 1 IER MS wet AuqH agale zi auan aga 56 T ET ai aaa auai s eloo aui 8 E an9a aries anoa z wr ad 0ZL 3r ozi 40 ozi 3d s 444 dmoo 3 5 doo we sec EJ jai gan 1H a ad uz A ZL aqA s SS t z ZN dU Z au CE Zt laam l ep ss v L D ji L du ot glaad ano e elo ano c Gor SS SR 4982 mo ei oNas ovs z leL onas ovs SL00vSd mes S vs Wong 91607 19410 L uL ES A ZH 00 indu 49019 2NAS lt F0S1L2ATrZNS TTT ON OL 37 Submit Documentation Feedback Product Folder Link s TPS40075 Figure 38 Sequenc
17. any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such inform
18. closely but their absolute values can vary as much as 3095 so adding external resistance to alter the gain is not accurate in a production environment SYNCHRONIZATION The SYNC pin accepts logic level signals and is used to synchronize the TPS40075 to an external clock source Synchronization occurs on the rising edge of the signal at the SYNC pin There is a fixed delay of approximately 300 ns from the rising edge of the waveform at SYNC to the HDRV output turning on the high side FET The pin may be left floating in this function is not used or it may be connected to GND The frequency of the external clock must be greater than the free running frequency of the device as set by the resistor on the RT pin Rpr This pin requires a totem pole drive or open collector drain if pull up resistor to either LVBP or a separate supply between 2 5 V and 5 V is used Synchronization does not affect the modulator gain due to the voltage feed forward circuitry The programmable UVLO thresholds are affected by synchronization The thresholds are shifted by the ratio of the sync frequency to the free running frequency of the converter For example synchronizing to a frequency 2096 higher than the free running frequency results in the programmable UVLO thresholds shifting up 20 from their calculated free run values The synchronization frequency should be kept less than 1 5 times the free run frequency for best performance although higher multiples can be used
19. for TPS40075 3 2 1 Timing Resistor Rz The timing resistor is calculated using the following equation 1 Ry 23 few X 17 82 x 1076 33 This gives a resistor value of 89 2 kO Using the E24 range of resistor values a 118 kO resistor was selected The nominal frequency using this resistor is 398 kHz 3 2 2 Feed Forward and UVLO Resistor Butt A resistor connected to the KFF pin of the device feeds into the ramp generator This resistor provides current into the ramp generator proportional to the input voltage The ramp is then adjusted to compensate for different input voltages Is provides the voltage feed forward feature of the TPS40075 The same resistor also sets the under voltage lock out point The input start voltage should be used to calculate a value for Rer For this converter the minimum input voltage is 10 8 V however due to tolerances in the device a start voltage of 15 less than the minimum input voltage is selected The start voltage for Ryee calculation is 9 18 V Using Equation 34 Ree can be selected 28 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 K TEXAS INSTRUMENTS TPS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 ME 0 5 5 re 8 amp 34 This equation gives a Bur value of 136 kQ The closest lower standard value should be selected For this design and using E24 resistor range 133 kQ was chosen
20. in capacitance A 2 2 uF 16 V MLCC is also added in parallel to reduce high frequency noise Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Link s TPS40075 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 3 1 3 Input Capacitor Cin ELCO and MLCC The input capacitor is selected to handle the ripple current of the buck stage Also a relative large capacitance is used to keep the ripple voltage on the supply line low This is especially important where the supply line is high impedance It is recommended that the supply line be kept low impedance The input capacitor ripple current can be calculated using Equation 23 2 AI 2 IcAP RMS we iN avg X D linvavg X 1 D os where liavg i the average input current This is calculated simply by multiplying the output DC current by the duty cycle The ripple current in the input capacitor is 5 05 A A 1206 MLCC using X7R material has a typical dissipation factor of 5 For a 2 2 pF capacitor at 400 kHz the ESR is approximately 7 2 mQ If two capacitors are used in parallel the power dissipation in each capacitor is less than 46 mW A 470 uF 16 V electrolytic capacitor is added to maintain the voltage on the input rail 3 1 4 Switching MOSFET QSW The following key parameters must be met by the selected MOSFET e Drain source voltage Vos must be able to withstand the i
21. mm BO mm KO mm P1 w Pin1 Type Drawing Diameter Width mm mm Quadrant mm W1 mm TPS40075RHLR QFN RHL 20 3000 330 0 12 4 3 8 4 8 1 6 8 0 12 0 Q1 TPS40075RHLT QFN RHL 20 250 180 0 12 4 3 8 4 8 1 6 8 0 12 0 Q1 Pack Materials Page 1 X3 Texas PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 11 Mar 2008 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TPS40075RHLR QFN RHL 20 3000 346 0 346 0 29 0 TPS40075RHLT QFN RHL 20 250 190 5 212 7 31 8 Pack Materials Page 2 MECHANICAL DATA RHL R PQFP N20 PLASTIC QUAD FLATPACK a dd 2 Index Area 1 00 0 8 Laar 0 20 REF Seating Plane 08 C 0 0 0 0 0 325 2 PLCS Exposed Thermal Pad 4205346 2 C 12 04 NOTES A All linear dimensions are in millimeters Dimensioning and tolerancing per ASME Y14 5M 1994 B This drawing is subject to change without notice C QFN Quad Flatpack No Lead Package configuration A The package thermal pad must be soldered to the board for thermal and mechanical performance See the Product Data Sheet for details regarding the exposed thermal pad dimensions 35 TEXAS INSTRUMENTS www ti com 9 TEXAS THERMAL PAD MECHANICAL DATA INSTRUMENTS www ti com RHL R PVQFN N20
22. 00000 N00 oi 67 solder coverage by printed area on center thermal pad Non Solder Mask hu Example Via Layout Design x may vary depending on constraints Defined Pad S y vary aep g Example x Note D F Solder Mask Opening Pad Geometry S eg 40 725 0 07 4 Note C NAII Around 4207830 2 A 03 06 All linear dimensions are in millimeters This drawing is subject to change without notice Publication IPC 7351 is recommended for alternate designs This package is designed to be soldered to a thermal pad on the board Refer to Application Note Quad Flat Pack Packages Texas Instruments Literature No SCBAO17 SLUA271 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents are available at www ti com http www ti com gt Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Refer to IPC 7525 for stencil design considerations Customers should contact their board fabrication site for minimum solder mask web tolerances between signal pads d Texas INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at
23. Capacitor Co ELCO and MLCC Several parameters must be considered when selecting the output capacitor The capacitance value should be selected based on the output overshoot Vover and undershoot Vunper during a transient load Istep on the converter The equivalent series resistance ESR is chosen to allow the converter meet the output ripple specification Vgppig The voltage rating must be greater than the maximum output voltage Other parameters to consider are equivalent series inductance which is important in fast transient load situations Also size and technology can be factors when choosing the output capacitor In this design a large capacitance electrolytic type capacitor Co ELCO is used to meet the overshoot and under shoot specifications Its ESR is chosen to meet the output ripple specification While a smaller multiple layer ceramic capacitor Co MLCC is used to filter high frequency noise The minimum required capacitance and maximum ESR can be calculated using the equations below 2 Go L X Istep O 2 X Vunper X Dmax X Vin Vo 20 Lx C gt STEP 9 2x Vover X Vo 21 ESR V RIPPLE Al 22 Using Equation 20 through Equation 22 the capacitance for Co should be greater than 495 uF and its ESR should be less than 9 1mO The 1000 yF 25 V capacitor from Rubycon s MBZ or Panasonic s series EEU FL was chosen Its ESR is 19 mQ so two in parallel are used The slightly higher ESR is offset by the four times increase
24. E CLOCK OSCILLATOR The TPS40075 has independent clock oscillator and PWM ramp generator circuits The clock oscillator serves as the master clock to the ramp generator circuit Connecting a single resistor from RT to ground sets the switching frequency of the clock oscillator The clock frequency is related to Rr by Rr 1 23 ka fa KHz x 17 82 x 10 3 PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO FUNCTION The ramp generator circuit provides the actual ramp used by the PWM comparator and provides voltage feed forward by varying the PWM ramp slope as the line voltage changes As the input voltage to the converter increases the slope of the PWM ramp increase by a proportionate amount The programmable UVLO circuit works by monitoring the level reached by the PWM ramp during a clock cycle The PWM ramp must reach approximately 1 V in amplitude during a clock cycle or the converter is not be allowed to start This programmable UVLO point is set via a single resistor vr connected from KFF to VDD Rer Vsragr and Ber are related by approximately Ree 0 131 x Rz X Vyy gg 1 61 x 107 x Mes 1 886 x Vig 1 363 0 02 x R 4 87 x 1075 x R 4 where VuvLO on is in volts e Rkrr and Rr are in KQ This yields typical numbers for the programmed startup voltage The minimum and maximum values may vary up 15 from this number Figure 19 through Figure 21 show the typical relationship of Vuut cent Vuvro or and Re
25. PS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 Figure 26 shows the effect of changing input voltage on the duty cycle and how that change takes place The pulse width modulator PWM ramp input is generated using a current that is proportional to the current into the KFF pin The TPS40075 holds this pin at a constant 400 mV so connecting a resistor from KFF to the input power supply causes a current to flow into the KFF pin that is proportional to the input voltage The slope of the ramp signal to the PWM is therefore proportional to the input voltage This allows the duty cycle to change with variations in Vin without requiring much response from the error amplifier resulting in very good line transient response Another benefit is essentially constant PWM gain over the entire input voltage operating range This makes the output control loop easier to design for a wide input range converter VIN VIN I I l l jl l l 1 I 1 l I SW SW l RAMP if l COMP RAMP P d VVALLEY l l I l I T4 m T if om ton ton2 L 2 P Lou gt Lous and d gt do VDG 03172 Figure 26 Voltage Feed Forward and PWM Duty Cycle Waveforms PROGRAMMING SOFT START TPS40075 uses a closed loop approach to ensure a controlled ramp on the output during start up Soft start is programmed by connecting an external capacitor Cas from the SS pin to GND This capacitor is charged by a fixed current gener
26. SFET off For proper operation the total gate charge of the MOSFET connected to LDRV should be less than 50nC LVBP 17 o 4 2 V reference used for internal device logic and analog functions This pin should be bypassed to GND with a 0 1 pF ceramic capacitor External loads less than 1 mA and electrically quiet may be applied PGD 18 o This is an open drain output that pulls to ground when soft start is active or when the FB pin is outside a 10 band around the 700 mV reference voltage PGND 7 Power ground reference for the device There should be a low impedance path from this pin to the source s of the lower MOSFET s RT 16 l A resistor is connected from this pin to GND to set the switching frequency SA 20 l Noninverting input of the remote voltage sense amplifier SA 1 l Inverting input of the remote voltage sense amplifier SAO 2 O Output of the remote voltage sense amplifier Soft start programming pin A capacitor connected from this pin to GND programs the soft start time The capacitor is charged with an internal current source of 12 pA The resulting voltage ramp on the SS pin is used as a second non inverting input to the error amplifier The voltage at this error amplifier input is approximately 1 V ss 4 I less that that on the SS pin Output voltage regulation is controlled by the SS voltage ramp until the voltage on the SS pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV If SS is below
27. TEXAS INSTRUMENTS www ti com TPS40075 SLUS676A MAY 2006 REVISED SEPTEMBER 2007 GROUNDING AND BOARD LAYOUT The TPS40075 provides separate signal ground GND and power ground PGND pins Care should be given to proper separation of the circuit grounds Each ground should consist of a plane to minimize its impedance if possible The high power noisy circuits such as the output synchronous rectifier MOSFET driver decoupling capacitor DBP and the input capacitor should be connected to PGND plane Sensitive nodes such as the FB resistor divider and RT should be connected to the GND plane The GND plane should only make a single point connection to the PGND plane It is suggested that the GND pin be tied to the copper area for the PowerPAD underneath the chip Tie the PGND to the PowerPAD copper area as well and make the connection to the power circuit ground from the PGND pin Reference the output voltage divider to the GND pin Component placement should ensure that bypass capacitors LVPB and DBP are located as close as possible to their respective power and ground pins Also sensitive circuits such as FB RT and ILIM should not be located near high dv dt nodes such as HDRV LDRV BOOST and the switch node SW Failure to follow careful layout practices results in sub optimal operation SYNCHRONOUS RECTIFIER CONTROL Table 2 describes the state of the rectifier MOSFET control under various operating conditions Table 2 Synchr
28. This yields a typical start voltage of 8 52 V Rkrr 3 2 3 Soft Start Capacitor It is good practice to limit the rise time of the output voltage This helps prevent output overshoot and possible damage to the load The selection of the soft start time is arbitrary but it must meet one condition it should be greater than the time constant of the output filter L and Co This time is given by Equation 35 totant 2m X JL x Co 35 The soft start time must be greater than 0 281 ms A time of 1 ms was chosen this time also helps keep the initial input current during start up low The value of Css can be calculated using Equation 36 12 x 10 6 Css 97 X START 36 Css should be greater than 17 nF a 22 nF MLCC was chosen The calculated start time using this capacitor is 1 28 ms 3 2 4 Short Circuit Protection Bum and Cum Short circuit protection is programmed using the Ri iy resistor Selection of this resistor depends on the Rps on of the switching MOSFET selected and the required short circuit current trip point lscp The minimum lscp is limited by the inductor peak current the output voltage the output capacitor and the soft start time Their relationship is given by Equation 37 A short circuit current trip point greater than that calculated by this equation should be used Ca x V 0 OUT Al ISTART LAD 2 37 The minimum short circuit current trip point for this design is 16 35 A This value is used in Equ
29. VDG 03174 Figure 28 Typical Fault Protection Waveforms Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link s TPS40075 d Texas TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 The minimum short circuit limit threshold lacg depends on tstart Cour Vout and the load current at turn on ILoap C x V OUT OUT gt HI A SCP START LOAD 7 The short circuit limit programming resistor Ri jy is calculated from Iscp X Rps onMAX VILIM ofs o Nim 8 Rium where luu is the current into the ILIM pin 135 pA typical Viumotsy IS the offset voltage of the ILIM comparator 30 mV typical lscpe is the short circuit protection current RopstonwaAx is the drain to source resistance of the high side MOSFET To find the range of the short circuit threshold values use the following equations liti M max X Rium 90 mV SCP max Rps onMIN 9 liLiM min X Rium 10 mV SCP min Rps onMAX 10 The TPS40075 provides short circuit protection only As such it is recommended that the minimum short circuit protection level be placed at least 20 above the maximum output current required from the converter The maximum output of the converter should be the steady state maximum output plus any transient specification that may exist The ILIM capacitor maximum value can be found from Vout X 0 2 Une Vin X Riu
30. ain is shown in Equation 45 V 1 sxESR x G sx lak E LOAD 45 To describe this in a Bode plot the DC gain must be expressed in dB The DC gain is equal to Kpwy To express this in dB we take its LOG and multiple by 20 For this converter the DC gain is shown in Equation 46 Vuvio DCGAIN 20 x LOG ay J 20 x LOG 8 752 18 8 dB 46 The pole and zero frequencies should be calculated also A double pole is associated with the L C and a zero is associated with the ESR of the output capacitor The frequency at where these occur can be calculated using the following two equations 30 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 K TEXAS INSTRUMENTS www ti com 1 f LC_Pole On x L x Ca x m _ 1 ESR Zero 25 x ESR x Co 3559 Hz 8377 Hz The resulting bode plot is shown in Figure 30 30 TPS40075 SLUS676A MAY 2006 REVISED SEPTEMBER 2007 20 LT TTI Double Pole 10 ESR Zero Gain dB I E 0 Slope 40 dB ESR decade 10k Frequency Hz Figure 30 PWM and LC Filter Gain 100 k 47 48 The next step is to establish the required compensation gain to achieve the desired overall system response The target resp
31. ating a ramp signal The voltage on SS is level shifted down approximately 1 V and fed into a separate non inverting input to the error amplifier The loop is closed on the lower of the level shifted SS voltage or the 700 mV internal reference voltage Once the level shifted SS voltage rises above the internal reference voltage output voltage regulation is based on the internal reference To ensure a controlled ramp up of the output voltage the soft start time should be greater than the L Cour time constant or teranr gt 27 X L x Cour Seconds 5 where e Lis the value of the filter inductor e Cour is the value of the output capacitance s tstart is the output ramp up time For a desired soft start time the soft start capacitance Css can be found from l ss Css tss X V FB 6 Please note There is a direct correlation between tstart and the input current required during start up The lower terAnT is the higher the input current required during start up since the output capacitance must be charged faster Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link s TPS40075 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 PROGRAMMING SHORT CIRCUIT PROTECTION The TPS40075 uses a two tier approach to short circuit protection The first tier is a pulse by pulse protection scheme Short circuit protection is implemented by sensing the
32. ation 38 to calculate the minimum Ry y value lecp Iscp X Rps on MAx ViLiM min Rium SINK max 38 Rium is calculated to be 1 14 KQ The closest standard value greater than 1 14 KQ is chose this is 1 15 kO To verify that the short circuit current requirements are met the minimum and maximum short circuit current can be calculated using Equation 39 and Equation 40 _ leiNK min X RiLIM min V ILIM max SCP min pe ISINK max Du IM max B Vit IM min SCP max Rps on MAX 40 The minimum lscp is 17 09 A and the maximum is 29 45 A It is recommended to add a small capacitor Cy jy across Ry jy The value of this capacitor should be less than that calculated in Equation 41 Vo x 0 2 Une Vin X Rim X fow 41 This equation yields a maximum Cj y of 44 pF A value half this is chosen 22 pF Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Link s TPS40075 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 3 2 5 Voltage Decoupling Capacitors Cpgp C ygp and Cypp Several pins on the TPS40075 have DC voltages It is recommended to add small decoupling capacitors to these pins Below is a list of the recommended values Copp 1 0 HF Cuvgp 0 1 uF Cupp 4 7 HF 3 2 6 Boost Voltage Cgoost and Dgoost optional A capacitor charge pump or boost circuit is required to drive an N
33. ation may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requiremen
34. ceramic capacitor FB 5 I Inverting input to the error amplifier In normal operation the voltage on this pin is equal to the internal reference voltage 0 7 V GND 3 Ground reference for the device HDRV 42 o Floating gate drive for the high side N channel MOSFET This pin switches from BOOST MOSFET on to SW MOSFET off Short circuit protection programming pin This pin is used to set the overcurrent threshold An internal current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD The voltage on this pin is compared to the voltage drop Vypp Vsw across the high side N channel MOSFET during ILIM 14 l conduction Just prior to the beginning of a switching cycle this pin is pulled to approximately Vvpp 2 and released when SW is within 2 V of Vvpp or after a timeout the precondition time whichever occurs first Placing a capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch on time effectively programming the ILIM blanking time See Applications Information section A resistor is connected from this pin to VDD programs the amount of input voltage feed forward The current fed KFF 15 l into this pin is used to control the slope of the PWM ramp and program undervoltage lockout Nominal voltage at this pin is maintained at 400 mV LDRV 8 o Gate drive for the N channel synchronous rectifier This pin switches from DBP MOSFET on to PGND MO
35. channel MOSFET in the switch location of a buck converter The TPS40075 contains the elements for this boost circuit The designer just has to add a capacitor Cgoost from the switch node of the buck power stage to the BOOST pin of the device Selection of this capacitor is based on the total gate charge of the switching MOSFET and the allowable ripple on the boost voltage AVgoosr A ripple of 0 15 V is assumed for this design Using these two parameters and Equation 42 the minimum value for Cpoosr can be calculated _ aora AVgoost 42 The total gate charge of the switching MOSFET is 13 3 nC A minimum Cgoosz of 0 089 pF is required A 0 1 UF capacitor was chosen C BOOST This capacitor must be able to withstand the maximum voltage on DPP 10 V in this instance A 50 V capacitor is used for expediancy To reduce losses in the TPS40075 and to increase the available gate voltage for the switching MOSFET an external diode can be added between the DBP pin and the BOOST pin of the device A small signal schottky should be used here such as the BAT54 3 3 Closing the Feedback Loop Rz Roe Hpzo Fiseri Fisero Cr Dos and Cpz1 A graphical method is used to select the compensation components This is a standard feedforward buck converter Its PWM gain is shown in Equation 43 K s VuvLO PWM 1V 43 The gain of the output L C filter is given by Equation 44 1 s x ESR x Co Kic s x lek lep LOAD 44 The PWM and LC g
36. d TEXAS INSTRUMENTS www ti com lt TPS40075 SLUS676A MAY 2006 REVISED SEPTEMBER 2007 MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER WITH VOLTAGE FEED FORWARD FEATURES Operation Over 4 5 V to 28 V Input Range s Fixed Frequency Voltage Mode Controller e Integrated Unity Gain Amplifier for Remote Output Sensing e Predictive Gate Drive Generation II for Improved Efficiency e lt 1 Internal 700 mV Reference Input Voltage Feed Forward Control s Prebiased Output Compatible e Internal Gate Drive Outputs for High Side and Synchronous N Channel MOSFETs e Switching Frequency Programmable to 1 MHz e 20 Pin QFN Package s Thermal Shutdown Protection s Software Design Tool and EVM Available APPLICATIONS s Power Modules s Networking Telecom e Industrial e Servers CONTENTS Device Ratings 2 Electrical Characteristics 4 Terminal Information 12 Application Information 15 Design Example 26 Additional References 40 DESCRIPTION The TPS40075 is a mid voltage wide input 4 5 V to 28 V synchronous step down controller offering design flexibility for a variety of user programmable functions including soft start UVLO operating frequency voltage feed forward and high side FET sensed short circuit protection The TPS40075 drives external N channel MOSFETs using second generation Predictive Gate Drive to minimize conduction in the body diode of the low side FET and maximize efficiency Pre biased outputs a
37. e slew rate is too great this regulator can over shoot and damage to the part can occur To ensure that the part operates properly limit the slew rate to no more than 0 12 V us as the voltage at VDD crosses 8 V If necessary an R C filter can be used on the VDD pin of the device Connect the resistor from the VDD pin to the input supply of the converter Connect the capacitor from the VDD pin to PGND There should not be excessive more than a 200 mV voltage drop across the resistor in normal operation This places some constraints on the R C values that can be used Figure 25 is a schematic fragment that shows the connection of the R C slew rate limit circuit Equation 1 and Equation 2 give values for R and C that limits the slew rate in the worst case condition TPS40075 UDG 05058 Figure 25 Limiting the Slew Rate Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link s TPS40075 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 R lt 0 2 V few X Hamon lipo 1 c gt Vun 8V R x SR 2 where e Vyn is the final value of the input voltage ramp fsw is the switching frequency Qgcror is the combined total gate charge for both upper and lower MOSFETs from MOSFET data sheet e lnn is the TPS40075 input current 3 5 mA maximum e SR is the maximum allowed slew rate 12 x10 V s SETTING THE SWITCHING FREQUENCY PROGRAMMING TH
38. ed Supplies Synchronized 180 Out of Phase Copyright 2006 2007 Texas Instruments Incorporated 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 ADDITIONAL REFERENCES The following parts are similar to the TPS40075 and may be of interest 1 TPS40071 Mid Range Input 4 5 V to 28 V up to 1 MHz Frequency Synchronous Buck Controller 2 TPS40100 Wide Input Range Synchronous Buck Controller for Sequencing 3 TPS40057 Wide Input 8 V to 40 V up to 1MHz Frequency Synchronous Buck Controller source sink with prebias 4 TPS40190 Low Pin Count Synchronous Buck DC DC Controller 38 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 d TEXAS INSTRUMENTS TPS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 EXAMPLE LAND PATTERN RHL R PQFP N20 Example Stencil Design Example Board Layout 0 125mm Stencil Thickness Note E EL JUD I U U J J S 1 32 LE 4 ap 67 solder un by printed area on center thermal pad Pad Geometry Non Solder Mask Defined Pad Example Solder Mask Opening Note F Example Pad Geometry 0 07 Note C All Around PRELIMINARY FOR REFERENCE ONLY NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Publication IPC SM 782 is recommended for alternate designs D This package is designed to be solde
39. erminals 6 V at SA and SA pins 4 Ensured by design Not production tested Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link s TPS40075 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS continued T4 40 C to 85 C Vin 12 Vac Rr 90 9 kO Ikre 300 pA fsw 500 KHz all parameters at zero power dissipation unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Shutdown temperature threshold 165 T Hysteresis 15 TYPICAL CHARACTERISTICS LVBP VOLTAGE DBP VOLTAGE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 4 30 8 15 8 10 4 25 Vpp 28 V Vpp 28 V gt JL Leet gt 805 4 20 1 S S HER ND RR NEN E D 2 8 00 S 4 15 Vpp 12V amp Vpp 12V 3 A 795 n n 4 10 gt gt 7 90 4 05 7 85 4 00 7 80 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 T Junction Temperature C Ty Junction Temperature C Figure 1 Figure 2 6 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 4
40. etween these two voltages the regulator is in whatever state it was in when VDD entered this region The LVBP pin is connected to a 4 2 V regulator that supplies power for the internal control circuitry Small amounts of current can be drawn from these pins for other external circuit functions as long as power dissipation in the controller chip remains at acceptable levels and junction temperature does not exceed 125 C Any external load connected to LVBP should be electrically quiet to avoid degrading performance of the TPS40075 Typical output voltages for these two regulators are shown in Figure 23 and Figure 24 20 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 K TEXAS INSTRUMENTS TPS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 DIFFERENTIAL SENSE AMPLIFIER The TPS40075 has an on board differential amplifier intended for use as a remote sensing amplifier for the output voltage Use of this amplifier for remote sensing eliminates load regulation issues due to voltage drops that occur between the converter and the actual point of load The amplifier is powered from the DBP pin and can be used to monitor output voltages up to 6 V with a DBP voltage of 8 V For lower DBP voltages the sense amplifier can be used to monitor output voltages up to 2 V below the DBP voltage The internal resistors used to configure the amplifier for unity gain match each other
41. g 0 7 V 250 0 nA SHORT CIRCUIT CURRENT PROTECTION li iM Current sink into ILIM pin 115 135 150 HA Vitimofst Current limit offset voltage Vim 11 5 V Vsw Vium Vvpp 12 V 50 30 10 1 mV tusc Minimum HDRV pulse width During short circuit 135 225 ns Propagation delay to output 50 ns tBLANK Blanking time 50 ns 1 Ensured by design Not production tested 4 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 K TEXAS INSTRUMENTS TPS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS continued T4 40 C to 85 C Vn 12 Vac Rr 90 9 KO Iker 300 pA fsw 500 kHz all parameters at zero power dissipation unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT torr Off time during a fault SS cycle times 7 cycles Vsw Switching level to end precondition Vvpp Vsw 2 V tec Precondition time 2 100 ns ViLimpre Current limit precondition voltage threshold 6 8 V OUTPUT DRIVERS tHFALL EE REEF B in Cunny 2200 pF HDAV SW 36 D tHRISE High side driver rise time 48 tHFALL High side driver fall time 2200 pF HDRV SW 72 tHRISE High side driver rise time vu 4 5 V ES i 96 Ge tLFALL SONIS diiva Bl dua
42. ing and Current Limit Waveforms and Timing Relationship The second event that can cause ILIM to return to its nominal value is for an internal timeout to expire This is illustrated in Figure 27 B as T3 Here SW never rises to VDD 2 for whatever reason and the internal timer times out This allows the ILIM pin to start its transition back to its nominal value Prior to ILIM starting back to its nominal value short circuit sensing is not enabled In normal operation this insures that the SW node is at a higher voltage than ILIM when short circuit sensing starts avoiding false trips while allowing for a quicker blanking delay than would ordinarily be possible Placing a capacitor across Rim sets an exponential approach to the normal voltage at the ILIM pin This exponential decay of the short circuit threshold can be used to compensate for ringing on the SW node after its rising edge and to help compensate for slower turn on MOSFETs Choosing the proper capacitance requires care If the capacitance is too large the voltage at ILIM does not approach the desired short circuit level quickly enough resulting in an apparent shift in short circuit threshold as pulse width changes 18 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 K TEXAS INSTRUMENTS TPS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 The comparator that looks at ILIM and SW to determine if a
43. m X fsw Farads 11 Note that this is a recommended maximum value If a smaller value can be used it should be to improve protection For most applications consider using half the maximum value shown in Equation 11 BOOST AND DBP BYPASS CAPACITANCE The BOOST capacitance provides a local low impedance flying source for the high side driver The BOOST capacitor should be a good quality high frequency ceramic capacitor A minimum value of 100 nF is suggested The DBP capacitor has to provide energy storage for switching both the synchronous MOSFET and the high side MOSFET via the BOOST capacitor The suggested value for this capacitor is 1 uF ceramic minimum INTERNAL REGULATORS The internal regulators are linear regulators that provide controlled voltages for the drivers and the internal circuitry to operate from The low side driver operates directly from the 8 V regulator supply while the high side driver bootstrap capacitor is charged from this supply The actual voltage delivered to the high side driver is the voltage on the DBP pin less any drop from the bootstrap diode If the internal bootstrap diode is used the drop across that diode is nominally 1 4 V at room temperature This regulator has two modes of operation At voltages below 8 5 V on VDD the regulator is in a low dropout mode of operation and tries to provide as little impedance as possible from VDD to DBP When VDD is above 10 V the regulator regulates DBP to 8 V B
44. nown at this time so assume 0 1 W gate losses This leaves 0 258 W for conduction losses Using this figure a target Rps on of 1 1 mO was calculated This is an extremely low value It is not possible to meet this without paralleling multiple MOSFETs Paralleling MOSFETs increases the gate capacitance and slows down switching speeds This increases body diode and gate losses The PH2625L from Philips was chosen Using the parameters from its data sheet the actual expected power losses were calculated Conduction loss is 0 527 W body diode loss is 0 142 W and the gate loss was 0 174 W This totals 0 843 W associated with the rectifier MOSFET This is somewhat greater than the initial allowance Because of this the converter may not hit its efficiency figure at the maximum load Two other criteria should be verified before finalizing on the rectifier MOSFET One is the requirement to ensure that predictive gate drive functions correctly The maximum turn off delay of the PH2625L is 67 ns The minimum turn on delay of the PH6325L is 25 ns These devices easily meet the 100 ns difference requirement Secondly the ratio between Cas and C should be greater than 1 The Cos of the PH2625L is 2133 pF and the Cgd is 1622 pF so the C C ratio is 1 3 1 This helps reduce the risk of dv dt induced turn on of the rectifier MOSFET If this is likely to be a problem a small resistor may be added in series with the boost capacitor Caoosr 3 2 Component Selection
45. nput voltage plus spikes that may be on the switching node For this design a Vps rating of 25 V to 30 V is recommended e Drain current lp at 25 C must be greater than that calculated using Equation 24 For this design Ip should be greater than 5 A Vo 2 AI D x ViN min LOAD max 12 eu e Gate source voltage Vas must be able to withstand the gate voltage from the control device For the TPS40075 this is 9 V Once the above boundary parameters are defined the next step in selecting the switching MOSFET is to select the key performance parameters Efficiency is the performance characteristic which drives the other selection criteria Target efficiency for this design is 9096 Based on 1 5 V output and 15 A this equates to a power loss in the converter of 2 5 W Using this figure a target of 0 5 W dissipated in the switching MOSFET was chosen 26 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 K TEXAS INSTRUMENTS TPS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 Equation 25 through Equation 28 can be used to calculate the power loss Posw in the switching MOSFET Pasw Paswicon Paswisw Posw GATE 25 2 Vo 2 Al2 Pasw coN Rps ton X Ip Rps on X Vin n oan 5 a Al p y f Los L 3 i Qs Qua Qossisw Qoss sn asw sw Vin X sw X Ig 5 27 Posw GATE Hamon X Vg X Fsw 28 where Pas
46. nverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Clocks and Timers www ti com clocks Digital Control www ti com digitalcontrol Interface interface ti com Medical www ti com medical Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Telephony www ti com telephony RF IF and ZigBee Solutions www ti com Iprf Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2008 Texas Instruments Incorporated
47. on Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 K TEXAS INSTRUMENTS TPS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 3 COMPONENT SELECTION 3 1 Power Train Components Designers familiar with the buck converter can skip to section 3 2 Component Selection for TPS40075 3 1 1 Output Inductor Lo The output inductor is one of the most important components to select It stores the energy necessary to keep the output regulated when the switch MOSFET is turned off The value of the output inductor dictates the peak and RMS currents in the converter These currents are important when selecting other components Equation 17 can be used to calculate a value for L Vo S V inma Vo L ViN max 17 Alis the allowable ripple in the inductor Selecting Al also sets the output current when the converter goes into discontinuous mode DCM operation Since this converter utilizes MOSFETS for the rectifier DCM is not a major concern Select Al to be between 20 and 30 of maximum Loan For this design Al of 3 A was selected The calculated L is 1 1 uH A standard inductor with value of 1 0 uH was chosen This increases Al by about 10 to 3 3 A With this Al value calculate the RMS and peak current flowing in Lo Note this peak current is also seen by the switching MOSFET and synchronous rectifier E 2 Al lLoap Rms y Loap 45 15 03 A u AI 3 1 2 Output
48. onous Rectifier MOSFET States SYNCHRONOUS RECTIFIER OPERATION DURING FAULT SOFT START NORMAL FAULT RECOVERY IS SAME OVERVOLTAGE AS SOFT START Off until first high side pulse is Turns off at the start of a new detected then on when high side cycle Turns on when the OFF ON EU A deg MOSFET is off high side MOSFET is turned off y yes For proper operation the total gate charge of the MOSFET connected to LDRV should be less than 50nC Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link s TPS40075 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 DESIGN EXAMPLE 1 SPECIFICATIONS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENT ViN Input voltage 10 8 12 0 13 2 Vo Output voltage lour 10A 1 5 5 V Regulation 1 47 1 53 VRIPPLE Output ripple voltage lanai 15 A 30 VovER Output overshoot Istep 8 A 50 mV VUNDER Output undershoot Istep 8A 50 hoan Output current 0 15 Iscp Short circuit current trip point 16 30 n Efficiency Vin 12V ligap 15A 85 few Switching frequency 400 kHz 2 SCHEMATIC Vin O mec asas sess O Cn o M ELCO SENSE Rp Cpz1 Rz 19 Cz 8 en SCH 7 EM D ll IL bam L CvivBP Cvpp Vo RT O QSR CBoosT Co Co ELCO MLCC oV 8 UDG 04125 Figure 29 TPS40075 Reference Design Schematic 24 Submit Documentati
49. onse is to have the crossover frequency between 1 10 to 1 4 times the switching frequency To have a phase margin greater than 45 and a gain margin greater than 6 dB A Type Ill compensation network as shown in Figure 31 was used for this design This network gives the best overall flexibility for compensating the converter Rpi Cpzi TPS40075 UDG 04126 Figure 31 Type Ill Conpensation with TPS40075 Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Link s TPS40075 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 A typical bode plot to this type of compensation network is shown in Figure 32 40 30 High Frequency Gain Gain dB 100 1k 10k 100k 1M fz fz2 fpi fp2 Frequency Hz Figure 32 Type Ill Compensation Bode Plot The high frequency gain and the break pole and zero frequencies are calculated using the following equations Ts pis us 49 Bass SR GE SET1 t RsET2 50 GAIN PES E in a Rz Rp 51 In 7 23x R x C P1 PZ1 52 f Cp2 Cz 1 P2 2x x Rpzo X Cpo X Czo 2m X Rpz X Cpo 53 Ui a P x C zi PZ1 54 fz2 l 2x x Rpz Rp X Gas 2 X Rpz X Go 55 Using this PWM and L C bode plot the following actions ensure stabili
50. r at three common frequencies The programmable UVLO circuit incorporates 2096 hysteresis from the start voltage to the shutdown voltage For example if the startup voltage is programmed to be 10 V the controller starts when Vpp reaches 10 V and shuts down when Von falls below 8 V The maximum duty cycle begins to decrease as the input voltage rises to twice the startup voltage Below this point the maximum duty cycle is as specified in the electrical table Note that with this scheme the theoretical maximum output voltage that the converter can produce is approximately two times the programmed startup voltage For design set the programmed startup voltage equal to or greater than the desired output voltage divided by maximum duty cycle 8596 for frequencies 500 kHz and below For example a 5 V output converter should not have a programmed startup voltage below 5 9 V Figure 22 shows the theoretical maximum duty cycle typical for various programmed startup voltages If the programmable UVLO voltage is set below 6 5V nominal a possibility exists that the part may enter factory test mode when powered down This can cause an undesired output rise as power is removed from the converter To prevent this from happening connect a 330 kOresistor from SS to GND An example of this can be seen in Figure 37 16 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 35 TEXAS INSTRUMENTS T
51. re supported by not allowing the low side FET to turn on until the voltage commanded by the closed loop soft start is greater than the pre bias voltage Voltage feed forward provides good response to input transients and provides a constant PWM gain over a wide input voltage operating range to ease compensation requirements Programmable short circuit protection provides fault current limiting and hiccup recovery to minimize power dissipation with a shorted output The 20 pin QFN package gives good thermal performance and a compact footprint SIMPLIFIED APPLICATION DIAGRAM Vour Vour at Load at Load SYNC IN TD O PowerGood OUT ww am De hI E Bea 3 d d o Vour IL Vour UDG 04075 Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet Predictive Gate Drive is a trademark of Texas Instruments PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 2006 2007 Texas Instruments Incorporated 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 ORDERING INFORMATION
52. red to a thermal pad on the board Refer to Application Note Quad Flat Pack Packages Texas Instruments Literature No SCBAO17 SLUA271 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents are available at www ti com http www ti com E Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Refer to IPC 7525 for stencil design considerations F Customers should contact their board fabrication site for minimum solder mask web tolerances between signal pads Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Link s TPS40075 X3 Texas PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 11 Mar 2008 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS A Heel Diameter Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Y Overall width of the carrier tape Pitch between successive cavity centers t Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes User Direction of Feed All dimensions are nominal Device Package Package Pins SPQ Reel Reel A0
53. s Go 2200 pF 24 n li RISE Low side driver rise time 2 48 li FALL SONIS SEHE t l nee Cinny 2200 pF Van 4 5 V 48 ns tLRISE Low side driver rise time 2 96 Vou High level output voltage HDRV mme 0 01 A Vaoosr VHoRv a 10 V lupRv 0 1 A Vaoosr Vupnv 0 95 1 35 VoL Low level output voltage HDRV Vupnv Zon om 0 01A 006 0 V Vupnv Vsw lupnv 0 1 A 0 65 1 00 Vou High level output voltage LDRV oer Vinny honv 0 01A 0 63 LOD V Voer Viprv ILorv 0 1 A 0 875 1 300 lLprv 0 01 A 0 03 0 05 VoL Low level output voltage LDRV V lipav 0 1 A 0 3 0 5 BOOST REGULATOR Vgoosr Output voltage Vvpp 12 V 15 2 17 0 V UVLO VuvLO Programmable UVLO threshold voltage Rkrr 90 9 KQ turn on Vypp rising 6 2 7 2 8 2 Programmable UVLO hysteresis Rer 90 9 KQ 1 10 1 55 2 00 V Fixed UVLO threshold voltage Turn on Vypp rising 4 15 4 30 4 45 Fixed UVLO hysteresis 275 365 mV POWER GOOD Veep Powergood voltage Ipep 1 mA 370 550 VEBH High level output voltage FB 770 mV VeBL Low level output voltage FB 630 SENSE AMPLIFIER Vio Input offset voltage osa m 1 25 V Offset referenced to 9 9 mV ApIFF Differential gain Van Vsa 4 5 V 0 995 1 000 1 005 VicM Input common mode range 9 0 6 V Re Internal resistance for setting gain 14 20 26 KQ loH Output source current 2 10 15 mA loL Output sink current 15 25 35 GBWP Gain bandwidth 2 MHz THERMAL SHUTDOWN 2 Ensured by design Not production tested 3 3 V at internal amplifier t
54. short circuit condition exists has a clamp on its SW input This clamp makes the SW node never appear to fall more than 1 4 V approximately could be as much as 2 V at 40 C below VDD While ILIM is more than 1 4 V below VDD short circuit sensing is effectively disabled giving a programmable absolute blanking time As a general rule it is best to make the time constant of the R C at the ILIM pin 20 or less of the nominal pulse width of the converter See Equation 11 The second tier protection incorporates a fault counter The fault counter is incremented on each cycle with an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse When the counter reaches seven 7 a fault condition is declared by the controller When this happens the output drivers turn both MOSFETs off Seven soft start cycles are initiated without activity on the HDRV and LDRV outputs and the PWM is disabled during this period The counter is decremented on each soft start cycle When the counter is decremented to zero the PWM is re enabled and the controller attempts to restart If the fault has been removed the output starts up normally If the output fault is still present the counter counts seven overcurrent pulses and re enters the second tier fault mode Refer to Figure 28 for typical fault protection waveforms L l Clock tBLANKING 7 Current Limit Trips HDRV Cycle Terminated by Current Limit Trip 7 Soft Start Cycles
55. synchronous voltage mode buck converters with inputs ranging from 4 5 V to 28 V and outputs as low as 700 mV Predictive gate drive circuitry optimizes switching delays for increased efficiency and improved converter output power capability Voltage feed forward is employed to ease loop compensation for wide input range designs and provide better line transient response An on board unity gain differential amplifier is provided for remote sensing in applications that require the tightest load regulation The TPS40075 incorporates circuitry to allow startup into a pre existing output voltage without sinking current from the source of the pre existing output voltage This avoids damaging sensitive loads at startup The controller can be synchronized to an external clock source or can free run at a user programmable frequency An integrated power good indicator is available for logic open drain output of the condition of the output of the converter MINIMUM PULSE WIDTH The TPS40075 has limitations on the minimum pulse width that can be used to design a converter Reliable operation is guaranteed for nominal pulse widths of 150 ns and above This places some restrictions on the conversion ratio that can be achieved at a given switching frequency See Figure 16 SLEW RATE LIMIT ON VDD The regulator that supplies power for the drivers on the TPS40075 requires a limited rising slew rate on VDD for proper operation if the input voltage is above 10 V If th
56. the internal offset voltage of 1 V 800 mV minimum ensured the resulting output voltage is zero Also provides timing for fault recovery attempts Pulling this pin below 250 mV causes the controller to enter a shutdown state with HDRV and LDRV held in a low state This pin is connected to the switched node of the converter and used for overcurrent sensing as well as gate drive SW 10 l timing This pin is also the return path from the high side FET for the floating high side FET driver A 1 5 O resistor in series with this pin is required for protection against substrate current issues SYNC 19 l Logic input for pulse train to synchronize oscillator VDD 13 l Supply voltage for the device Copyright 2006 2007 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link s TPS40075 35 TEXAS TPS40075 INSTRUMENTS www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 SIMPLIFIED BLOCK DIAGRAM TPS40075 UVLO Controller pine Generato SW Pulse 19 15 770 mV FB 630 mV SS Active Overcurrent Comparator and Control Soft Start and Fault Control Predictive Gate Drive Control Logic UDG 04076 14 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 K TEXAS INSTRUMENTS TPS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 APPLICATION INFORMATION The TPS40075 allows the user to construct
57. the high side and synchronous rectifier is described in Equation 13 2 x Pp P Von lq x Vum Watts or P 2 x Q x fsw lal x Vin Watts where lois the quiescent operating current neglecting drivers The maximum power capability of the TPS40075 PowerPAD package is dependent on the layout as well as air flow The thermal impedance from junction to air ambient assuming 2 0z copper trace and thermal pad with solder and no air flow is Ou 60 C W The maximum allowable package power dissipation is related to ambient temperature by Equation 15 Ty 7 TA JA 15 Substituting Equation 15 into Equation 14 and solving for fsw yields the maximum operating frequency for the TPS4007x The result is described in Equation 16 Ty Ta Dia X Vin S few 2 F aj Hz 16 BOOST DIODE The TPS40075 has internal diodes to charge the boost capacitor connected from SW to BOOST The drop across this diode is rather large at 1 4 V nominal at room temperature resulting in the drive voltage to the high side MOSFET being reduced by this amount from the DBP voltage If this drop is too large for a particular application an external diode may be connected from DBP anode to BOOST cathode This provides significantly improved gate drive for the high side MOSFET especially at lower input voltages 22 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 ki
58. ts concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataco
59. ty 1 Place two zero s close to the double pole i e fz fz2 3559 Hz 2 Place a pole at one octave below the desired crossover frequency The crossover frequency was selected as one quarter the switching frequency fco 100 KHz fp 50 kHz 3 Place the second pole about an octave above feo This ensures that the overall system gain falls off quickly to give good gain margin fp 200 kHz 4 The high frequency gain is sufficient to ensure 0 dB at the required crossover frequency GAIN 2 1 GAIN of PWM and LC at the crossover frequency GAIN 17 6 dB or 7 586 32 Submit Documentation Feedback Copyright 2006 2007 Texas Instruments Incorporated Product Folder Link s TPS40075 K TEXAS INSTRUMENTS TPS40075 www ti com SLUS676A MAY 2006 REVISED SEPTEMBER 2007 Desired frequency response and resultant overall system response can be seen in Figure 33 40 e r a Overall System GBWP 30 T Response L Overall System Tv ESR 0 Q Response 20 N ESR 0 0095 2 10 0 S SN S I Compensation SSS E 10 Response H SW N w N 20 PWM and LC Response N N SS ESR 00 N s d I N N K N 40 PWM and LC Response i N ESR 0 0095 Q H N 50 t N fco2 fco1 N 60 ld ri I lf LI K 100 1k 10k 100 k 1M Frequency Hz
60. voltage drop across the high side MOSFET while it is turned on The MOSFET drain to source voltage is compared to the voltage dropped across a resistor Rium connected from VDD to the ILIM pin The voltage drop across this resistor is produced by a constant current sink If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor the switching pulse is immediately terminated The MOSFET remains off until the next switching cycle is initiated In addition just prior to the high side MOSFET turning on the ILIM pin is pulled down to approximately half of VDD The ILIM pin is allowed to return to its nominal value after one of two events occur 1 The SW node rises to within approximately 2 V of VDD 2 An internal timeout occurs approximately 125 ns after ILIM is initially pulled down If the SW node rises to within approximately 2 V of VDD the device allows ILIM to go back to its nominal value This is illustrated in Figure 27 A T1 is the delay time from the internal PWM signal being asserted and the rise of SW This includes the driver delay of 50 ns typical and the turn on time of the high side MOSFET The MOSFET used should have a turn on time less than 75 ns T2 is the reaction time of the sensing circuit that allows ILIM to start to return to its nominal value typically 20ns ILIM pm Threshold A Overcurrent SW ILIM Threshold B SW Ti e T3 UDG 03173 Figure 27 Switch
61. w cow conduction losses Paswsw Switching losses Paswate gate drive losses Dug drain source charge or miller charge Qs gate source post threshold charge 1 gate drive current Qossgisw switching MOSFET output charge Qossisn synchronous MOSFET output charge gron total gate charge from zero volts to the gate voltage e Vg gate voltage If the total estimated loss is split evenly between conduction and switching losses Equation 25 and Equation 26 yields preliminary values for Rpos on and Qgs1 Q4 Note output losses due to Qoss and gate losses have been ignored here Once a MOSFET is selected these parameters can be added The switching MOSFET for this design should have an Rps on of less than 9 mQ The sum of Qy4 and Guas should be approximately 4 nC It is not always possible to get a MOSFET which meets both these criteria so a comprise may have to be made Also by selecting different MOSFETs close to this criteria and calculating power loss the final selection can be made It was found that the PH6325L MOSFET from Philips semiconductor gave reasonable results This device has an Rps on Of 6 3 mO and a Qgs1 Qgd of 5 9 nC The estimated conduction losses are 0 178 W and the switching losses are 0 270 W This gives a total estimated power loss of 0 448 W versus 0 5 W for our initial boundary condition Note this does not include gate losses of approximately 10 mW and output losses of less than 1 mW

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