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NATIONAL SEMICONDUCTOR DP83848I Guide

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1. DATA CODES 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010 B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111 IDLE AND CONTROL CODES H 00100 HALT code group Error code 11111 Inter Packet IDLE 0000 Note 1 J 11000 First Start of Packet 0101 Note 1 K 10001 Second Start of Packet 0101 Note 1 T 01101 First End of Packet 0000 Note 1 R 00111 Second End of Packet 0000 Note 1 INVALID CODES V 00000 V 00001 V 00010 V 0001 1 V 00101 V 00110 V 01000 V 01100 Note Control code groups J T and in data fields will be mapped as invalid codes together with RX ER as serted The code group encoder converts 4 bit 4B nibble data generated by the MAC into 5 bit 5B code groups for transmission This conversion is required to allow control data to be combined with packet data code groups Refer to Table 5 for 4B to 5B code group mapping details The code group encoder substitutes the first 8 bits of the MAC preamble with a J K code group pair 11000 10001 upon transmission The code group encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code groups At the end of the transmit packet upon the deassertion of Transmit Enable signal from the MAC the code gr
2. 37 Table 10 Register Table u pu u ee eem Moe xu ERREUR ERR E 38 Table 11 Basic Mode Control Register BMCR address 0x00 41 Table 12 Basic Mode Status Register address 0x01 43 Table 13 PHY Identifier Register 1 PHYIDR1 address 0 02 44 Table 14 PHY Identifier Register 2 PHYIDR2 address 0 03 44 Table 15 Negotiation Advertisement Register address 0 04 44 Table 16 Auto Negotiation Link Partner Ability Register ANLPAR BASE Page address 0x05 46 Table 17 Auto Negotiation Link Partner Ability Register ANLPAR Next Page address 0x05 47 Table 18 Auto Negotiate Expansion Register address 0x06 47 Table 19 Auto Negotiation Next Page Transmit Register ANNPTR address 0x07 48 Table 20 PHY Status Register PHYSTS address 0 10 49 Table 21 Interrupt Control Register MICR address 0 11 51 Table 22 Interrupt Status and Misc Control Register MISR address 0x12 52 Table 23 False Carrier Sense Counter Register FCSCR address 0x14 53
3. 135 eYALAHd 8 88 TX_CLK MII RMII SNI INTERFACES TX DATA 10BASE T amp Registers 10BASE T amp 100BASE Transmit Block Boundary Scan JTAG MII RMII SNI SERIAL MANAGEMENT CRS CRS_DV RX_ER RX_DV RXD 3 0 RX CLK RX DATA MII TX 100BASE TX Auto Negotiation R State Machine Bok S Clock Generation Auto MDIX LED Drivers TD RD REFERENCE CLOCK LEDS Figure 1 DP83848l Functional Block Diagram 2 www national com I8r8 8da Table of Contents 1 0 dir 9 1 1 Serial Management Interface 9 1 2 MAC Data Interface 9 1 9 Gloek Interface ALI 11 1 4 LED Interface moe Re oe Eee tn 11 1 5 TAG Interfaces uci ees o prre beu Rs n Rima ike a EI E ASENA A ae 12 1 6 Reset and Power Down 12 1 7 Strap Options ss teks wr LEE ke Eder RU Rp Op ma sta dte egere 12 1 8 10 Mb s 100 Mb s PMD Interface 14 1 9 Special Connections 14 1 10 Power Supply Pins 2 12 14 1 11 Package Pin Assignments
4. 53 7 2 6 100 Mb s PCS Configuration and Status Register PCSR 54 7 2 7 RMII and Bypass Register RBR 55 7 2 8 LED Direct Control Register LEDCR 55 7 2 9 PHY Control Register 1 2 56 7 2 10 10Base T Status Control Register 1OBTSCR 57 7 2 11 CD Test and BIST Extensions Register 59 7 2 12 Energy Detect Control EDCR 60 8 0 Electrical 61 8 1 96 5 U decet e E gases eres 61 8 2 AG EA ego 63 82 1 scho ie BS abe ed bode bea aie ee 63 8 2 2 Reset Timing DRAN AERAR T ie 64 8 2 3 Serial Management Timing 1 5 4 65 8 2 4 100 Mb s Transmit Timing 4 65 8 2 5 100 Mb s MII Receive Timing 66 8 2 6 100BASE TX Transmit Packet Latency Timing 66 4 www national com 8
5. H H H H H H H H H H ssed g pue 1ejsiDoH LI AALL www national com 39 7 1 Register Definition In the register definitions under the Default heading the following definitions hold true RW Read Write access SC Register sets on event occurrence and Self Clears when event ends RW SC Read Write access Self Clearing bit RO Read Only access COR Clear on Read RO COR Read Only Clear on Read RO P Read Only Permanently set to a default value LL Latched Low and held until read based upon the occurrence of the corresponding event LH Latched High and held until read based upon the occurrence of the corresponding event 40 www national com 137858 7 1 1 Basic Mode Control Register BMCR Table 12 Basic Mode Control Register BMCR address 0x00 14 Loopback Speed Selection Strap R Auto Negotiation Strap R Enable Power Down Restart Auto 0 RW SC Negotiation Duplex Mode Strap R Description Reset 1 Initiate software Reset Reset in Process 0 Normal operation This bit which is self clearing returns a value of one until the reset process is complete The configuration is re strapped Loopback 1 Loopback enabled 0 Normal operation The loopback function enables MII transmit data to be routed to the receive data path
6. 15 2 0 Configuration OR a 16 2 1 Auto Negotiation 1 1 16 2 1 1 Auto Negotiation Pin Control 1 16 2 1 2 Auto Negotiation Register 16 2 1 3 Auto Negotiation Parallel Detection 17 2 1 4 Auto Negotiation Restart 21 4 17 2 1 5 Enabling Auto Negotiation via Software 17 2 1 6 Auto Negotiation Complete 17 2 2 Auto MDIX sss e Lent evtl arde t aq ates er RN 17 2 3 PHY Address delia ed 18 2 371 Mililsolate Mode eo tke Casu 18 244 LED Interface ier EAn EE ARSE REX ER uo E ee aed 19 2 4 1 LEDS oe Se ee ee ee ee 19 24 2 LED Direct Control ER ee eS 20 2 5 Half Duplex vs Full Duplex 20 2 6 Internal ia care cue Rue ace gue te SURE a 20 2 4 3BIST eh dats wo te T AP EET EDS and a M DEN ERR wa A 20 3 0 Functional
7. H H H H H H H H H H H H H H H yor Qqa3Auasaud 3 1NNO LNNO ANNO LNNO les les 20 dis ir OLN pewes O HOU 29151 weado 0 1sia eu qua 19 ua 1918 u3 H3 1918 H3 1918 43 1918 u3 1918 u3 1sig 7941909 ug suoisueix3 1519 pue 1591 qO 1 3 sid sid ien Pus AL pn oF H H H 00 u3aaavr 1uv3H Hv Od SIG d1 vadoo1 o13nos o1anos oanos 123738 1801 S 1801 1eisiDeu jo4u09 sniels esego T luv Snivis _ _ _ XL X8 _ N AHd AHd AHd AHd qa q31 uis 15 1sia 1519 9 1918 asnvd asnvd 30804 3 XIGN uel JejsiDeg 041002 aai penes penes pewes penes penes penes 5 5 AWG eu H SIS SIS panies panies pe es peues panies pewes pewes parses qu xu xu Xu ad
8. atid Stee atone aed 26 4 2 2 Digital Signal 26 4 2 2 1 Digital Adaptive Equalization and Gain 28 4 2 2 2 Base Line Wander Compensation 29 4 2 3 Signal Detect ee em C RET ea See 29 4 2 4 MLT 3 to 29 42 5 eae ea ele eee gs 29 42 6 Serial to Parallel mu ee tes le ee eee cae Aa ee BE Res 29 4 2 7 Descrambler i ose odeur ia eme cde od endear ee ed er care 30 3 www national com I8v8 8da 4 2 8 Code group 30 4 2 9 AB OB Decoder PIRE eene yd ee pele e hg 30 4 2 10 100BASE TX Link Integrity Monitor 30 42 11 Bad SSD Detection orrs as seht debo pex uu EUR UR Axe AERE d 30 4 3 10BASE T TRANSCEIVER MODULE 30 43 1 Operational bee pe Maa d 30 4 3 2 Smart Squelch RETE er A RS 31 4 3 3 Collision Detection and SQE 31 4 34 Carrier Sensei Re I E Wig p eI RESP E T
9. T2 26 1 X1 IE MEMO T2 26 2 T2 26 3 TXD 1 0 i TX Valid Data T2 26 4 PMD Output Pair X X Symbol x Parameter Description Notes Min Typ Max Units T2 26 1 X1 Clock Period 50 MHz Reference Clock 20 ns T2 26 2 TXD 1 0 TX EN Data Setup 4 ns to X1 rising T2 26 3 TXD 1 0 TX EN Data Hold 2 ns from X1 rising T2 26 4 X1 Clock to PMD Output Pair From X1 Rising edge to first bit of symbol 17 bits Latency 78 www national com I8v8 8da 8 2 27 Receive Timing PMD Input Pair IDLE Data TR Data L T2274 ts oe x 2 27 T2273 T2272 12273 RX_DV CRS_DV 2 2 T2 27 2 89189 0 0 0 0 0 0 RXD 1 0 Description Notes Min Typ Max Units T2 27 1 X1 Clock Period 50 MHz Reference Clock 20 ns T2 27 2 RXD 1 0 CRS DV RX DV 2 14 ns and RX ER output delay from X1 rising T2 27 3 CRS ON delay From JK symbol on PMD Receive Pair to 18 5 bits initial assertion of CRS DV T2 27 4 CRS OFF delay From TR symbol on PMD Receive Pair to 27 bits initial deassertion of CRS DV T2 27 5 RXD 1 0 and RX ER latency From symbol on Receive Pair Elasticity 38 bits buffer set to default value 01 Note Per the RMII Specification output delays assume a 25pF load Note CRS DV is asserted asynchronously i
10. 21 3 1 Interface us cuc ed id baer ue RUE Laine 21 3 1 1 Nibble wide MII Data 21 3 1 2 Collision Detect indem I ee SCENE RES OR ERR Rn 21 3 1 3 Carriere Sese ctis det Du d Ag a de NG Rod RAUM GO eG a ate PER oid 21 3 2 Reduced Interface 21 3 3 10 Mb Serial Network Interface 22 3 4 802 3u Serial Management Interface 22 3 4 1 Serial Management Register Access 22 3 4 2 Serial Management Access 22 3 4 3 Serial Management Preamble Suppression 23 4 0 Architecture 24 4 1 100BASE TX TRANSMITTER 24 4 1 1 Code group Encoding and 1 26 AA 2 Scrambler Se oi uk Uer RUE aha 26 44 3 NRZ to NRZl Encoder beeen bo beh be eee biog 26 4 1 4 Binary to MLT 3 1 26 4 2 100BASE TX RECEIVER 26 42 1 Analog Front End 2
11. Ix eren Ix 2 hs x F F z 5 8 99 View NS Package Number VBH48A RBIAS PFBOUT AVDD33 RESERVED RESERVED AGND RD www national com 137858 1 0 Pin Descriptions The DP838481l pins are classified into the following inter Note Strapping pin option Please see Section 1 7 for strap face categories each interface is described in the sections definitions that follow Serial Management Interface MAC Data Interface Clock Interface LED Interface JTAG Interface Reset and Power Down Strap Options 10 100 Mb s PMD Interface Special Connect Pins Power and Ground pins 1 1 Serial Management Interface All DP83848l signal pins are I O cells regardless of the par ticular use The definitions below define the functionality of the I O cells for each pin Input Type O Output Type Input Output Type OD Open Drain Type PD PU Internal Pulldown Pullup Type S Strapping Pin All strap pins have weak in ternal pull ups or pull downs If the default strap value is needed to be changed then an external 2 2 resistor should be used Please see Section 1 7 for details Signal Name Type Pin Description MDC l 31 MANAGEMENT DATA CLOCK Synchronous clock to the MDIO management d
12. Automatically begin power up sequence when Energy Detect Data Threshold value EDCR 3 0 is reached Alternatively device could be powered up manually using the ED MAN bit ECDR 12 ED AUTO DOWN 1 RW Energy Detect Automatic Power Down Automatically begin power down sequence when no energy is de tected Alternatively device could be powered down using the ED MAN bit EDCR 12 0 RW SC Energy Detect Manual Power Up Down Begin power up down sequence when this bit is asserted When set the Energy Detect algorithm will initiate a change of Energy De tect state regardless of threshold error or data and timer values In managed applications this bit can be set after clearing the Ener gy Detect interrupt to control the timing of changing the power state ED BURST DIS Energy Detect Bust Disable Disable bursting of energy detect data pulses By default Energy Detect ED transmits a burst of 4 ED data pulses each time the CD is powered up When bursting is disabled only a single ED data pulse will be send each time the CD is powered up ED PWR STATE Energy Detect Power State Indicates current Energy Detect Power state When set Energy Detect is in the powered up state When cleared Energy Detect is in the powered down state This bit is invalid when Energy Detect is not enabled 0 RO COR Energy Detect Error Threshold Met No action is automatically taken upon receipt of error events This bit is informational only
13. February 2007 National Semiconductor DP83848l PHYTER Industrial Temperature Single Port 10 100 Mb s Ethernet Physical Layer Transceiver General Description Features DP83848l is a robust fully featured 10 100 single Low power 3 3V 0 18um CMOS technology port Physical Layer device offering low power con power consumption lt 270mW Typical sumption including several intelligent power down 3 3 MAC Intert states These low power modes increase overall prod Menace uct reliability due to decreased power dissipation Sup Auto MDIX for 10 100 Mb s porting multiple intelligent power modes allows the Energy Detection Mode application to use the absolute minimum amount of 25 MHz clock out power needed for operation In addition to low power the DP83848l is optimized for cable length perfor Interface configurable mance far exceeding IEEE specifications Rev 1 2 Interface configurable The DP83848l includes 25MHz clock out This Serial Management Interface MDC and means that the application can be designed with a IEEE 802 3u MII minimum of external parts which in turn results in the m lowest possible total cost of the solution EEE 802 3u Auto Negotiation and karahe Detection The DP83848I easily interfaces to twisted pair media IEEE Su ENDEC transceivers ang titers via an external transformer and fully supports JTAG IEEE 8
14. No False Carrier event has occurred Signal Detect 0 RO LL 100Base TX unconditional Signal Detect from PMD Descrambler Lock 0 RO LL 100Base TX Descrambler Lock from PMD Page Received MII Interrupt Remote Fault Link Code Word Page Received This is a duplicate of the Page Received bit in the ANER register but this bit will not be cleared upon a read of the PHYSTS register 1 A new Link Code Word Page has been received Cleared on read of the ANER address 0x06 bit 1 0 Link Code Word Page has not been received Interrupt Pending 1 Indicates that an internal interrupt is pending Interrupt source can be determined by reading the MISR Register 0x12h Reading the MISR will clear the Interrupt 0 No interrupt pending Remote Fault 1 Remote Fault condition detected cleared on read of BMSR ad dress 01h register or by reset Fault criteria notification from Link Partner of Remote Fault via Auto Negotiation 0 No remote fault condition detected 49 www national com Table 21 PHY Status Register PHYSTS address 0x10 Continued 5 Jabber Detect Auto Neg Complete Description Jabber Detect This bit only has meaning in 10 Mb s mode This bit is a duplicate of the Jabber Detect bit in the BMSR register except that it is not cleared upon a read of the PHYSTS register 1 Jabber condition detected 0 No Jabber Auto Negotiation Complete 1 Auto Negotiation c
15. mat is shown below in Table 5 The pin requires a pull up resistor 1 5 which during IDLE and turnaround will pull MDIO high In order to initialize the MDIO interface the station management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83848l with a sequence that can be used to establish synchronization This preamble may be gener ated either by driving MDIO high for 32 consecutive MDG clock cycles or by simply allowing the MDIO pull up resis tor to pull the MDIO pin high during which time 32 MDC clock cycles are provided In addition 32 MDC clock cycles should be used to re sync the device if an invalid start opcode or turnaround bit is detected DP83848l waits until it has received this preamble sequence before responding to any other transaction Once the DP83848I serial management port has been ini tialized no further preamble sequencing is required until after a power on reset invalid Start invalid Opcode or invalid turnaround bit has occurred The Start code is indicated by a 01 pattern This assures the MDIO line transitions from the default idle line state Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field To avoid con tention during a read transaction no device shall actively drive the MDIO signal during the first bit of Turnaround The addressed DP83848l drives the with a zero for the second bit of
16. 4 1 100BASE TX TRANSMITTER The 100BASE TX transmitter consists of several functional blocks which convert synchronous 4 bit nibble data as pro vided by the to a scrambled MLT 3 125 Mb s serial data stream Because the 100BASE TX TP PMD is inte grated the differential output pins PMD Output Pair can be directly routed to the magnetics TX_CLK DIVIDE BY5 125MHZ CLOCK _ 100BASE TX LOOPBACK MLT 1 0 SCRAMBLER The block diagram in Figure 6 provides an overview of each functional block within the 100BASE TX transmit sec tion The Transmitter section consists of the following functional blocks QCode group Encoder and Injection block Scrambler block bypass option NRZ to NRZI encoder block Binary to MLT 3 converter Common Driver The bypass option for the functional blocks within the 100BASE TX transmitter provides flexibility for applications where data conversion is not always required The DP83848l implements the 100BASE TX transmit state machine diagram as specified in the IEEE 802 3u Stan dard Clause 24 TXD 3 0 TX 4B5B CODE GROUP ENCODER amp 5B PARALLEL TO SERIAL NRZ TO NRZI ENCODER BINARY TOMLT 3 COMMON DRIVER PMD OUTPUT PAIR Figure 6 100BASE TX Transmit Block Diagram 24 www national com Table 5 4B5B CCode group Encoding and Injection
17. _ 32 clocks MDC 5 5 2 2 2 Latch In of Hardware T22 3 Configuration Pins input output Dual Function Pins Become Enabled As Outputs Parameter Description Notes Min Typ Max Units T2 2 1 Post RESET Stabilization time MDIO is pulled high for 32 bit serial man 3 us prior to MDC preamble for reg agement initialization ister accesses T2 2 2 Hardware Configuration Latch Hardware Configuration Pins are de 3 us in Time from the Deassertion scribed in the Pin Description section of RESET either soft or hard T2 2 3 Hardware Configuration pins 50 ns transition to output drivers T2 2 4 RESET pulse width X1 Clock must be stable for at min of 1us 1 us during RESET pulse low time Note It is important to choose pull up and or pull down resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch in the proper value prior to the pin transitioning to an output driver 64 www national com I8v8 8da 8 2 3 Serial Management Timing MDC MDIO output X X MDC T2 3 2 T2 3 3 MDIO input Valid Data Parameter Description Notes Min Typ Max Units T2 3 1 MDC to MDIO Output Delay Time 0 30 ns T2 3 2 MDIO Input to MDC Setup Time 10 ns T2 3 3 MDIO Input to MDC Hold Time 10 ns T2 3 4 MDC Frequency 2 5 25 MHz 8 2 4 100 Mb s MII
18. 7 Automatic Link Polarity Detection and Correction 0 838481 5 10BASE T transceiver module incorpo rates an automatic link polarity detection circuit When three consecutive inverted link pulses are received bad polarity is reported A polarity reversal can be caused by a wiring error at either end of the cable usually at the Main Distribution Frame MDF or patch panel in the wiring closet The bad polarity condition is latched in the 10BTSCR regis ter The DP83848I s 10BASE T transceiver module cor rects for this error internally and will continue to decode received data correctly This eliminates the need to correct the wiring error immediately 4 3 8 Transmit and Receive Filtering External 10BASE T filters are not required when using the 0 838481 as the required signal conditioning is integrated into the device Only isolation transformers and impedance matching resis tors are required for the 10BASE T transmit and receive interface The internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated by at least 30 dB 4 3 9 Transmitter The encoder begins operation when the Transmit Enable input TX_EN goes high and converts NRZ data to pre emphasized Manchester data for the transceiver For the duration of TX_EN the serialized Transmit Data TXD is encoded for the transmit driver pair PMD Output Pair TXD must be valid on the rising edge of Transmit Clock TX_CLK Transmi
19. PAUSE bit indicates that the device is capable of providing the symmetric PAUSE functions as defined in Annex 31B Encoding and resolution of PAUSE bits is defined in IEEE 802 3 Annex 28B Tables 28B 2 and 28B 3 respectively Pause resolu tion status is reported in PHYCR 13 12 1 Advertise that the DTE MAC has implemented both the op tional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802 3u o 0 No MAC based full duplex flow control 100 4 Support 1 100 4 is supported by the local device 0 100 4 not supported Strap RW 100BASE TX Full Duplex Support 1 100BASE TX Full Duplex is supported by the local device 0 100BASE TX Full Duplex not supported Strap RW 100BASE TX Support 1 100BASE TX is supported by the local device 0 100BASE TX not supported Strap RW 10BASE T Full Duplex Support 1 10BASE T Full Duplex is supported by the local device 0 10BASE T Full Duplex not supported Strap RW 10BASE T Support 1 10BASE T is supported by the local device 0 10BASE T not supported lt 00001 gt RW Protocol Selection Bits These bits contain the binary encoded protocol selector supported by this port 00001 indicates that this device supports IEEE 802 3u gt Selector 45 www national com I8v8 8da 7 1 6 Auto Negotiation Link Partner Ability Register ANLPAR BASE This regis
20. RXD 1 RXD 2 RXD 3 S O PD 43 44 45 46 MII RECEIVE DATA Nibble wide receive data signals driven syn chronously to the RX_CLK 25 MHz for 100 Mb s mode 2 5 MHz for 10 Mb s mode RXD 3 0 signals contain valid data when RX DV is asserted RMII RECEIVE DATA 2 bits receive data signals RXD 1 0 driv en synchronously to the X1 clock 50 MHz SNI RECEIVE DATA Receive data signal RXD 0 driven syn chronously to the RX_CLK RXD 0 contains valid data when CRS is asserted RXD 3 1 are not used in this mode CRS CRS DV S O PU 40 MII CARRIER SENSE Asserted high to indicate the receive me dium is non idle RMII CARRIER SENSE RECEIVE DATA VALID This signal combines the RMII Carrier and Receive Data Valid indications For a detailed description of this signal see the RMII Specifica tion SNI CARRIER SENSE Asserted high to indicate the receive me dium is non idle It is used to frame valid receive data on the RXD 0 signal COL S O PU 42 MII COLLISION DETECT Asserted high to indicate detection of a collision condition simultaneous transmit and receive activity in 10 Mb s and 100 Mb s Half Duplex Modes While in 10BASE T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1us at the end of transmission to indicate heartbeat SQE test In Full Duplex Mode for 10 Mb s or 100 Mb s operation this sig nal is always logic 0 There is no h
21. Writes ignored Read as 0 ED_INT 0 RO COR Energy Detect interrupt 1 Energy detect interrupt is pending and is cleared by the current read 14 0 No energy detect interrupt pending 0 RO COR Change of Link Status interrupt 1 Change of link status interrupt is pending and is cleared by the current read LINK_INT 0 No change of link status interrupt pending 0 RO COR Change of speed status interrupt 1 Speed status change interrupt is pending and is cleared by the current read SPD INT 0 No speed status change interrupt pending 0 RO COR Change of duplex status interrupt 1 Duplex status change interrupt is pending and is cleared by the current read DUP INT 0 No duplex status change interrupt pending 0 RO COR Auto Negotiation Complete interrupt 1 Auto negotiation complete interrupt is pending and is cleared by the current read ANC INT 0 No Auto negotiation complete interrupt pending 0 RO COR False Carrier Counter half full interrupt 1 False carrier counter half full interrupt is pending and is cleared by the current read FHF INT 0 No false carrier counter half full interrupt pending 0 RO COR Receive Error Counter half full interrupt 1 Receive error counter half full interrupt is pending and is cleared by the current read INT 0 No receive error carrier counter half full interrupt pending RESERVED Writes ignored Read as 0 0 RW Enable In
22. and would be cleared on a read 0 RO COR Energy Detect Data Threshold Met The number of data events that occurred met or surpassed the En ergy Detect Data Threshold This bit is cleared on a read 0001 RW Energy Detect Error Threshold Threshold to determine the number of energy detect error events that should cause the device to take action Intended to allow aver aging of noise that may be on the line Counter will reset after ap proximately 2 seconds without any energy detect data events 0001 RW Energy Detect Data Threshold Threshold to determine the number of energy detect events that should cause the device to take actions Intended to allow averag ing of noise that may be on the line Counter will reset after approx imately 2 seconds without any energy detect data events ED ERR MET ED DATA MET 74 ED ERR COUNT 3 0 ED DATA COUNT 60 www national com 137858 8 0 Electrical Specifications Note All parameters are guaranteed by test statistical analysis or design Absolute Maximum Ratings Supply Voltage DC Input Voltage DC Output Voltage Storage Temperature 0 5 V to 4 2 V 0 5V to Voc 0 5V 0 5V to Voc 0 5V Max case temp for 85 C Max die temperature Tj Lead Temp TL Soldering 10 sec ESD Rating Rzap 1 5k Czap 100 pF 65 C to 150 C Recommended Operating Conditions 107 C 150 C 26
23. at address 04h via FLP Bursts Any combination of 10 Mb s 100 Mb s Half Duplex and Full Duplex modes may be selected Auto Negotiation Priority Resolution 1 100BASE TX Full Duplex Highest Priority 2 100BASE TX Half Duplex 3 10BASE T Full Duplex 4 10BASE T Half Duplex Lowest Priority The Basic Mode Control Register BMCR at address 00h provides control for enabling disabling and restarting the Auto Negotiation process When Auto Negotiation is dis abled the Speed Selection bit in the BMCR controls switching between 10 Mb s or 100 Mb s operation and the Duplex Mode bit controls switching between full duplex operation and half duplex operation The Speed Selection and Duplex Mode bits have no effect on the mode of oper ation when the Auto Negotiation Enable bit is set The Link Speed can be examined through the PHY Status Register PHYSTS at address 10h after a Link is achieved The Basic Mode Status Register BMSR indicates the set of available abilities for technology types Auto Negotiation ability and Extended Register Capability These bits are permanently set to indicate the full functionality of the 0 838481 only the 100BASE T4 bit is not set since the 0 838481 does not support that function The BMSR also provides status on Whether or not Auto Negotiation is complete Whether or not the Link Partner is advertising that a re mote fault has occurred Whet
24. at either 2 5 MHz or 25 MHz Additionally the MII includes the carrier sense signal CRS as well as a collision detect signal COL The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode The COL signal asserts as an indication of a collision which can occur during half duplex operation when both a transmit and receive operation occur simultaneously 3 1 2 Collision Detect For Half Duplex a 10BASE T or 100BASE TX collision is detected when the receive and transmit channels are active simultaneously Collisions are reported by the COL signal on the MII If the DP83848l is transmitting in 10 Mb s mode when collision is detected the collision is not reported until seven bits have been received while in the collision state This prevents a collision being reported incorrectly due to noise on the network The COL signal remains set for the dura tion of the collision If a collision occurs during a receive operation it is immedi ately reported by the COL signal When heartbeat is enabled only applicable to 10 Mb s operation approximately ips after the transmission of each packet a Signal Quality Error SQE signal of approx imately 10 bit times is generated internally to indicate successful transmission SQE is reported as a pulse on the COL signal of the 3 1 3 Carrier Sense Carrier Sense CRS is asserted due to receive activity once valid d
25. not prefixed by the code group pair J K If this condition is detected the DP83848I will assert RX ER and present RXD 3 0 1110 to the for the cycles that correspond to received 5B code groups until at least two IDLE code groups are detected In addition the False Carrier Sense Counter register FCSCR will be incremented by one Once at least two IDLE code groups are detected RX ER and CRS become de asserted 4 3 10BASE T TRANSCEIVER MODULE The 10BASE T Transceiver Module is IEEE 802 3 compli ant It includes the receiver transmitter collision heart beat loopback jabber and link integrity functions as defined in the standard An external filter is not required on the 10BASE T interface since this is integrated inside the DP83848l This section focuses on the general 10BASE T System level operation 4 3 1 Operational Modes The DP83848l has two basic 10BASE T operational modes Half Duplex mode Full Duplex mode Half Duplex Mode In Half Duplex mode the DP83848l functions as a standard IEEE 802 3 10BASE T transceiver supporting the CSMA CD protocol Full Duplex Mode In Full Duplex mode the DP83848l is capable of simulta neously transmitting and receiving without asserting the collision signal The DP83848l s 10 Mb s ENDEC is designed to encode and decode simultaneously 30 www national com I8v8e 8da 4 3 2 Smart Squelch The smart squelch is responsible for determining whe
26. ns in 100 Mb s mode 66 www national com I8v8 8da 8 2 7 100 Transmit Packet Deassertion Timing TX_CLK EX TX EN EE 42724222 TXD T2 7 1 PMD Output Pair DATA T R IDLE Parameter Description Notes Min Typ Units T2 7 1 TX CLK to PMD Output Pair 100 Mb s Normal mode 6 bits Deassertion Note Deassertion is determined by measuring the time from the first rising edge of TX CLK occurring after the deasser tion of TX EN to the first bit of the T code group as output from the PMD Output Pair 1 bit time 10 ns in 100 Mb s mode 67 www national com I8v8 8da 8 2 8 100BASE TX Transmit Timing amp Jitter T2 8 1 1 rise gt 90 10 PMD Output Pair Se 10 1 fall T2 8 1 90 1 fall 4 rise T2 8 1 T2 8 1 gt PMD Output Pair Parameter Description Notes Min Typ Units T2 8 1 100 Mb s PMD Output Pair ta 3 4 5 ns and te 100 Mb s and te Mismatch 500 ps T2 8 2 100 Mb s PMD Output Pair 1 4 ns Transmit Jitter Note Normal Mismatch is the difference between the maximum and minimum of all rise and fall times Note Rise and fall times taken at 10 and 90 of the 1 or 1 amplitude 68 www national com I8v8 8da 8 2 9 100BASE TX Receiv
27. oscilloscope plot provided in Figure 9 illustrates the severity of the BLW event that can theoretically be gen erated during 100BASE TX packet transmission This event consists of approximately 800 mV of DC offset for a period of 120 us Left uncompensated events such as this can cause packet loss 4 2 3 Signal Detect The signal detect function of the DP83848l is incorporated to meet the specifications mandated by the ANSI FDDI TP PMD Standard as well as the IEEE 802 3 100BASE TX Standard for both voltage thresholds and timing parame ters Note that the reception of normal 10BASE T link pulses and fast link pulses per IEEE 802 3u Auto Negotiation by the 100BASE TX receiver do not cause the DP83848l to assert signal detect 4 2 4 MLT 3 to NRZI Decoder The DP83848l decodes the MLT 3 information from the Digital Adaptive Equalizer block to binary NRZI data 4 2 5 NRZI to NRZ In a typical application the NRZI to NRZ decoder is required in order to present NRZ formatted data to the descrambler 4 2 6 Serial to Parallel The 100BASE TX receiver includes a Serial to Parallel converter which supplies 5 bit wide data symbols to the PCS Rx state machine 29 www national com I8v8e 8da 4 2 7 Descrambler A serial descrambler is used to de scramble the received NRZ data The descrambler has to generate an identical data scrambling sequence N in order to recover the origi nal unscrambled data UD from the s
28. unaligned 5 bit data from the descrambler or if the descrambler is bypassed directly from the NRZI NRZ decoder and con verts it into 5B code group data 5 bits Code group align ment occurs after the J K code group pair is detected Once the J K code group pair 11000 10001 is detected subsequent data is aligned on a fixed boundary 4 2 9 4B 5B Decoder The code group decoder functions as a look up table that translates incoming 5B code groups into 4B nibbles The code group decoder first detects the J K code group pair preceded by IDLE code groups and replaces the J K with MAC preamble Specifically the J K 10 bit code group pair is replaced by the nibble pair 0101 0101 All subsequent 5B code groups are converted to the corresponding 4B nibbles for the duration of the entire packet This conver sion ceases upon the detection of the T R code group pair denoting the End of Stream Delimiter ESD or with the reception of a minimum of two IDLE code groups 4 2 10 100BASE TX Link Integrity Monitor The 100 Base TX Link monitor ensures that a valid and sta ble link is established before enabling both the Transmit and Receive PCS layer Signal detect must be valid for 395us to allow the link mon itor to enter the Link Up state and enable the transmit and receive functions 4 2 11 Bad SSD Detection A Bad Start of Stream Delimiter Bad SSD is any transition from consecutive idle code groups to non idle code groups which is
29. will be selected based on the advertised ability of the Link Partner The Auto Negotiation function within the DP83848l can be controlled either by internal register access or by the use of the AN_EN AN1 and ANO pins 2 1 1 Auto Negotiation Pin Control The state of AN EN ANO and AN1 determines whether the DP83848l is forced into a specific mode or Auto Negotia tion will advertise a specific ability or set of abilities as given in Table 1 These pins allow configuration options to be selected without requiring internal register access The state of AN EN ANO and AN1 upon power up reset determines the state of bits 8 5 of the ANAR register The Auto Negotiation function selected at power up or reset can be changed at any time by writing to the Basic Mode Control Register BMCR at address OxOOh Table 1 Auto Negotiation Modes ANEN Aw ANO o o OBASET o r 169587 Hat upon r Fur Duplex __ AN EN ANT ANO Advertised Mode 0 Halffrul Duplex 1 0 1 I008ASETX HatfiFul Duptex 1 1 10BASE T Half Duplex esse raros _ 1 1 1 Half Full Duplex Prise hats 2 1 2 Auto Negotiation Register Control When Auto Negotiation is enabled the DP83848l transmits the abilities programmed into the Auto Negotiation Adver tisement register ANAR
30. 0 C 4 0 kV Supply voltage Vcc Power Dissipation Pp Industrial Ambient Temperature TA 3 3 Volts 3V 40 to 85 C 267 mW Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the device should be operated at these limits Thermal Characteristic Max Units Theta Junction to Case T 28 7 C W Theta Junction to Ambient Tja degrees Celsius Watt No Airflow 1 0W 83 6 C W Note This is done with a JEDEC 2 layer 2 oz CU thermal test board 8 1 DC Specs Symbol Pin Types Parameter Conditions Min Typ Max Units Vin Input High Voltage Nominal Vcc 2 0 V l Input Low Voltage 0 8 V Input High Current 10 l Input Low Current ViN GND 10 uA VoL O Output Low lo 4 mA 0 4 Voltage Output High lon 4 mA 0 5 V y o Voltage loz TRI STATE Vour 10 Leakage Vtptp 100 PMD Output 100M Transmit 0 95 1 1 05 V Voltage PMD Output 100M Transmit 2 Pair Voltage Symmetry 10 PMD Output 10M Transmit 2 2 2 5 2 8 V d Pair Voltage CMOS Input 5 pF Capacitance CMOS Output 5 pF Capacitance 61 www national com 137858 8 1 DC Specs Continued Sy
31. 00 Mb s Internal Loopback Timing 76 8 2 25 10 Mb s Internal Loopback Timing 77 8 2 26 Transmit Timing 1 4 4 78 8 2 27 Receive Timing 79 8 2 28 Isolation Timing pete Bde Pu e qr px qr et vr Rer 80 8 229 25 MHz OUT Ips iqu hipaka h php ERI 80 9 0 Physical Dimensions 81 5 www national com I8v8e8da List of Figures Figure 1 DP83848l Functional Block 2 Figure 2 PHYAD Strapping Example 18 Figure 3 AN Strapping and LED Loading 19 Figure 4 Typical MDC MDIO Read Operation 23 Figure 5 Typical MDC MDIO Write Operation 23 Figure 6 100 Transmit Block Diagram 24 Figure 7 100BASE TX Receive Block Diagram 27 Figure 8 EIA TIA Attenuation vs Frequency for 0 50 100 130 amp 150 meters of CAT 5 cable 28 Figure 9 100BASE TX BLEW Event gt oie a
32. 02 3u PCS 100BASE TX transceivers and filters IEEE specification 1149 1 for ease of manufacturing IEEE 1149 1 JTAG Additionally both MII and RMII are supported ensuring Integrated ANSI X3 263 compliant TP PMD physical sub ease and flexibility of design layer with adaptive equalization and Baseline Wander com The DP83848l features integrated sublayers to sup pensation port both 10BASE T and 100BASE TX Ethernet proto Operation up to 150 meters cols which ensures compatibility and interoperability 2 3 with all other standards based Ethernet solutions Programmable LED support Link 10 100 Mb s Mode Activ ity and Collision Detect The 838481 is offered a small form factor 48 pin LQFP so that a minimum of board space is needed Single register access for complete PHY status 10 100 Mb s packet BIST Built in Self Test Applications e 48 pin LQFP package 7mm x 7mm High End Peripheral Devices Industrial Controls and Factory Automation General Embedded Applications System Diagram 10BASE T gt or 100BASE TX DP83848l MII RMII SNI RJ 45 MPU CPU 10 100 Mb s Magnetics Media Access Controller Clock Status Source LEDs Typical Application PHYTER is a registered trademark of National Semiconductor 2007 National Semiconductor Corporation www national com Jo e 5 19449433 S qIN 001 01 Mog lBu S
33. 2 8 bits 6 bits 7200 bytes 3600 bytes 3 12 bits 10 bits 12000 bytes 6000 bytes 0 16 bits 14 bits 16800 bytes 8400 bytes 3 3 10 Mb Serial Network Interface SNI The DP83848l incorporates 10 Mb Serial Network Inter face SNI which allows a simple serial data interface for 10 Mb only devices This is also referred to as a 7 wire inter face While there is no defined standard for this interface it is based on early 10 Mb physical layer devices Data is clocked serially at 10 MHz using separate transmit and receive paths The following pins are used in SNI mode TX_CLK TX_EN RX_CLK RXD 0 CRS COL 3 4 802 3u MII Serial Management Interface 3 4 1 Serial Management Register Access The serial management MII specification defines a set of thirty two 16 bit status and control registers that are acces sible through the management interface pins MDC and The DP83848l implements all the required MII reg isters as well as several optional registers These registers are fully described in Section 7 0 A description of the serial management access protocol follows 3 4 2 Serial Management Access Protocol The serial control interface consists of two pins Manage ment Data Clock MDC and Management Data Input Out put MDIO MDC has a maximum clock rate of 25 MHz and no minimum rate The MDIO line is bi directional and may be shared by up to 32 devices The MDIO frame for
34. 2 7 100BASE TX Transmit Packet Deassertion 0 67 8 2 8 100BASE TX Transmit Timing tR F 68 8 2 9 100BASE TX Receive Packet Latency Timing 69 8 2 10 100BASE TX Receive Packet Deassertion Timing 69 8 2 11 10 Mb s Transmit Timing 0 70 8 2 12 10 Mb s MII Receive Timing 4 70 8 2 13 10 Mb s Serial Mode Transmit Timing 71 8 2 14 10 Mb s Serial Mode Receive Timing 71 8 2 15 10BASE T Transmit Timing Start of Packet 72 8 2 16 10BASE T Transmit Timing End of Packet 72 8 2 17 10BASE T Receive Timing Start of Packet 73 8 2 18 10BASE T Receive Timing End of Packet 73 8 2 19 10 Mb s Heartbeat Timing 74 8 2 20 10 Mb s Jabber TIMING oer dee uev RE ee ESOS 74 8 2 21 10BASE T Normal Link Pulse Timing 1 75 8 2 22 Auto Negotiation Fast Link Pulse FLP Timing 75 8 2 23 100BASE TX Signal Detect Timing 76 8 2 24 1
35. 2 and 10BASE5 implementations which used a shared medium Setting this bit disables the loopback function This bit does not affect loopback due to setting BMCR 14 57 www national com 137858 Table 30 10Base T Status Control Register 10BTSCR address 0x1A 7 LP_DIS 0 RW Normal Link Pulse Disable 1 Transmission of NLPs is disabled 0 Transmission of NLPs is enabled FORCE_LINK_10 0 RW Force 10Mb Good Link 1 Forced Good 10Mb Link 0 Normal Link Status RESERVED 0 RW RESERVED Must be zero POLARITY RO LH 10Mb Polarity Status This bit is a duplication of bit 12 in the PHYSTS register Both bits will be cleared upon a read of 10BTSCR register but not upon a read of the PHYSTS register 1 Inverted Polarity detected 0 Correct Polarity detected RESERVED 0 RW RESERVED Ned Must be zero RESERVED 1 RW RESERVED pues Must be set to one HEARTBEAT DIS 0 RW Heartbeat Disable This bit only has influence in half duplex 10Mb mode 1 Heartbeat function disabled 0 Heartbeat function enabled When the device is operating at 100Mb or configured for full duplex operation this bit will be ignored the heartbeat func tion is disabled JABBER DIS 0 RW Jabber Disable Applicable only in 10BASE T 1 Jabber function disabled 0 Jabber function enabled 58 www national com 7 2 11 CD Test and BIST Extensions Register CDCTRL1 Table 31 CD Test and BIST Extensi
36. D CNFG 0 Mode Description Don t care 1 Mode 1 0 0 Mode 2 1 0 Mode 3 In Mode 1 LEDs are configured as follows LED LINK ON for Good Link OFF for No Link LED SPEED ON in 100 Mb s OFF in 10 Mb s LED ACT COL ON for Activity OFF for No Activity In Mode 2 LEDs are configured as follows LED LINK ON for good Link BLINK for Activity LED SPEED ON in 100 Mb s OFF in 10 Mb s LED ACT COL ON for Collision OFF for No Collision Full Duplex OFF for Half Duplex In Mode 3 LEDs are configured as follows LED LINK ON for Good Link BLINK for Activity LED SPEED ON in 100 Mb s OFF in 10 Mb s LED ACT COL ON for Full Duplex OFF for Half Duplex PHYADDR 4 0 Strap RW PHY Address PHY address for port 7 2 10 10Base T Status Control Register 10BTSCR Table 30 10Base T Status Control Register 10BTSCR address 0x1A 15 10BT SERIAL Strap RW 10Base T Serial Mode SNI 1 Enables 10Base T Serial Mode 0 Normal Operation Places 10 Mb s transmit and receive functions in Serial Network Interface SNI Mode of operation Has no effect on 100 Mb s operation 14 12 RESERVED RESERVED SQUELCH 100 RW Squelch Configuration Used to set the Squelch ON threshold for the receiver Default Squelch ON is 330mV peak LOOPBACK_10_D In half duplex mode default 10BASE T operation loops Transmit IS data to the Receive data in addition to transmitting the data on the physical medium This is for consistency with earlier 1OBASE
37. Down state 5 5 2 Interrupt Mechanisms The interrupt function is controlled via register access All interrupt sources are disabled by default Setting bit 1 INTEN of MICR 0x11h will enable interrupts to be out put dependent on the interrupt mask set in the lower byte of the MISR 0x12h The PWR DOWN INT pin is asyn chronously asserted low when an interrupt condition occurs The source of the interrupt can be determined by reading the upper byte of the MISR One or more bits in the MISR will be set denoting all currently pending interrupts Reading of the MISR clears ALL pending interrupts Example To generate an interrupt on a change of link sta tus or on a change of energy detect power state the steps would be Write 0003h to MICR to set INTEN and INT OE Write 0060h to MISR to set ED INT EN and LINK INT EN Monitor PWR DOWN INT pin When PWR DOWN INT pin asserts low user would read the MISR register to see if the ED INT or LINK INT bits are set i e which source caused the interrupt After read ing the MISR the interrupt bits should clear and the PWR DOWN INT pin will deassert 5 6 Energy Detect Mode When Energy Detect is enabled and there is no activity on the cable the DP83848l will remain in a low power mode while monitoring the transmission line Activity on the line will cause the DP83848l to go through a normal power up sequence Regardless of cable activity the DP83848I will occasionally wak
38. GAGNALXA ponies 5 pin Qe eon is jou pna id penes pin 2 H H 10 80 Q3AH3sau pewes al 38090 3000 2xov SOW H HLdNNV u XL 1xeN uonenoDeN oiny 318V XY 318V oar sere 22 ien n us 5 pg n Nvdi 39Vd H3NV uoisuedx3 uonenoDeN oiny 1X9N epoo e660 soy NY uso 8 Jeuueg uonenoDeN oiny uono l s uonoejeg uono l s uonoejes u pewes pul eseg 191 1090014 1090 01d 090 014 QJ 0L Qd vL 3snvd Id Wsv eu xov uso 8 Jeuueg yur uonenoDeN oiny uonoejes uonoejes uonoejes uono l s uonoejes ponies ney 0204044 10201014 10201014 1090 01d Qd 01 Qd vl 3snvd Id eu H HVNV upo _ JuswesieApy 4 YANA HO
39. N Data Hold from TX rise 10 Mb s MII mode 0 ns Note An attached Mac should drive the transmit signals using the positive edge of TX_CLK As shown above the signals are 8 2 12 10M RX_CLK ampled on the falling edge of TX_CLK b s Receive Timing RXD 3 0 RX DV Valid Data Parameter Description Notes Min Typ Max Units T2 12 1 RX CLK High Low Time 160 200 240 ns T2 12 2 RX CLK to RXD 3 0 RX_DV Delay 10 Mb s MII mode 100 ns T2 12 3 RX CLK rising edge delay from RXD 3 0 10 Mb s MII mode 100 ns RX DV Valid Note RX CLK may be held low for a longer period of time during transition between reference and recovered clocks Minimum high and low times will not be violated 70 www national com 8 2 13 10 Mb s Serial Mode Transmit Timing TX_CLK TXD 0 TX_EN Valid Data Parameter Description Notes Min Typ Max Units T2 13 1 TX CLK High Time 10 Mb s Serial mode 20 25 30 ns T2 13 2 TX CLK Low Time 10 Mb s Serial mode 70 75 80 ns T2 13 3 TXD 0 TX EN Data Setup to TX CLK rise 10 Mb s Serial mode 25 ns 2 13 4 TXD O0 TX EN Data Hold from TX_CLK rise 10 Mb s Serial mode 0 ns 8 2 14 10 Mb s Serial Mode Receive Timing RX CLK RXD 0 X X RX DV Valid Data Parameter Description Notes Min Typ Units T2 14 1 RX CLK Hi
40. NA ES YONA YONA 8S110O 881100 881100 881100 881100 8S110O ug JeisiDeu ASW INO gsN INO ASW INO ASW INO AS INO SW INO aS INO ASW INO SW INO 8S INO GSW INO BSW INO GSW INO GSW m 4e1siDeg d edeg pa snes yne panes pans panies XL XL tl puex3 yun ony es ao s g01 sego0 52800 52800 SNIS seg ejgeu3 panes jog 7 5 s oiny 5 H 5 J MOd ony peeds doo7 yesey uo Jejsibeu O4JUOD 21529 eiqer 518680 LE eger www national com 38 oe rs ir or jos goa geo por d H Q3AH3sadu Noo V Noor V Nios 1 INNOD 1 INNOD LAW V 13N 1 16 E SIG 1 Moa O ano 1va aa aa aa uua aa qa3 NvW JeisiDeg 19e1eq penes penes pewes pewes penes penes penes pewes pewes p m s penes
41. Negotiate or parallel detect to a specific technology depending on the receive signal at the PMD input pair A valid link can be established for the receiver even when the DP83848l is in Isolate mode COL PHYAD4 0 PHYADS 0 PHYAD2 e a gt lt cc 0 PHYAD1 1 PHYADO 1 Figure 2 PHYAD Strapping Example 18 www national com I8v8e8da 2 4 LED Interface The DP83848l supports three configurable Light Emitting Diode LED pins The device supports three LED configu rations Link Speed Activity and Collision Function are multiplexed among the LEDs The PHY Control Register PHYCR for the LEDs can also be selected through address 19h bits 6 5 See Table 3 for LED Mode selection Table 3 LED Mode Select Mode LED_CFG 1 LED CFG 0 LED LINK LED SPEED LED ACT COL bit 6 bit 5 or pin40 1 don t care 1 ON for Good Link ON in 100 Mb s for Activity OFF for No Link OFF in 10 Mb s OFF for No Activity 2 0 0 ON for Good Link ON in 100 Mb s for Collision BLINK for Activity OFF in 10 Mb s OFF for No Collision 3 1 0 ON for Good Link ON in 100 Mb s ON for Full Duplex BLINK for Activity OFF in 10 Mb s OFF for Half Duplex The LED LINK pin in Mode 1 indicates the link status of the port In 100BASE T mode link is established as a result of input receive amplitude compliant with the TP PMD specifications which will result in internal gene
42. R Figure 5 Typical MDC MDIO Write Operation 3 4 3 Serial Management Preamble Suppression The DP83848l supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Regis ter BMSR address 01h If the station management entity i e MAC or other management controller determines that all PHYs in the system support Preamble Suppression by returning a one in this bit then the station management entity need not generate preamble for each management transaction The DP83848l requires a single initialization sequence of 32 bits of preamble following hardware software reset This requirement is generally met by the mandatory pull up resistor on MDIO in conjunction with a continuous MDC or the management access made to determine whether Pre amble Suppression is supported While the DP83848l requires an initial preamble sequence of 32 bits for management initialization it does not require a full 32 bit sequence between each subsequent transac tion A minimum of one idle bit between management transactions is required as specified in the IEEE 802 3u specification 23 www national com I8v8 8da 4 0 Architecture This section describes the operations within each trans ceiver module 100BASE TX and 10BASE T Each opera tion consists of several functional blocks and described in the following 100BASE TX Transmitter 100BASE TX Receiver 10BASE T Transceiver Module
43. R P EHE 31 4 3 5 Normal Link Pulse Detection Generation 31 4 3 6 Jabber Function ch rer bd ee Renee Rest A Red E 32 4 3 7 Automatic Link Polarity Detection and Correction 32 4 3 8 Transmit and Receive Filtering 32 4 3 9 x ues can is We We gee eee pa tie er a bee 32 43 10 FRGCOIVOE oe ae ele eoe eae he ae URS 32 5 0 Design Guidelines 2 sse Eu eas na ee ee 33 5 1 TPI Network iei REY REC dee he Rx ee a eee GTS 33 5 2 ESD Protection zs er to disent ib Det be Sa tne Pea trae 34 5 3 Clock In X1 Requirements 34 5 4 Power Feedback Circuit 35 5 5 Power Down Interr pt oie x d RR RE a ee acs e RR a 35 5 5 1 Power Down Control Mode 35 5 5 2 Interrupt Mechanisms REIR REMO ERE Re E e ete es Roe a Roe qs h 35 5 6 Energy Detect 35 6 0 Reset Operation essee ei Tk e alae E ioe e a 36 6 h Hardware aa Pb wa 36 6 2 Software 36 7 0 Register Blo
44. RVED RESERVED 54 www national com 137858 7 2 7 RMII and Bypass Register RBR This register configures the RMII Mode of operation When mode is disabled the RMII functionality is bypassed Table 27 RMII and Bypass Register RBR addresses 0x17 Description RESERVED Writes ignored read as 0 Strap RW Reduced Mode 0 Standard Mode 1 Reduced MII Mode REV1 0 Reduce MII Revision 1 0 0 revision 1 2 CRS will toggle at the end of a packet to indicate deassertion of CRS 1 RMII revision 1 0 CRS_DV will remain asserted until final data is transferred CRS DV will not toggle at the end of a packet RX FIFO Over Flow Status 0 Normal Bit Name RESERVED RMII MODE RX OVF STS 1 Overflow detected RX FIFO Under Flow Status 0 Normal RX UNF STS 1 Underflow detected ELAST_BUF 1 0 Receive Elasticity Buffer This field controls the Receive Elastic ity Buffer which allows for frequency variation tolerance between the 50MHz clock and the recovered data The following val ues indicate the tolerance in bits for a single packet The minimum setting allows for standard Ethernet frame sizes at 50 accu racy for both and Receive clocks For greater frequency tol erance the packet lengths may be scaled i e for 100ppm the packet lengths need to be divided by 2 00 14 bit tolerance up to 16800 byte packets 01 2 bit tolerance u
45. SSVdA8 8 pewes 001 E 39 as pones WvHOS IZHN 3ouo4 17 as uod ds OL e snes Jefe 1 qns 94 LINO INO LINO INO INO INO INO INO jen ge 5 pud 2 43X84 Em ug 1ejsiDeu Jejunoo pus ic De ponas is E pss pansies 140899 LNOSO4 LNOSOH LNOSOS INOSO4 LNOSO4 130899 LNOSOJ uosod 1 su s espe penes jns ju P ius ponas xe penes pewes penes penes peues Q3AHasau _ 3HH ONV ave 2 ED 1 l S panes 19161 XSIAND SN YSWNN E 3i ANI NI ONV NI NI aas NI NIT LNI uz OSIN pue snes E P 52 E ps ed xcd Pen D Pen panas 1 LNIL HOIIN JejsiDeg Ionuoo JN sni 1901 esueg snigls snieis 1115 eis joejeg jne4 wes joejeg Jeu sniels uoje1 ponies peedg doo1 IN yeubig u3xu SLSAHd uot JejsiDeg SNIS SYALSIDAY
46. ST I PU 11 TEST RESET Active low asynchronous test reset This pin has a weak internal pullup 1 6 Reset and Power Down Signal Name Type Pin Description RESET_N PU 29 RESET Active Low input that initializes or re initializes the DP83848l Asserting this pin low for at least 1 us will force a reset process to occur All internal registers will re initialize to their de fault states as specified for each bit in the Register Block section All strap options are re initialized as well PWR_DOWN INT OD PU 7 See Section 5 5 for detailed description The default function of this pin is POWER DOWN POWER DOWN The pin is an active low input in this mode and should be asserted low to put the device in a Power Down mode INTERRUPT The pin is an open drain output in this mode and will be asserted low when an interrupt condition occurs Although the pin has a weak internal pull up some applications may require an external pull up resister Register access is required for the pin to be used as an interrupt mechanism See Section 5 5 2 Interrupt Mechanism for more details on the interrupt mechanisms 1 7 Strap Options The 0 838481 uses many of the functional pins as strap 2 2 resistor should be used for pull down or pull up to options The values of these pins are sampled during reset change the default strap option If the default option is and used to strap the device into specific modes of opera r
47. Setting this bit may cause the descrambler to lose synchronization and produce a 500 us dead time before any valid data will appear at the receive outputs Speed Select When auto negotiation is disabled writing to this bit allows the port speed to be selected 1 100 Mb s 0 10 Mb s Auto Negotiation Enable Strap controls initial value at reset 1 Auto Negotiation Enabled bits 8 and 13 of this register are ig nored when this bit is set 0 Auto Negotiation Disabled bits 8 and 13 determine the port speed and duplex mode Power Down 1 Power down 0 Normal operation Setting this bit powers down the PHY Only the register block is en abled during a power down condition This bit is OR d with the input from the PWR_DOWN INT pin When the active low PWR DOWN INT pin is asserted this bit will be set Isolate 1 Isolates the Port from the with the exception of the serial man agement 0 Normal operation Restart Auto Negotiation 1 Restart Auto Negotiation Re initiates the Auto Negotiation pro cess If Auto Negotiation is disabled bit 12 0 this bit is ignored This bit is self clearing and will return a value of 1 until Auto Negotiation is initiated whereupon it will self clear Operation of the Auto Negotiation process is not affected by the management entity clearing this bit 0 Normal operation Duplex Mode When auto negotiation is disabled writing to this bit allo
48. Table 24 Receiver Error Counter Register address 0 15 53 Table 25 100 Mb s PCS Configuration and Status Register PCSR address 0x16 54 Table 26 RMII and Bypass Register RBR addresses 0X17 55 Table 27 LED Direct Control Register LEDCR address 0X18 55 Table 28 PHY Control Register PHYCR address 0 19 56 Table 29 10Base T Status Control Register 10BTSCR address OX1A 57 Table 30 CD Test and BIST Extensions Register CDCTRL1 address 0 18 59 Table 31 Energy Detect Control EDCR address OX1D 60 7 www national com I8v8 8da Pin Layout z 5 o lt a 9 gt Zao o a a Oo lt 5 9 g Hn a a a O k Fosse tue N e e e N N N N N PFBIN2 37 24 RX CLK 38 23 RX DV MII MODE 39 22 CRS CRS DV LED CFG 40 24 RX ER MDIX EN 41 20 COL PHYADO 42 19 RXD_0 PHYAD1 43 0 838481 18 Fo RXD_1 PHYAD2 44 17 RXD_2 PHYAD3 45 16 5 RXD_3 PHYAD4 46 15 L3 IOGND 47 14 IOVDD33 48 13 O N N e o ZOrNW EX OD
49. Transmit Timing TX_CLK TXD 3 0 TX_EN Valid Data Parameter Description Notes Min Typ Max Units T2 4 1 TX CLK High Low Time 100 Mb s Normal mode 16 20 24 ns T2 4 2 TXD 3 0 TX EN Data Setup to TX CLK 100 Mb s Normal mode 10 ns 2 4 3 TXD 3 0 TX EN Data Hold TX CLK 100 Mb s Normal mode 0 ns 65 www national com I8v8 8da 8 2 5 100 Mb s Receive Timing RX_CLK RXD 3 0 RX DV X Valid Data 1 RX ER Description Notes Min Typ Max Units T2 5 1 RX CLK High Low Time 100 Mb s Normal mode 16 20 24 ns T2 5 2 RX CLK to RXD 3 0 RX DV RX ER Delay 100 Mb s Normal mode 10 30 ns Note RX CLK may be held low or high for a longer period of time during transition between reference and recovered clocks Minimum high and low times will not be violated 8 2 6 100BASE TX Transmit Packet Latency Timing TX CLK LAE SECRET TX EN TXD zo c qe x T2 6 1 gt PMD Output Pair IDLE DATA Parameter Description Notes Min Max Units 2 6 1 TX_CLK to PMD Output Pair 100 Mb s Normal mode 6 bits Latency Note For Normal mode latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX EN to the first bit of the J code group as output from the PMD Output Pair 1 bit time 10
50. a 7 2 Extended Registers 7 2 1 PHY Status Register PHYSTS This register provides a single location within the register set for quick access to commonly accessed information Table 21 PHY Status Register PHYSTS address 0x10 15 RESERVED 14 MDI X mode Description RESERVED Write ignored read as 0 MDI X mode as reported by the Auto Negotiation logic This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the PHYCR register When MDIX is en abled but not forced this bit will update dynamically as the Auto MDIX algorithm swaps between MDI and MDI X configu rations 1 MDI pairs swapped Receive on TPTD pair Transmit on TPRD pair 0 MDI pairs normal Receive on TRD pair Transmit on TPTD pair Receive Error Latch 0 RO LH Receive Error Latch This bit will be cleared upon a read of the RECR register 1 Receive error event has occurred since last read of RXERCNT address 0x15 Page 0 0 No receive error event has occurred Polarity Status Polarity Status This bit is a duplication of bit 4 in the 10BTSCR register This bit will be cleared upon a read of the 10BTSCR register but not upon a read of the PHYSTS register 1 Inverted Polarity detected 0 Correct Polarity detected False Carrier Sense 0 RO LH False Carrier Sense Latch Latch This bit will be cleared upon a read of the FCSR register 1 False Carrier event has occurred since last read of FCSCR ad dress 0x14 0
51. ameter Description Notes Min Typ Max Units T2 17 1 Carrier Sense Turn On Delay PMD 630 1000 ns Input Pair to CRS T2 17 2 RX_DV Latency 10 bits T2 17 3 Receive Data Latency Measurement shown from SFD 8 bits Note 10BASE T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV Note 1 bit time 100 ns in 10 Mb s mode 8 2 18 10BASE T Receive Timing End of Packet 1 0 1 IDLE PMD Input Pair lt REED CT GM CRS T2 18 1 Parameter Description Notes Min Typ Max Units T2 18 1 Carrier Sense Turn Off Delay 1 0 us 73 www national com I8v8 8da 8 2 19 10 Mb s Heartbeat Timing TX_EN TX_CLK 2 19 2 lt T2 19 1 COL Parameter Description Notes Min Typ Max Units T2 19 1 CD Heartbeat Delay All 10 Mb s modes 1200 ns T2 19 2 CD Heartbeat Duration All 10 Mb s modes 1000 ns 8 2 20 10 Mb s Jabber Timing TXE T2 20 1 gt PMD Output Pair T2 20 2 COL Parameter Description Notes Min Typ Max Units T2 20 1 Ja
52. ansmit Output pair These pins require 3 3V bias for operation 1 9 Special Connections Signal Name Type Pin Description RBIAS 24 Bias Resistor Connection 4 87 1 resistor should be con nected from RBIAS to GND PFBOUT 23 Power Feedback Output Parallel caps 10u Tantalum pre ferred and 0 1uF should be placed close to the PFBOUT Con nect this pin to PFBIN1 pin 18 and PFBIN2 pin 37 See Section 5 4 for proper placement pin PFBIN1 18 Power Feedback Input These pins are fed with power from PFBIN2 37 PFBOUT pin A small capacitor of 0 1uF should be connected close to each pin Note Do not supply power to these pins other than from PFBOUT RESERVED 20 21 RESERVED These pins must be pulled up through 2 2 resis tors to AVDD33 supply 1 10 Power Supply Pins Signal Name Pin Description IOVDD33 32 48 3 3V Supply IOGND 35 47 Ground DGND 36 Digital Ground AVDD33 22 Analog 3 3V Supply AGND 15 19 Analog Ground 14 www national com I8v8 8da 1 11 Package Pin Assignments VBH48A Pin Name 1 TX_CLK 2 TX_EN 3 TXD_0 4 TXD_1 5 TXD_2 6 TXD 3 SNI MODE 7 PWR DOWN INT 8 TCK 9 TDO 10 TMS 11 TRST 12 TDI 13 RD 14 RD 15 AGND 16 TD 17 TD 18 PFBIN1 19 AGND 20 RESERVED 21 RESERVED 22 AVDD33 23 PFBOUT 24 RBIAS 25 25MH
53. ap Since the pins include internal pull downs the default values are 0 The following table details the configurations MIL MODE SNI MODE MAC Interface Mode 0 X MII Mode 1 0 RMII Mode 1 1 10 Mb SNI Mode LED CFG CRS S O PU 40 LED CONFIGURATION This strapping option determines the mode of operation of the LED pins Default is Mode 1 Mode 1 and Mode 2 can be controlled via the strap option All modes are con figurable via register access SeeTable 3 for LED Mode Selection MDIX EN RX ER S O PU 41 MDIX ENABLE Default is to enable MDIX This strapping option disables Auto MDIX An external pull down will disable Auto MDIX mode 13 www national com I8v8 8da 1 8 10 Mb s and 100 Mb s PMD Interface Signal Name Type Pin Description TD TD 16 17 Differential common driver transmit output PMD Output Pair These differential outputs are automatically configured to either 10BASE T or 100BASE TX signaling In Auto MDIX mode of operation this pair can be used as the Re ceive Input pair These pins require 3 3V bias for operation RD RD 13 14 Differential receive input PMD Input Pair These differential in puts are automatically configured to accept either 100 or 10BASE T signaling In Auto MDIX mode of operation this pair can be used as the Tr
54. apacitance 25 40 pF 5 4 Power Feedback Circuit To ensure correct operation for the DP83848l parallel caps with values of 10 uF Tantalum and 0 1 uF should be placed close to pin 23 PFBOUT of the device Pin 18 PFBIN1 and pin 37 PFBIN2 must be connected to pin 23 PFBOUT each pin requires a small capacitor 1 uF See Figure 13 below for proper connections Pin 23 PFBOUT 1 Pin 18 PFBIN1 Pin 37 PFBIN2 1 uF Figure 13 Power Feeback Connection 5 5 Power Down Interrupt The Power Down and Interrupt functions are multiplexed on pin 7 of the device By default this pin functions as a power down input and the interrupt function is disabled Setting bit 0 INT OE of MICR 0x11h will configure the pin as an active low interrupt output 5 5 1 Power Down Control Mode The PWR DOWN INT pin can be asserted low to put the device in a Power Down mode This is equivalent to setting bit 11 Power Down in the Basic Mode Control Register BMCR 0x00h An external control signal can be used to drive the pin low overcoming the weak internal pull up resistor Alternatively the device can be configured to ini tialize into a Power Down state by use of an external pull down resistor on the PWR DOWN INT pin Since the device will still respond to management register accesses setting the INT OE bit in the MICR register will disable the PWR DOWN INT input allowing the device to exit the Power
55. ared by a read to this register by the management interface or by a reset Extended Capability 1 Extended register capabilities 0 Basic register set capabilities only 43 www national com I8v8 8da The PHY Identifier Registers 1 and 2 together form a unique identifier for the DP83848l The Identifier consists of a concatenation of the Organizationally Unique Identifier OUI the vendor s model number and the model revision num ber A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired The PHY Identifier is intended to support network management National s IEEE assigned OUI is 080017h 7 1 3 PHY Identifier Register 1 PHYIDR1 Table 14 PHY Identifier Register 1 PHYIDR1 address 0x02 OUI 0010 0000 0000 OUI Most Significant Bits Bits 3 to 18 of the OUI 080017h are 0000 RO P stored in bits 15 to O of this register The most significant two bits of the OUI are ignored the IEEE standard refers to these as bits 1 and 2 7 1 4 PHY Identifier Register 2 PHYIDR2 Table 15 PHY Identifier Register 2 PHYIDR2 address 0x03 OUI LSB 0101 11 gt RO P OUI Least Significant Bits Bits 19 to 24 of the OUI 080017h are mapped from bits 15 to 10 of this register respectively VNDR MDL 00 10012 RO P Vendor Model Number The six bits of vendor model number are mapped from bits 9 to 4 most significant bit to bit 9 MDL REV 0000 RO P Model Revision Number F
56. ata input output serial interface which may be asynchronous to transmit and receive clocks The maximum clock rate is 25 MHz with no minimum clock rate MDIO 30 MANAGEMENT DATA I O Bi directional management instruc tion data signal that may be sourced by the station management entity or the PHY This pin requires 1 5 pullup resistor 1 2 MAC Data Interface Signal Name Type Pin Description TX_CLK TRANSMIT CLOCK 25 MHz Transmit clock output in 100 Mb s mode or 2 5 MHz in 10 Mb s mode derived from the 25 MHz reference clock Unused mode The device uses the X1 reference clock in put as the 50 MHz reference for both transmit and receive SNI TRANSMIT CLOCK 10 MHz Transmit clock output in 10 Mb SNI mode The MAC should source TX EN and TXD 0 using this clock TX EN I PD TRANSMIT ENABLE Active high input indicates the pres ence of valid data inputs on TXD 3 0 RMII TRANSMIT ENABLE Active high input indicates the pres ence of valid data on TXD 1 0 SNI TRANSMIT ENABLE Active high input indicates the pres ence of valid data on TXD 0 TXD 0 TXD 1 TXD 2 TXD 3 PD TRANSMIT DATA Transmit data input pins TXD 3 0 that accept data synchronous to the TX_CLK 2 5 MHz in 10 Mb s mode or 25 MHz in 100 Mb s mode RMII TRANSMIT DATA Transmit data input pins 0 that accept data synch
57. ata is detected via the squelch function during 10 Mb s operation During 100 Mb s operation CRS is asserted when a valid link SD and two non contiguous zeros are detected on the line For 10 or 100 Mb s Half Duplex operation CRS is asserted during either packet transmission or reception For 10 or 100 Mb s Full Duplex operation CRS is asserted only due to receive activity CRS is deasserted following an end of packet 3 2 Reduced MII Interface The DP83848l incorporates the Reduced Media Indepen dent Interface RMII as specified in the RMII specification rev1 2 from the RMII Consortium This interface may be used to connect PHY devices to a MAC in 10 100 Mb s Systems using a reduced number of pins In this mode data is transferred 2 bits at a time using the 50 MHz RMII REF clock for both transmit and receive The follow ing pins are used in RMII mode TX EN TXD 1 0 RX ER optional for Mac CRS DV RXD 1 0 X1 RMII Reference clock is 50 MHz In addition the RMII mode supplies an RX DV signal which allows for a simpler method of recovering receive data without having to separate RX_DV from the CRS DV indication This is especially useful for systems which do not require CRS such as systems that only support full duplex operation This signal is also useful for diagnostic testing where it may be desirable to loop Receive RMII data directly to the transmitter Since the reference clock oper
58. ates at 10 times the data rate for 10 Mb s operation transmit data is sampled every 10 clocks Likewise receive data will be generated every 10th clock so that an attached device can sample the data every 10 clocks RMII mode requires a 50 MHz oscillator be connected to the device X1 pin A 50 MHz crystal is not supported 21 www national com I8v8e8da To tolerate potential frequency differences between the 50 MHz reference clock and the recovered receive clock the receive function includes a programmable elasticity buffer The elasticity buffer is programmable to minimize propagation delay based on expected packet size and clock accuracy This allows for supporting a range of packet sizes including jumbo frames The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the FIFO Underrun and Overrun conditions can be reported in the and Bypass Register RBR The following table indi cates how to program the elasticity buffer fifo in 4 bit incre ments based on expected max packet size and clock accuracy It assumes both clocks Reference clock and far end Transmitter clock have the same accuracy Table 4 Supported packet sizes at 50ppm 100ppm for each clock Start Threshold Latency Tolerance Recommended Packet Size Recommended Packet Size RBR 1 0 at 50ppm at 100 1 4 bits 2 bits 2400 bytes 1200 bytes
59. atly during normal operation based primarily on the random ness of the scrambled data stream This variation in signal attenuation caused by frequency variations must be com pensated to ensure the integrity of the transmission In order to ensure quality transmission when employing MLT 3 encoding the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment The selection of long cable lengths for a given implementation requires significant compensa tion which will over compensate for shorter less attenuat ing lengths Conversely the selection of short or intermediate cable lengths requiring less compensation will cause serious under compensation for longer length cables The compensation or equalization must be adap tive to ensure proper conditioning of the received signal independent of the cable length The DP83848l utilizes an extremely robust equalization scheme referred as Digital Adaptive Equalization The Digital Equalizer removes ISI inter symbol interfer ence from the receive data stream by continuously adapt ing to provide a filter with the inverse frequency response of the channel Equalization is combined with an adaptive gain control stage This enables the receive eye pattern to be opened sufficiently to allow very reliable data recovery The curves given in Figure 8 illustrate attenuation at certain frequencies for given cable lengths This is deri
60. bber Activation Time 85 ms T2 20 2 Jabber Deactivation Time 500 ms 74 www national com I8v8 8da 8 2 21 10BASE T Normal Link Pulse Timing T2 21 2 4 p 3 4 12 21 1 Normal Link Pulse s E Parameter Description Notes Min Typ Max Units T2 21 1 Pulse Width 100 ns T2 21 2 Pulse Period 16 ms Note These specifications represent transmit timings 8 2 22 Auto Negotiation Fast Link Pulse FLP Timing T2 22 2 gt T2 22 3 lt 22 T2 22 1 72221 gt 6 Fast Link Pulse s clock data clock 2 pulse pulse pulse T2 22 5 lt T2 22 4 lt FLP Burst FLP Burst Parameter Description Notes Min Typ Units T2 22 1 Clock Data Pulse Width 100 ns T2 22 2 Clock Pulse to Clock Pulse 125 us Period T2 22 3 Clock Pulse to Data Pulse Data 1 62 us Period T2 22 4 Burst Width ms T2 22 5 FLP Burst to FLP Burst Period 16 ms Note These specifications represent transmit timings 75 www national com I8r8 8da 8 2 23 100BASE TX Signal Detect Timing PMD Input Pair T2 23 1 lt T2 23 2 lt 0 internal Parameter Descr
61. bit 13 of this register then the code shall be interpreted as a Message as defined in annex 28C of Clause 28 Otherwise the code shall be interpreted as an Unfor matted Page and the interpretation is application specific 7 1 8 Auto Negotiate Expansion Register ANER This register contains additional Local Device and Link Partner status information Table 19 Auto Negotiate Expansion Register ANER address 0x06 Bit Name Defaut Description RESERVED RESERVED Writes ignored Read as 0 PDF Parallel Detection Fault 1 A fault has been detected via the Parallel Detection function 0 fault has not been detected LP_NP_ABLE Link Partner Next Page Able 1 Link Partner does support Next Page 0 Link Partner does not support Next Page NP_ABLE 1 RO P Next Page Able 1 Indicates local device is able to send additional Next Pages PAGE_RX 0 RO COR Link Code Word Page Received 1 Link Code Word has been received cleared on a read 0 Link Code Word has not been received 47 www national com 137858 Table 19 Auto Negotiate Expansion Register address 0x06 Continued LP_AN_ABLE Link Partner Auto Negotiation Able 1 indicates that the Link Partner supports Auto Negotiation 0 indicates that the Link Partner does not support Auto Negotia tion 7 1 9 Auto Negotiation Next Page Transmit Register ANNPTR This register contains the next page information sent
62. by this device to its Link Partner during Auto Negotiation Table 20 Auto Negotiation Next Page Transmit Register ANNPTR address 0x07 Description Next Page Indication 0 No other Next Page Transfer desired 1 Another Next Page desired RESERVED Writes ignored read as 0 Message Page 1 Message Page 0 Unformatted Page EE A Acknowledge2 1 2 Will comply with message 0 Cannot comply with message Acknowledgez is used by the next page function to indicate that Lo cal Device has the ability to comply with the message received Toggle 1 Value of toggle bit in previously transmitted Link Code Word was 0 0 Value of toggle bit in previously transmitted Link Code Word was 1 Toggle is used by the Arbitration function within Auto Negotiation to ensure synchronization with the Link Partner during Next Page exchange This bit shall always take the opposite value of the Tog gle bit in the previously exchanged Link Code Word 000 er 0001 This field represents the code field of the next page transmission If the MP bit is set bit 13 of this register then the code shall be interpreted as a Message as defined in annex 28C of IEEE 802 3u Otherwise the code shall be interpreted as an Unformat ted and the interpretation is application specific The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802 3u 48 www national com I8v8 8d
63. ck asc Sai cron rr EUR YR dos ru clos 37 7 1 Register Detinilion scies oe ath kicha irae gus 40 7 1 1 Basic Mode Control Register BMCR 41 7 1 2 Basic Mode Status Register 43 7 1 3 PHY Identifier Register 1 1 1 44 7 1 4 PHY Identifier Register 2 1 2 44 7 1 5 Auto Negotiation Advertisement Register 44 7 1 6 Auto Negotiation Link Partner Ability Register ANLPAR 46 7 1 7 Auto Negotiation Link Partner Ability Register ANLPAR Next Page 47 7 1 8 Auto Negotiate Expansion Register 47 7 1 9 Auto Negotiation Next Page Transmit Register 48 7 2 Extended Registers 49 7 2 1 PHY Status Register PHYSTS 49 7 2 2 Interrupt Control Register MICR 1 51 7 2 3 Interrupt Status and Misc Control Register 52 7 2 4 False Carrier Sense Counter Register 53 7 2 5 Receiver Error Counter Register
64. crambled data SD as represented in the equations SD UD N UD 50 Synchronization of the descrambler to the original scram bling sequence N is achieved based on the knowledge that the incoming scrambled data stream consists of scrambled IDLE data After the descrambler has recog nized 12 consecutive IDLE code groups where an unscrambled IDLE code group in 5B NRZ is equal to five consecutive ones 11111 it will synchronize to the receive data stream and generate unscrambled data in the form of unaligned 5B code groups In order to maintain synchronization the descrambler must continuously monitor the validity of the unscrambled data that it generates To ensure this a line state monitor and a hold timer are used to constantly monitor the synchroniza tion status Upon synchronization of the descrambler the hold timer starts a 722 us countdown Upon detection of sufficient IDLE code groups 58 bit times within the 722 us period the hold timer will reset and begin a new count down This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity If the line state monitor does not recognize sufficient unscrambled IDLE code groups within the 722 us period the entire descrambler will be forced out of the cur rent state of synchronization and reset in order to re acquire synchronization 4 2 8 Code group Alignment The code group alignment module operates on
65. d twisted pair cable 4 1 3 Binary to MLT 3 Convertor The Binary to MLT 3 conversion is accomplished by con verting the serial binary data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events These two binary streams are then fed to the twisted pair output driver which converts the voltage to current and alternately drives either side of the transmit transformer primary winding resulting in a MLT 3 signal The 100BASE TX MLT 3 signal sourced by the PMD Out put Pair common driver is slew rate controlled This should be considered when selecting AC coupling magnetics to ensure TP PMD Standard compliant transition times 3 ns Tr 5 ns The 100BASE TX transmit TP PMD function within the 0 838481 is capable of sourcing only MLT 3 encoded data Binary output from the PMD Output Pair is not possible in 100 Mb s mode 4 2 100BASE TX RECEIVER The 100BASE TX receiver consists of several functional blocks which convert the scrambled MLT 3 125 Mb s serial data stream to synchronous 4 bit nibble data that is pro vided to the MII Because the 100BASE TX TP PMD is integrated the differential input pins RD can be directly routed from the AC coupling magnetics See Figure 7 for a block diagram of the 100BASE TX receive function This provides an overview of each func tional block within the 100BASE TX receive section The Receive section consists of the following functional bloc
66. da 7 0 Register Block Table 10 Register Map Access Tag Description Hex Decimal 00h 0 RW BMCR Basic Mode Control Register 01h 1 RO BMSR Basic Mode Status Register 02h 2 RO PHYIDR1 PHY Identifier Register 1 03h 3 RO PHYIDR2 PHY Identifier Register 2 04h 4 RW ANAR Auto Negotiation Advertisement Register 05h 5 RW ANLPAR Auto Negotiation Link Partner Ability Register Base Page 05h 5 RW ANLPARNP Auto Negotiation Link Partner Ability Register Next Page 06h 6 RW ANER Auto Negotiation Expansion Register 07h 7 RW ANNPTR Auto Negotiation Next Page TX 08h Fh 8 15 RW RESERVED RESERVED Extended Registers 10h 16 RO PHYSTS PHY Status Register 11h 17 RW MICR MII Interrupt Control Register 12h 18 RO MISR MII Interrupt Status Register 13h 19 RW RESERVED RESERVED 14h 20 RO FCSCR False Carrier Sense Counter Register 15h 21 RO RECR Receive Error Counter Register 16h 22 RW PCSR PCS Sub Layer Configuration and Status Register 17h 23 RW RBR RMII and Bypass Register 18h 24 RW LEDCR LED Direct Control Register 19h 25 RW PHYCR PHY Control Register 1Ah 26 RW 10BTSCR 10Base T Status Control Register 1Bh 27 RW CDCTRL1 CD Test Control Register and BIST Extensions Register 1Ch 28 RW RESERVED RESERVED 1Dh 29 RW EDCR Energy Detect Control Register 1Eh 1Fh 30 31 RW RESERVED RESERVED 37 www national com I8v8e8da SSVdAd INVHOS SSVd 8
67. e Packet Latency Timing PMD Input Pair IDLE J K Data 12 91 gt CRS T2 9 2 RXD 3 0 RX DV RX ER Parameter Description Notes Min Typ Units T2 9 1 Carrier Sense ON Delay 100 Mb s Normal mode 20 bits T2 9 2 Receive Data Latency 100 Mb s Normal mode 24 bits Note Carrier Sense On Delay is determined by measuring the time from the first bit of the J code group to the assertion of Carrier Sense Note 1 bit time 10 ns in 100 Mb s mode Note PMD Input Pair voltage amplitude is greater than the Signal Detect Turn On Threshold Value 8 2 10 100BASE TX Receive Packet Deassertion Timing PMD Input Pair DATA T R IDLE T2 10 1 CRS Parameter Description Notes Min Typ Max Units T2 10 1 Carrier Sense OFF Delay 100 Mb s Normal mode 24 bits Note Carrier Sense Off Delay is determined by measuring the time from the first bit of the T code group to the deasser tion of Carrier Sense Note 1 bit time 10 ns in 100 Mb s mode 69 www national com 137858 8 2 11 10 Mb s Transmit Timing T2 11 1 TX CLK TXD 3 0 T2 11 1 TX EN Valid Data Parameter Description Notes Min Typ Max Units T2 11 1 TX CLK High Low Time 10 Mb s MII mode 190 200 210 ns T2 11 2 TXD 3 0 TX EN Data Setup to TX CLK fall 10 Mb s MII mode 25 ns 2 11 3 TXD 3 0 TX E
68. e up the transmitter to put ED pulses on the line but will otherwise draw as little power as possible Energy detect functionality is controlled via register Energy Detect Control EDCR address 0x1Dh 35 www national com I8v8e8da 6 0 Reset Operation The DP83848l includes an internal power on reset POR function and does not need to be explicitly reset for normal operation after power up If required during normal opera tion the device can be reset by a hardware or software reset 6 1 Hardware Reset A hardware reset is accomplished by applying a low pulse TTL level with a duration of at least 1 us to the RESET N This will reset the device such that all registers will be reinitialized to default values and the hardware con figuration values will be re latched into the device similar to the power up reset operation 6 2 Software Reset A software reset is accomplished by setting the reset bit bit 15 of the Basic Mode Control Register BMCR The period from the point in time when the reset bit is set to the point in time when software reset has concluded is approx imately 1 us The software reset will reset the device such that all regis ters will be reset to default values and the hardware config uration values will be maintained Software driver code must wait 3 us following a software reset before allowing further serial operations with the DP83848l 36 www national com I8v8e8
69. eartbeat function during 10 Mb s full duplex operation RMII COLLISION DETECT Per the RMII Specification no COL signal is required The MAC will recover CRS from the CRS DV signal and use that along with its TX EN signal to determine col lision SNI COLLISION DETECT Asserted high to indicate detection of a collision condition simultaneous transmit and receive activity in 10 Mb s SNI mode 10 www national com I8v8 8da 1 3 Clock Interface Signal Name Type Pin Description 34 CRYSTAL OSCILLATOR INPUT This is the primary clock reference input for the DP83848l and must be connected to 25 MHz 0 005 50 ppm clock source The DP83848I supports ei ther an external crystal resonator connected across pins X1 and X2 or an external CMOS level oscillator source connected to pin X1 only RMII REFERENCE CLOCK This pin is the primary clock refer ence input for the RMII mode and must be connected to a 50 MHz 0 005 50 ppm CMOS level oscillator source X2 33 CRYSTAL OUTPUT This pin is the primary clock reference out put to connect to an external 25 MHz crystal resonator device This pin must be left unconnected if an external CMOS oscillator clock source is used 25MHz OUT 25 25 MHz CLOCK OUTPUT In MII mode this pin provides a 25 MHz clock output to the sys tem In RMII mode this pin provides a 50 MHz clock output to the sys tem Th
70. els are reduced to minimize the effect of noise causing premature End of Packet detection 150ns 150 ns gt 150 ns Vsq4 reduced eee E VsQ reduced Sate eas Vsq start of packet end of packet Figure 10 10BASE T Twisted Pair Smart Squelch Operation 4 3 3 Collision Detection and When in Half Duplex a 10BASE T collision is detected when the receive and transmit channels are active simulta neously Collisions are reported by the COL signal on the MII Collisions are also reported when a jabber condition is detected The COL signal remains set for the duration of the collision If the PHY is receiving when a collision is detected it is reported immediately through the COL pin When heartbeat is enabled approximately 1 us after the transmission of each packet a Signal Quality Error SQE signal of approximately 10 bit times is generated to indi cate successful transmission SQE is reported as a pulse on the COL signal of the MII The SQE test is inhibited when the PHY is set in full duplex mode SQE can also be inhibited by setting the HEARTBEAT DIS bit in the 10BTSCR register 4 3 4 Carrier Sense Carrier Sense CRS may be asserted due to receive activ ity once valid data is detected via the squelch function For 10 Mb s Half Duplex operation CRS is asserted during either packet transmission or reception For 10 Mb s Full Duplex operation CRS is as
71. equired then there is no need for external pull up or pull tion The strap option pin assignments are defined below down resistors Since these pins may have alternate func The functional pin name is indicated in parentheses tions after reset is deasserted they should not be con nected directly to VCC or GND Signal Name Type Pin Description PHYADO COL S O PU 42 PHY ADDRESS 4 0 The DP838468l provides five PHY address PHYAD1 RXD 0 S O PD 43 pins the state of which are latched into the PHYCTRL register at system Hardware Reset 2 RXD_1 44 The DP83848l supports PHY Address strapping values 0 PHYADS RXD 2 45 00000 through 31 lt 11111 gt A PHY Address of 0 puts the PHYAD4 RXD 3 46 part into the MII Isolate Mode The MII isolate mode must be se i lected by strapping Phy Address 0 changing to Address 0 by reg ister write will not put the Phy in the MII isolate mode Please refer to section 2 3 for additional information gt YS o pin has weak internal pull up resistor 0 4 1 pins have weak internal pull down resistors 12 www national com I8v8 8da 1 7 Strap Options Continued Signal Name AN_EN LED_ACT COL 1 LED SPEED AN 0 LED LINK Type Pin Description S O PU 26 27 28 Auto Negotiation Enable When high this enables Auto Negoti ation with the capability set by ANO and AN1 pins Whe
72. evel a current limiting resistor should be placed in series between X2 and the crystal As a starting point for evaluating an oscillator circuit if the requirements for the crystal not known C and Cj should be set at 33 pF and R4 should be set at 00 Specification for 25 MHz crystal are listed in Table 9 x1 X2 Ry Figure 12 Crystal Oscillator Circuit Table 7 25 MHz Oscillator Specification Parameter Min Typ Max Units Condition Frequency 25 MHz Frequency 50 Operational Temperature Tolerance Frequency 50 ppm 1 year aging Stability Rise Fall Time 6 nsec 20 80 Jitter Short term 50 psec Cycle to cycle Jitter Long term 1 nsec Accumulative over 10us Symmetry 40 60 Duty Cycle Table 8 50 MHz Oscillator Specification Parameter Min Typ Max Units Condition Frequency 50 MHz Frequency 50 ppm Operational Temperature Tolerance Frequency 50 ppm Operational Temperature Stability Rise Fall Time 6 nsec 20 80 Jitter Short term 50 psec Cycle to cycle Jitter Long term 1 nsec Accumulative over 10us Symmetry 40 60 Duty Cycle www national com I8r8 8da Table 9 25 MHz Crystal Specification Parameter Min Typ Max Units Condition Frequency 25 MHz Frequency 50 ppm Operational Tolerance Temperature Frequency 50 ppm 1 year aging Stability Load C
73. ex The DP83848l supports both half and full duplex operation at both 10 Mb s and 100 Mb s speeds Half duplex relies on the CSMA CD protocol to handle colli sions and network access In Half Duplex mode CRS responds to both transmit and receive activity in order to maintain compliance with the IEEE 802 3 specification Since the DP83848l is designed to support simultaneous transmit and receive activity it is capable of supporting full duplex switched applications with a throughput of up to 200 Mb s per port when operating in 100BASE TX mode Because the CSMA CD protocol does not apply to full duplex operation the DP83848l disables its own internal collision sensing and reporting functions and modifies the behavior of Carrier Sense CRS such that it indicates only receive activity This allows a full duplex capable MAC to operate properly All modes of operation 100BASE TX and 10BASE T can run either half duplex or full duplex Additionally other than CRS and Collision reporting all remaining MII signaling remains the same regardless of the selected duplex mode It is important to understand that while Auto Negotiation with the use of Fast Link Pulse code words can interpret and configure to full duplex operation parallel detection can not recognize the difference between full and half duplex from a fixed 10 Mb s or 100 Mb s link partner over twisted pair As specified in the 802 3u specification if a far end link partner is co
74. form 10BASE T in full duplex mode 10BASE T Half Duplex Capable 1 Device able to perform 10BASE T in half duplex mode RESERVED Write as 0 read as 0 Preamble suppression Capable 1 Device able to perform management transaction with preamble suppressed 32 bits of preamble needed only once after reset invalid opcode or invalid turnaround 0 Normal management operation Auto Negotiation Complete 1 Auto Negotiation process complete 0 Auto Negotiation process not complete Remote Fault 1 Remote Fault condition detected cleared on read or by reset Fault criteria Far End Fault Indication or notification from Link Part ner of Remote Fault 0 No remote fault condition detected Auto Negotiation Ability 1 Device is able to perform Auto Negotiation 0 Device is not able to perform Auto Negotiation Link Status 1 Valid link established for either 10 or 100 Mb s operation 0 Link not established The criteria for link validity is implementation specific The occurrence of a link failure condition will causes the Link Status bit to clear Once cleared this bit may only be set by establishing a good link condition and a read via the management interface Jabber Detect This bit only has meaning in 10 Mb s mode 1 Jabber condition detected 0 No Jabber This bit is implemented with a latching function such that the occur rence of a jabber condition causes it to set until it is cle
75. gh Low Time 35 50 65 ns T2 14 2 RX CLK fall to RXD 0 RX DV Delay 10 Mb s Serial mode 10 10 ns Note RX CLK may be held high for a longer period of time during transition between reference and recovered clocks Minimum high and low times will not be violated 71 www national com I8v8 8da 8 2 15 10BASE T Transmit Timing Start of Packet m a a ae a TX_EN TXD 12 15 2 PMD Output Pair 2 15 1 Description Notes Min Typ Max Units T2 15 1 Transmit Output Delay from the 10 Mb s MII mode 3 5 bits Falling Edge of TX CLK T2 15 2 Transmit Output Delay from the 10 Mb s Serial mode 3 5 bits Rising Edge of TX CLK Note 1 bit time 100 ns in 10Mb s 8 2 16 10BASE T Transmit Timing End of Packet TOK G sn G Nan TX_EN PMD Output Pair T2 16 2 Pair Parameter Description Notes Min Typ Max Units T2 16 1 End of Packet High Time 250 300 ns with 0 ending bit T2 16 2 End of Packet High Time 250 300 ns with 1 ending bit 72 www national com I8v8 8da 8 2 17 10BASE T Receive Timing Start of Packet 1st SFD bit decoded TPRD E T2 17 1 CRS RX_CLK lef 2 17 2 lt gt RX_DV T2 17 3 lt gt 0000 Preamble SFD X Data RXD 3 0 Par
76. her or not valid link has been established Support for Management Frame Preamble suppression The Auto Negotiation Advertisement Register ANAR indicates the Auto Negotiation abilities to be advertised by the DP83848l All available abilities are transmitted by default but any ability can be suppressed by writing to the 16 www national com I8v8e 8da ANAR Updating the ANAR to suppress an ability is one way for a management agent to change restrict the tech nology that is used The Auto Negotiation Link Partner Ability Register ANLPAR at address 05h is used to receive the base link code word as well as all next page code words during the negotiation Furthermore the ANLPAR will be updated to either 0081h or 0021h for parallel detection to either 100 Mb s or 10 Mb s respectively The Auto Negotiation Expansion Register indi cates additional Auto Negotiation status The ANER pro vides status on Whether or not a Parallel Detect Fault has occurred Whether or not the Link Partner supports the Next Page function Whether or not the DP83848l supports the Next Page function Whether or not the current page being exchanged by Auto Negotiation has been received Whether or not the Link Partner supports Auto Negotia tion 2 1 3 Auto Negotiation Parallel Detection The DP83848I supports the Parallel Detection function as defined in the IEEE 802 3u specification Parallel De
77. il aol eile eat etr a et ry 29 Figure 10 10BASE T Twisted Pair Smart Squelch Operation 31 Figure 11 10 100 Mb s Twisted Pair Interface 33 Figure 12 Crystal Oscillator Circuit 34 Figure 13 Power Feeback Connection 35 6 www national com I8v8 8da List of Tables Table 1 Auto Negotiation 16 Table 2 PHY Address Mapping 18 Table 3 LED Mode Select inene dc rrr era n eer pac mx mem als eee Rn n 19 Table 4 Supported packet sizes at 50 100ppm for each 22 Table 5 Typical Frame 23 Table 5 4B5B Code Group Encoding Decoding 25 Table 6 25 MHz Oscillator Specification 34 Table 7 50 MHz Oscillator Specification 34 Table 8 25 MHz Crystal Specification 35 Table 9 Register Map
78. in the PHY Control Register PHYCR The received data is compared to the generated pseudo ran dom data by the BIST Linear Feedback Shift Register LFSR to determine the BIST pass fail status The pass fail status of the BIST is stored in the BIST status bit in the PHYCR register The status bit defaults to 0 BIST fail and will transition on a successful comparison If an error mis compare occurs the status bit is latched and is cleared upon a subsequent write to the Start Stop bit For transmit VOD testing the Packet BIST Continuous Mode can be used to allow continuous data transmission setting BIST CONT MODE bit 5 of CDCTRL1 0x1Bh The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 0x1Bh bits 15 8 20 www national com 3 0 Functional Description The DP83848I supports several modes of operation using the MIl interface pins The options are defined in the follow ing sections and include Mode 10 Mb Serial Network Interface SNI The modes of operation can be selected by strap options or register control For RMII mode it is recommended to use the strap option since it requires a 50 MHz clock instead of the normal 25 MHz In each of these modes the IEEE 802 3 serial manage ment interface is operational for device configuration and status The serial management interface of the MII allows for the configuratio
79. ing bits in the MII Inter rupt Status and Event Control Register MISR Table 22 Interrupt Control Register MICR address 0x11 Reserved Reserved Write ignored Read as 0 TINT 0 RW Test Interrupt Forces the PHY to generate an interrupt to facilitate interrupt test ing Interrupts will continue to be generated as long as this bit re mains set 1 Generate an interrupt 0 Do not generate interrupt Interrupt Enable Enable interrupt dependent on the event enables in the MISR reg ister 1 Enable event based interrupts 0 Disable event based interrupts Interrupt Output Enable Enable interrupt events to signal the PWR_DOWN INT by configuring the PWR_DOWN INT pin as an output 1 PWR_DOWN INT is an Interrupt Output 0 PWR_DOWN INT is a Power Down Input 51 www national com 137858 7 2 3 Interrupt Status and Misc Control Register MISR This register contains event status and enables for the interrupt function If an event has occurred since the last read of this register the corresponding status bit will be set If the corresponding enable bit in the register is set an interrupt will be generated if the event occurs The MICR register controls must also be set to allow interrupts The status indi cations in this register will be set even if the interrupt is not enabled Table 23 Interrupt Status and Misc Control Register MISR address 0x12 Reserved RESERVED
80. iption Notes Min Typ Units T2 23 1 SD Internal Turn on Time 1 ms T2 23 2 SD Internal Turn off Time 350 us Note The signal amplitude on PMD Input Pair must be TP PMD compliant 8 2 24 100 Mb s Internal Loopback Timing TX_CLK ae ae TX_EN E TXD 3 0 Xx Z O o CRS T2 24 1 gt RX_CLK PNE NN RX DV RXD 3 0 Parameter Description Notes Min Typ Units T2 24 1 TX EN to RX DV Loopback 100 Mb s internal loopback mode 240 ns Note1 Due to the nature of the descrambler function all 100BASE TX Loopback modes will cause an initial dead time of up to 550 us during which time no data will be present at the receive MII outputs The 100BASE TX timing specified is based on device delays after the initial 550us dead time Note2 Measurement is made from the first rising edge of TX CLK after assertion of TX EN 76 www national com I8v8 8da 8 2 25 10 Mb s Internal Loopback Timing TX CLK a c a m TX EN Ji TXD 3 0 EE ONE SUM coe CRS T2 25 1 gt RX_CLK WEN RX_DV RXD 3 0 N Parameter Description Notes Min Max Units T2 25 1 TX EN to RX DV Loopback 10 Mb s internal loopback mode 2 us Note Measurement is made from the first rising edge of TX CLK after assertion of TX EN 77 www national com 137858 8 2 26 Transmit Timing
81. is allows other devices to use the reference clock from the DP83848l without requiring additional clock sources 1 4 LED Interface See Table 3 for LED Mode Selection Signal Name Type Pin Description LED_LINK 5 0 PU 28 LINK LED In Mode 1 this pin indicates the status of the LINK The LED will be ON when Link is good LINK ACT LED In Mode 2 and Mode 3 this pin indicates transmit and receive activity in addition to the status of the Link The LED will be ON when Link is good It will blink when the transmitter or receiver is active LED SPEED S O PU 27 SPEED LED The LED is ON when device is in 100 Mb s and OFF when in 10 Mb s Functionality of this LED is independent of mode selected LED ACT COL S O PU 26 ACTIVITY LED In Mode 1 this pin is the Activity LED which is ON when activity is present on either Transmit or Receive COLLISION DUPLEX LED In Mode 2 this pin by default indi cates Collision detection For Mode 3 this LED output may be programmed to indicate Full duplex status instead of Collision 11 www national com 1 5 JTAG Interface Signal Name Type Pin Description TCK I PU 8 TEST CLOCK This pin has a weak internal pullup TDI I PU 12 TEST DATA INPUT This pin has a weak internal pullup TDO 9 TEST OUTPUT TMS I PU 10 TEST MODE SELECT This pin has a weak internal pullup TR
82. ks Analog Front End Digital Signal Processor Signal Detect MLT 3 to Binary Decoder NRZI to NRZ Decoder Serial to Parallel Descrambler Code Group Alignment 4B 5B Decoder Link Integrity Monitor Bad SSD Detection 4 2 1 Analog Front End In addition to the Digital Equalization and Gain Control the 0 838481 includes Analog Equalization and Gain Control in the Analog Front End The Analog Equalization reduces the amount of Digital Equalization required in the DSP 4 2 2 Digital Signal Processor The Digital Signal Processor includes Adaptive Equaliza tion with Gain Control and Base Line Wander Compensa tion 26 www national com RX_DV CRS A RX DATA VAL DE D SSD TECT RX_CLK A Figure 7 100 Receive Block Diagram RXD 3 0 RX_ER 4B 5B DECODER CODE GROUP ALIGNMENT DESCRAMBLER NRZI TO NRZ DECODER MLT 3 TO BINARY DECODER DIGITAL SIGNAL PROCESSOR ANALOG FRONT END RD LINK INTEGRITY MONITOR SIGNAL DETECT 27 www national com 4 2 2 1 Digital Adaptive Equalization and Gain Control When transmitting data at high speeds over copper twisted pair cable frequency dependent attenuation becomes a concern In high speed twisted pair signalling the fre quency content of the transmitted signal can vary gre
83. lid carrier is present and there is at least one occurrence of an invalid data symbol this 8 bit counter increments for each re ceive error detected This event can increment only once per valid carrier event If a collision is present the attribute will not incre ment The counter sticks when it reaches its max count 53 www national com 137858 7 2 6 100 Mb s PCS Configuration and Status Register PCSR Table 26 100 Mb s PCS Configuration and Status Register PCSR address 0x16 15 13 RESERVED Writes ignored Read as 0 12 RESERVED RESERVED 11 RESERVED RESERVED 10 TQ_EN 0 RW 100Mbs True Quiet Mode Enable 1 Transmit True Quiet Mode 0 Normal Transmit Mode SD FORCE PMA 0 RW Signal Detect Force PMA 1 Forces Signal Detection in PMA 0 Normal SD operation SD_OPTION Signal Detect Option 1 Enhanced signal detect algorithm 0 Reduced signal detect algorithm DESC_TIME Descrambler Timeout Increase the descrambler timeout When set this should allow the device to receive larger packets gt 9k bytes without loss of syn chronization 1 2ms 0 722us per ANSI X3 263 1995 TP PMD 7 2 3 3e RESERVED RESERVED Must be zero FORCE 100 OK 0 RW Force 100Mb s Good Link 1 Forces 100Mb s Good Link 0 Normal 100Mb s operation RESERVED RESERVED RESERVED RESERVED NRZI BYPASS 0 RW NRZI Bypass Enable 1 Bypass Enabled 0 Bypass Disabled RESERVED RESERVED RESE
84. mbol Pin Types Parameter Conditions Min Typ Max Units SDtHon PMD Input 100BASE TX 1000 diff pk pk Pair Signal detect turn on threshold PMD Input 100BASE TX 200 diff pk pk Pair Signal detect turn off threshold Vout PMD Input 10BASE T 585 mV Pair ceive Threshold ldd100 Supply 100BASE TX 81 mA Full Duplex lda10 Supply 10BASE T 92 mA Full Duplex lad Supply Power Down 14 mA Mode 62 www national com I8v8 8da 8 2 Specs 8 2 1 Power Up Timing Vcc T2 1 1 Hardware RESET N 32 clocks MDC 5 5 T2 1 2 Latch In of Hardware T24 3 Configuration Pins input output Dual Function Pins Become Enabled As Outputs Parameter Description Notes Min Typ Max Units T2 1 1 Post Power Up Stabilization MDIO is pulled high for 32 bit serial man 167 ms time prior to MDC preamble for agement initialization register accesses X1 Clock must be stable for a min of 167ms at power up T2 1 2 Hardware Configuration Latch Hardware Configuration Pins are de 167 ms in Time from power up scribed in the Pin Description section X1 Clock must be stable for a min of 167ms at power up T2 1 3 Hardware Configuration pins 50 ns transition to output drivers 63 www national com I8v8 8da 8 2 2 Reset Timing Vcc aa Hardware gt
85. millimeters unless otherwise noted 8 12 amp 9 mim 120 1 930 25 TYP R0 08 MIN RO 08 0 20 0 25 48 GAGE PLAN p 1 PIN 1 IDENT 05 PT 5 OPTIONAL Peat 0 2 0 05 TYP SHARP CORNERS 0 08 CAS 189 EXCEPT PIN 1 IDENT 0 640 15 SEATING PLANE CORNER a DETAIL A A DETAIL A i TYP SCALE 40X 1 4 0 05 i cary rn M a 0 125 TYP DIMENSIONS ARE IN MILLIMETERS VBH48A Rev D Lead Quad Frame Package LQFP NS Package Number VBH48A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATI 1 Life support devices or systems are devices or systems which are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user ON As used herein 2 Acritical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to af fect its safety or effectiveness BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing material
86. n valid data is present on the differential receive inputs The 0 838481 implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal Smart squelch operation is independent of the 10BASE T operational mode The squelch circuitry employs a combination of amplitude and timing measurements as specified in the IEEE 802 3 10BSE T standard to determine the validity of data on the twisted pair inputs refer to Figure 10 The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the squelch level either positive or negative depending upon polarity will be rejected Once this first squelch level is overcome cor rectly the opposite squelch level must then be exceeded within 150 ns Finally the signal must again exceed the original squelch level within a 150 ns to ensure that the input waveform will not be rejected This checking proce dure results in the loss of typically three preamble bits at the beginning of each packet Only after all these conditions have been satisfied will control signal be generated to indicate to the remainder of the circuitry that valid data is present At this time the smart squelch circuitry is reset Valid data is considered to be present until the squelch level has not been generated for a time longer than 150 ns indicating the End of Packet Once good data has been detected the squelch lev
87. n and control of multiple PHY devices gathering of status error information and the determina tion of the type and capabilities of the attached PHY s 3 1 MII Interface The DP83848l incorporates the Media Independent Inter face as specified in Clause 22 of the IEEE 802 3u standard This interface may be used to connect PHY devices to a MAC in 10 100 Mb s systems This section describes the nibble wide MII data interface The nibble wide MII data interface consists of a receive bus and a transmit bus each with control signals to facilitate data transfer between the PHY and the upper layer MAC 3 1 1 Nibble wide MII Data Interface Clause 22 of the IEEE 802 3u specification defines the Media Independent Interface This interface includes a dedicated receive bus and a dedicated transmit bus These two data buses along with various control and status sig nals allow for the simultaneous exchange of data between the DP83848l and the upper layer agent MAC The receive interface consists of a nibble wide data bus RXD 3 0 a receive error signal RX ER a receive data valid flag RX DV and a receive clock RX CLK for syn chronous transfer of the data The receive clock operates at either 2 5 MHz to support 10 Mb s operation modes or at 25 MHz to support 100 Mb s operational modes The transmit interface consists of a nibble wide data bus TXDJ 3 0 a transmit enable control signal TX EN and a transmit clock TX CLK which runs
88. n low this puts the part into Forced Mode with the capability set by ANO and AN1 pins ANO AN1 These input pins control the forced or advertised op erating mode of the DP83848l according to the following table The value on these pins is set by connecting the input pins to GND 0 or Vcc 1 through 2 2 resistors These pins should NEVER be connected directly to GND or VCC The value set at this input is latched into the DP83848l at Hard ware Reset The float pull down status of these pins are latched into the Basic Mode Control Register and the Auto Negotiation Advertisement Register during Hardware Reset The default is 111 since these pins have internal pull ups ANEN ANT ANO Forced o o CS r 6 Far Dupe t EN ant Advertised Mode o 9 HaFu Duplex 1 1 10BASE T Half Duplex 1 1 1 10BASE T Half Full Duplex MODE RX DV SNI MODE TXD 3 5 0 PD 39 MODE SELECT This strapping option pair determines the operating mode of the MAC Data Interface Default operation No pull ups will enable normal MII Mode of operation Strapping MODE high will cause the device to be in SNI mode of operation determined by the status of the SNI MODE str
89. n order to minimize latency of control signals through the why CRS DV may toggle synchronously at the end of the packet to indicate CRS deassertion Note RX DV is synchronous to X1 While not part of the RMII specification this signal is provided to simplify recovery of receive data 79 www national com I8v8 8da 8 2 28 Isolation Timing Clear bit 10 of BMCR return to normal operation from Isolate mode 4 T2 28 1 H W or S W Reset with PHYAD 00000 N T2282 y MODE ISOLATE NORMAL Parameter Description Notes Min Typ Max Units T2 28 1 From software clear of bit 10 in 100 us the BMCR register to the transi tion from Isolate to Normal Mode T2 28 2 From Deassertion of S W or H W 500 us Reset to transition from Isolate to Normal mode 8 2 29 25 MHz_OUT Timing X1 25 MHz OUT Parameter Description Notes Min Typ Units T2 29 1 25 MHz OUT High Low Time MII mode 20 ns RMII mode 10 ns T2 29 2 25 MHz OUT propagation delay Relative to X1 8 ns Note 25 MHz OUT characteristics are dependent upon the X1 input characteristics 80 www national com NOTES www national com Isp8esdd DP83848l PHYTER Industrial Temperature Single Port 10 100 Mb s Ethernet Physical Layer Transceiver 9 0 Physical Dimensions inches
90. nfigured to a forced full duplex 100BASE TX ability the parallel detection state machine in the partner would be unable to detect the full duplex capa bility of the far end link partner This link segment would negotiate to a half duplex 100BASE TX configuration same scenario for 10 Mb s 2 6 Internal Loopback The DP83848l includes a Loopback Test mode for facilitat ing system diagnostics The Loopback mode is selected through bit 14 Loopback of the Basic Mode Control Reg ister BMCR Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs Loopback status may be checked in bit 3 of the PHY Status Register PHYSTS While in Loopback mode the data will not be transmitted onto the media To ensure that the desired operating mode is maintained Auto Negotiation should be disabled before selecting the Loopback mode 2 7 BIST The DP83848l incorporates an internal Built in Self Test BIST circuit to accommodate in circuit testing or diagnos tics The BIST circuit can be utilized to test the integrity of the transmit and receive data paths BIST testing can be performed with the part in the internal loopback mode or externally looped back using a loopback cable fixture The BIST is implemented with independent transmit and receive paths with the transmit block generating a continu ous stream of a pseudo random sequence The user can select a 9 bit or 15 bit pseudo random sequence from the PSR 15 bit
91. ntained if the cable becomes disconnected A renegotiation request from any entity such as a manage ment agent will cause the DP838468l to halt any transmit data and link pulse activity until the break link timer expires 71500 ms Consequently the Link Partner will go into link fail and normal Auto Negotiation resumes The DP83848l will resume Auto Negotiation after the break_link_timer has expired by issuing FLP Fast Link Pulse bursts 2 1 5 Enabling Auto Negotiation via Software It is important to note that if the DP83848l has been initial ized upon power up as a non auto negotiating device forced technology and it is then required that Auto Nego tiation or re Auto Negotiation be initiated via software bit 12 Auto Negotiation Enable of the Basic Mode Control Register BMCR must first be cleared and then set for any Auto Negotiation function to take effect 2 1 6 Auto Negotiation Complete Time Parallel detection and Auto Negotiation take approximately 2 3 seconds to complete In addition Auto Negotiation with next page should take approximately 2 3 seconds to com plete depending on the number of next pages sent Refer to Clause 28 of the IEEE 802 3u standard for a full description of the individual timers related to Auto Negotia tion 2 2 Auto MDIX When enabled this function utilizes Auto Negotiation to determine the proper configuration for transmission and reception of data and subsequently selects the appro
92. omplete 0 Auto Negotiation not complete Loopback Status Duplex Status Speed Status Loopback 1 Loopback enabled 0 Normal operation Duplex This bit indicates duplex status and is determined from Auto Nego tiation or Forced Modes 1 Full duplex mode 0 Half duplex mode Note This bit is only valid if Auto Negotiation is enabled and com plete and there is a valid link or if Auto Negotiation is disabled and there is a valid link Speed10 This bit indicates the status of the speed and is determined from Auto Negotiation or Forced Modes 1 10 Mb s mode 0 100 Mb s mode Note This bit is only valid if Auto Negotiation is enabled and com plete and there is a valid link or if Auto Negotiation is disabled and there is a valid link Link Status This bit is a duplicate of the Link Status bit in the BMSR register except that it will not be cleared upon a read of the PHYSTS regis ter 1 Valid link established for either 10 or 100 Mb s operation 0 Link not established Link Status 50 www national com 137858 7 2 2 Interrupt Control Register MICR This register implements the Interrupt PHY Specific Control register Sources for interrupt generation include Energy Detect State Change Link State Change Speed Status Change Duplex Status Change Auto Negotiation Complete or any of the counters becoming half full The individual interrupt events must be enabled by sett
93. ons Register CDCTRL1 address 0x1B BIST_ERROR_CO BIST ERROR Counter UNT Counts number of errored data nibbles during Packet BIST This value will reset when Packet BIST is restarted The counter sticks when it reaches its max count RESERVED 0 RW RESERVED Must be zero BIST us MOD Packet BIST Continuous Mode Allows continuous pseudo random data transmission without any break in transmission This can be used for transmit VOD testing This is used in conjunction with the BIST controls in the PHYCR Register 0x19h For 10Mb operation jabber function must be dis abled bit 0 of the 10BTSCR 0x1Ah JABBER DIS 1 CDPATTEN 10 CD Pattern Enable for 10Mb 1 Enabled 0 Disabled RESERVED RESERVED Must be zero 10MEG Defines gap between data or NLP test sequences 1 15 us 0 10 us CDPATTSEL 1 0 00 RW CD Pattern Select 1 0 If CDPATTEN_10 1 00 Data EOPO sequence 01 Data EOP1 sequence 10 NLPs 11 Constant Manchester 15 10MHz sine wave for harmonic dis tortion testing 59 www national com Igsp8esdd 7 2 12 Energy Detect Control EDCR Table 32 Energy Detect Control EDCR address 0x1D Bit Name Description ED_EN 2 2 Energy Detect Enable Allow Energy Detect Mode When Energy Detect is enabled and Auto Negotiation is disabled via the BMCR register Auto MDIX should be disabled via the PHY CR register ED AUTO UP Energy Detect Automatic Power Up
94. oup encoder injects the T R code group pair 01101 00111 indicating the end of the frame After the T R code group pair the code group encoder continuously injects IDLEs into the transmit data stream until the next transmit packet is detected reassertion of Transmit Enable 4 1 1 Scrambler The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable for 25 www national com 100BASE TX applications By scrambling the data the total energy launched onto the cable is randomly distrib uted over a wide frequency range Without the scrambler energy levels at the PMD and on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences i e continuous transmission of IDLEs The scrambler is configured as a closed loop linear feed back shift register LFSR with an 11 bit polynomial The output of the closed loop LFSR is X ORd with the serial NRZ data from the code group encoder The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB The DP83848l uses the PHY_ID pins PHYAD 4 0 to set a unique seed value 4 1 2 NRZ to NRZI Encoder After the transmit data stream has been serialized and scrambled the data must be NRZI encoded in order to comply with the TP PMD standard for 100BASE TX trans mission over Category 5 Unshielde
95. our bits of the vendor model revision number are mapped from bits 3 to 0 most significant bit to bit 3 This field will be incremented for all major device changes 7 1 5 Auto Negotiation Advertisement Register ANAR This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto Nego tiation Table 16 Negotiation Advertisement Register ANAR address 0x04 15 NP 0 RW Next Page Indication 0 Next Page Transfer not desired 1 Next Page Transfer desired RESERVED by IEEE Writes ignored Read as 0 RF 0 RW Remote Fault 1 Advertises that this device has detected a Remote Fault 0 No Remote Fault detected 0 RW RESERVED for Future IEEE use Write as 0 Read as 0 44 www national com 10 Table 16 Negotiation Advertisement Register ANAR address 0x04 Continued Bit Name ASM DIR Description o Asymmetric PAUSE Support for Full Duplex Links The ASM_DIR bit indicates that asymmetric PAUSE is supported Encoding and resolution of PAUSE bits is defined in IEEE 802 3 Annex 28B Tables 28B 2 and 28B 3 respectively Pause resolu tion status is reported in PHYCR 13 12 1 Advertise that the DTE MAC has implemented both the op tional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802 3u 0 No MAC based full duplex flow control PAUSE Support for Full Duplex Links The
96. p to 2400 byte packets 10 6 bit tolerance up to 7200 byte packets 11 10 bit tolerance up to 12000 byte packets 7 2 8 LED Direct Control Register LEDCR This register provides the ability to directly control any or all LED outputs It does not provide read access to LEDs Table 28 LED Direct Control Register LEDCR address 0x18 Bit Name Description RESERVED RESERVED Writes ignored read as 0 DRV SPDLED 0 RW 1 Drive value of SPDLED bit onto LED SPD output 0 Normal operation DRV LNKLED 0 RW 1 Drive value of LNKLED bit onto LED LNK output 0 Normal operation DRV ACTLED 0 RW 1 Drive value of ACTLED bit onto LED ACT COL output 0 Normal operation 0 RW Value to force on SPD output 0 RW Value to force on LED LNK output 0 RW Value to force on LED ACT COL output SPDLED LNKLED ACTLED 55 www national com I8v8 8da 7 2 9 PHY Control Register PHYCR Table 29 PHY Control Register PHYCR address 0x19 Bit Name Description MDIX_EN Strap RW Auto MDIX Enable 1 Enable Auto neg Auto MDIX capability 0 Disable Auto neg Auto MDIX capability The Auto MDIX algorithm requires that the Auto Negotiation En able bit in the BMCR register to be set If Auto Negotiation is not enabled Auto MDIX should be disabled as well Force MDIX 1 Force MDI pairs to cross FORCE_MDIX Receive on TPTD pair Transmit on TPRD pair 0 Normal operation PAUSE_RX Pause Receive Negotiated Indicates that pause
97. priate MDI pair for MDI MDIX operation The function uses a ran dom seed to control switching of the crossover circuitry This implementation complies with the corresponding IEEE 802 3 Auto Negotiation and Crossover Specifications Auto MDIX is enabled by default and can be configured via strap or via PHYCR 0x19h register bits 15 14 Neither Auto Negotiation nor Auto MDIX is required to be enabled in forcing crossover of the MDI pairs Forced crossover can be achieved through the FORCE MDIX bit bit 14 of PHYCR 0x19h register Note Auto MDIX will not work in a forced mode of opera tion 17 www national com I8v8e8da 2 3 PHY Address The 5 PHY address inputs pins are shared with the RXD 3 0 pins and COL pin as shown below Table 2 PHY Address Mapping Pin PHYAD Function RXD Function 42 PHYADO COL 43 PHYAD1 RXD 0 44 PHYAD2 RXD_1 45 PHYAD3 RXD_2 46 PHYAD4 RXD_3 The DP83848l can be set to respond to any of 32 possible PHY addresses via strap pins The information is latched into the PHYCR register address 19h bits 4 0 at device power up and hardware reset The PHY Address pins are shared with the RXD and COL pins Each DP83848l or port sharing an MDIO bus in a system must have a unique physical address The DP83848l supports PHY Address strapping values 0 lt 00000 gt through 31 lt 11111 gt Strapping PHY Address 0 puts the part into Isolate Mode It sho
98. ration of signal detect A 10 Mb s Link is established as a result of the reception of at least seven consecutive normal Link Pulses or the reception of a valid 10BASE T packet This will cause the assertion of LED LINK LED LINK will deas sert in accordance with the Link Loss Timer as specified in the IEEE 802 3 specification The LED LINK pin in Mode 1 will be OFF when no LINK is present The LED LINK pin in Mode 2 and Mode 3 will be ON to indicate Link is good and BLINK to indicate activity is present on either transmit or receive activity The LED SPEED pin indicates 10 or 100 Mb s data rate of the port The standard CMOS driver goes high when oper ating in 100 Mb s operation The functionality of this LED is independent of mode selected The LED ACT COL pin in Mode 1 indicates the presence of either transmit or receive activity The LED will be ON for Activity and OFF for No Activity In Mode 2 this pin indi cates the Collision status of the port The LED will be ON for Collision and OFF for No Collision The LED ACT COL pin in Mode 3 indicates the presence of Duplex status for 10 Mb s or 100 Mb s operation The LED will be ON for Full Duplex and OFF for Half Duplex In 10 Mb s half duplex mode the collision LED is based on the COL signal Since these LED pins are also used as strap options the polarity of the LED is dependent on whether the pin is pulled up or down 2 4 1 LEDs Since the Auto Negotiation AN strap op
99. receive should be enabled in the MAC Based on ANAR 11 10 and ANLPAR 11 10 settings This function shall be enabled according to IEEE 802 3 Annex 28B Table 28B 3 Pause Resolution only if the Auto Negotiated High est Common Denominator is a full duplex technology PAUSE_TX Pause Transmit Negotiated Indicates that pause transmit should be enabled in the MAC Based on ANAR 11 10 and ANLPAR 11 10 settings This function shall be enabled according to IEEE 802 3 Annex 28B Table 28B 3 Pause Resolution only if the Auto Negotiated High est Common Denominator is a full duplex technology 0 RW SC BIST Force Error 1 Force BIST Error 0 Normal operation BIST FE This bit forces a single error and is self clearing BIST Sequence select 1 PSR15 selected 0 PSRO selected BIST Test Status 1 BIST pass 0 BIST fail Latched cleared when BIST is stopped For a count number of BIST errors see the BIST Error Count in the CDCTRL1 register BIST Start 1 BIST start 0 BIST stop Bypass LED Stretching This will bypass the LED stretching and the LEDs will reflect the in ternal value BIST STATUS D 2 2 2 BIST_START e 2 BP_STRETCH e 2 1 Bypass LED stretching 0 Normal operation 56 www national com 137858 Table 29 PHY Control Register PHYCR address 0x19 Continued LED CNFG 1 0 RW LEDs Configuration LED CNFG 0 Strap RW LED CNFG 1 LE
100. ronous to the 50 MHz reference clock SNI TRANSMIT DATA Transmit data SNI input pin 0 that accept data synchronous to the TX_CLK 10 MHz in 10 Mb s SNI mode 9 www national com 137858 Signal Pin Description RX_CLK 38 RECEIVE CLOCK Provides the 25 MHz recovered receive clocks for 100 Mb s mode and 2 5 MHz for 10 Mb s mode Unused mode The device uses the X1 reference clock in put as the 50 MHz reference for both transmit and receive SNI RECEIVE CLOCK Provides the 10 MHz recovered receive clocks for 10 Mb s SNI mode RX_DV 5 0 PD 39 MII RECEIVE DATA VALID Asserted high to indicate that valid data is present on the corresponding RXD 3 0 MII mode by de fault with internal pulldown RMII Synchronous Receive Data Valid This signal provides the RMII Receive Data Valid indication independent of Carrier Sense This pin is not used in SNI mode RX ER S O PU 41 RECEIVE ERROR Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a re ceived packet in 100 Mb s mode RMII RECEIVE ERROR Assert high synchronously to X1 when ever it detects a media error and RXDV is asserted in 100 Mb s mode This pin is not required to be used by a MAC in either MII or RMII mode since the Phy is required to corrupt data on a receive error This pin is not used in SNI mode RXD 0
101. rt 1 10BASE T Full Duplex is supported by the Link Partner 0 10BASE T Full Duplex not supported by the Link Partner 10BASE T Support 1 10BASE T is supported by the Link Partner 0 10BASE T not supported by the Link Partner 4 0 Selector lt 0 00005 RO Protocol Selection Bits Link Partner s binary encoded protocol selector 46 www national com I8v8 8da 7 1 7 Auto Negotiation Link Partner Ability Register ANLPAR Next Page Table 18 Auto Negotiation Link Partner Ability Register ANLPAR Next Page address 0x05 Bit Bit Name 15 P Description Next Page Indication 1 Link Partner desires Next Page Transfer 0 Link Partner does not desire Next Page Transfer Acknowledge 1 Link Partner acknowledges reception of the ability data word 0 Not acknowledged The Auto Negotiation state machine will automatically control the this bit based on the incoming FLP bursts Software should not at tempt to write to this bit Message Page 1 Message Page 0 Unformatted Page Acknowledge 2 1 Link Partner does have the ability to comply to next page mes sage 0 Link Partner does not have the ability to comply to next page message Toggle 1 Previous value of the transmitted Link Code word equalled 0 0 Previous value of the transmitted Link Code word equalled 1 000 0000 0000 gt Code RO This field represents the code field of the next page transmission If the MP bit is set
102. s meet the provisions of the Customer Products Stewardship Specification CSP 9 111C2 and the Banned Substances and Materials of Interest Specification CSP 9 111S2 and contain no Banned Substances as defined in CSP 9 111S2 Leadfree products are RoHS compliant National Semiconductor National Semiconductor Corporation Europe Tel 1 800 272 9959 Fax 449 0 180 530 85 86 Fax 1 800 737 7018 Email europe support nsc com Email support nsc com Deutsch Tel 49 0 69 9508 6208 English Tel 44 0 870 24 0 2171 Francais Tel www national com 33 0 1 41 91 8790 National Semiconductor Japan Ltd Tel 81 3 5639 7560 Fax 81 3 5639 7507 National Semiconductor Asia Pacific Customer Response Group Tel 65 254 4466 Fax 65 250 4466 Email ap support nsc com National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
103. serted only during receive activity CRS is deasserted following an end of packet 4 3 5 Normal Link Pulse Detection Generation The link pulse generator produces pulses as defined in the IEEE 802 3 10BASE T standard Each link pulse is nomi nally 100 ns in duration and transmitted every 16 ms in the absence of transmit data Link pulses are used to check the integrity of the connec tion with the remote end If valid link pulses are not received the link detector disables the 10BASE T twisted pair transmitter receiver and collision detection functions When the link integrity function is disabled FORCE_LINK_10 of the 10BTSCR register a good link is forced and the 10BASE T transceiver will operate regard less of the presence of link pulses 31 www national com I8v8e8da 4 3 6 Jabber Function The jabber function monitors the DP83848l s output and disables the transmitter if it attempts to transmit a packet of longer than legal size A jabber timer monitors the transmit ter and disables the transmission if the transmitter is active for approximately 85 ms Once disabled by the Jabber function the transmitter stays disabled for the entire time that the ENDEC module s inter nal transmit enable is asserted This signal has to be de asserted for approximately 500 ms the unjab time before the Jabber function re enables the transmit outputs The Jabber function is only relevant in 1OBASE T mode 4 3
104. ssion ends when TX_EN deasserts The last transition is always positive it occurs at the center of the bit cell if the last bit is a one or at the end of the bit cell if the last bit is a zero 4 3 10 Receiver The decoder detects the end of a frame when no additional mid bit transitions are detected Within one and a half bit times after the last bit carrier sense is de asserted Receive clock stays active for five more bit times after CRS goes low to guarantee the receive timings of the controller 32 www national com I8v8e8da 5 0 Design Guidelines 5 1 TPI Network Circuit Figure 11 shows the recommended circuit for a 10 100 Mb s twisted pair interface To the right is a partial list of recommended transformers It is important that the user realize that variations with PCB and component character istics requires that the application be tested to ensure that the circuit meets the requirements of the intended applica tion RD TD Vdd TD PLACE RESISTORS AND CAPACITORS CLOSE TO THE DEVICE Figure 11 10 100 Mb s Twisted Pair Interface Pulse H1102 Pulse H2019 Pulse 0011021 Pulse J0011D21B Vdd COMMON MODE CHOKES MAY BE REQUIRED RD RD TD i 19902 gn NA TD RJ45 NOTE CENTER TAP IS PULLED TO VDD CAPACITORS CLOSE TO THE TRANSFORMER CENTER TAPS All val
105. tection requires both the 10 Mb s and 100 Mb s receivers to moni tor the receive signal and report link status to the Auto Negotiation function Auto Negotiation uses this informa tion to configure the correct technology in the event that the Link Partner does not support Auto Negotiation but is transmitting link signals that the 100BASE TX or 10BASE T recognize as valid link signals If the DP83848l completes Auto Negotiation as a result of Parallel Detection bits 5 and 7 within the ANLPAR register will be set to reflect the mode of operation present in the Link Partner Note that bits 4 0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to indicate a valid 802 3 selector field Software may deter mine that negotiation completed via Parallel Detection by reading a zero in the Link Partner Auto Negotiation Able bit once the Auto Negotiation Complete bit is set If configured for parallel detect mode and any condition other than a sin gle good link occurs then the parallel detect fault bit will be set 2 1 4 Auto Negotiation Restart Once Auto Negotiation has completed it may be restarted at any time by setting bit 9 Restart Auto Negotiation of the BMCR to one If the mode configured by a successful Auto Negotiation loses a valid link then the Auto Negotiation process will resume and attempt to determine the configu ration for the link This function ensures that a valid config uration is mai
106. ter contains the advertised abilities of the Link Partner as received during Auto Negotiation The content changes after the successful auto negotiation if Next pages are supported Table 17 Auto Negotiation Link Partner Ability Register ANLPAR BASE Page address 0x05 15 NP Next Page Indication 0 Link Partner does not desire Next Page Transfer 1 Link Partner desires Next Page Transfer Acknowledge 1 Link Partner acknowledges reception of the ability data word 0 Not acknowledged The Auto Negotiation state machine will automatically control the this bit based on the incoming FLP bursts Remote Fault 1 Remote Fault indicated by Link Partner 0 No Remote Fault indicated by Link Partner RESERVED RESERVED for Future IEEE use puse Write as 0 read as 0 ASM DIR ASYMMETRIC PAUSE 1 Asymmetric pause is supported by the Link Partner 0 Asymmetric pause is not supported by the Link Partner PAUSE 1 Pause function is supported by the Link Partner 0 Pause function is not supported by the Link Partner 100BASE T4 Support 1 100BASE T4 is supported by the Link Partner 0 100BASE T4 not supported by the Link Partner 100BASE TX Full Duplex Support 1 100BASE TX Full Duplex is supported by the Link Partner 0 100BASE TX Full Duplex not supported by the Link Partner 100BASE TX Support 1 100BASE TX is supported by the Link Partner 0 100BASE TX not supported by the Link Partner 10BASE T Full Duplex Suppo
107. terrupt on energy detect event RESERVED ED INT EN LINK INT EN SPD INT EN DUP INT EN ANC INT EN FHF INT EN RHF INT EN 0 RW Enable Interrupt on change of link status 0 RW Enable Interrupt on change of speed status 0 RW Enable Interrupt change of duplex status 0 RW Enable Interrupt on Auto negotiation complete event 0 RW Enable Interrupt on False Carrier Counter Register half full event 0 RW Enable Interrupt on Receive Error Counter Register half full event 52 www national com I8v8 8da 7 2 4 False Carrier Sense Counter Register FCSCR This counter provides information required to implement the False Carriers attribute within the MAU managed object class of Clause 30 of the IEEE 802 3u specification Table 24 False Carrier Sense Counter Register FCSCR address 0x14 RESERVED RESERVED Writes ignored Read as 0 FCSCNT 7 0 0 False Carrier Event Counter This 8 bit counter increments on every false carrier event This counter sticks when it reaches its max count FFh 7 2 5 Receiver Error Counter Register RECR This counter provides information required to implement the Symbol Error During Carrier attribute within the PHY man aged object class of Clause 30 of the IEEE 802 3u specification Table 25 Receiver Error Counter Register RECR address 0x15 RESERVED RESERVED Writes ignored Read as 0 RXERONTT 7 0 0 RO COR RX_ER Counter When a va
108. tions share the LED output pins the external components required for strapping and LED usage must be considered in order to avoid contention Specifically when the LED outputs are used to drive LEDs directly the active state of each output driver is dependent on the logic level sampled by the corresponding AN input upon power up reset For example if a given AN input is resistively pulled low then the corresponding output will be configured as an active high driver Conversely if a given AN input is resistively pulled high then the corresponding output will be configured as an active low driver Refer to Figure 3 for an example of AN connections to external components In this example the AN strapping results in Auto Negotiation with 10 100 Half Full Duplex advertised The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual purpose pins S a 2 lt a a A AN 1 ANO N N ai g S vec Figure 3 AN Strapping and LED Loading Example 19 www national com I8v8e8da 2 4 2 LED Direct Control The DP83848I provides another option to directly control any or all LED outputs through the LED Direct Control Reg ister LEDCR address 18h The register does not provide read access to LEDs 2 5 Half Duplex vs Full Dupl
109. turnaround and follows this with the required data Figure 4 shows the timing relationship between MDC and the MDIO as driven received by the Sta tion STA and the DP83848I PHY for a typical register read access For write transactions the station management entity writes data to the addressed DP83848I thus eliminating the requirement for MDIO Turnaround The Turnaround time is filled by the management entity by inserting 10 Figure 5 shows the timing relationship for a typical MII register write access 22 www national com I8v8e8da Table 5 Typical Frame Format Management Serial Protocol lt idle gt lt start gt lt op code gt lt device addr gt lt reg addr gt lt turnaround gt lt data gt lt idle gt Read Operation lt idle gt lt 01 gt lt 10 gt lt AAAAA gt lt RRRRR gt lt Z0 gt lt XXxXX XXXx gt lt idle gt Write Operation lt idle gt lt 01 gt lt 01 gt lt AAAAA gt lt RRRRR gt lt 10 gt lt xxxx XXXX gt lt gt 0 1 1 0 0 1 1 0 0 0 0 0 0 0j20 0 0 1 1 0 0 0 1 0 0 010101 Register Address Opcode Idle Start 00h BMCR PHY Address Read Register Data Idle PHYAD T Figure 4 Typical MDC MDIO Read Operation 2 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 01 0 01010 0 010 0 012 iate Start Gpcode x Register Data Write PHYAD 0Ch 00h BMC
110. ues are typical and are 1 33 www national com 137858 5 2 ESD Protection Typically ESD precautions are predominantly in effect when handling the devices or board before being installed in a system In those cases strict handling procedures need be implemented during the manufacturing process to greatly reduce the occurrences of catastrophic ESD events After the system is assembled internal compo nents are less sensitive from ESD events See Section 8 0 for ESD rating 5 3 Clock In X1 Requirements The DP83848l supports an external CMOS level oscillator Source or a crystal resonator device Oscillator If an external clock source is used X1 should be tied to the clock source and X2 should be left floating Specifications for CMOS oscillators 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 7 and Table 8 Note Maximum Reference Clock Jitter should not exceed 1ns peak to peak or 78ps rms from 50 kHz to 1 MHz Crystal 25 MHz parallel 20 pF load crystal resonator should be used if a crystal source is desired Figure 12 shows a typi cal connection for a crystal resonator circuit The load capacitor values will vary with the crystal vendors check with the vendor for the recommended loads The oscillator circuit is designed to drive a parallel reso nance AT cut crystal with a minimum drive level of 100uW and a maximum of 500uW If a crystal is specified for lower drive l
111. uld also be noted that selecting PHY Address 0 via an MDIO write to PHYCR will not put the device in Isolate Mode See Section 2 3 1 for more information For further detail relating to the latch in timing requirements of the PHY Address pins as well as the other hardware configuration pins refer to the Reset summary Section 6 0 RXD_3 RXD_2 RXD_1 Since the PHYAD 0 pin has weak internal pull up resistor and PHYAD 4 1 pins have weak internal pull down resis tors the default setting for the PHY address is 00001 01h Refer to Figure 2 for an example of a PHYAD connection to external components In this example the PHYAD strap ping results in address 00011 03h 2 3 1 MII Isolate Mode The DP83848l can be put into Isolate mode by writing to bit 10 of the BMCR register or by strapping in Physical Address 0 It should be noted that selecting Physical Address 0 via an write to PHYCR will not put the device in the MII isolate mode When in the isolate mode the DP83848l does not respond to packet data present at TXD 3 0 TX EN inputs and presents a high impedance on the TX CLK RX CLK RX DV RX ER RXD 3 0 COL and CRS outputs When in Isolate mode the 0 838481 will continue to respond to all management transactions While in Isolate mode the PMD output pair will not transmit packet data but will continue to source 100BASE TX scrambled idles or 10BASE T normal link pulses The DP83848l can Auto
112. ved from the worst case frequency vs attenuation figures as speci fied in the EIA TIA Bulletin TSB 36 These curves indicate the significant variations in signal attenuation that must be compensated for by the receive adaptive equalization cir cuit Attenuation vs Frequency 15 Attanualion 98 Rs 20 a 69 a 150m 130m 100m som 80 190 120 Frequency MHz Figure 8 EIA TIA Attenuation vs Frequency for 0 50 100 130 amp 150 meters of CAT 5 cable 28 www national com I8v8 8da 4 2 2 2 Base Line Wander Compensation Figure 9 100 BLW Event The DP83848l is completely ANSI TP PMD compliant and includes Base Line Wander BLW compensation The BLW compensation block can successfully recover the TP PMD defined killer pattern BLW can generally be defined as the change in the aver age DC content relatively short period over time of an AC coupled digital transmission over a given transmission medium i e copper wire BLW results from the interaction between the low fre quency components of a transmitted bit stream and the fre quency response of the AC coupling component s within the transmission system If the low frequency content of the digital bit stream goes below the low frequency pole of the AC coupling transformers then the droop characteris tics of the transformers will dominate resulting in potentially serious BLW The digital
113. ws the port Du plex capability to be selected 1 Full Duplex operation 0 Half Duplex operation 41 www national com I8r8 8da Table 12 Basic Mode Control Register BMCR address 0x00 Continued Collision Test Collision Test 1 Collision test enabled 0 Normal operation When set this bit will cause the COL signal to be asserted in response to the assertion of TX_EN within 512 bit times The COL signal will be de asserted within 4 bit times in response to the de assertion of TX_EN RESERVED RESERVED Write ignored read as 0 42 www national com 7 1 2 Basic Mode Status Register BMSR Bit 15 14 13 12 11 10 7 RESERVED Table 13 Basic Mode Status Register BMSR address 0x01 100BASE T4 100BASE TX Full Duplex 100BASE TX Half Duplex 10BASE T Full Duplex 10BASE T Half Duplex MF Preamble Suppression Auto Negotiation Com plete Remote Fault Auto Negotiation Abili ty Link Status Jabber Detect Extended Capability 0 RO P 1 RO P 1 RO P 1 RO P 1 RO P 1 RO P 0 RO LH 0 RO LL 0 RO LH Description 100BASE T4 Capable 0 Device not able to perform 100BASE T4 mode 100BASE TX Full Duplex Capable 1 Device able to perform 100BASE TX in full duplex mode 100BASE TX Half Duplex Capable 1 Device able to perform 100BASE TX in half duplex mode 10BASE T Full Duplex Capable 1 Device able to per
114. z_OUT 26 LED_ACT COL AN_EN 27 LED_SPEED AN1 28 LED_LINK ANO 29 RESET_N 30 MDIO 31 MDC 32 IOVDD33 33 X2 34 x1 35 IOGND 36 DGND 37 PFBIN2 38 RX_CLK 39 RX DV MII MODE 40 CRS CRS DV LED CFG VBH48A Pin Pin Name 41 RX ER MDIX EN 42 COL PHYADO 43 RXD_0 PHYAD1 44 RXD_1 PHYAD2 45 RXD_2 PHYAD3 46 RXD_3 PHYAD4 47 IOGND 48 IOVDD33 www national com Isp8esdd 2 0 Configuration This section includes information on the various configura tion options available with the DP83848l The configuration options described below include Auto Negotiation PHY Address and LEDs Half Duplex vs Full Duplex Isolate mode Loopback mode BIST 2 1 Auto Negotiation The Auto Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest per formance mode of operation supported by both devices Fast Link Pulse FLP Bursts provide the signalling used to communicate Auto Negotiation abilities between two devices at each end of a link segment For further detail regarding Auto Negotiation refer to Clause 28 of the IEEE 802 3u specification The 838481 supports four different Ethernet protocols 10 Mb s Half Duplex 10 Mb s Full Duplex 100 Mb s Half Duplex and 100 Mb s Full Duplex so the inclusion of Auto Negotiation ensures that the high est performance protocol

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