ANALOG DEVICES - Zero-Drift Digitally Programmable Sensor Signal Amplifier AD8555 handbook
Contents
1. OUTPUT lt BUFFER g 9 5 9 o tc rI gt o 9 5 n E 2 o 0 1 1 0 10 0 1000 5 LOAD nF Figure 28 Output Buffer Positive Overshoot 5 lt 5 o gt gt 10 10 0 1000 LOAD CAPACITANCE nF Figure 29 Output Buffer Negative Overshoot 1 000 Vs 2 5 0 100 SOURCE d 9 o g SINK a 3 0 010 5 a gt 0 001 8 0 01 0 10 1 00 10 0 LOAD CURRENT mA Ei Figure 30 Output Voltage to Supply Rail vs Load Current Rev 0 Page 13 of 28 AD8555 75 50 25 0 25 50 75 100 125 150 175 TEMPERATURE Figure 31 Output Short Circuit vs Temperature TIME 10015 0 Figure 32 Power On Response at 25 C TIME 100 s DIV Figure 33 Power On Response at 125 C 04598 0 031 04598 0 032 04598 0 033 108959 VOLTAGE 1V DIV PSRR dB PSRR dB SUPPLY VOLTAGEN TIME 100us DIV Figure 34 Power On Response at 40 C 140 120 100 50 25 0 25 50 75 100 TEMPERATURE Figure 35 PSRR vs Temperature 80 60 40 20 0 1 1 10 FREQUENCY kHz Figure 36 PSRR vs Frequency 100 VOUT 50mV DIV 04598 0 034 VOUT 50mV DIV 04592. Field 5 Bits 26 to 37 12 Bit End of Packet 0111 1111 1110 38 bit serial word is used divided into 6 fields Assuming Fields 0 and 5 are the start of packet and end of packet field each bit can be loaded in 60 us the 38 bit serial word transfers respectively Matching the start of packet field with 1000 0000 in 2 3 ms Table 11 summarizes the word format 0001 and the end of packet field with 0111 1111 1110 ensures that the serial word is valid and enables decoding of the other fields Field 3 breaks up the data and ensures that no data com bination can inadvertently trigger the start of packet and end of packet fields Field 0 should be written first and Field 5 written last Within each field the MSB must be written first and the LSB written last The shift register features power on reset to minimize the risk of inadvertent programming power on reset occurs when VDD is between 0 7 V and 2 2 V Rev 0 Page 20 of 28 Initial State Initially all the polysilicon fuses are intact Each parameter has the value 0 assigned see Table 12 Table 12 Initial State before Programming Second Stage Gain Code 0 Second Stage Gain 17 5 First Stage Gain Code 0 First Stage Gain 4 0 Output Offset Code 0 Output Offset VSS Master Fuse 0 Master Fuse Not Blown When power is applied to a device parameter values are taken either from internal registers if the master fuse is not blown or from the polysilicon f
3. R 10kOto 0 V 4 94 V POWER SUPPLY Supply Current Isy Vo 2 5 V VPOS VNEG 2 5V 2 0 2 5 mA VDAC Code 128 Power Supply Rejection Ratio PSRR Av 70 109 125 dB DYNAMIC PERFORMANCE Gain Bandwidth Product GBP First Gain Stage Ta 25 C 2 MHz Second Gain Stage Ta 25 C 8 MHz Output Buffer Stage 1 5 MHz Output Buffer Slew Rate SR Av 70 10 kO C 100 pF 1 2 V us Settling Time To 0 196 70 4 V Output Step 8 us NOISE PERFORMANCE Input Referred Noise Ta 25 C 1 kHz 32 nV 4Hz Low Frequency Noise Cnp p 0 1 Hz to 10 Hz 0 5 HV Total Harmonic Distortion THD Vin 16 75 mV rms f 1 kHz Av 100 100 Rev 0 Page 3 of 28 108959 Parameter DIGITAL INTERFACE Input Current DIGIN Pulse Width to Load 0 DIGIN Pulse Width to Load 1 Time between Pulses at DIGIN DIGIN Low DIGIN High DIGOUT Logic 0 DIGOUT Logic 1 Symbol two twi tws Conditions Ta 25 C Ta 25 C Ta 25 C Ta 25 C Ta 25 C Ta 25 C Ta 25 C Unit Rev 0 Page 4 of 28 At Vpp 2 7 V Vss 0 0 V 1 35 V Vo 1 35 V 40 C Ta 125 C unless otherwise specified AD8555 Table 2 Parameter Symbol Conditions Typ Max Unit INPUT STAGE Input Offset Voltage Vos 2 10 uV Input Offset Voltage Drift TcVos 25 60 nV C Input Bias Current le Ta 25 12 16 Input Offset Current los Ta 25 0 2 1 1 5
4. 0 2 x VDD are recognized as a low and voltages at DIGIN between 0 8 x VDD and VDD are recognized as a high A timing dia gram example showing the waveform for entering code 010011 into the shift register is shown in Figure 51 Rev 0 Page 19 of 28 108959 twi tws twi tws tws two tws two two tws twi WAVEFORM 04598 0 003 CODE 0 1 0 0 1 1 Figure 51 Timing Diagram for Code 010011 Table 10 Timing Specifications Timing Parameter Description Specification two Pulse Width for Loading 0 into Shift Register Between 50 ns and 10 us tw Pulse Width for Loading 1 into Shift Register gt 50 us tws Width between Pulses gt 10 us Table 11 38 Bit Serial Word Format Field No Bits Description Field 0 Bits O to 11 12 Bit Start of Packet 1000 0000 0001 Field 1 Bits 12 to 13 2 Bit Function 00 Change Sense Current 01 Simulate Parameter Value 10 Program Parameter Value 11 Read Parameter Value Field 2 Bits 14 to 15 2 Bit Parameter 00 Second Stage Gain Code 01 First Stage Gain Code 10 Output Offset Code 11 Other Functions Field 3 Bits 16 to 17 2 Bit Dummy 10 Field 4 Bits 18 to 25 8 Bit Value Parameter 00 Second Stage Gain Code 3 LSBs Used Parameter 01 First Stage Gain Code 7 LSBs Used Parameter 10 Output Offset Code All 8 Bits Used Parameter 11 Other Functions Bit 0 LSB Master Fuse Bit 1 Fuse for Production Test at Analog Devices Bit 2 Parity Fuse
5. Input Voltage Range 0 5 1 6 V Common Mode Rejection Ratio CMRR Vem 0 9 V to 1 3 V Av 70 80 92 dB 0 9 V to 1 3 V Av 1 280 96 112 dB Linearity Vo 0 2 V to 3 4 V 20 ppm Vo 0 2 V to 4 8 V 1000 ppm Differential Gain Accuracy Second Stage Gain 17 5 to 100 0 35 Second Stage Gain 140 to 200 0 5 Differential Gain Temperature Coefficient Second Stage Gain 17 5 to 100 15 ppm C Second Stage Gain 140 to 200 40 ppm C RF 14 18 22 RF Temperature Coefficient 700 ppm C DAC Accuracy Av 70 Offset Codes 8 to 248 0 7 Ratiometricity Av 70 Offset Codes 8 to 248 50 ppm Output Offset Av 70 Offset Codes 8 to 248 5 35 mV Temperature Coefficient 3 3 ppm FS C VCLAMP Input Bias Current Ta 25 C VCLAMP 2 7 V 200 nA 500 nA Input Voltage Range 1 25 2 64 V OUTPUT BUFFER STAGE Buffer Offset 7 15 mV Short Circuit Current 4 5 9 5 Output Voltage Low Vor 10 kO to5V 30 Output Voltage High Von 10kOto0V 2 64 V POWER SUPPLY Supply Current Isy Vo 1 35 V VPOS VNEG 1 35 V 2 0 mA VDAC Code 128 Power Supply Rejection Ratio PSRR 70 109 125 DYNAMIC PERFORMANCE Gain Bandwidth Product GBP First Gain Stage TA 25 2 MHz Second Gain Stage Ta 25 8 MHz Output Buffer Stage 1 5 MHz Output Buffer Slew Rate SR Av 70 10 kO C 100 pF 1 2 V us Settling Time ts To 0 1 Av 70 4 V Output Step 8 us NOISE PERFORMANCE Input Referred Noise Ta 25 C f 1 kHz 32 nV 4
6. Ordering G den ntt ee tH 28 Rev 0 Page 2 of 28 AD8555 ELECTRICAL SPECIFICATIONS At Vpp 5 0 V Vss 0 0 V Vem 2 5 V Vo 2 5 V 40 C lt Ta 125 C unless otherwise specified Table 1 Parameter Symbol Conditions Min Typ Max Unit INPUT STAGE Input Offset Voltage Vos 2 10 HV Input Offset Voltage Drift TcVos 25 65 nv C Input Bias Current lp Ta 25 12 16 22 nA 25 nA Input Offset Current los Ta 25 0 2 1 1 5 Input Voltage Range 0 6 3 8 V Common Mode Rejection Ratio CMRR Vem 0 9 V to 3 6 V Ay 70 80 92 dB 0 9 V to 3 6 V Av 1 280 96 112 dB Linearity Vo 0 2 V to 3 4 V 20 ppm Vo 0 2 V to 4 8 V 1000 ppm Differential Gain Accuracy Second Stage Gain 17 5 to 100 0 35 1 6 Second Stage Gain 140 to 200 0 5 2 5 Differential Gain Temperature Coefficient Second Stage Gain 17 5 to 100 15 40 Second Stage Gain 140 to 200 40 100 14 18 22 kO RF Temperature Coefficient 700 ppm C DAC Accuracy Av 70 Offset Codes 8 to 248 0 7 0 8 Ratiometricity Av 70 Offset Codes 8 to 248 50 ppm Output Offset 70 Offset Codes 8 to 248 5 35 mV Temperature Coefficient 33 15 ppm FS C VCLAMP Input Bias Current 25 VCLAMP 25V 200 500 Input Voltage Range 1 25 494 V OUTPUT BUFFER STAGE Buffer Offset 7 15 mV Short Circuit Current Isc 5 10 mA Output Voltage Low VoL 10kO to 5 30 mV Output Voltage High
7. and VSS A lockout trim after gain and offset adjustment further ensures field reliability The AD8555AR is fully specified over the extended industrial temperature range of 40 C to 125 C Operating from single supply voltages of 2 7 V to 5 5 V the AD8555 is offered in the narrow 8 lead SOIC package and the 4 mm x 4mm 16 lead LFCSP One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved 108959 TABLE OF CONTENTS Electrical Specifications sse 3 Absolute Maximum Ratings seen 7 Pin Configurations and Function Descriptions 8 Typical Performance Characteristics sse 9 Theory of Operation iet treten 17 Gain Values zc iet eR Hrs 18 Open Wire Fault Detection sse 19 Shorted Wire Fault Detection sss 19 Floating VPOS VNEG or VCLAMP Fault Detection 19 REVISION HISTORY 4 04 Revision 0 Initial Version Device Programming sese 19 Filtering Functions etit ete etd eee 25 Driving Capacitive Loads sse 25 P EO a EH etat 26 Single Supply Data Acquisition System 26 Using the AD8555 with Capacitive Sensors 27 Outlin Dimensions erede entere e Ib re o 28
8. DAT_SUM DAT_SUM 0 if there is an even number of 1s in the 18 bit word DAT SUM 1 if there is an odd number of 1s in the 18 bit word Examples are given in Table 13 The function of the 2 input AND gate cell and2 is to ignore the output of the parity circuit signal PAR SUM when the master fuse has not been blown PARITY ERROR is set to 0 when MFUSE 0 In the simulation mode for example parity check is disabled After the master fuse has been blown i e after the AD8555 has been programmed the output from the parity circuit signal PAR SUM is fed to PARITY ERROR Rev 0 Page 22 of 28 After the second stage gain first stage gain and output offset have been programmed SUM should be computed and the parity bit should be set equal to DAT SUM If DAT SUM is 0 the parity fuse should not be blown in order for the PFUSE signal to be 0 If DAT SUM is 1 the parity fuse should be blown to set the PFUSE signal to 1 The code to blow the parity fuse is 1000 0000 0001 10 11 10 0000 0100 0111 1111 1110 After setting the parity bit the master fuse can be blown to pre vent further programming using the code 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110 Signal PAR SUM is the output of the 2 input exclusive OR gate Cell EOR2 After the master fuse has been blown PARITY ERROR is set to PAR SUM As mentioned earlier the AD8555 behaves as a programmed amplifier when PARITY ERROR 0 no parity error On the other h
9. a Logic 1 depending on temperature supply voltage and other variables To detect this undesirable situation the sense current can be lowered by a factor of 4 using a special code The voltage devel oped across the fuse would then change from 1 5 V to 0 38 V and the output of the OTP would be a Logic 0 instead of the Logic 1 expected from a blown fuse Correctly blown fuses would still output a Logic 1 In this way incorrectly blown fuses can be detected Another special code would return the sense current to the normal larger value The sense current cannot be permanently programmed to the low value When the AD8555 is powered up the sense current defaults to the high value The code to use the low sense current is 1000 0000 0001 00 00 10 XXXX 0111 1111 1110 The code to use the normal high sense current is 1000 0000 0001 00 00 10 XXXX 0111 1111 1110 Rev 0 Page 23 of 28 108959 Suggested Programming Procedure 1 Set VDD and VSS to the desired values in the application Use simulation mode to test and determine the desired codes for the second stage gain first stage gain and output offset The nominal values for these parameters are shown in Table 6 Table 7 Equation 1 and Equation 2 the codes corresponding to these values can be used as a starting point However since actual parameter values for given codes vary from device to device some fine tuning is nec essary for the best possible accura
10. z z lt lt 20 tc u tc 2 5 e 1 i z BUT EO 3 0 3 6 9 3 0 125 250 375 500 625 750 3 Vos uV 3 TcVos nV C 3 Figure 4 Input Offset Voltage Distribution Figure 7 TcVos Vs 5 V 1 0 0 5 0 0 5 2 1 0 E 15 2 8 5 gt 20 2 5 2 k a 3 5 a Minn 1 s 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 0 12 5 25 0 37 5 50 0 62 5 75 0 Vom V 8 TcVos nV C E Figure 5 Input Offset Voltage vs Common Mode Voltage Figure 8 TcVos Vs 2 7 V 10 10 0 8 7 5 6 gt 5 0 L5 4 _ 25 NES 9 o 8 8 5 2 25 9 4 2 5 0 8 7 5 10 10 0 8 50 25 0 25 50 75 100 125 150 50 5 TEMPERATURE P TEMPERATURE C Figure 6 Input Offset Voltage vs Temperature Figure 9 Output Buffer Offset vs Temperature Rev 0 Page 9 of 28 108959 T 5 T o 5 2 d lt a 2 0 1 2 3 4 5 6 3 TEMPERATURE C 3 DIGITAL INPUT VOLTAGE V Figure 10 Input Bias Current at VPOS VNEG vs Temperature Figure 13 Digital Input Current vs Digital Input Voltage Pin 3 1000 2 100 2 o n lt d o 5 10 Vem V VCLAMP VOLT
11. 638 72 5 221 104 5 878 9 4 135 41 4 655 73 5 241 105 5 900 10 4 151 42 4 673 74 5 260 106 5 921 11 4 166 43 4 690 75 5 280 107 5 943 12 4 182 44 4 707 76 5 299 108 5 965 13 4 197 45 4 725 77 5 319 109 5 988 14 4 213 46 4 742 78 5 339 110 6 010 15 4 228 47 4 760 79 5 358 111 6 032 16 4 244 48 4 778 80 5 378 112 6 054 17 4 260 49 4 795 81 5 398 113 6 077 18 4 276 50 4 813 82 5 418 114 6 099 19 4 291 5 4 831 83 5 438 115 6 122 20 4 307 52 4 849 84 5 458 116 6 145 21 4 323 53 4 867 85 5 479 117 6 167 22 4 339 54 4 885 86 5 499 118 6 190 23 4 355 55 4 903 87 5 519 119 6 213 24 4 372 56 4 921 88 5 540 120 6 236 25 4 388 57 4 939 89 5 560 121 6 259 26 4 404 58 4 958 90 5 581 122 6 283 27 4 420 59 4 976 91 5 602 123 6 306 28 4 437 60 4 995 92 5 622 124 6 329 29 4 453 61 5 013 93 5 643 125 6 353 30 4 470 62 5 032 94 5 664 126 6 376 31 4 486 63 5 050 95 5 685 127 6 400 2 Table 7 Second Stage Gain and Gain Ranges vs Gain Code GAINISAx 122 3 Second Second Minimum Maximum 4 Stage Gain Stage Combined Combined Code Gain Gain Gain 0 17 5 70 112 1 25 100 160 2 35 140 224 3 50 200 320 4 70 280 448 5 100 400 640 6 140 560 896 7 200 800 1280 Rev 0 Page 18 of 28 OPEN WIRE FAULT DETECTION The inputs to A1 and A2 VNEG and VPOS each have a com parator to detect whether VNEG or VPOS exceeds a threshold voltage nominally VDD 1 1 V If VNEG gt VDD 1 1 V or VPOS VDD 1 1 V VOUT is clamped to VSS The out
12. 7 they allow the gain to be varied over a wide range R4 R5 R6 R7 P3 and P4 each have a similar temperature coefficient so the second stage gain temperature coefficient is lower than 100 ppm C RF together with an external capacitor connected between FILT DIGOUT and VSS or VDD form a low pass filter The filtered signal is buffered by A4 to give a low impedance output at VOUT RF is nominally 16 allowing a 1 kHz low pass filter to be implemented by connecting a 10 nF external capacitor between FILT DIGOUT and VSS or between FILT DIGOUT and VDD If low pass filtering is not needed then the FILT DIGOUT pin must be left floating A5 implements a voltage buffer which provides the positive supply to the amplifier output buffer A4 Its function is to limit VOUT to a maximum value useful for driving analog to digital converters ADC operating on supply voltages lower than VSS AD8555 VDD The input to A5 VCLAMP has a very high input resis tance It should be connected to a known voltage and not left floating However the high input impedance allows the clamp voltage to be set using a high impedance source e g a potential divider If the maximum value of VOUT does not need to be limited VCLAMP should be connected to VDD A4 implements a rail to rail input and output unity gain volt age buffer The output stage of A4 is supplied from a buffered version of VCLAMP instead of VDD allowing the positive swing to be
13. 8 0 035 VOUT 1V DIV 04598 0 068 Rev 0 Page 14 of 28 Tek Run Trig d Vg 32 5 GAIN 70 C O 1uF 10kHz TIME 100us DIV Figure 37 Small Signal Response Tek Run Trig d Vg 2 5V GAIN 70 100pF Fin 1kHz TIME 100 s DIV Figure 38 Small Signal Response Tek Run Trig d Vg 2 5V GAIN 70 100pF TIME 10 s DIV Figure 39 Large Signal Response 04598 0 036 04598 0 037 04598 0 038 108959 Tek Run Trig d Vs z2 5V GAIN 70 C 0 05uF E 2 o gt 3 2007 M1 00us Chi X 57 TIME 10us DIV 3 Figure 40 Large Signal Response Figure 43 Positive Overload Recovery Gain 70 OV 1 ViN 2 lt a ov 2 5V 04598 0 071 10 0mv aap 2 00 V _M4 00us Chl 4 9 40mV 04598 0 046 FREQUENCY kHz Figure 41 Output Impedance vs Frequency Figure 44 Negative Overload Recovery Gain 1280 ov 1 Vin Vin ov ov B Vour Vour OV 2 04598 0 069 04598 0 072 10 0mV 2 2 00 V 4 0046 A Chi x 8 40mV Chi 50 0mV 2 00V M1 00us Chi J 21 0mV Figure 42 Negative Overload Recovery Gain 70 Figure 45 Posi
14. AGE V Figure 11 Input Bias Current at VPOS VNEG vs Common Mode Voltage Figure 14 VCLAMP Current Over Temperature at Vs 5 V vs VCLAMP Voltage 0 5 1000 0 4 0 3 0 2 25 E 0 1 B 2 o o 2 9 o1 gt 0 2 5 0 3 0 4 0 5 5 50 25 0 25 50 75 100 125 150 3 TEMPERATURE C E VCLAMP VOLTAGE V Figure 12 Input Offset Current vs Temperature Figure 15 VCLAMP Current Over Temperature at Vs 2 7 vs VCLAMP Voltage Rev 0 Page 10 of 28 SUPPLY CURRENT mA SUPPLY CURRENT mA CMRR dB 1 0 gs 1 2 3 4 5 6 SUPPLY VOLTAGE V Figure 16 Supply Current vs Supply Voltage TEMPERATURE Figure 17 Supply Current vs Temperature Vg 22 5V GAIN 70 120 80 40 0 100 1k 10k 100k 1M FREQUENCY Hz Figure 18 CMRR vs Frequency CMRR dB 04598 0 014 CMRR dB 04598 0 015 VOLTAGE NOISE DENSITY nV AHz 04598 0 016 AD8555 Vg 2 5V GAIN 1280 FREQUENCY Hz Figure 19 CMRR vs Frequency TEMPERATURE C Figure 20 CMRR vs Temperature at Different Gains Vg 2 5V GAIN 70 o a 2B a ETT ein D ia ts la
15. ANALOG DEVICES Zero Drift Digitally Programmable Sensor Signal Amplifier AD8555 FUNCTIONAL BLOCK DIAGRAM VDD FEATURES Very low offset voltage 10 HV maximum over temperature Very low input offset voltage drift 60 nV C maximum High CMRR 96 dB minimum Digitally programmable gain and output offset voltage Single wire serial interface Open and short wire fault detection Low pass filtering Stable with any capacitive load Externally programmable output clamp voltage for driving low voltage ADCs LFCSP 16 and SOIC 8 packages 2 7 V to 5 5 V operation 40 C to 125 C operation APPLICATIONS Automotive sensors Pressure and position sensors Thermocouple amplifiers Industrial weigh scales Precision current sensing Strain gages GENERAL DESCRIPTION The AD8555 is a zero drift sensor signal amplifier with digi tally programmable gain and output offset Designed to easily and accurately convert variable pressure sensor and strain bridge outputs to a well defined output voltage range the AD8555 also accurately amplifies many other differential or single ended sensor outputs The AD8555 uses the ADI pat ented low noise auto zero and DigiTrim technologies to create an incredibly accurate and flexible signal processing solution in a very compact footprint Gain is digitally programmable in a wide range from 70 to 1 280 through a serial data interface Gain adjustment can be fully simulated in circuit and then
16. CITIVE LOADS The AD8555 can drive large capacitive loads This feature is useful when the amplifier placed close to the sensor has to drive long cables Most instrumentation amplifiers have diffi culty driving capacitance due to the degradation of the phase margin caused by the additional phase lag from the capacitive load Higher capacitance at the output can increase the amount of overshoot and ringing in the amplifier s step response and could even affect the stability of the device Additionally the value of the capacitive load that an amplifier can drive before oscillation varies with gain supply voltage input signal and temperature Figure 57 and Figure 58 show the overshoot response of AD8555 versus the capacitive load with a different value isolation resistor Rs in Figure 56 Similar to all amplifi ers the AD8555 responds with overshoot when driving large but after a point approximately 22 nF the overshoot decreases This is because the pole created by dominates at first how ever at some point the pole is farther in than the pole setting of the buffer amplifier and is ignored by AD8555 VDD VSS CFILTER 04598 0 054 OUTPUT BUFFER OVERSHOOT 04598 0 028 LOAD CAPACITANCE nF Figure 57 Positive Overshoot Graph vs C Rev 0 Page 25 of 28 108959 OVERSHOOT 0 1 1 0 10 0 100 0 LOAD CAPACITANCE nF 04598 0 029 Figure 58 Negative Overshoot Graph v
17. CLAMP SE VNEG a Es Pos NC 1 12 VOUT FILT DIGOUT 2 INDICATOR FH 44 NC Figure 2 8 Lead SOIC Not Drawn to Scale NC 3 AD8555 vcLAMP TOP VIEW DIGIN 4 f 9 NC o 6 M o eges 8 2 a 5 gt gt 2 NC NO CONNECT Figure 3 16 Lead LFCSP Not Drawn to Scale Table 5 Pin Configuration SOIC LFCSP Pin No Mnemonic Pin No Mnemonic Description 1 VDD N A N A Positive Supply Voltage 2 FILT DIGOUT 2 FILTDIGOUT Unbuffered Amplifier Output In Series with a Resistor RF Adding a capacitor between FILT and VDD or VSS implements a low pass filtering function In read mode this pin functions as a digital output 3 DIGIN 4 DIGIN Digital Input 4 VNEG 6 VNEG Negative Amplifier Input Inverting Input 5 VPOS 8 VPOS Positive Amplifier Input Noninverting Input 6 VCLAMP 10 VCLAMP Set Clamp Voltage at Output 7 VOUT 12 VOUT Buffered Amplifier Output Buffered version of the signal at the FILT DIGOUT pin In read mode VOUT is a buffered digital output 8 VSS N A N A Negative Supply Voltage N A N A 13 14 DVSS AVSS Negative Supply Voltage N A N A 15 16 DVDD AVDD Positive Supply Voltage N A N A 1 3 5 7 9 11 NC Do Not Connect Rev 0 Page 8 of 28 108555 TYPICAL PERFORMANCE CHARACTERISTICS 40 o 2 30 ui nm a amp
18. Hz Low Frequency Noise Cn pp 0 1 Hz to 10 Hz 0 3 uV Total Harmonic Distortion THD Vin 16 75 mV rms f 1 kHz Av 100 100 dB Rev 0 Page 5 of 28 108959 Parameter Symbol Conditions Min Max Unit DIGITAL INTERFACE Input Current 2 uA DIGIN Pulse Width to Load 0 two Ta 25 C 0 05 10 us DIGIN Pulse Width to Load 1 twi Ta 25 50 HS Time between Pulses at DIGIN tws Ta 25 C 10 HS Rev 0 Page 6 of 28 ABSOLUTE MAXIMUM RATINGS AD8555 Table 3 Table 4 Parameter Rating Package Type Osa Unit Supply Voltage 6V 8 Lead SOIC R 158 43 C W Input Voltage VSS 0 3 V to VDD 0 3 V 16 Lead LFCSP CP 44 31 5 C W Differential Input Voltage 5 0V Output Short Circuit Indefinite Duration to VSS or VDD Storage Temperature Range 65 C to 150 C 1 Differential input voltage is limited to 5 0 V or the supply voltage which Operating Temperature Range 40 C to 125 C ever is less _ amp R9 as 2 0j is specified for the worst case conditions i e is specified for device Junction mperature Rang soldered in circuit board for SOIC and LFCSP packages Lead Temperature Range 300 C Soldering 10 sec Rev 0 Page 7 of 28 108595 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 88299 vDD 1 e 8 VSS gt gt gt gt FILT DIGOUT 2 AREE VOUT D un TOP VIEW DIGIN 3 Not to Scale S
19. and VOUT is connected to VSS when a parity error has been detected i e when PARITY ERROR 1 Read Mode The values stored by the polysilicon fuses can be sent to the FILT DIGOUT pin to verify correct programming Normally the FILT DIGOUT pin is connected to only the second gain stage output via RF During read mode however the FILT DIGOUT pin is also connected to the output of a shift register to allow the polysilicon fuse contents to be read Since VOUT is a buffered version of FILT DIGOUT VOUT also out puts a digital signal during read mode Read mode is entered by setting Field 1 to 11 and selecting the desired parameter in Field 2 Field 4 is ignored The parameter value stored in the polysilicon fuses is loaded into an internal shift register and the MSB of the shift register is connected to the FILT DIGOUT pin Pulses at DIGIN shift the shift register contents out to the FILT DIGOUT pin allowing the 8 bit parameter value to be read after seven additional pulses shift ing occurs on the falling edge of DIGIN An eighth pulse at DIGIN disconnects FILT DIGOUT from the shift register and terminates the read mode If a parameter value is less than 8 bits long the MSBs of the shift register are padded with 08 For example to read the second stage gain the code 1000 0000 0001 11 00 10 0000 0000 0111 1111 1110 can be used Since the second stage gain parameter value is only three bits long the FILT DIGOUT pin has a value of 0
20. cy One way to choose these values is to set the output offset to an approximate value e g Code 128 for midsupply to allow the required gain to be determined Then set the sec ond stage gain such that the minimum first stage gain Code 0 gives a lower gain than required and the maxi mum first stage gain Code 127 gives a higher gain than required After choosing the second stage gain the first stage gain can be chosen to fine tune the total gain Finally the output offset can be adjusted to give the desired value After determining the desired codes for second stage gain first stage gain and output offset the device is ready for permanent programming Set VSS to 0 V and VDD to 5 5 V Use program mode to permanently enter the desired codes for the second stage gain first stage gain and output offset Blow the master fuse to allow the AD8555 to read data from the fuses and to prevent further programming Set VDD and VSS to the desired values in the application Use read mode with low sense current followed by high sense current to verify programmed codes Measure gain and offset to verify correct functionality Rev 0 Page 24 of 28 Suggested Algorithm to Determine Optimal Gain and Offset Codes 1 2 Determine the desired gain Ga e g using measure ments Use Table 7 to determine the second stage gain G2 such that 4 00 x 1 04 lt G4 G lt 6 4 1 04 This ensures that the first and last codes for th
21. e N E FREQUENCY kHz 04598 0 017 04598 0 018 04598 0 019 Figure 21 Input Voltage Noise Density vs Frequency 0 Hz to 10 kHz Rev 0 Page 11 of 28 108955 GAIN 70 CLOSED LOOP GAIN dB VOLTAGE NOISE DENSITY nVAHz 04598 0 021 FREQUENCY kHz Figure 22 Input Voltage Noise Density vs Frequency 0 Hz to 500 kHz 1k 10k 100k 1M FREQUENCY Hz Figure 25 Closed Loop Gain vs Frequency Measured at Filter Pin 04598 0 025 Vg 2 5 GAIN 1000 a z es lt E 5 E z o al o 8 1k 10k 100k 1M 2 8 FREQUENCY Hz TIME 1s DIV Figure 23 Low Frequency Input Voltage Noise 0 1 Hz to 10 Hz Figure 26 Closed Loop Gain vs Frequency Measured at Output Pin Vs 22 5V 8 4 gt z m B 0 z 2 8 4 8 4 1k 10k 100k 1M 10M 2 TIME 1s DIV 3 FREQUENCY Hz 2 Figure 24 Low Frequency Input Voltage Noise 0 1 Hz to 10 Hz 0 Page 12 of 28 Figure 27 Output Buffer Gain vs Frequency
22. e Description Package Option AD8555AR 40 C to 125 C 8 Lead SOIC R 8 AD8555AR REEL 40 C to 125 8 Lead SOIC R 8 AD8555AR REEL7 40 C to 125 C 8 Lead SOIC R 8 AD8555AR EVAL Evaluation Board AD8555ACP R2 40 C to 125 C 16 Lead LFCSP CP 16 AD8555ACP REEL 40 C to 125 C 16 Lead LFCSP CP 16 AD8555ACP REEL7 40 C to 125 C 16 Lead LFCSP CP 16 2004 Analog Devices Inc All rights reserved Trademarks and regis ANALOG tered trademarks are the property of their respective owners WWW ana l 0 g com se a Lal DEVICES Rev 0 Page 28 of 28
23. e a bit value of 0 Bits with a desired value of 1 need to have the associated fuse blown Since a relatively large current is needed to blow a fuse only one fuse can be reliably blown at a time Thus a given parameter value may need several 38 bit words to allow reliable programming A 5 5 V supply is required when blowing fuses to minimize the on resistance of the internal MOS switches that blow the fuse The power supply must be able to deliver 250 mA of current and at least 0 1 uF of decoupling capacitance is needed across the power pins of the device A minimum period of 1 ms should be allowed for each AD8555 fuse to blow There is no need to measure the supply current during programming the best way to verify correct program ming is to use the read mode to read back the programmed values and to remeasure the gain and offset to verify these values Programmed fuses have no effect on the gain and output offset until the master fuse is blown after blowing the master fuse the gain and output offset are determined solely by the blown fuses and the simulation mode is permanently deacti vated Parameters are programmed by setting Field 1 to 10 selecting the desired parameter in Field 2 and selecting a single bit with the value 1 in Field 4 As an example suppose the user wants to permanently set the second stage gain to 50 Parameter 00 needs to have the value 0000 0011 assigned Two bits have the value 1 so two fuses need to be bl
24. e first stage gain are not used thereby allowing enough first stage gain codes within each second stage gain range to adjust for the 396 accuracy Use simulation mode to set the second stage gain to G2 Set the output offset to allow the AD8555 gain to be measured e g use Code 128 to set it to midsupply Use Table 6 or Equation 3 to set the first stage gain code Ca such that the first stage gain is nominally GA G Measure the resulting gain Gs Gs should be within 396 of Ga Calculate the first stage gain error in relative terms Ea Gs Ga m 1 Calculate the error the number of the first stage gain codes 1 0 00370 Set the first stage gain code to Cai Ceci Measure the gain Gc Gc should be closer to Ga than to Gs Calculate the error in relative terms Ec Gc Ga 1 Calculate the error in the number of the first stage gain codes 2 0 00370 Set the first stage gain code to Cai The resulting gain should be within one code of Ga Determine the desired output offset Oa e g using the measurements Use Equation 1 to set the output offset code Co such that the output offset is nominally Measure the output offset Os Os should be within 3 of Oa Calculate the error in relative terms Eo Op Oa 1 Calculate the error in the number of the output offset codes Cro Eo1 0 00392 Set the output offset code to Co Measure the outpu
25. h no differential offset This common mode shift is attenuated by the AD8555 common mode rejection Further more changes in input bias current e g with temperature manifest as an input common mode change also rejected by the AD8555 VDD 04598 0 060 Figure 62 Recommended Way of Using the AD8555 with Capacitive Sensors Rev 0 Page 27 of 28 108595 OUTLINE DIMENSIONS 5 00 0 1968 MS 0 1890 H H R R 4 00 0 1574 6 20 0 2440 3 80 0 1497 5 80 0 2284 Oo Oo 8 B 1 27 0 0500 27 0 0 50 0 0196 BSC 1 75 0 0688 0 25 0 0099 9 0 25 0 0098 1 35 0 0532 0 10 0 0040 0 51 0 0201 KA 8 COPLANARITY SEATING 0 37 0 0122 0 25 0 0098 0 1 27 0 0500 0 10 0 1710 0067 0 40 0 0157 PLANE 0 17 0 0067 COMPLIANT TO JEDEC STANDARDS MS 012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 63 8 Lead Standard Small Outline Package SOIC Narrow Body R 8 Dimensions shown in millimeters inches PIN 1 INDICATOR 1 00 0 85 0 35 0 80 0 28 0 20 ANARITY SEATING 0 25 0 08 PLANE COMPLIANT TO JEDEC STANDARDS MO 220 VGGC Figure 64 16 Lead Lead Frame Chip Scale Package LFCSP 4 mm x 4 mm Body CP 16 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Packag
26. limited The maximum output current is limited between 5 mA to 10 mA An 8 bit digital to analog converter DAC is used to generate a variable offset for the amplifier output This DAC is guaranteed to be monotonic To preserve the ratiometric nature of the input signal the DAC references are driven from VSS and VDD and the DAC output can swing from VSS Code 0 to VDD Code 255 The 8 bit resolution is equivalent to 0 39 of the differ ence between VDD and VSS e g 19 5 mV with a 5 V supply The DAC output voltage VDAC is given approximately by Code 0 5 VDACx VDD 85 VSS 1 256 The temperature coefficient of VDAC is lower than 200 ppm C The amplifier output voltage VOUT is given by VOUT GAIN VPOS VNEG VDAC 2 where GAIN is the product of the first and second stage gains 04598 0 001 Figure 49 AD8555 Functional Schematic Rev 0 Page 17 of 28 108959 GAIN VALUES Table 6 First Stage Gain vs Gain Code First Stage First Stage First Stage First Stage Gain Code First Stage Gain Gain Code First Stage Gain Gain Code First Stage Gain Gain Code First Stage Gain 0 4 000 32 4 503 64 5 069 96 5 706 1 4 015 33 4 520 65 5 088 97 5 727 2 4 030 34 4 536 66 5 107 98 5 749 3 4 045 35 4 553 67 5 126 99 5 770 4 4 060 36 4 570 68 5 145 100 5 791 5 4 075 37 4 587 69 5 164 101 5 813 6 4 090 38 4 604 70 5 183 102 5 834 7 4 105 39 4 621 71 5 202 103 5 856 8 4 120 40 4
27. nals to single supply analog to digital converters ADCs presents a challenge The bipolar signal must be mapped into the input range of the ADC Figure 60 shows how this translation can be achieved The output offset can be programmed to a desirable level to accommodate the input voltage requirement of the ADC 12 BIT 5 AD7476 AD8555 04598 0 058 Figure 60 A Single Supply Data Acquisition Circuit Using the AD8555 Rev 0 Page 26 of 28 The bridge circuit with a sensitivity of 2 mV V is excited by a 5 V supply The full scale output voltage from the bridge 10 mV therefore has a common mode level of 2 5 V The AD8555 removes the common mode component and amplifies the input signal by a factor of 200 G1 4 G2 50 Offset 128 This results in an output signal of 2 0 V In order to pre vent this signal from running into the AD8555 s ground rail the output offset voltage has to be raised to 2 5 V This signal is within the input voltage range of the ADC USING THE AD8555 WITH CAPACITIVE SENSORS Figure 61 shows a crude way of using the AD8555 with capaci tive sensors and R resistors implementing a potential divider to bias VNEG to VDD 2 Recommended values range from 1 kO to 1 MQ Cs is the capacitive sensor and Rs is a shunt resistor used to prevent leakage currents from integrating on the sensor The value of Rs is application specific Note that although VNEG is tied to a dc voltage the o
28. nly impedance across the capacitive sensor is Rs Therefore the only way for charge to leak away from Cs is through Rs assuming the input bias currents at VPOS and VNEG are negligible VDD 04598 0 059 Figure 61 Crude Way of Using the AD8555 with Capacitive Sensors The weakness of the circuit in Figure 61 is that the AD8555 input bias current at VPOS flows into Rs and creates a differen AD8555 tial offset voltage between VPOS and VNEG This differential offset voltage is amplified by the AD8555 The input bias cur rent at VNEG on the other hand flows into Rr and create common mode shift This has little impact on VOUT Despite this weakness the arrangement in Figure 61 should work if the user wants to minimize the number of components around the sensor and if the error introduced by the input bias current at VPOS is considered negligible If greater accuracy is needed the circuit in Figure 62 is recom mended Re and Cs are the same as in Figure 61 Rei and R should be between 1 to 1 Rs in Figure 61 has been split into two resistors Rs and Rs in Figure 62 Again the only way for the capacitive sensor to discharge is through Rs Rs The input bias current at VPOS flows through Rs and and the input bias current at VNEG flows through Rs and If is made equal to Rs and if the input bias currents are equal the input bias currents give common mode shift at VPOS and VNEG wit
29. own Since only one fuse can be blown at a time the code 1000 0000 0001 10 00 10 0000 0010 0111 1111 1110 can be used to blow one fuse The MOS switch that blows the fuse closes when the complete packet is recognized and opens when the start of packet dummy or end of packet fields are no longer valid After 1 ms the second code 1000 0000 0001 10 00 10 0000 0001 0111 1111 1110 can be entered to blow the second fuse To set the first stage gain permanently to a nominal value of 4 151 Parameter 01 needs to have the value 000 1011 assigned Three fuses need to be blown and the following codes can be used with a 1 ms delay after each code 1000 0000 0001 10 01 10 0000 1000 0111 1111 1110 1000 0000 0001 10 01 10 0000 0010 011111111110 1000 0000 0001 10 01 10 0000 0001 011111111110 To set the output offset permanently to a nominal value of 1 260 V when VDD 5 V and VSS 0 V Parameter 10 needs to have the value 0100 0000 assigned One fuse needs to be blown and the following code can be used 1000 0000 0001 10 10 10 0100 0000 0111 1111 1110 Finally to blow the master fuse to deactivate the simulation mode and prevent further programming the code 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110 can be used There are a total of 20 programmable fuses Since each fuse requires 1 ms to blow and each serial word can be loaded in 2 3 ms the maximum time needed to program the fuses can be as low as 66 ms Parity Error Detection A pa
30. permanently programmed with proven and reliable poly fuse technology Output offset voltage is also digitally programmable and is ratiometric to the supply voltage Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners VNEG O VOUT FILT DIGOUT VPOS O 04598 0 001 Figure 1 In addition to extremely low input offset voltage and input off set voltage drift and very high dc and ac CMRR the AD8555 also includes a pull up current source at the input pins and a pull down current source at the VCLAMP pin This allows open wire and shorted wire fault detection A low pass filter function is implemented via a single low cost external capacitor Output clamping set via an external reference voltage allows the AD8555 to drive lower voltage ADCs safely and accurately When used in conjunction with an ADC referenced to the same supply the system accuracy becomes immune to normal supply voltage variations Output offset voltage can be adjusted with a resolution of better than 0 4 of the difference between VDD
31. put current limit circuit is disabled in this mode but the maximum sink current is approximately 50 mA when VDD 5 V The inputs to 1 and A2 VNEG and VPOS are also pulled up to VDD by currents IP1 and IP2 These are both nominally 18 nA and matched to within 5 nA If the inputs to A1 or A2 are acci dentally left floating e g an open wire fault IP1 and IP2 pull them to VDD which would cause VOUT to swing to VSS al lowing this fault to be detected It is not possible to disable IP1 and IP2 nor the clamping of VOUT to VSS when VNEG or VPOS approaches VDD SHORTED WIRE FAULT DETECTION The AD8555 provides fault detection the case where VPOS VNEG or VCLAMP shorts to VDD and VSS Figure 50 shows the voltage regions at VPOS VNEG and VCLAMP that trigger an error condition When an error condition occurs the VOUT pin is shorted to VSS Table 8 lists the voltage levels shown in Figure 50 VPOS VCLAMP VINL VINL L ERROR vss ERROR vss 04598 0 002 Figure 50 Voltage Regions at VPOS VNEG and VCLAMP That Trigger a Fault Condition Table 8 Typical VINL VINH and VCLL Values VDD 5 V AD8555 FLOATING VPOS VNEG OR VCLAMP FAULT DETECTION A floating fault condition at the VPOS VNEG or VCLAMP pins is detected by using a low current to pull a floating input into an error voltage range which is defined in the previous section In this way the VOUT pin is shorted to VSS when a floating input is detec
32. rity check is used to determine whether the programmed data of an AD8555 is valid or whether data corruption has occurred in the nonvolatile memory Figure 52 shows the sche matic implemented in the AD8555 Rev 0 Page 21 of 28 108959 0 VA1 VA2 VBO VB1 VB2 VB3 VB4 VB5 VB6 vco vc2 vc4 vcs VC6 DOT SUM EOR18 OUT dp n PAR SUM PARITY ERROR EOR2 MFUSE 04598 0 004 Figure 52 Functional Circuit of AD8555 Parity Check Table 13 Examples of DAT SUM Second Stage Gain Code First Stage Gain Code Output Offset Code Number of Bits with 1 DAT SUM 000 000 0000 0000 0000 0 0 000 000 0000 1000 0000 1 1 000 000 0000 1000 0001 2 0 000 000 0001 0000 0000 1 1 000 100 0001 0000 0000 2 0 001 000 0000 0000 0000 1 1 001 000 0001 1000 0000 3 1 111 1111111 11111111 18 0 When PARITY ERROR is 0 the AD8555 behaves as a pro grammed amplifier When PARITY ERROR is 1 a parity error has been detected and VOUT is connected to VSS VAO to VA2 is the 3 bit control signal for the second stage gain VBO to VB6 is the 7 bit control signal for the first stage gain and VCO to VC7 is the 8 bit control signal for the output offset PFUSE is the signal from the parity fuse and MFUSE is the The 18 bit data signal VAO to VA2 VBO to VB6 and to signal from the master fuse VC7 is fed to an 18 input exclusive OR gate Cell EOR18 The output of Cell EOR18 is the signal
33. s C RF INTERFERENCE All instrumentation amplifiers show dc offset as the result of rectification of high frequency out of band signals that appear at their inputs The circuit in Figure 59 provides good RFI sup pression without reducing performance within the AD8555 pass band Resistor R1 and Capacitor C1 and likewise Resistor R2 and Capacitor C2 form a low pass RC filter that has a 3 dB bandwidth equal 1 2 m x x C1 It can be seen that R1 R2 and C2 form a bridge circuit whose output appears across the amplifiers input pins Any mismatch between C1 C2 unbalances the bridge and reduce the common mode rejection Using the component values shown this filter has a bandwidth of approximately 40 kHz To preserve common mode rejection in the AD85555 pass band capacitors need to be 596 silver mica or better and should be placed as close to its inputs as possible Resistors should be 196 metal film Capacitor C3 is VDD VNEG 1000 1000 1000 u 1000 V0 O SpIGIN needed to maintain common mode rejection at low frequencies This introduces a second low pass network R1 R2 and C3 that has a 3 dB frequency equal to 1 2 n x R1 R2 C3 This circuits 3 dB signal bandwidth is approximately 4 kHz when a C3 value of 0 047 uF is used see Figure 59 VDD vss 04598 0 057 Figure 59 RFI Suppression Method SINGLE SUPPLY DATA ACQUISITION SYSTEM Interfacing bipolar sig
34. t offset Oc Oc should be closer to O4 than to Os Calculate the error in relative terms Eo 1 Calculate the error in the number of the output offset codes Eo2 0 00392 Set the output offset code to Coi Czoi Croz The resulting offset should be within one code of FILTERING FUNCTION The AD85555 FILT DIGOUT pin can be used to create a simple low pass filter AD8555 s internal 18 resistor can be used with an external capacitor for this purpose Typical responses of the AD8555 configured for a gain of 70 and gain of 1280 are shown in Figure 54 and Figure 55 respectively This filtering feature can be used to pass the signals within the filter s pass band while limiting the out of band signals bandwidth and therefore reducing the noise of the overall solution VDD vss 2 FILT DIGOUT VOUT 7 3 DIGIN VCLAMP 6 4 VNEG VPOS AD8555 O VDD 04598 0 051 10 100 1k 10k 50k 04598 0 052 Figure 54 Typical Response of the AD8555 at FILT DIGOUT Pin Gain 70 CriLTER 0 0014F 60 40 3 Critter 0 010uF 20 0 CFILTER 0 100uF 10 100 1k 10k 100k 04598 0 053 Figure 55 Typical Response of the AD8555 at FILT DIGOUT Pin Gain 1280 AD8555 DRIVING CAPA
35. ted Table 9 lists the currents used Table 9 Floating Fault Detection at VPOS VNEG and VCLAMP Pin Typical Current Goal of Current Pull VPOS above VINH Pull VNEG above VINH Pull VCLAMP below VCLL VPOS 16 nA pull up VNEG 16 nA pull up VCLAMP 0 2 uA pull down Voltage Typical Min Typical Max Purpose VINH 3 9V 4 2V Short to VDD Fault Detection VINL 0 195 V 0 55 V Short to VSS Fault Detection VCLL 1V 12 Short to VSS Fault Detection DEVICE PROGRAMMING Digital Interface The digital interface allows the first stage gain second stage gain and output offset to be adjusted and allows desired values for these parameters to be permanently stored by selectively blowing polysilicon fuses To minimize pin count and board space a single wire digital interface is used The digital input pin DIGIN has hysteresis to minimize the possibility of inad vertent triggering with slow signals It also has a pull down current sink to allow it to be left floating when programming is not being performed The pull down ensures inactive status of the digital input by forcing a dc low voltage on DIGIN A short pulse at DIGIN from low to high and back to low again e g between 50 ns and 10 us long loads a 0 into a shift register A long pulse at DIGIN e g 50 us or longer loads a 1 into the shift register The time between pulses should be at least 10 us Assuming 55 0 V voltages at DIGIN between VSS
36. tive Overload Recovery Gain 1280 Rev 0 Page 15 of 28 108955 10kQ 817 2 00mV 1 00 6 Al CI V 1kQ 10kQ GAIN 70 OFFSET 128 Vg 2 5V 1 7 40 0mV Figure 46 Settling Time 0 1 GAIN 70 OFFSET 128 10kQ 817 2 00mV v Mi1 00us A Chi V 1kQ 10kQ Vg 2 5V 40 0mV Figure 47 Settling Time 0 01 04598 0 073 04598 0 074 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY Hz Figure 48 THD vs Frequency Rev 0 Page 16 of 28 04598 0 075 THEORY OF OPERATION A1 A2 R1 R2 R3 P1 and P2 form the first gain stage of the differential amplifier 1 and A2 are auto zeroed op amps that minimize input offset errors P1 and P2 are digital potentiome ters guaranteed to be monotonic Programming P1 and P2 allows the first stage gain to be varied from 4 0 to 6 4 with 7 bit resolution see Table 6 and Equation 3 giving a fine gain adjustment resolution of 0 3796 R1 R2 R3 P1 and P2 each have a similar temperature coefficient so the first stage gain temperature coefficient is lower than 100 ppm C A3 R4 R5 R6 R7 P3 and P4 form the second gain stage of the differential amplifier A3 is also an auto zeroed op amp that minimize input offset errors P3 and P4 are digital potentiome ters allowing the second stage gain to be varied from 17 5 to 200 in eight steps see Table
37. uses if the master fuse is blown Programmed values have no effect until the master fuse is blown The internal registers feature power on reset so that unprogrammed devices enter a known state after power up power on reset occurs when VDD is between 0 7 V and 2 2 V Simulation Mode The simulation mode allows any parameter to be changed tem porarily These changes are retained until the simulated value is reprogrammed the power is removed or the master fuse is blown Parameters are simulated by setting Field 1 to 01 select ing the desired parameter in Field 2 and the desired value for the parameter in Field 4 Note that a value of 11 for Field 2 is ignored during the simulation mode Examples of temporary settings follow By setting the second stage gain code Parameter 00 to 011 and the second stage gain to 50 1000 0000 0001 01 00 10 0000 0011 0111 1111 1110 is the result By setting the first stage gain code Parameter 01 to 000 1011 and the first stage gain to 4 166 1000 0000 0001 01 01 10 0000 1011 0111 1111 1110 is the result first stage gain of 4 166 with a second stage gain of 50 gives a total gain of 208 3 This gain has a maximum tolerance of 2 596 e Set the output offset code Parameter 10 to 0100 0000 and the output offset to 1 260 V when VDD 5 V and VSS 0 V This output offset has a maximum tolerance of 0 896 1000 0000 0001 01 10 10 0100 0000 0111 1111 1110 Programming Mode Intact fuses giv
38. when this code is entered and remains 0 during four additional pulses at DIGIN The fifth sixth and seventh pulse at DIGIN returns the 3 bit value at FILT DIGOUT the seventh pulse returning the LSB An eighth pulse at DIGIN terminates the read mode AD8555 Sense Current A sense current is sent across each polysilicon fuse to determine whether it has been blown or not When the voltage across the fuse is less than approximately 1 5 V the fuse is considered not blown and Logic 0 is output from the OTP cell When the volt age across the fuse is greater than approximately 1 5 V the fuse is considered blown and Logic 1 is output When the AD8555 is manufactured all fuses have a low resis tance When a sense current is sent through the fuse a voltage less than 0 1 V is developed across the fuse This is much lower than 1 5 V so Logic 0 is output from the OTP cell When a fuse is electrically blown it should have a very high resistance When the sense current is applied to the blown fuse the voltage across the fuse should be larger than 1 5 V so Logic 1 is output from the OTP cell It is theoretically possible though very unlikely for a fuse to be incompletely blown during programming assuming the required conditions are met In this situation the fuse could have a medium resistance neither low nor high and a voltage of approximately 1 5 V could be developed across the fuse Thus the OTP cell could sometimes output Logic 0 or
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