LINEAR TECHNOLOGY LT1725 General Purpose Isolated Flyback Controller Manual
Contents
1. Minimum Switch On Time vs Minimum Enable Time vs Enable Delay Time vs Temperature Temperature Temperature 275 F 275 50k RMINENAB 50k 250 _ 250 250 2 225 gt 225 225 gt 2 200 CETT lt 200 m c 5 175 2 175 175 2 150 150 150 125 125 Fx O 125 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 TEMPERATURE C TEMPERATURE C TEMPERATURE C 1725610 1725 611 1725 612 Feedback Amplifier Output Current Feedback Amplifier vs FB Pin Voltage Transconductance vs Temperature 80 1600 3 amp 60 1400 cc lt a S 1200 5 20 8 E 9 1000 p Em 800 20 600 40 E 60 400 fre m 80 200 n l jt _ 105 110 115 120 125 130 135 140 50 25 0 25 50 75 100 125 FB PIN VOLTAGE V TEMPERATURE C 1725 G13 1725 G14 Soft Start Charging Current vs Soft Start Sink Current vs Temperature Temperature 60 V SFST OV V SFST 1 5V zi 50 20 5 40 m 2 d g m 10 lt lt 22 ke 05 10 9 72 0 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 TEMPERATURE C TEMPERATURE C 1725 G152. Temperature 6 50 6 25 6 00 5 S 575 e amp 5 50 m c 2 5 25 S 5 00 4 15 50 25 0 25 50 75 100 125 TEMPERATURE C 1725 602 UVLO Pin Input Current vs Temperature 3 2 gt a a 2 50 25 0 25 50 75 100 125 TEMPERATURE C 1725 G05 Vcc Vaare VS Isource 0 5 1 0 gt TA 125 C ats r 2 2 5 3 0 1 10 100 1000 Isource 1725 608 START UP CURRENT uA Start Up Current vs Temperature 250 200 150 100 0 25 0 2 50 75 100 125 TEMPERATURE C 1725 603 Oscillator Frequency vs Temperature 115 OSCILLATOR FREQUENCY kHz 110 105 100 95 90 50 25 0 25 50 75 100 125 TEMPERATURE 1725 606 Vc Clamp Voltage Switching Threshold vs Temperature 3 0 2 5 CLAMP VOLTAGE 2 0 Vc CLAMP VOLTAGE SWITCHING THRESHOLD V 1 5 1 0 SWITCHING THRESHOLD 0 5 0 LL AA 50 25 0 25 50 75 100 125 TEMPERATURE C 1725 G09 1725fa neve 11725 TYPICAL PERFORMANCE CHARACTERISTICS
3. MINENAB OSCAP SGND Vc UVLO FB 3VouT GN PACKAGE S PACKAGE 16 LEAD PLASTIC SSOP 16 LEAD PLASTIC SO Tymax 125 C 110 C W GN Tymax 125 C 100 C W 50 ORDER PART NUMBER GN PART MARKING LT1725CGN 1725 LT1725IGN 1725 LT1725CS LT17251S Order Options Tape and Reel Add TR Lead Free Add ZPBF Lead Free Tape and Reel Add ZTRPBF Lead Free Part Marking http www linear com leadfree Consult LTC Marketing for parts specified with wider operating temperature ranges ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range otherwise specifications are at Ta 25 C Vec 14V GATE open Vc 1 4V unless otherwise noted SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply Vcc Vcc Turn On Voltage e 140 15 1 16 0 V Vcc Turn Off Voltage e 8 9 7 11 V Voc Hysteresis Note 3 VTURN 0N VTURN OFF 40 5 4 6 5 V lec Supply Current Vc Open 6 10 15 mA Start Up Current 120 280 uA Feedback Amplifier Feedback Voltage 1 230 1 245 1 260 V 1 220 1 270 Feedback Pin Input Current 500 nA m Feedback Amplifier Transconductance Alc 10uA 400 1000 1800 umho lsnc Isuk Feedback Amplifier Source or Sink Current e 30 50 80 VeL Feedback Amplifier Clamp Voltage 2 5 V Reference Voltage Current Line Regulation 12V lt Vin lt 18V e 0 01 0 05
4. Voltage Gain V 1V to 2V 2000 VN Soft Start Charging Current Vsest 25 40 50 uA Soft Start Discharge Current Vsest 1 5V Vuvio 0 8 1 5 mA 1725fa LI Ure 11725 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range otherwise specifications are at TA 25 C Vec 14V GATE open Ve 1 4V unless otherwise noted SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Gate Output Output High Level Igate 100mA e 12 1 V Igate 500mA 11 8 Output Low Level Igate 100mA 0 3 0 45 Igate 500mA 0 6 1 0 IGATE Output Sink Current in Shutdown Vyyig OV 2V 12 2 5 tr Rise Time C 1000pF 30 ns 9 Fall Time 1000pF 30 ns Current Amplifier Vc Control Pin Threshold Duty Cycle Min 0 90 1 12 1 25 V e 0 80 1 35 V VisENSE Switch Current Limit Duty Cycle lt 30 220 250 270 mV Duty Cycle lt 30 e 200 280 mV Duty Cycle 8096 220 mV AVisENSE AVc 0 30 mV Timing f Switching Frequency Coscap 100pF 90 100 115 kHz e 80 125 kHz CoscAP Oscillator Capacitor Value Note 2 33 200 pF ton Minimum Switch On Time Rion 50k 200 ns tep Flyback Enable Delay Time 50k 200 ns ten Minimum Flyback Enable Time Renae 50k 200 ns Ri Timing Resistor Value Note 2 24 200 kQ Maximum Switch Duty Cycle
5. ten to Vour lour Which yields a minimum output constraint 1 1 2 loUT MIN Er Js ten where f switching frequency transformer secondary side inductance Vout output voltage tep enable delay time tey minimum enable time Note that generally depending on the particulars of input and output voltages and transformer inductance one of the above constraints will prove more restrictive In other words the minimum load current in a particular applica tion will be either output switch minimum on time constrained or minimum flyback pulse time constrained A final note Lpg and Lsgc refer to transformer induc tance as seen from the primary or secondary side respec tively This general treatment allows these expressions to be used when the transformer turns ratio is nonunity 1725fa 19 11725 APPLICATIONS INFORMATION MAXIMUM LOAD SHORT CIRCUIT CONSIDERATIONS The LT1725 is a current mode controller It uses the Vc node voltage as an input to a current comparator which turns off the output switch on a cycle by cycle basis as this peak current is reached The internal clamp on the Vc node nominally 2 5V then acts as an output switch peak current limit This 2 5V at the Vc pin corresponds to a value of 250mV at the Isense pin when the ON switch duty cycle is less than 40 For a duty cycle above 40 the internal slope compensation mechanism lowers the effective
6. 1725fa 20 LT LIAR 11725 APPLICATIONS INFORMATION SWITCH NODE CONSIDERATIONS For maximum efficiency gate drive rise and fall times are made as short as practical To prevent radiation and high frequency resonance problems proper layout of the components connected to the IC is essential especially the power paths primary and secondary B field mag netic radiation is minimized by keeping MOSFET leads output diode and output bypass capacitor leads as short as possible E field radiation is kept low by minimizing the length and area of all similar traces A ground plane should always be used under the switcher circuitry to prevent interplane coupling The high speed switching current paths are shown sche matically in Figure 8 Minimum lead length in these paths are essential to ensure clean switching and minimal EMI The path containing the input capacitor transformer pri mary and MOSFET and the path containing the trans former secondary output diode and output capacitor contain nanosecond rise and fall times Keep these paths as short as possible PATH GATE DISCHARGE GATE DRIVE RESISTOR CONSIDERATIONS The gate drive circuitry internal to the LT1725 has been designed to have as low an output impedance as practi cally possible only a few ohms A strong L C resonance is potentially presented by the inductance of the path leading to the gate of the power MOSFET and its overall gat
7. ESR R2 where Vour desired output voltage Vr switching diode forward voltage ESR Secondary resistive losses Veg data sheet reference voltage value Nsr effective secondary to third winding turns ratio The above equation defines only the ratio of R1 to R2 not their individual values However a Second equation for two unknowns is obtained from noting that the Thevenin impedance of the resistor divider should be roughly 3k for bias current cancellation and other reasons SELECTING Rocmp RESISTOR VALUE The Operation section previously derived the following expressions for Roy i e effective output impedance and the external resistor value required for its nominal compensation 1 ESR R K1 Beense ate OUT While the value for may therefore be theoretically determined it is usually better in practice to employ empirical methods This is because several ofthe required input variables are difficult to estimate precisely For instance the ESR term above includes that of the trans former secondary but its effective ESR value depends on high frequency behavior not simply DC winding resis tance Similarly K1 appears to be a simple ratio of Viy to Vour times differential efficiency but theoretically esti mating efficiency is not a simple calculation The sug gested empirical method is as follows Build a prototype of the desired suppl
8. ECHNOLOGY FEATURES Drives External Power MOSFET with External Isense Resistor Application Input Voltage Limited Only by External Power Components Senses Output Voltage Directly from Primary Side Winding No Optoisolator Required Accurate Regulation Without User Trims Regulation Maintained Well into Discontinuous Mode Switching Frequency from 50kHz to 250kHz with External Capacitor Optional Load Compensation Optional Undervoltage Lockout Available in 16 Pin SO and SSOP Packages APPLICATIONS Telecom Isolated Converters m Offline Isolated Power Supplies m Instrumentation Power Supplies 7 LTC and LT are registered trademarks of Linear Technology Corporation All other trademarks are the property of their respective owners PD 171725 General Purpose Isolated Flyback Controller DESCRIPTION LT 1725 is a monolithic switching regulator control ler specifically designed for the isolated flyback topology It drives the gate of an external MOSFET and is generally powered from a third transformer winding These features allow for an application input voltage limited only by external power path components The third transformer winding also provides output voltage feedback informa tion such that an optoisolator is not required Its gate drive capability coupled with a suitable external MOSFET can deliver load power up to tens of watts The LT1725 has a number of features not found on most other swi
9. voltage limit For example at a duty cycle of 80 the nominal Isense voltage limit is 220mV This action be comes the switch current limit specification Maximum available output power is then determined by the switch current limit which is somewhat duty cycle dependent due to internal slope compensation action Overcurrent conditions are handled by the same mecha nism The output switch turns on the peak current is quickly reached and the switch is turned off Because the output switch is only on for a small fraction of the available period power dissipation is controlled Loss of current limit is possible under certain conditions Remember that the LT1725 normally exhibits a minimum switch on time irrespective of currenttrip point Ifthe duty cycle exhibited by this minimum on is greater than the ratio of secondary winding voltage referred to primary divided by input voltage then peak current will not be controlled at the nominal value and will cycle by cycle ratchet up to some higher level Expressed mathemati cally the requirement to maintain short circuit control is lsc Vin ton f where ton output switch minimum on time f switching frequency Isc short circuit output current Vr output diode forward voltage at lac resistance of transformer secondary Vin input voltage secondary to primary turns ratio Nsgc Npgi Trouble is typically only encountered
10. 85 90 Load Compensation Sense 0ffset Voltage 2 5 mV Current Gain Factor 0 80 0 95 1 05 mV UVL0 Function VuvLo UVLO Pin Threshold e 121 1 25 1 29 V luvo UVLO Pin Bias Current Vuvio 1 2V 0 25 0 1 0 25 Vuvio 1 3V 4 50 3 5 2 50 3V Output Function VREF Reference Output Voltage ILoap 1mA 2 8 3 0 3 2 Output Impedance 10 Q Current Limit e 8 15 mA Vote 1 Absolute Maximum Ratings are those values beyond which the life of a device may be impaired Note 2 Component value range guaranteed by design Vote 3 The Vcc turn on turn off voltages and hysteresis voltage are proportional in magnitude to each other guaranteed by design 1725fa 3 11725 TYPICAL PERFORMANCE CHARACTERISTICS Vcc Turn On Voltage vs Temperature 16 00 15 75 ON VOLTAGE V a a a S z 15 00 Vec TURN a 14 50 14 25 50 25 0 25 50 75 100 125 TEMPERATURE C 1725 601 Supply Current vs Temperature 13 12 E 11 m gt 10 a e 72 9 8 50 25 0 25 50 75 100 125 TEMPERATURE C 1725 604 VS Isink 0 8 ed 05 y i Ty 25 C A J gt 04 A 02 E TA 55 C 0 1 10 100 1000 Isink mA 1725 G07 Vcc Hysteresis Voltage vs
11. MOSFET D1 Motorola MBRD660 6A 60V Schottky diode D2 Motorola MBRS1100 1A 100V Schottky diode D3 D4 1N5257 33V 500mW Zener diode D5 BAS16 75V rectifier diode C1 AVX TPSD226M025R0200 22uF 25V tantalum Capacitor C2a C2b C2c Vishay Vitramon VJ1825Y155MXB 1 5uF 100V X7R ceramic capacitor C3 100pF 100V X7R ceramic capacitor C4 Sanyo 20SV150M 150uF 20V OS CON electrolytic capacitor C5 1uF 25V Z5U ceramic capacitor C6 1nF 25V X7R ceramic capacitor C7 47pF 25V NPO COG ceramic capacitor Application Efficiency Vin 48V Vour 15 EFFICIENCY 0 01 0 1 1 10 1725 F09c C8 0 1uF 25V Z5U ceramic capacitor C9 470pF 25V X7R ceramic capacitor C10 100pF 25V X7R ceramic capacitor R1 24k 1 4W 5 resistor R2 IRC LR2010 0 10 1 2W current sense resistor R3 34 0k 1 resistor R4 3 01k 1 resistor R5 R6 R7 51k 5 resistor R8 6 2k 5 resistor R9 510 5 resistor R10 180 5 resistor R11 150Q 1 4W 5 resistor R12 5 1Q 5 resistor R13a R13b 1 5k 1 2W 5 resistor R14 820k 5 resistor R15 33k 5 resistor 1725fa 23 11725 TYPICAL APPLICATIONS TELECOM 48V TO ISOLATED 5V APPLICATION The design in Figure 10 accepts an input voltage in the range of 36V to 72V and outputs an isolated 5V at up to 2A Transformer T1 is available as a Coi
12. oscillator switching frequency See Applications Informa tion for details Vc pin 7 This is the control voltage pin which is the output of the feedback amplifier and the input of the current comparator Frequency compensation of the overall loop is effected in most cases by placing a capaci tor between this node and ground FB Pin 8 Input pin for external feedback resistor divider The ratio of this divider times the internal bandgap reference times the effective output to third winding transformer turns ratio is the primary deter minant of the output voltage The Thevenin equivalent resistance of the feedback divider should be roughly 3k See Applications Information for more details Pin 9 Output pin for nominal 3V reference This facilitates various user applications This node is internally current limited for protection and is intended to drive either moderate capacitive loads of several hundred pF or less or very large capacitive loads of 0 1uF or more See Applications Information for more details UVLO Pin 10 This pin allows the use of an optional external resistor divider to set an undervoltage lockout based upon Viy not Voc level Note If the Vcc voltage is sufficient to allow the part to start up but the UVLO pin is held below its threshold output switching action will be disabled but the part will draw its normal quiescent current from Voc This typically causes a benign relaxat
13. CcoMP PARASITIC 7 Lp FOR CANCELLATION L INDUCTANCE Ccomp TT 1725 05 Figure 5 SOFT START FUNCTION The LT1725 contains an optional soft start function that is enabled by connecting an explicit external capacitor be tween the SFST pin and ground Internal circuitry prevents the control voltage atthe Vc pin from exceeding that on the SFST pin The soft start function is enagaged whenever Voc power is removed or as a result of either undervoltage lockout orthermal overtemperature shutdown The SFST node is then discharged to roughly a Vgg above ground Rememberthatthe Vc pin control node switching thresh old is deliberately set at a Vgg plus several hundred millivolts When this condition is removed a nominal 40uA current acts to charge up the SFST node towards roughly 3V So for example a 0 1uF soft start capacitor will place a 0 4V ms limit on the ramp rate at the Vc node UVLO PIN FUNCTION The UVLO pin effects an undervoltage lockout function with at threshold of roughly 1 25V An external resistor divider between the input supply and ground can then be used to achieve a user programmable undervoltage lock out see Figure 6a An additional feature of this pin is that there is a change in the input bias current at this pin as a function of the state of the internal UVLO comparator As the pin is brought above the UVLO threshold the bias current sourced by the part increases This positive feedback ef
14. controllers uti lizing indirect output voltage sensing techniques Specifically it contains circuitry to detect flyback pulse collapse thereby supporting operation well into discon tinuous mode Nevertheless there still remain constraints to ultimate low load operation These relate to the mini mum switch on time and the minimum enable time Discontinuous mode operation will be assumed in the following theoretical derivations As outlined in the Operation section the LT1725 utilizes a minimum output switch on time toy This value can be combined with expected and switching frequency to yield an expression for minimum delivered power Minimum Power ton 2 Ler Vout lour This expression then yields a minimum output current constraint where 1 loUT MIN f switching frequency transformer primary side inductance Vin input voltage Vout output voltage ton output switch minimum on time An additional constraint has to do with the minimum enable time The LT1725 derives its output voltage infor mation from the flyback pulse If the internal minimum enable time pulse extends beyond the flyback pulse loss of regulation will occur The onset of this condition can be determined by setting the width of the flyback pulse equal to the sum of the flyback enable delay tgp plus the minimum enable time tey Minimum power delivered to the load is then Minimum Power di n
15. divider calculations Lot to lot and ambient tem perature variations will show up as output voltage shift drift Secondary Leakage Inductance Leakage inductance on the transformer secondary re duces the effective secondary to third winding turns ratio Ns N7 from its ideal value This will increase the output voltage target by a similar percentage To the extent that secondary leakage inductance is constant from part to part this can be accommodated by adjusting the feedback resistor ratio 1725fa 18 11725 APPLICATIONS INFORMATION Output Impedance Error An additional error source is caused by transformer sec ondary current flow through the real life nonzero imped ances of the output rectifier transformer secondary and output capacitor Because the secondary current only flows during the off portion of the duty cycle the effective Output impedance equals the DC lumped secondary impedance times the inverse of the off duty cycle If the output load current remains relatively constant or less critical applications the error may be judged acceptable and the feedback resistor divider ratio adjusted for nomi nal expected error In more demanding applications out put impedance error may be minimized by the use of the load compensation function see Load Compensation MINIMUM LOAD CONSIDERATIONS The LT1725 generally provides better low load perfor mance than previous generation switcher
16. in applications with arelatively high product of input voltage times secondary to primary turns ratio and or a relatively long minimum switch ontime Additionally several real world effects such astransformerleakage inductance AC winding losses and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate THERMAL CONSIDERATIONS Care should be taken to ensure that the worst case input voltage condition does not cause excessive die tempera tures The 16 lead SO package is rated at 100 C W and the 16 lead GN at 110 C W Average supply current is simply the sum of quiescent current given in the specifications section plus gate drive current Gate drive current can be computed as la f Q where Qg total gate charge f switching frequency Note Total gate charge is more complicated than Cas Va as it is frequently dominated by Miller effect of the Furthermore both capacitances are nonlinear in practice Fortunately most MOSFET data sheets provide figures and graphs which yield the total gate charge directly per operating conditions Nearly all gate drive power is dissi pated in the IC except for a small amount in the external gate series resistor so total IC dissipation may be com puted as Vcc la f Qg where lg quiescent current from specifications Qg total gate charge f switching frequency Vcc LT1725 supply voltage
17. itself is the real flyback signal It then reverts to a potentially stable state whereby the top of the leakage spike is the control point and the trailing edge of the leakage spike triggers the collapse detect circuitry This will typically reduce the output volt age abruptly to a fraction perhaps between one third to two thirds of its correct value If load current is reduced sufficiently the system will snap back to normal opera tion When using transformers with considerable leakage inductance it is important to exercise this worst case check for potential bistability 1 Operate the prototype supply at maximum expected load current 2 Temporarily short circuit the output 3 Observe that normal operation is restored If the output voltage is found to hang up at a abnormally low value the system has a problem This will usually be evident by simultaneously monitoring the Vsw waveform on an oscilloscope to observe leakage spike behavior firsthand A final note the susceptibility of the system to bistable behavior is somewhat a function of the load IV characteristics A load with resistive i e V R behavior is the most susceptible to bistability Loads which exhibit CMOSsy i e V R behavior are less susceptible Secondary Leakage Inductance In addition to the previously described effects of leakage inductance in general leakage inductance on the second ary in particular exhibits an additional phenomenon I
18. tion For example assume 3nH of parasitic inductance equivalentto about 0 1 inch of wire in free space is in series with an ideal 0 0250 sense resistor A zero will be formed at f R 2nL or 1 3MHz Above this frequency the sense resistor will behave like an inductor Several techniques can be used to tame this potential parasitic inductance problem First any resistor used for current sensing purposes must be of an inherently non inductive construction Mounting this resistor directly above an unbroken ground plane and minimizing its ground side connection will serve to absolutely minimize parasitic inductance In the case of low valued sense resistors these may be implemented as a parallel combi nation of several resistors for the thermal considerations cited above The parallel combination will help to lower the parasitic inductance Finally it may be necessary to place a pole between the current sense resistor and the LT1725 Isense pin to undo the action of the inductive zero see Figure 5 Avalue 01510 is suggested for the resistor while the capacitor is selected empirically for the particular application and layout Using good high frequency mea surement techniques the Iseyse pin waveform may be observed directly with an oscilloscope while the capacitor value is varied SENSE RESISTOR ZERO AT r RSENSE 2nLp GATE ISENSE SGND PGND 2 COMPENSATING POLE AT RSENSE 1 7 2 519
19. with the previous Vg pk expression yields an expression for Voyr in terms of the internal reference programming resistors transformer turns ratio and diode forward voltage drop VBG R1 R2 Vout Vac ELE Nsr lggc ESR Additionally it includes the effect of nonzero secondary output impedance which is discussed below in further detail see Load Compensation Theory The practical as pects of applying this equation for Vour are found in the Applications Information section 0 far this has been a pseudo DC treatment of flyback error amplifier operation But the flyback signal is a pulse not a DC level Provision must be made to enable the flyback amplifier only when the flyback pulse is present This is accomplished by the dotted line connections to the block labeled ENAB Timing signals are then required to enable and disable the flyback amplifier ERROR AMPLIFIER DYNAMIC THEORY There are several timing signals which are required for proper LT1725 operation Please refer to the Timing Diagram Minimum Output Switch On Time The LT1725 affects output voltage regulation via flyback pulse action If the output switch is not turned on at all there will be no flyback pulse and output voltage informa tion is no longer available This would cause irregular loop response and start up latchup problems The solution cho sen is to require the output switch to be on for an absolute minimum time per each oscil
20. 00 0165 0015 lt 1 0250 BSC RECOMMENDED SOLDER PAD LAYOUT 12345678 0382 0 10 x 45 0532 0688 004 0098 38 0 10 1 35 1 75 0 102 0 249 007 0098 s 0 178 0 249 1 22 016 050 008 0121 0250 eee 0 406 1 270 0 203 0 305 0 635 NOTE TYP BSC 1 CONTROLLING DIMENSION INCHES INCHES 2 DIMENSIONS ARE IN rc eres 3 DRAWING NOT TO SCALE DIMENSION DOES NOT INCLUDE MOLD FLASH MOLD FLASH SHALL NOT EXCEED 0 006 0 152mm PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH INTERLEAD FLASH SHALL NOT EXCEED 0 010 0 254mm PER SIDE 1725fa 20 LT MYR 11725 PACKAGE DESCRIPTION S Package 16 Lead Plastic Small Outline Narrow 150 Inch Reference LTC DWG 05 08 1610 E 386 394 045 3 005 9 804 10 008 050 BSC lt 3 1615 14 13 12 1 10 9 245 I 160 005 MIN 150 157 8 810 3 988 NOTE 3 4 30 0054 1 RECOMMENDED SOLDER PAD LAYOUT 0 254 0 508 1 346 1 752 1 346 1 752 004 010 008 010 A ED a Er 010 400 5 i P 053 069 t 014 019 050 gt leg 0 355 0 483 1270 i BSC 16 0502 NOTE INCHES 1 DIMENSIONS IN MILLIMETERS 2 DRAWING NOT TO SCALE 3 TH
21. 10 180 C10 R15 SE 100pF 2 33k R3 34 0k 1 LT1725 Vc R4 3 01k OSCAP SFST toy ENDLY MENAB Remec 1 6 s mMm 5 C6 C7 R5 R6 R7 R8 C8 1nF 47pF 51k 51k 51k 6 2k WI 0 1uF 1 5uF x3 ground referred version of the flyback voltage waveform for both feedback information and providing power to the LT1725 itself Capacitor C7 sets the switching frequency at approxi mately 200kHz Optimal load compensation for the trans former and secondary circuit components is set by resistor R8 Output voltage regulation and overall efficiency are shown in the accompanying graphs The resistor divider formed by R14 and R15 sets the undervoltage lockout threshold atabout 32V with a hysteresis band of about 2V The soft start and 3Vour features are unused as shown VERSA PAK is a trademark of Coiltronics Inc VP5 0155 7 D3 D1 1N5257 MBRD660 R11 10 1500 4 D4 1N5257 9 D2 100pF MBRS1100 R12 16 9 12 1 R9 IRF620 2 510 ISENSE SGND PGND EA E us bo x 1725 09 Figure 9 48V to Isolated 15V Converter 1725fa 22 LI Ure 11725 TYPICAL APPLICATIONS Application Regulation Vin 48V Vin 36V Vin 72V 14 5 0 0 5 1 0 1 5 2 0 ILoap A 1725 FO9b 48V to Isolated 15V Application Parts List T1 Coiltronics VP5 0155 VERSA PAK M1 International Rectifier IRF620 200V 0 80 N channel
22. 1725 G16 1725fa 7 LINEAR 5 11725 PIN FUNCTIONS PGND Pin 1 The power ground pin carries the GATE node discharge current This is typically a current spike of several hundred mA with a duration of tens of nanosec onds It should be connected directly to a good quality ground plane Isense Pin 2 Pin to measure switch current with exter nal sense resistor The sense resistor should be of a noninductive construction as high speed performance is essential Proper grounding technique is also required to avoid distortion of the high speed current waveform A preset internal limit of nominally 250mV at this pin effects a Switch current limit SFST Pin 3 Pin for optional external capacitor to effect soft start function See Applications Information for details Rocmp Pin 4 Input pin for optional external load compen sation resistor Use of this pin allows nominal compensa tion for nonzero output impedance in the power transformer secondary circuit including secondary winding impedance output Schottky diode impedance and output capacitor ESR In less demanding applications this resistor is not needed See Applications Information for more details Rempc Pin 5 Pin for external filter capacitor for optional load compensation function A common 0 1uF ceramic capacitor will suffice for most applications See Applica tions Information for further details OSCAP Pin 6 Pin for external timing capacitor to set
23. D1 International Rectifier 12CWQO6FN 12A 60V Schottky diode D2 BAS16 75V switching diode C1 AVX TPSD156M035R0300 15uF 35V tantalum capacitor C2 Vishay Vitramon VJ1825Y155MXB 1 5uF 100V X7R ceramic capacitor C3 Sanyo 6SA150M 150uF 6 3V OS CON electrolytic capacitor C4 150pF 100V X7R ceramic capacitor C5 470pF 50V X7R ceramic capacitor C6 1nF 25V X7R ceramic capacitor C7 47pF 25V NPO ceramic capacitor C8 0 1uF 25V Z5U ceramic capacitor C9 100pF 25V X7R ceramic capacitor C10 1uF 25V 250 ceramic capacitor R1 47k 1 4W 5 resistor R2 Panasonic type ERJ 14RSJ 0 180 1 4W 5 resistor R3 35 7k 1 resistor R4 3 01k 196 resistor R5 R6 R7 51k 5 resistor R8 2 7k 5 resistor R9 180 5 resistor R10 220 5 resistor R11 510 1W 5 resistor R12 680 5 resistor R13 820k 5 resistor R14 33k 5 resistor 1725fa 25 11 25 PACKAGE DESCRIPTION GN Package 16 Lead Plastic SSOP Narrow 150 Inch Reference LTC DWG 05 08 1641 189 196 045 005 i 48001 4978 1 009 gt 0 229 16 15 14 13 12 11 10 9 REF n 254 MIN 150 165 229 244 150 157 5 817 6 198 3 810 3 988 00
24. ESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 006 0 15mm 1725fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable CAR However no responsibility is assumed for its use Linear Technology Corporation makes no represen T ECHNOLOGY tation thatthe interconnection of its circuits as described herein will notinfringe on existing patent rights 11725 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1424 5 Isolated Flyback Switching Regulator 5V Output Voltage No Optoisolator Required LT1424 9 Isolated Flyback Switching Regulator 9V Output Regulation Maintained Under Light Loads LT1425 Isolated Flyback Switching Regulator No Third Winding or Optoisolator Required LT1533 Ultralow Noise 1A Switching Regulator Low Switching Harmonics and Reduced EMI 2 7V to 23V LTC1693 High Speed Single Dual N Channel MOSFET Drivers CMOS Compatible Input Vcc Range 4 5V to 12V LTC1698 Secondary Synchronous Rectifier Controller Use with the LT1681 Optocoupler Driver Pulse Transformer Synchronization LT1737 High Power Isolated Flyback Controller Powered from a DC Supply Voltage LT1950 Single Switch Controller Used for 20W to 500W Forward Converters LTC3705 2 Switch Forward Controller and Gate Driver 2 Switch Version of LTC3725 LTC3706 Polyphase Secondary Side Synchronous Fast Transient Res
25. are found in the Applications Information section 1725fa LI WIR 11 11725 APPLICATIONS INFORMATION TRANSFORMER DESIGN CONSIDERATIONS Transformer specification and design is perhaps the most critical part of applying the LT1725 successfully In addi tion to the usual list of caveats dealing with high frequency isolated power supply transformer design the following information should prove useful Turns Ratios Note that due to the use of the external feedback resistor divider ratio to set output voltage the user has relative freedom in selecting transformer turns ratio to suit a given application In other words screwball turns ratios like 1 736 1 0 can scrupulously be avoided In contrast simpler ratios of small integers e g 1 1 2 1 3 2 etc can be employed which yield more freedom in setting total turns and mutual inductance Turns ratio can then be chosen on the basis of desired duty cycle However remember that the input supply voltage plus the second ary to primary referred version of the flyback pulse in cluding leakage spike must not exceed the allowed external MOSFET breakdown rating Leakage Inductance Transformer leakage inductance on either the primary or secondary causes a spike after output switch turnoff This is increasingly prominent at higher load currents where more stored energy must be dissipated In many cases a snubber circuit will be required to avoid overvoltage b
26. ck waveform becomes lazy and some time elapses before it indicates the actual secondary output voltage see Figure 4C So the enable delay time should also be set long enough to ignore the irrelevant portion of the flyback waveform at light load Additionally there are cases wherein the gate output is called upon to drive a large geometry MOSFET such that the turnoff transition is slowed significantly Under such circumstances the enable delay time may be increased to accommodate for the lengthy transition MOSFET GATE DRIVE A IDEALIZED FLYBACK WAVEFORM FLYBACK WAVEFORM WITH LARGE LEAKAGE SPIKE AT HEAVY LOAD ENABLE DELAY TIME DISCONTINUOUS NEEDED MODE RINGING C SLOW FLYBACK WAVEFORM AT LIGHT LOAD ENABLE DELAY TIME NEEDED 1725 F04 Figure 4 Minimum Enable Time This function sets a minimum duration for the expected flyback pulse Its primary purpose is to provide a mini mum source current at the Vc node to avoid start up problems Average start up Vc current Minimum Enable Time Switching Frequency Minimum enable time can also have implications at light load see Minimum Load Considerations The temptation is to set the minimum enable time to be fairly short as this is the least restrictive in terms of minimum load behavior However to providea reliable minimum start up current of say nominally 1 the user should set the minimum enable time at no less that 2 of the switch
27. e capacitance For this reason the path from the GATE package pin to the physical MOSFET gate should be kept as short as possible and good layout ground plane prac tice used to minimize the parasitic inductance An explicit series gate drive resistor may be useful in some applications to damp out this potential L C resonance typically tens of MHz A minimum value of perhaps several ohms is suggested and higher values typically a few tens of ohms will offer increased damping However as this resistor value becomes too large gate voltage rise time will increase to unacceptable levels and efficiency will suffer due to the sluggish switching action Vin foe SECONDARY POWER PATH PRIMARY POWER PATH Y 1725 F08 Figure 8 High Speed Current Switching Paths 1725fa 21 11725 TYPICAL APPLICATIONS TELECOM 48V TO ISOLATED 15V APPLICATION The design in Figure 9 accepts an input voltage in the range of 36V to 72V and outputs an isolated 15V at up to 2A Transformer T1 is an off the shelf VERSA PAK VP5 0155 produced by Coiltronics As manufactured it consists of six ideally identical independent windings In this application three windings are stacked in series on the primary side and two are placed in parallel on the secondary side This arrangement provides a 3 1 primary to secondary turns ratio while maximizing overall effi ciency The remaining winding provides a primary side VIN C2 R
28. fects a hysteresis band for reliable switching action Note that the size of the hysteresis is proportional to the Thevenin impedance of the external UVLO resistor divider network which makes it user programmable As a rough rule of thumb each 4k or so of impedance generates about 196 of hysteresis This is based on roughly 1 25V for the threshold and 3uA for the bias current shift Even in good quality ground plane layouts it is common for the switching node MOSFET drain to couple to the UVLO pin with a stray capacitance of several thousandths ofa pF To ensure proper UVLO action a 100pF capacitor is recommended from this pin to ground as shown in Figure 6b This will typically reduce the coupled noise to a few millivolts The UVLO filter capacitor should not be made much larger than a few hundred pF however as the hysteresis action will become too slow In cases where further filtering is required e g to attenuate high speed supply ripple the topology in Figure 6c is recommended Resistor R1 has been split into two equal parts This provides a node for effecting capacitor filtering of high 1725fa 16 11725 APPLICATIONS INFORMATION UVLO C1 T 190 Standard UVLO Divider Topology 6b Filter Capacitor Directly On UVLO Node 1725 F06 6c Recommended Topology to Filter High Frequency Ripple Figure 6 speed supply ripple while leaving the UVLO pin node impedance relati
29. ing period 1 switching frequency CURRENT SENSE RESISTOR CONSIDERATIONS The external current sense resistor allows the user to optimize the current limit behavior for the particular appli cation under consideration As the current sense resistor is varied from several ohms down to tens of milliohms peak switch current goes from a fraction of an ampere to tens of amperes Care must be taken to ensure proper circuit operation especially with small current sense resistor values For example a peak switch current of 10A requires a sense resistor of 0 0250 Note thatthe instantaneous peak power inthe sense resistor is 2 5W and it must be rated accord ingly The LT1725 has only a single sense line to this re sistor Therefore any parasitic resistance inthe ground side connection of the sense resistor will increase its apparent value Inthe case of a0 025Q sense resistor one milliohm of parasitic resistance will cause a 4 reduction in peak switch current So resistance of printed circuit copper traces and vias cannot necessarily be ignored An additional consideration is parasitic inductance Induc tance in series with the current sense resistor will accen tuate the high frequency components of the current waveform In particular the gate switching spike and multimegahertz ringing atthe MOSFET can be considerably 1725fa 15 11725 APPLICATIONS INFORMATION amplified If severe enough this can cause erratic opera
30. intain regu lation see Minimum Load Considerations Similarly minimum on time has a direct affect on short circuit be havior see Maximum Load Short Circuit Considerations The user is normally tempted to set the minimum on time to be short to minimize these load related consequences Afterall a smaller minimum approaches the ideal case of zero or no minimum However a longer time may be required in certain applications based on MOSFET switching current spike considerations Enable Delay Time This function provides a programmed delay between turnoff of the gate drive node and the subsequent enabling of the feedback amplifier At high loads a primary side voltage spike after MOSFET turnoff may be observed due 1725fa 14 LT M 11725 APPLICATIONS INFORMATION to transformer leakage inductance This spike is not in dicative of actual output voltage see Figure 4B Delaying the enabling of the feedback amplifier allows this system to effectively ignore most or all of the voltage spike and maintain proper output voltage regulation The enable delay time should therefore be set to the maximum ex pected duration of the leakage spike This may have implications regarding output voltage regulation at mini mum load see Minimum Load Considerations A second benefit of the enable delay time function occurs at light load Under such conditions the amount of energy stored in the transformer is small The flyba
31. ion oscillation action on the Vcc pin in the conventional trickle charge bootstrapped configuration The bias current on this pin is a function of the state of the UVLO comparator as the threshold is exceeded the bias current increases This creates a hysteresis band equal to the change in bias current times the Thevenin impedance ofthe user s resistive divider The user may thereby adjust the impedance of the UVLO divider to achieve a desired degree of hysteresis A 100pF capacitor to ground is recommended on this pin See Applications Information for details SGND Pin 11 The signal ground pin is a clean ground The internal reference oscillator and feedback amplifier are referred to it Keep the ground path connection to the FB pin OSCAP capacitor and the Vc compensation capaci tor free of large ground currents MINENAB Pin 12 Pin for external programming resistor to set minimum enable time See Applications Information for details 1725fa 11725 PIN FUNCTIONS ENDLY Pin 13 Pin for external programming resistor to set enable delay time See Applications Information for details ton Pin 14 Pin for external programming resistor to set switch minimum on time See Applications Information for details Vcc Pin 15 Supply voltage for the LT1725 Bypass this pin to ground with 1uF or more GATE Pin 16 This is the gate drive to the external power MOSFET switch and has large dynamic curren
32. ives its feedback informa tion from the flyback pulse Due to space constraints this discussion will not reiterate the basics of current mode switcher controllers and isolated flyback converters A good source of information on these topics is Application Note AN19 ERROR AMPLIFIER PSEUDO DC THEORY Please refer to the simplified diagram of the Flyback Error Amplifier Operation is as follows when MOSFET output switch M1 turns off its drain voltage rises above the Viy rail The amplitude of this flyback pulse as seen on the third winding is given as Vout ESR 01 forward voltage legc transformer secondary current ESR total impedance of secondary circuit Nsr transformer effective secondary to third winding turns ratio The flyback voltage is then scaled by external resistor divider R1 R2 and presented at the FB pin This is then compared to the internal bandgap reference by the differ ential transistor pair Q1 Q2 The collector current from Q1 is mirrored around and subtracted from fixed current source at the Vc pin An external capacitor integrates this net current to provide the control voltage to set the current mode trip point The relatively high gain in the overall loop will then cause the voltage at the FB pin to be nearly equal to the bandgap reference Vag The relationship between and may then be expressed as R1 R2 R2 Combination
33. lable input voltage significantly lower than say 48V If this input voltage is within the allowable range i e perhaps 20V maximum the internal wide hysteresis range UVLO function becomes counterproductive In such cases itis simply better to operate the LT1725 directly from the available DC input supply The LT1737 is identical to the LT1725 with the exception that it lacks the internal wide hysteresis UVLO function It is therefore designed to operate directly from DC input supplies in the range of 4 5V to 20V See the LT1737 data sheet for further information FREQUENCY COMPENSATION Loop frequency compensation is performed by connect ing a capacitor from the output of the error amplifier Vc pin to ground An additional series resistor often re quired in traditional current mode switcher controllers is usually not required and can even prove detrimental The phase margin improvement traditionally offered by this extra resistor will usually be already accomplished by the nonzero secondary circuit impedance which adds a zero to the loop response In further contrast to traditional current mode switchers Vc pin ripple is generally notan issue with the LT1725 The dynamic nature of the clamped feedback amplifier forms an effective track hold type response whereby the Vc voltage changes during the flyback pulse but is then held during the subsequent switch on portion of the next cycle This action naturally holds
34. lator cycle This in turn estab lishes a minimum load requirement to maintain regula tion See Applications Information for further details 1725fa AL YR 9 11725 OPERATION Enable Delay When the output switch shuts off the flyback pulse appears However it takes a finite time until the trans former primary side voltage waveform approximately rep resents the output voltage This is partly due to rise time on the MOSFET drain node but more importantly due to transformer leakage inductance The latter causes a volt age spike on the primary side not directly related to output voltage Some time is also required for internal settling of the feedback amplifier circuitry In order to maintain immunity to these phenomena a fixed delay is introduced between the switch turnoff command and the enabling of the feedback amplifier This is termed enable delay In certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period regulation error may result See Applications Information for further details Collapse Detect Once the feedback amplifier is enabled some mechanism is then required to disable it This is accomplished by a collapse detect comparator which compares the flyback voltage FB referred to a fixed reference nominally 80 Of Vpg When the flyback waveform drops below this level the feedback amplifier is disabled This action accommodates both continuous a
35. ltronics CTX02 14989 Capacitor C7 sets the switching frequency at approxi mately 275kHz Optimal load compensation for the trans former and secondary circuit components is set by resistor R8 Output voltage regulation and overall efficiency are shown in the accompanying graphs Efficiency is shown both with and withoutthe R11 preload The resistor divider formed by R13 and R14 sets the undervoltage lockout threshold at about 32V with a hysteresis band of about 2V The soft start and 3Vour features are unused as shown Ti CTX02 14989 6 BAS16 VIN RO C2 2 29 4 1 5uF TU C9 R14 C4 R3 C10 150pF mi T eis TE p 1 4 1 1 1725 IRF620 R4 ISENSE 3 01k OSCAP SFST toy ENDLY Rocmp Rempe SGND PGND Th 6 s 2 5 1 1 C6 C7 R5 R6 R7 R8 C8 d I inF T 47pF 51k 51k 2 7k T 0 1uF Figure 10 48V to Isolated 5V Converter Application Regulation 5 25 Vout V ILoap A 1725 F10b Application Efficiency 90 Vin 48V 80 WITH PRELOAD 70 0 60 50 EFFICIENCY 40 30 20 0 01 01 1 10 ILoAD A 1725 F10c 1725fa 11725 TYPICAL APPLICATIONS 48V to Isolated 5V Application Parts List T1 Coiltronics CTX02 14989 M1 International Rectifier IRF620 200V 0 80 N channel MOSFET
36. nd discontinuous mode operation Minimum Enable Time The feedback amplifier once enabled stays enabled for a fixed minimum time period termed minimum enable time This prevents lockup especially when the output voltage is abnormally low e g during start up The mini mum enable time period ensures that the Vc node is able to pump up and increase the current mode trip point to the level where the collapse detect system exhibits proper operation The minimum enable time often determines the lowload level at which output voltage regulation is lost See Applications Information for details Effects of Variable Enable Period It should now be clear that the flyback amplifier is enabled during only a portion of the cycle time This can vary from the fixed minimum enable time described to amaximum of roughly the off switch time minus the enable delay time Certain parameters of flyback amp behavior will then be directly affected by the variable enable period These include effective transconductance and Vc node slew rate LOAD COMPENSATION THEORY The LT1725 uses the flyback pulse to obtain information about the isolated output voltage A potential error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier Ti M1 ISENSE R3 50k RSENSE Figure 1 Load Compensation Diagram 1725fa 10 LT M 11725 OPERATION transf
37. ormer secondary and output capacitor This has been represented previously by the expression ESR However it is generally more useful to convert this expression to an effective output impedance Because the secondary current only flows during the off portion of the duty cycle the effective output impedance equals the lumped secondary impedance times the inverse of the OFF duty cycle That is 1 Rout where DCorr Rour effective supply output impedance ESR lumped secondary impedance DCorr OFF duty cycle Expressing this in terms of the ON duty cycle remember ing DCorr 1 DC 1 Rour ESR T DC ON duty cycle In less critical applications or if output load current remains relatively constant this output impedance error may be judged acceptable and the external FB resistor divider adjusted to compensate for nominal expected error In more demanding applications output impedance error may be minimized by the use of the load compensa tion function Toimplementthe load compensation function a voltage is developed that is proportional to average output switch current This voltage is then impressed across the external resistor and the resulting current acts to increase the Vgg reference used by the flyback error amplifier As output loading increases average switch current increases to maintain rough output voltage regulation This causes an increase in resisto
38. osc kHz 30 100 200 Coscap PF 1725 F02 Figure 2 fosc vs OSCAP Value SELECTING TIMING RESISTOR VALUES There are three internal one shot times that are pro grammed by external application resistors minimum on time enable delay time and minimum enable time These are all part of the isolated flyback control technique and their functions have been previously outlined in the Theory of Operation section Figures 3 shows nominal observed time versus external resistor value for these functions The following information should help in selecting and or optimizing these timing values 1000 100 20 100 250 Rr 1725 F03 Figure 3 One Shot Times vs Programming Resistor Minimum On Time This time defines a period whereby the normal switch current limit is ignored This feature provides immunity to the leading edge current spike often seen at the source node ofthe external power MOSFET due to rapid charging of its gate source capacitance This current spike is not indicative of actual current level in the transformer pri mary and may cause irregular current mode switching action especially at light load However the user must remember that the LT1725 does not skip cycles at light loads Therefore minimum on time will seta limit on minimum delivered power and con sequently a minimum load requirement to ma
39. ponse Self Starting Architecture Current Mode Control Forward Controller LT3710 Secondary Side Synchronous Post Regulator For Regulated Auxiliary Output in Isolated DC DC Converters LTC3726 Secondary Side Synchronous Forward Controller Similar to the LTC3706 LT3781 Bootstrap Start Dual Transistor Synchronous 72V Operation Synchronous Switch Output Forward Controller LTC3803 SOT 23 Flyback Controller Adjustable Slope Compensation Internal Soft Start 200kHz LT3804 Secondary Side Dual Output Controller Regulates Two Secondary Outputs Optocoupler Feedback Driver with Opto Driver and Second Output Synchronous Driver Controller LTC3806 Synchronous Flyback DC DC Controller Medium Power High Efficiency Forced Continuous Operation 250kHz LTC3901 Secondary Side Synchronous Driver for Similar Function to LTC3900 Used in Full Bridge and Push Pull Converter Push Pull and Full Bridge Converter LTC4440 LTC4440 5 Linear Technology Corporation 1630 McCarthy Blvd Milpitas CA 95035 7417 408 432 1900 FAX 408 434 0507 www linear com 1725fa LT 1105 REV A PRINTED IN THE USA TECHNOLOGY LINEAR TECHNOLOGY CORPORATION 2000
40. r current which effects a corresponding increase in target output voltage Assuming a relatively fixed power supply efficiency Eff Power Out Eff e Power In Vout lour Eff Vin liy Average primary side current may be expressed in terms of output current as follows combining the efficiency and voltage terms in a single variable K1 lout where Vout e 4 Switch current is converted to voltage by the external sense resistor and averaged lowpass filtered by R3 and the external capacitor on This voltage is then impressed across the external Rocyp resistor by op amp A1 and transistor Q3 This produces a current at the collector of Q3 which is then mirrored around and then subtracted from the FB node This action effectively in creases the voltage required at the top of the R1 R2 feedback divider to achieve equilibrium So the effective change in Vour target is AVgyr REESE ett or AVour _ Ri Ner Nominal output cancellation is obtained by equating this expression with Rout ESR R 1 SENSE C K1 Rsense ESR R19 dimensionless variable related to Vout and efficiency as above Rsense external sense resistor Rout uncompensated output impedance The practical aspects of applying this equation to deter mine an appropriate value for the resistor
41. reakdown at the output switch node Application Note AN19 is a good reference on snubber design In situations where the flyback pulse extends beyond the enable delay time the output voltage regulation will be affected to some degree It is important to realize that the feedback system has a deliberately limited input range roughly 50 referred to the FB node and this works to the user s advantage in rejecting large i e higher voltage leakage spikes In other words once a leakage spike is several volts in amplitude a further increase in amplitude has little effect on the feedback system So the user is generally advised to arrange the snubber circuit to clamp at as high a voltage as comfortably possible observing MOSFET breakdown such that leakage spike duration is as short as possible As a rough guide total leakage inductances of several percent of mutual inductance or less may require a snubber but exhibit little to no regulation error due to leakage spike behavior Inductances from several percent up to perhaps ten percent cause increasing regulation error Severe leakage inductances in the double digit percentage range should be avoided if at all possible as there is a potential for abrupt loss of control at high load current This curious condition potentially occurs when the leak age spike becomes such a large portion of the flyback waveform that the processing circuitry is fooled into thinking that the leakage spike
42. t forms an inductive divider on the transformer secondary 1725fa 12 LT MR 11725 APPLICATIONS INFORMATION which reduces the size of the primary referred flyback pulse used for feedback This will increase the output voltage target by a similar percentage Note that unlike leakage spike behavior this phenomena is load indepen dent To the extent that the secondary leakage inductance is a constant percentage of mutual inductance over manufacturing variations this can be accommodated by adjusting the feedback resistor divider ratio Winding Resistance Effects Resistance in either the primary or secondary will act to reduce overall efficiency Resistance in the secondary increases effective output impedance which degrades load regulation at least before load compensa tion is employed Bifilar Winding A bifilar or similar winding technique is a good way to minimize troublesome leakage inductances However re member that this will increase primary to secondary ca pacitance and limit the primary to secondary breakdown voltage so bifilar winding is not always practical Finally the LTC Applications group is available to assist in the choice and or design of the transformer Happy Winding SELECTING FEEDBACK RESISTOR DIVIDER VALUES The expression for Vour developed in the Operation sec tion can be rearranged to yield the following expression for the R1 R2 ratio R14 R2 Vour Ve
43. tching regulator ICs By utilizing current mode switching techniques it provides excellent AC and DC line regulation Its unique control circuitry can maintain regu lation well into discontinuous mode in most applications Optional load compensation circuitry allows for improved load regulation An optional undervoltage lockout pin halts operation when the application input voltage is too low An optional external capacitor implements a soft start function A 3V output is available at up to several mA for powering primary side application circuitry TYPICAL APPLICATION 48V to Isolated 5V Converter CTX02 14989 1 1725 3VOUT BAS16 Vin 36V TO 72V 35 7k 1 Output Load Regulation Vy 36V T lour 010 2 z Vin 72V 510 55 00 1W 475 0 0 5 10 15 2 0 1725 F10b 1725fa 1 11 25 ABSOLUTE MAXIMUM RATINGS Note 1 Voc Supply 22V UVLO Pin VOLU ism Voc Isense Pin Voltage 2V FB PUN UNM 2mA Operating Junction Temperature Range NIU ec rere ter rent 0 C to 100 C Bu 22 E 40 125 C Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 10 5 300 C PACKAGE ORDER INFORMATION TOP VIEW PGND GATE ISENSE Voc SFST ton Rocmp ENDLY
44. the Vc voltage stable duringthe current comparator sense action current mode switching OUTPUT VOLTAGE ERROR SOURCES Conventional nonisolated switching power supply ICs typically have only two substantial sources of output voltage error the internal or external resistor divider network that connects to Vour and the internal IC refer ence The LT1725 which senses the output voltage in both a dynamic and an isolated manner exhibits additional potential error sources to contend with Some of these errors are proportional to output voltage others are fixed in an absolute millivolt sense Here is a list of possible error sources and their effective contribution Internal Voltage Reference The internal bandgap voltage reference is of course imperfect Its error both at 25 C and over temperature is already included in the specifications User Programming Resistors Output voltage is controlled by the user supplied feedback resistor divider ratio To the extent that the resistor ratio differs from the ideal value the output voltage will be proportionally affected Highest accuracy systems will demand 1 components Schottky Diode Drop The LT1725 senses the output voltage from the trans former primary side during the flyback portion of the cycle This sensed voltage therefore includes the forward drop Vr of the rectifier usually a Schottky diode The nominal Vr of this diode should therefore be included in feedback resistor
45. the value of capacitor C1 In this case the normal supply current LT1725 GATE PGND SGND T 1725 F07 Von THRESHOLD Vvcc 0 VGATE Figure 7 drawn by the 171725 will discharge C1 too rapidly before thethird winding drive becomes effective the Vcc turn off threshold will be reached The LT1725 turns off and the Vcc node begins to charge via R1 back up to the turn on threshold Depending upon the particular situation this may result in either several on off cycles before proper operation is reached or permanent relaxation oscillation at the Vcc node Component selection is as follows Resistor R1 should be selected to yield a worst case minimum charging current greater than the maximum rated LT1725 start up current and a worst case maxi mum charging current less than the minimum rated LT1725 supply current 1725fa 17 11725 APPLICATIONS INFORMATION Capacitor C1 should then be made large enough to avoid the relaxation oscillatory behavior described above This is complicated to determine theoretically as it depends on the particulars of the secondary circuit and load behavior Empirical testing is recommended Use of the optional soft start function will lengthen the power up timing and require a correspondingly larger value for C1 A further note certain users may wish to utilize the general functionality of the LT1725 but may have an avai
46. ts flowing through it Keep the trace to the MOSFET as short as possible to minimize electromagnetic radiation and volt age spikes A series resistance of 5Q or more may help to dampen ringing in less than ideal layouts BLOCK DIAGRAM 3V REG INTERNAL toy MINENAB GATE LOAD COMPENSATION RocuP Rempe 1725fa 7 11725 TIMING DIAGRAM Vsw VOLTAGE COLLAPSE DETECT VIN GND STATE OFF ON OFF ON MINIMUM toy gt ENABLE DELAY FLYBACK EE DISABLED ENABLED DISABLED MINIMUM ENABLE TIME lt yit FLYBACK ERROR AMPLIFIER Ti D1 ISOLATED d Vout 1725fa neve 11725 OPERATION The LT1725 is a current mode switcher controller IC designed specifically for the isolated flyback topology The Block Diagram shows an overall view of the system Many of the blocks are similar to those found in traditional designs including Internal Bias Regulator Oscillator Logic Current Amplifier and Comparator Driver and Out put Switch The novel sections include a special Flyback Error Amplifier and a Load Compensation mechanism Also due to the special dynamic requirements of flyback control the Logic system contains additional functionality not found in conventional designs The LT1725 operates much the same as traditional current mode switchers the major difference being a different type of error amplifier that der
47. vely unchanged at high frequency INTERNAL WIDE HYSTERESIS UNDERVOLTAGE LOCKOUT The LT1725 is designed to implement isolated DC DC converters operating from input voltages of typically 48V or more The standard operating topology utilizes a third transformer winding on the primary side that provides both feedback information and local power for LT1725 viaits Voc pin However this arrangement is not inherently self starting Start up is effected by the use of an external trickle charge resistor and the presence of an internal wide hysteresis undervoltage lockout circuitthat monitors Vcc pin voltage see Figure 7 Operation is as follows Trickle charge resistor R1 is connected to Vis and supplies a small current typically on the order of a single mA to charge C1 At first the 11725 is off and draws only its start up current After some time the voltage on C1 Voc reaches the Vec turn on threshold The LT1725 then turns on abruptly and draws its normal supply current Switching action commences at the GATE pin and the MOSFET begins to deliver power The voltage on C1 begins to decline as the LT1725 draws its normal supply current which greatly exceeds that delivered by R1 After some time typically tens of milliseconds the output voltage approaches its desired value By this time the third transformer winding is providing virtually all the supply current required by the LT1725 One potential design pitfall is undersizing
48. y using the eventual secondary components Temporarily ground the Rempe pin to disable the load compensation function Operate the supply over the expected range of output current loading while measuring the output voltage deviation Approxi mate this variation as a single value of Rour straight line approximation Calculate a value for the K1 constant based on Vout and the measured differential effi ciency These are then combined with Rsense as indicated to yield a value for Verify this result by connecting a resistor of roughly this value from the pin to ground Disconnect the ground short to Rempe and connect the requisite 0 1uF filter capacitor to ground Measure the output impedance 1725fa 13 11 25 APPLICATIONS INFORMATION with the new compensation in place Modify the original Rocmp value if necessary to increase or decrease the effective compensation SELECTING OSCILLATOR CAPACITOR VALUE The switching frequency of the LT1725 is set by an external capacitor connected between the OSCAP pin and ground Recommended values are between 200pF and 33pF yielding switching frequencies between 50kHz and 250kHz Figure 2 shows the nominal relationship between external capacitance and switching frequency To mini mize stray capacitance and potential noise pickup this capacitor should be placed as close as possible to the IC and the OSCAP node length area minimized 300 200 f
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LINEAR TECHNOLOGY LT1725 General Purpose Isolated Flyback Controller Manual