Home

ANALOG DEVICES AD8197B English products handbook Rev 0

1. Table 2 Parameter Rating AVCC to AVEE 37V DVCC to DVEE 37V DVEE to AVEE 0 3V VTTI AVCC 0 6V VTTO AVCC 0 6 V AMUXVCC 5 5V Internal Power Dissipation 2 2W AVCC 1 4V VN lt AVCC 0 6V High Speed Differential Input Voltage 2 0V Low Speed Input Voltage DVEE 0 3 V lt Vin lt High Speed Input Voltage AMUXVCC 0 6 V 12C and Parallel Logic Input Voltage DVEE 0 3 V lt Vn lt DVCC 0 6 V Storage Temperature Range 65 C to 125 C Operating Temperature Range 40 C to 85 C Junction Temperature 150 C AD8197B THERMAL RESISTANCE Oya is specified for the worst case conditions a device soldered in a 4 layer JEDEC circuit board for surface mount packages Orc is specified for no airflow Table 3 Thermal Resistance Package Type Osa Osc Unit 100 Lead LQFP 56 19 C W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8197B is limited by the associated rise in junction temperature The maximum safe junction temperature for plastic encapsulated devices is
2. 1 data rate 2 25 Gbps unless otherwise noted HDMI CABLE visita e AD8197B SERIAL DATA PATTERN Y EVALUATION ANALYZER GENERATOR To BOARD SMA COAX CABLE REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07015 009 Figure 9 Test Circuit Diagram for Tx Eye Diagrams 250mV DIV 250mV DIV 07015 010 07015 012 0 125UI DIV AT 2 25Gbps 0 125UI DIV AT 2 25Gbps Figure 10 Tx Eye Diagram at TP2 PE 2 dB Figure 12 Tx Eye Diagram at TP3 PE 2 dB Cable 2 meters 30 AWG 250mV DIV 250mV DIV nemer 2 PISTE 0 125UI DIV AT 2 25Gbps 07015 011 07015 013 0 125UI DIV AT 2 25Gbps Figure 11 Tx Eye Diagram at TP2 PE 6 dB Figure 13 Tx Diagram at TP3 PE 2 6 dB Cable 10 meters 28 AWG Rev 0 Page 10 of 28 AD8197B Ta 27 C AVCC 3 3 V VTTI 3 3 V VITO 3 3 V DVCC 3 3 V AMUXVCC 5 V AVEE 0 V DVEE 0 V differential input swing 1000 mV TMDS outputs terminated with external 50 Q resistors to 3 3 V pattern PRBS 27 1 data rate 2 25 Gbps unless otherwise noted 0 6 2m CABLE 30AWG 2m CABLE 30AWG 5m TO 20m CABLES 24AWG 5m TO 20m CABLES 24AWG 0 5 S 3 m m 0 4 E 2 25Gbps E 5 EQ 12dB 5 1 65Gbps PE OFF o o 03 E 2 o z z 2 25Gbps PE E A 0 2
3. 13a Send a stop condition while holding the I2C SCL line high pull the SDA line high and release control of the bus to end the transaction shown in Figure 30 13b Send a repeated start condition while holding the I2C SCL line high pull the I2C SDA line low and continue with Step 2 of the write procedure previous Write Procedure section to perform a write 13c Send a repeated start condition while holding the I2C SCL line high pull the I2C_SDA line low and continue with Step 2 of this procedure to perform a read from another address 13d Send a repeated start condition while holding the I2C SCL line high pull the I2C_SDA line low and continue with Step 8 of this procedure to perform a read from the same address SWITCHING UPDATE DELAY There is a delay between when a user writes to the configura tion registers of the AD8197B and when that state change takes physical effect This update delay occurs regardless of whether the user programs the AD8197B via the serial or the parallel control interface When using the serial control interface the update delay begins at the falling edge of 12C_SCL for the last data bit transferred as shown in Figure 29 When using the parallel control interface the update delay begins at the transition edge of the relevant parallel interface pin This update delay is register specific and the times are specified in Table 1 During a delay window new values can be written to the config
4. HDCP encryption and other information depending upon the specific application All four high speed TMDS channels in a given link are identical that is the pixel clock can be run on any of the four TMDS channels Transmit and receive channel compensation is provided for the high speed channels where the user can manually select among a number of fixed settings The AD8197B has two control interfaces Users have the option of controlling the part through either the parallel control interface or the I C serial control interface However the parallel control interface is not able to control the switch status of the input termination resistors and therefore has limited usefulness in practical systems Most systems use only the IC serial interface The AD8197B has eight user programmable IC slave addresses to allow multiple AD8197Bs to be controlled by a single C bus A RESET pin is provided to restore the control registers of the AD8197B to the parallel control interface and some default values In all cases serial programming values override any prior parallel programming values and any use of the serial control interface disables the parallel control interface until the AD8197B is reset INPUT CHANNELS Each high speed input differential pair terminates to the 3 3 V VTTI power supply through a pair of single ended 50 Q on chip resistors as shown in Figure 25 The input termination status for each individual high speed diffe
5. bus should suffice The HDMI 1 3 specification however places a strict 50 pF limit on the amount of capacitance that can be measured on either SDA or SCL at the HDMI input connector This 50 pF limit includes the HDMI connector the PCB and whatever capacitance is seen at the input of the AD8197B or an equivalent receiver There is a similar limit of 100 pF of input capacitance for the CEC line The parasitic capacitance of traces on a PCB increases with trace length To help ensure that a design satisfies the HDMI specification the length of the CEC and DDC lines on the PCB should be made as short as possible Additionally if there is a reference plane in the layer adjacent to the auxiliary traces in the PCB stack up relieving or clearing out this reference plane immediately under the auxiliary traces significantly decreases the amount of parasitic trace capacitance An example of the board stackup is shown in Figure 33 SILKSCREEN 1 LAYER 2 GND REFERENCE PLANE d PCB DIELECTRIC PCB DIELECTRIC LAYER 4 SIGNAL MICROSTRIP Jis Ta SILKSCREEN REFERENCE LAYER RELIEVED UNDERNEATH MICROSTRIP 07015 032 Figure 33 Example Board Stackup HPD is a dc signal presented by a sink to a source to indicate that the source EDID is available for reading The placement of this signal is not critical but it should be routed as directly as possible When the AD8197B is powered up one set of the auxiliary inputs is passively rou
6. 1 65Gbps E E EQ 12dB E ul ul a a 0 1 0 A R 0 5 10 15 20 25 0 5 10 15 20 5 HDMI CABLE LENGTH m g HDMI CABLE LENGTH m iS Figure 14 Jitter vs Input Cable Length See Figure 4 for Test Setup Figure 17 Jitter vs Output Cable Length See Figure 9 for Test Setup 50 1200 45 1000 40 35 1080p Ss 800 g 30 EST 1080p E g 12 BIT E 25 1 65Gbps 600 E 480p 1080i 720p u 5 20 t w 430i DJ p p tu 400 15 10 200 5 RJ rms 0 re 0 E 0 02 04 06 08 10 12 14 16 18 20 22 24 2 0 02 04 06 08 10 12 14 16 18 20 22 24 2 DATA RATE Gbps DATA RATE Gbps Figure 15 Jitter vs Data Rate Figure 18 Eye Height vs Data Rate 800 700 600 x 500 a E z E x hi 400 D E x 5 wt 300 tu 200 100 RJ rms o 0 o 3 0 3 1 3 2 3 3 3 4 3 5 3 6 5 25 26 27 28 29 30 31 32 33 34 35 36 2 SUPPLY VOLTAGE V E SUPPLY VOLTAGE V Figure 16 Jitter vs Supply Voltage Figure 19 Eye Height vs Supply Voltage Rev 0 Page 11 of 28 AD8197B Ta 27 C AVCC 3 3 V VTTI 3 3 V VITO 3 3 V DVCC 3 3 V AMUXVCC 5 V AVEE 0 V DVEE 0 V differential input swing 1000 mV TMDS outputs terminated with external 50 Q resistors to 3 3 V pattern PRBS 27 1 data rate 2 25 Gbps unless otherwise noted 50 50 40 40 30 T 30 2 m m ul u DJ p p E E o m FI
7. 3 2 7 8 mA AMUXVCC 0 01 0 1 mA POWER DISSIPATION Outputs disabled 115 271 361 mW Outputs enabled no pre emphasis 384 574 671 mW Outputs enabled maximum pre emphasis 704 910 1050 mW TIMING CHARACTERISTICS Switching Update Delay High speed switching register H5 CH 200 ms All other configuration registers 1 5 ms RESET Pulse Width 50 ns Rev 0 Page 3 of 28 AD8197B Parameter Conditions Comments Min Typ Max SERIAL CONTROL INTERFACE Input High Voltage Viu Input Low Voltage Vi Output High Voltage Vou Output Low Voltage Vo 2 4 0 8 0 4 PARALLEL CONTROL INTERFACE Input High Voltage Viu Input Low Voltage Vi 0 8 Differential interpair skew is measured between the TMDS pairs of a single link AD8197B output meets the transmitter eye diagram as defined in the DVI Standard Revision 1 0 and the HDMI Standard Revision 1 3 3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1 0 and the HDMI Standard Revision 1 3 4 Typical value assumes only the selected HDMI DVI link is active with nominal signal swings and that the unselected HDMI DVI links are deactivated Minimum and maximum limits are measured at the respective extremes of input termination resistance and input voltage swing 5 The AD8197B is an lC slave and its serial control interface is based on the 3 3 V lC bus specification Rev 0 Page 4 of 28 ABSOLUTE MAXIMUM RATINGS
8. Version Switching Update Delay eere 16 Parallel Control Interface sse 17 Serial Interface Configuration Registers sss 18 High Speed Device Modes Register sss 19 Auxiliary Device Modes Register sss 19 Receiver Settings Register coccion 19 Input Termination Select Register 1 and Register 2 19 Receive Equalizer Register 1 and Register 2 19 Transmitter Settings Register 20 Parallel Interface Configuration Registers 21 High Speed Device Modes Register sss 22 Auxiliary Device Modes Register sss 22 Input Termination Resistor Control Register 1 and Register De ies eerte E EO A 22 Receive Equalizer Register 1 and Register 2 22 Transmitter Settings Register 22 Application Information seseeeeeeeentetennne 23 Pinout M 23 Cable Lengths and Equalization sss 23 PCB Layout Guidelines eerte 24 O tline Dimensions icti titres 28 Ordering Guide eth ote pH 28 Rev 0 Page 2 of 28 SPECIFICATIONS AD8197B Ta 27 C AVCC 3 3 V VTTI 3 3 V VITO 3 3 V DVCC 3 3 V AMUXVCC 5 V AVEE 0 V DVEE 0 V differential input swing 1000 mV TMDS outputs terminated with external 50 Q resistors to 3 3 V unless o
9. determined by the glass transition temperature of the plastic approximately 150 C Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package Exceeding a junction temperature of 175 C for an extended period can result in device failure To ensure proper operation it is necessary to observe the maximum power rating as determined by the coefficients in Table 3 ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Avad Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 5 of 28 AD8197B sige 3 Oot nun oran OOO Oor nyo LQor ao EX lt lt lt 46MADODOODOVDOSADAALDAOZ Oo ul ru Lu 1X X OX Kw OX X OX OX KKK KK KK X Q2 X X x x LEA gt A im gt gt 3S 3 gt 25 9 2 2 2 25 225 277 Sa a a a a ca a a a a a a a a a a a a a a a a a SIs s s s s s s s s s s ss s s s eg s s se eae avcc 1 75 AVCC IN BO 2 bid n 74 IP C3 iP Bo 3 73 iN c3 AVEE 4 72 AVEE IN_B1 5 71 IP c2 iP B1 6 70 IN c2 vrn 7 69 VTTI IN_B2 8 68 IP_C1 iP B2 9 67 IN C1 AVEE 10 66 AVEE IN B3 11 65 iP co i
10. for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM 1 0 I o a a do p n ee paih IP A 3 0 2 q VTTO IN A 3 0 IP B 3 0 G 5 y IN B 3 9 SWITCH O OP 3 0 IP C 3 0 34 x ci CORE s ON 3 0 Esame REN n IP D 3 0 94239 IN D 3 0 AUX AB 0 mmm AUX B 3 0 A SWITCH AUX_C 3 0 do CORE AUX_D 3 0 NN LOW SPEED UNBUFFERED BIDIRECTIONAL O AUX COM 3 0 07015 001 Figure 2 GENERAL DESCRIPTION The AD8197B is an HDMI DVI switch featuring equalized TMDS inputs and pre emphasized TMDS outputs ideal for systems with long cable runs The AD8197B offers individual control of the on off state of the TMDS input termination resistors via C control Outputs can be set to a high impedance state to reduce the power dissipation and or to allow the construction of larger arrays using the wire OR technique The AD8197B is provided in a 100 lead LQFP Pb free surface mount package specified to operate over the 40 C to 85 C temperature range PRODUCT HIGHLIGHTS 1 Supports data rates up to 2 25 Gbps enabling 1080p deep color 12 bit
11. is using 5 V C then AMUXVCC should be connected to 5 V relative to DVEE In a typical application all pins labeled AVEE or DVEE should be connected directly to ground All pins labeled AVCC DVCC VTTI or VITO should be connected to 3 3 V and Pin AMUXVCC should be tied to 5 V The supplies can also be powered individually but care must be taken to ensure that each stage of the AD8197B is powered correctly Rev 0 Page 26 of 28 Power Supply Bypassing The AD8197B requires minimal supply bypassing When powering the supplies individually place a 0 01 uF capacitor between each 3 3 V supply pin AVCC DVCC VTTL and VTTO and ground to filter out supply noise Generally bypass capacitors should be placed near the power pins and should connect directly to the relevant supplies without long intervening traces For example to improve the parasitic inductance of the power supply decoupling capacitors minimize the trace length between capacitor landing pads and the vias as shown in Figure 34 M RECOMMENDED N EXTRA ADDED INDUCTANCE NOT RECOMMENDED 07015 033 Figure 34 Recommended Pad Outline for Bypass Capacitors AD8197B In applications where the AD8197B is powered by a single 3 3 V supply it is recommended to use two reference supply planes and bypass the 3 3 V reference plane to the ground reference plane with one 220 pF one 1000 pF two 0 01 uF and one 4 7 uF capacitors The capacitors should via down d
12. on off select level select PP PE 1 PP PE O PP OTO PP OCL Rev 0 Page 21 of 28 AD8197B HIGH SPEED DEVICE MODES REGISTER PP EN High Speed TMDS Channels Enable Bit Table 19 PP EN Description PP EN Description 0 High speed channels off low power standby mode 1 High speed channels on PP CH 1 0 High Speed TMDS Switch Source Select Bus Table 20 PP CH Mapping RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2 PP EQ High Speed TMDS Inputs Equalization Level Select Bit For All TMDS Input Channels The input equalization cannot be set individually per channel when using the parallel interface one equalization setting affects all input channels Table 22 PP EQ Description PP EQ Description 0 Low equalization 6 dB 1 High equalization 12 dB PP CH 1 0 O 3 0 Description 00 A 3 0 High Speed Source A switched to output 01 B 3 0 High Speed Source B switched to output 10 C 3 0 High Speed Source C switched to output 11 D 3 0 High Speed Source D switched to output TRANSMITTER SETTINGS REGISTER PP PE 1 0 High Speed TMDS Output Pre Emphasis Level Select Bus For All TMDS Channels Table 23 PP PE 1 0 Description Note that after changing the status of the channel selection PP CH 1 0 0 it is necessary to assert a low logic level to RESET to ensure that the channel select status is properly updated AUXILIARY
13. 00 in the new configuration Ground Current Return In some applications it can be necessary to invert the output pin order of the AD8197B This requires a designer to route the TMDS traces on multiple layers of the PCB When routing differential pairs on multiple layers it is necessary to also reroute the corresponding reference plane in order to provide one continuous ground current return path for the differential signals Standard plated through hole vias are acceptable for both the TMDS traces and the reference plane An example of this is illustrated in Figure 32 THROUGH HOLE VIAS SILKSCREEN LAYER 1 SIGNAL MICROSTRIP PCB DIELECTRIC LAYER 2 GND REFERENCE PLANE PCB DIELECTRIC LAYER 3 PWR REFERENCE PLANE PCB DIELECTRIC LAYER 4 SIGNAL MICROSTRIP SILKSCREEN KEEP REFERENCE PLANE ADJACENT TO SIGNAL ON ALL LAYERS TO PROVIDE CONTINUOUS GROUND CURRENT RETURN PATH 07015 036 Figure 32 Example Routing of Reference Plane TMDS Terminations The AD8197B provides internal 50 single ended termina tions for all of its high speed inputs and outputs It is not necessary to include external termination resistors for the TMDS differential pairs on the PCB The output termination resistors of the AD8197B back terminate the output TMDS transmission lines These back terminations act to absorb reflections from impedance discontinuities on the output traces improving the signal integrity of t
14. ANALOG DEVICES 4 1 HDMI DVI Switch with Equalization AD8197B FEATURES 4 inputs 1 output HDMI DVI links Enables HDMI 1 3 compliant receiver Pin to pin compatible with the AD8197A 4TMDS channels per link Supports 250 Mbps to 2 25 Gbps data rates Supports 25 MHz to 225 MHz pixel clocks Equalized inputs allow use of long HDMI cables 20 meters at 2 25 Gbps Fully buffered unidirectional inputs outputs Per input switchable 50 O on chip terminations Switchable output 50 Q on chip terminations Pre emphasized outputs Low added jitter Single supply operation 3 3 V 4 auxiliary channels per link Bidirectional unbuffered inputs outputs Flexible supply operation 3 3 V to 5 V HDCP standard compatible Allows switching of DDC bus and 2 additional signals Output disable feature Reduced power dissipation Removable output termination Allows building of larger arrays Two AD8197Bs support HDMI DVI dual link Standards compatible HDMI receiver HDCP DVI Serial I C slave and parallel control interface 100 lead 14 mm x 14 mm LQFP Pb free package APPLICATIONS Multiple input displays Projectors ANN receivers Set top boxes Advanced television HDTV sets TYPICAL APPLICATION GAME CONSOLE MEDIA CENTER F SET TOP BOX 07015 002 Figure 1 Typical HDTV Application Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices
15. CEC AMUXVCC AD8197B SOURCE B 5VO BAT54L PIN 18 HDMI CONNECTOR PIN 18 HDMI CONNECTOR PIN 14 DVI CONNECTOR PIN 14 DVI CONNECTOR Figure 28 Suggested AMUXVCC Power Scheme O 5V SOURCE D BaTsaL 07015 027 Rev 0 Page 14 of 28 SERIAL CONTROL INTERFACE RESET On initial power up or at any point in operation the AD8197B register set can be restored to the status of the parallel control interface pins and some preprogrammed default values by pulling the RESET pin to low in accordance with the specifica tions in Table 1 During normal operation however the RESET pin must be pulled up to 3 3 V Following a reset the prepro grammed default values of the AD8197B register set correspond to the state of the parallel interface configuration registers and defaults as listed in Table 18 The AD8197B can be controlled through the parallel control interface until the first serial control event occurs As soon as any serial control event occurs the serial programming values corresponding to the state of the serial interface configuration registers Table 5 override any prior parallel programming values and the parallel control interface is disabled until the part is subsequently reset Note that the input termination resistor switch control is only via PC control Therefore any system that requires control of these switches cannot operate in parallel control mode WRITE PROCEDURE To wri
16. DEVICE MODES REGISTER PP CH 1 0 Auxiliary Switch Source Select Bus Table 21 PP CH Mapping PP PE 1 0 Description 00 No pre emphasis 0 dB 01 Low pre emphasis 2 dB 10 Medium pre emphasis 4 dB 11 High pre emphasis 6 dB PP OTO High Speed TMDS Output Termination On Off Select Bit For All TMDS Channels Table 24 PP OTO Description PP CH 1 0 AUX COM 3 0 Description 00 AUX A 3 0 Auxiliary Source A switched to output 01 AUX B 3 0 Auxiliary Source B switched to output 10 AUX C 3 0 Auxiliary Source C switched to output 11 AUX DI3 0 Auxiliary Source D switched to output PP OTO Description 0 Output termination off 1 Output termination on PP_OCL High Speed TMDS Output Current Level Select Bit For All TMDS Channels Table 25 TX OCL Description PP OCL Description 0 Output current set to 10 mA 1 Output current set to 20 mA INPUT TERMINATION RESISTOR CONTROL REGISTER 1 AND REGISTER 2 High speed input TMDS channels input terminations are off when using the parallel interface This can be changed only via serial programming Rev 0 Page 22 of 28 AD8197B APPLICATION INFORMATION x o 0 Ne D 07015 030 Figure 31 Layout of the TMDS Traces on the AD8197B Evaluation Board Only Top Signal Routing Layer is Sh
17. H 1 0 it is necessary to assert a low logic level to RESET to ensure that the channel select status is properly updated Note also that the input termination resistor switches can be controlled only via serial programming Therefore as most systems require controlling these resistors serial control is required and parallel control is of little use However the parallel control pins determine the AD8197B status between the time ofthe assertion of reset and the first serial program ming event Rev 0 Page 17 of 28 AD8197B SERIAL INTERFACE CONFIGURATION REGISTERS The serial interface configuration registers can be read and written using the IC serial control interface Pin I2C_SDA and Pin I2C SCL The least significant bits of the AD8197B IC part address are set by tying the Pin 12C_ADDR2 Pin 2C ADDRI and Pin I2C ADDRO to 3 3 V Logic 1 or 0 V Logic 0 As soon as the serial control interface is used the parallel control interface is disabled until the AD8197B is reset as described in the Serial Control Interface section Table 5 Serial PC Interface Register Map Name Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit O Addr Default High High High speed source select 0x00 0x40 Speed speed Device switch Modes enable HS EN 0 0 0 0 HS CH 1 HS CH 0 Auxiliary Auxiliary Auxiliary switch source 0x01 0x40 Device switch select
18. Modes enable AUX EN 0 0 0 0 AUX CH 1 AUX_CH 0 Receiver High speed 0x10 0x01 Settings input termination resistor select RX_TS Input Source A and Source B input termination select 0x11 0x00 Term RX_TO 7 RX_TO 6 RX TO 5 RX_TO 4 RX_TOI3 RX TO 2 RX TO 1 RX_TO O Resistor Control 1 Input Source C and Source D input termination select 0x12 0x00 d RX TO 15 RX TO 14 RX TO 13 RX TO 12 RX TO 11 RX TO 10 RX TO 9 RX_TO 8 esistor Control 2 Receive Source A and Source B input equalization level select 0x13 0x00 Equalizer 1 RX_EQ 7 RX_EQ 6 RX_EQ 5 RX_EQ 4 RX_EQ 3 RX_EQ 2 RX_EQ 1 RX EO O0 Receive Source C and Source D input equalization level select 0x14 0x00 Equalizer 2 gx EQ 15 RX_EQ 14 RX EOr13 RX EQr12 RX_EQ 11 RX Eor10 RX_EQI9 RX_EQI8 Transmitter High speed output High speed High speed 0x20 0x03 Settings pre emphasis level output output select termination current select level select TX_PE 1 TX_PE O TX_PTO TX_OCL Rev 0 Page 18 of 28 AD8197B HIGH SPEED DEVICE MODES REGISTER INPUT TERMINATION SELECT REGISTER 1 AND HS EN High Speed TMDS Channels Enable Bit REGISTER 2 Table 6 HS EN Description RX_ TO X I High Speed TMDS Input Channel X Termination Select Bit HS EN Description 0 High speed channels off low power standby mode Table 11 RX_TO X Description 1 High speed channels on RX TOIX Description 0 Inpu
19. NE 10 10 RJ rms 0 0 gt AAA AAA a cnt RE 0 02 04 06 08 10 12 14 16 18 20 8 2 5 2 7 2 9 3 1 3 3 3 5 3 7 DIFFERENTIAL INPUT SWING V E INPUT COMMON MODE VOLTAGE V E Figure 20 Jitter vs Differential Input Swing Figure 23 Jitter vs Input Common Mode Voltage 120 115 8 u 110 Eo az z 2E 105 s 2 amp Ea 100 P uz 5 de E 95 us az 90 ul m 85 x 80 x 3 40 20 0 20 40 60 80 100 8 TEMPERATURE C TEMPERATURE C E Figure 21 Jitter vs Temperature Figure 24 Differential Input Termination Resistance vs Temperature 160 140 FALL TIME lt 120 o eo RISE TIME 9 100 E Es u 8 E E 60 d Ei ie ul 40 o 4 20 0 40 20 0 20 40 60 80 100 07015 022 TEMPERATURE C Figure 22 Rise and Fall Time vs Temperature Rev 0 Page 12 of 28 THEORY OF OPERATION INTRODUCTION The AD8197B is a pin to pin HDMI 1 3 receive compliant replacement for the AD8197A The primary function of the AD8197B is to switch one of four HDMI or DVI single link sources to one output Each HDMI DVI link consists of four differential high speed channels and four auxiliary single ended low speed control signals The high speed channels include a data word clock and three transition minimized differ ential signaling TMDS data channels running at 10x the data word clock frequency for data rates up to 2 25 Gbps The four low speed control signals are 5 V tolerant bidirectional lines that can carry configuration signals
20. _CO HS High Speed Input Complement 65 IP_CO HS High Speed Input 67 IN C1 HS High Speed Input Complement 68 IP C1 HS High Speed Input 70 IN_C2 HS High Speed Input Complement 71 IP C2 HS High Speed Input 73 IN_C3 HS High Speed Input Complement 74 IP_C3 HS High Speed Input 76 PP_EN Control High Speed Output Enable Parallel Interface 77 PP_EQ Control High Speed Equalization Selection Parallel Interface 78 AUX_D3 LS 1 0 Low Speed Input Output 79 AUX_D2 LS 1 0 Low Speed Input Output 80 AUX_D1 LS 1 0 Low Speed Input Output 81 AUX_DO LS 1 0 Low Speed Input Output 82 AMUXVCC Power Positive Auxiliary Multiplexer Supply 5 V typical 83 AUX_C3 LS 1 0 Low Speed Input Output 84 AUX_C2 LS 1 0 Low Speed Input Output 85 AUX C1 LS 1 0 Low Speed Input Output 86 AUX CO LS 1 0 Low Speed Input Output 87 AUX COM3 LS 1 0 Low Speed Common Input Output 88 AUX COM2 LS 1 0 Low Speed Common Input Output Rev 0 Page 7 of 28 AD8197B Pin No Mnemonic Type Description 89 AUX_COM1 LS 1 0 Low Speed Common Input Output 90 AUX_COMO LS 1 0 Low Speed Common Input Output 91 AUX_B3 LS I O Low Speed Input Output 92 AUX_B2 LS 1 0 Low Speed Input Output 93 AUX_B1 LS 1 0 Low Speed Input Output 94 AUX_BO LS 1 0 Low Speed Input Output 96 AUX A3 LS 1 0 Low Speed Input Output 97 AUX A2 LS 1 0 Low Speed Input Output 98 AUX A1 LS 1 0 Low Speed Input Output 99 AUX A0 LS 1 0 Low Speed Input Ou
21. ce The signals are controlled by the C master unless otherwise specified For a diagram of the procedure see Figure 30 The steps for a read procedure are as follows 1 Senda start condition while holding the I2C SCL line high pull the 12C_SDA line low 2 Sendthe AD8197B part address seven bits The upper four bits of the AD8197B part address are the static value 1001 and the three LSBs are set by Input Pin 12C_ADDR2 Input Pin 2C ADDRI and Input Pin 12C_ADDRO LSB This transfer should be MSB first 3 Sendthe write indicator bit 0 4 Wait for the AD8197B to acknowledge the request 5 Sendthe register address eight bits from which data is to be read This transfer should be MSB first 6 Wait for the AD8197B to acknowledge the request 7 Sendarepeated start condition Sr by holding the I2C SCL line high and pulling the 12C_SDA line low 8 Resendthe AD8197B part address seven bits from Step 2 The upper four bits of the AD8197B part address are the static value 1001 and the three LSBs are set by the Input Pin I2C ADDR2 DC ADDRI and Input Pin DC ADDRO LSB This transfer should be MSB first 9 Send the read indicator bit 1 10 Wait for the AD8197B to acknowledge the request 11 The AD8197B serially transfers the data eight bits held in the register indicated by the address set in Step 5 This data is sent MSB first 12 Acknowledge the data from the AD8197B 13 Perform one of the following
22. color HDMI formats and greater than UXGA 1600 x 1200 DVI resolutions 2 Inputcable equalizer enables use of long cables at the input more than 20 meters of 24 AWG cable at 2 25 Gbps 3 Auxiliary switch routes a DDC bus and two additional signals for a single chip HDMI 1 3 receive compliant solution One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2008 Analog Devices Inc All rights reserved AD8197B TABLE OF CONTENTS ECM a 1 Applications vaciadas lili ii 1 Typical Application thee tette heit ebrei 1 Functional Block Diagram seen 1 General Description essent 1 Product Highlights tete 1 Revision History eeiteteterttee ttti rtt eerie tens 2 SPECiAM CATIONS R 3 Absolute Maximum Ratings essent 5 Thermal Resistance seen 5 Maximum Power Dissipation occnoncononcnnncnnccnccncrnsrnsirnsanss 5 ESD GCa tion cette eiecti terii tins 5 Pin Configuration and Function Descriptions 6 Typical Performance Characteristics sse 9 Theory of Operation ep RH UENIRE TRE 13 A E E EE E E S 13 Input Channels eiecit etit tie eret 13 Output Channels n ii 13 Auxiliary Swite lias iret nas 14 Serial Control Interface seen 15 jC 15 Write Proc dures iet mrt en 15 Read Procedure ui cli 16 REVISION HISTORY 1 08 Revision 0 Initial
23. d Input 26 I2C ADDRO Control lC Address 1 LSB 27 12C_ADDR1 Control lC Address 2 LSB 28 I2C ADDR2 Control C Address 3 LSB 29 95 DVEE Power Negative Digital and Auxiliary Multiplexer Power Supply 0 V nominal 30 PP CHO Control High Speed Source Selection Parallel Interface LSB 31 PP CHI Control High Speed Source Selection Parallel Interface MSB 32 38 47 DVCC Power Positive Digital Power Supply 3 3 V nominal 33 ONO HSO High Speed Output Complement 34 OPO HSO High Speed Output 35 41 VTTO Power Output Termination Supply Nominally connected to AVCC 36 ON1 HSO High Speed Output Complement 37 OP1 HSO High Speed Output 39 ON2 HSO High Speed Output Complement 40 OP2 HSO High Speed Output 42 ON3 HSO High Speed Output Complement 43 OP3 HSO High Speed Output 44 RESET Control Configuration Registers Reset Normally pulled up to AVCC 45 PP PREO Control High Speed Pre Emphasis Selection Parallel Interface LSB 46 PP PRETI Control High Speed Pre Emphasis Selection Parallel Interface MSB 48 PP OCL Control High Speed Output Current Level Parallel Interface 49 12C_SCL Control IC Clock 50 I2C SDA Control IC Data 52 IN DO HS High Speed Input Complement 53 IP_DO HS High Speed Input 55 IN_D1 HS High Speed Input Complement 56 IP_D1 HS High Speed Input 58 IN_D2 HS High Speed Input Complement 59 IP_D2 HS High Speed Input 61 IN_D3 HS High Speed Input Complement 62 IP_D3 HS High Speed Input 64 IN
24. e being sent over the cable The signal degradation of HDMI cables increases with data rate e Edge rates the edge rates of the source input Slower input edges result in more significant data eye closure at the end of a cable e Receiver sensitivity the sensitivity of the terminating receiver As such specific cable types and lengths are not recommended for use with a particular equalizer setting In nearly all applica tions the AD8197B equalization level can be set to high or 12 dB for all input cable configurations at all data rates without degrading the signal integrity PCB LAYOUT GUIDELINES The AD8197B is used to switch two distinctly different types of signals both of which are required for HDMI and DVI video These signal groups require different treatment when laying out a PC board The first group of signals carries the audiovisual AV data HDMU DVI video signals are differential unidirectional and high speed up to 2 25 Gbps The channels that carry the video data must be controlled impedance terminated at the receiver and capable of operating at the maximum specified system data rate It is especially important to note that the differential traces that carry the TMDS signals should be designed with a controlled differential impedance of 100 O The AD8197B provides single ended 50 terminations on chip for both its inputs and outputs and both the input and output terminations can be enabled or disabled thr
25. e ps 9 AD8197B a n co AVCC 13 Not to Scale 63 AVCC IN A0 14 62 iP n3 IP A0 15 61 IN p3 AVEE 16 60 AVEE IN A1 17 59 IP D2 IP A1 18 58 IN D2 vTTI 19 57 VTTI IN A2 20 56 IP D1 IP A2 21 55 IN D1 avcc 22 54 avcc IN A3 23 53 IP Do IP A3 24 52 IN Do AVEE 25 51 AVEE SIS gR Sas Sy Sess Eeee F SSS Sele O wuucec oococo crzowswoool eo ozid2a x SES AC lt E o Laa amp S 8 H 000 aa 2 Nag S Figure 3 Pin Configuration Table 4 Pin Function Descriptions Pin No Mnemonic Type Description 1 13 22 54 63 75 AVCC Power Positive Analog Supply 3 3 V nominal 2 IN_BO HS High Speed Input Complement 3 IP_BO HS High Speed Input 4 10 16 25 51 60 66 72 AVEE Power Negative Analog Supply 0 V nominal 5 IN B1 HS High Speed Input Complement 6 IP B1 HSI High Speed Input 7 19 57 69 VTTI Power Input Termination Supply Nominally connected to AVCC 8 IN B2 HS High Speed Input Complement 9 IP_B2 HS High Speed Input 11 IN_B3 HS High Speed Input Complement 12 IP_B3 HS High Speed Input 14 IN_AO HS High Speed Input Complement 15 IP_AO HS High Speed Input 17 IN_A1 HS High Speed Input Complement 18 IP_A1 HS High Speed Input 20 IN_A2 HS High Speed Input Complement 21 IP_A2 HS High Speed Input Rev 0 Page 6 of 28 AD8197B Pin No Mnemonic Type Description 23 IN_A3 HS High Speed Input Complement 24 IP_A3 HS High Spee
26. ested for a particular equalization setting because cable performance varies widely between manufacturers however in general the equalization of the AD8197B can be set to 12 dB without degrading the signal integrity even for short input cables At the 12 dB setting the AD8197B can equalize more than 20 meters of 24 AWG cable at 2 25 Gbps OUTPUT CHANNELS Each high speed output differential pair is terminated to the 3 3 V VITO power supply through two 50 Q on chip resistors see Figure 26 This termination is user selectable it can be turned on or off by programming the TX_PTO bit of the transmitter settings register through the serial control interface or by setting the PP OTO pin of the parallel control interface The output termination resistors of the AD8197B back terminate the output TMDS transmission lines These back terminations as recommended in the HDMI 1 3 specification act to absorb reflections from impedance discontinuities on the output traces improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed For example interlayer vias can be used to route the AD8197B TMDS outputs on multiple layers of the PCB without severely degrading the quality of the output signal The AD8197B output has a disable feature that places the outputs in a tristate mode This mode is enabled by program ming the HS EN bit of the high speed device modes register through the serial con
27. he output traces and adding flexibility to how the output traces can be routed For example interlayer vias can be used to route the AD8197B TMDS outputs on multiple layers of the PCB without severely degrading the quality of the output signal Auxiliary Control Signals There are four single ended control signals associated with each source or sink in an HDMI DVI application These are hot plug detect HPD consumer electronics control CEC and two display data channel DDC lines The two signals on the DDC bus are SDA and SCL serial data and serial clock respectively These four signals can be switched through the auxiliary bus of Rev 0 Page 25 of 28 AD8197B the AD8197B and do not need to be routed with the same strict considerations as the high speed TMDS signals In general it is sufficient to route each auxiliary signal as a single ended trace These signals are not sensitive to impedance discontinuities do not require a reference plane and can be routed on multiple layers of the PCB However it is best to follow strict layout practices whenever possible to prevent the PCB design from affecting the overall application The specific routing of the HPD CEC and DDC lines depends upon the application in which the AD8197B is being used For example the maximum speed of signals present on the auxiliary lines is 100 kHz I C data on the DDC lines therefore any layout that enables 100 kHz I C to be passed over the DDC
28. her write 9c Senda repeated start condition while holding the I2C SCL line high pull the 12C_SDA line low and continue with Step 2 of the read procedure in the Read Procedure section to perform a read from another address 9d Senda repeated start condition while holding the I2C SCL line high pull the 12C_SDA line low and continue with Step 8 of the read procedure in the Read Procedure section to perform a read from the same address set in Step 5 RW 1 1 1 1 I j j i i i l l l I i EXAMPLE I I l i I l l l l 1 l I I I l I l 12C SDA 1 I I l l 1 l 1 i Y l 1 I I l l I i 1 1 1 1 1 1 I l 1 1 THE SWITCHING UPDATE DELAY BEGINS AT THE FALLING EDGE OF THE LAST DATA BIT FOR EXAMPLE THE FALLING EDGE JUST BEFORE STEP 8 07015 028 Figure 29 PC Write Diagram Rev 0 Page 15 of 28 AD8197B MEME E A oo a at en da eS a ay LRA tal Uo ey Oe boc d c UN i M aN 1 AR RI pg p A A oO Ra S D S D O 1 GENERAL CASE FIXED PART FIXED PART I2C SDA START ADDR ADDR 99 REGISTER ADDR Xr ADDR ADDR a DATA C STOP ACK 1 n LIBI BEUEL BU THE TP BTE LL 00 CO 30000 Go Figure 30 PC Read Diagram 07015 029 READ PROCEDURE To read data from the AD8197B register set an I C master such as a microcontroller needs to send the appropriate control signals to the AD8197B slave devi
29. igh speed outputs must be disabled if there are no output termination resistors present in the system The output pre emphasis can be manually configured to provide one of four different levels of high frequency boost The specific boost level is selected by programming the TX_PE bits of the transmitter settings register through the serial control interface or by setting the PP_PE bus of the parallel control interface No specific cable length is suggested for a particular pre emphasis setting because cable performance varies widely between manufacturers AUXILIARY SWITCH The auxiliary low speed lines have no amplification They are routed using a passive switch that is bandwidth compatible with standard speed I C The schematic equivalent for this passive connection is shown in Figure 27 R AUX AUX A0 cp AUX COMO VC aux x a VC aux Figure 27 Auxiliary Channel Simplified Schematic AUX_A0 to AUX COMO Routing Example 07015 026 When turning off the AD8197B care needs to be taken with the AMUXVCC supply to ensure that the auxiliary multiplexer pins remain in a high impedance state A scenario that illustrates this requirement is one where the auxiliary multiplexer is used to switch the display data channel DDC bus In some applica tions additional devices can be connected to the DDC bus such as an EEPROM with EDID information upstream of the AD8197B Extended display identification data EDID is a VESA standard defi
30. in length to minimize intrapair skew Maintaining the physical symmetry of a differential pair is integral to ensuring its signal integrity excessive intrapair skew can introduce jitter through duty cycle distortion DCD The p and n of a given differential pair should always be routed together to establish the required 100 2 differ ential impedance Enough space should be left between the differential pairs of a given group so that the n of one pair does not couple to the p of another pair For example one technique is to make the interpair distance 4 to 10 times wider than the intrapair spacing Any group of four TMDS channels Input A Input B Input C Input D or the output should have closely matched trace lengths to minimize interpair skew Severe interpair skew can cause the data on the four different channels of a group to arrive out of alignment with one another A good practice is to match the trace lengths for a given group of four channels to within 0 05 inches on FR4 material Minimizing intrapair and interpair skew becomes increasingly important as data rates increase Any introduced skew consti tutes a correspondingly larger fraction of a bit period at higher data rates Though the AD8197B features input equalization and output pre emphasis the length of the TMDS traces should be minimized to reduce overall signal degradation Commonly used PC board material such as FR4 is lossy at high frequencies therefore long trace
31. irectly to the supply planes and be placed within a few centimeters of the AD8197B The AMUXVCC supply does not require additional bypassing This bypassing scheme is illustrated in Figure 35 DECOUPLING CAPACITORS 774 T EULTELEETHELHELTTLETLTT AD8197B STULL AUXILIARY LINES yy Ly TMDS TRACES 07015 034 Figure 35 Example Placement of Power Supply Decoupling Capacitors Around the AD8197B Rev 0 Page 27 of 28 AD8197B OUTLINE DIMENSIONS TOP VIEW PINS DOWN 1 45 140 E 1 35 f A ic AY vu 45 i X To 0 08 COPLANARITY VIEWA ROTATED 90 CCW 051706 A COMPLIANT TO JEDEC STANDARDS MS 026 BED Figure 36 100 Lead Low Profile Quad Flat Package LQFP ST 100 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Quantity AD8197BASTZ 40 C to 85 C 100 Lead Low Profile Quad Flat Package LQFP ST 100 AD8197BASTZ RL 40 C to 85 C 100 Lead Low Profile Quad Flat Package LOFP ST 100 1 000 AD8197B EVALZ Evaluation Board 1Z RoHS Compliant Part 2008 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D07015 0 1 08 0 DEVICES www analo g com Rev 0 Page 28 of 28
32. n internal layer of the board If microstrip traces are used there should be a continuous reference plane on the PCB layer directly below the traces If stripline traces are used they must be sandwiched between two continuous reference planes in the PCB stack up Additionally the p and n of each differential pair must have a controlled differential impedance of 100 O The characteristic impedance of a differential pair is a function of several variables including the trace width the distance separating the two traces the spacing between the traces and the reference plane and the dielectric constant of the PC board binder material Interlayer vias introduce impedance discontinuities that can cause reflections and jitter on the signal path therefore it is preferable to route the TMDS lines exclusively on one layer of the board particularly for the input traces In some applications such as using multiple AD8197Bs to construct large input arrays the use of interlayer vias becomes unavoidable In these situations the input termination feature of the AD8197B improves system signal integrity by absorbing reflections Take care to use vias minimally and to place vias symmetrically for each side of a given differential pair Furthermore to prevent unwanted signal coupling and Rev 0 Page 24 of 28 interference route the TMDS signals away from other signals and noise sources on the PCB Both traces of a given differential pair must be equal
33. ndard does not incorporate audio information The fourth high speed differ ential pair is used for the AV data word clock and runs at one tenth the speed of the TMDS data channels The four high speed channels of the AD8197B are identical No concession was made to lower the bandwidth of the fourth channel for the pixel clock so any channel can be used for any TMDS signal The user chooses which signal is routed over which channel Additionally the TMDS channels are symmetrical therefore the p and n of a given differential pair are inter changeable provided the inversion is consistent across all inputs and outputs of the AD8197B However the routing between inputs and outputs through the AD8197B is fixed For example Output Channel 0 always switches between Input AO Input BO Input CO Input DO and so forth The AD8197B buffers the TMDS signals and the input traces can be considered electrically independent of the output traces In most applications the quality of the signal on the input TMDS traces is more sensitive to the PCB layout Regardless of the data being carried on a specific TMDS channel or whether the TMDS line is at the input or the output of the AD8197B all four high speed signals should be routed on a PCB in accor dance with the same RF layout guidelines Layout for the TMDS Signals The TMDS differential pairs can be either microstrip traces routed on the outer layer of a board or stripline traces routed on a
34. ned data format for conveying display configuration information to sources to optimize display use EDID devices may need to be available via the DDC bus regardless of the state of the AD8197B and any downstream circuit For this configuration the auxiliary inputs of the powered down AD8197B need to be in a high impedance state to avoid pulling down on the DDC lines and preventing these other devices from using the bus The AD8197B requires 5 V on its supply pin AMUXVCC in order for the AUXMUX channels to be high impedance When a TV is powered off it cannot provide such a supply However it can be provided from any HDMI source that is plugged into it A Schottky diode network as shown in Figure 28 uses the 5 V supply Pin 18 from any HDMI DVI source to power AMUXVCC and guarantee high impedance of the auxiliary multiplexer pins The AMUXVCC supply does not draw any significant static current The use of diodes ensures that connected HDMI sources do not load this circuit if their 5 V pin is low impedance when powered off The 100 kQ resistor ensures that a minimum of current flows through the diodes to keep them forward biased This precaution does not need to be taken if the DDC peripheral circuitry is connected to the bus downstream of the AD8197B 5V INTERNAL IF ANY PIN 18 HDMI CONNECTOR PIN 14 DVI CONNECTOR BATS4L SOURCE A 5VO PIN 18 HDMI CONNECTOR PIN 14 DVI CONNECTOR BAT54L BAT54L f o O 5V 1 SOUR
35. ough the serial control interface The output termi nations can also be enabled or disabled through the parallel control interface Transmitter termination is not required by the HDMI 1 3 standard but its inclusion improves the overall system signal integrity The audiovisual AV data carried on these high speed channels is encoded by a technique called transmission minimized differ ential signaling TMDS and in the case of HDMI is also encrypted according to the high bandwidth digital copy protection HDCP standard The second group of signals consists of low speed auxiliary control signals used for communication between a source and a sink Depending upon the application these signals can include the DDC bus this is an PC bus used to send EDID information and HDCP encryption keys between the source and the sink the consumer electronics control CEC line and the hot plug detect HPD line These auxiliary signals are bidirectional low speed and transferred over a single ended transmission line that does not need to have controlled impedance The primary concern with laying out the auxiliary lines is ensuring that they conform to the IC bus standard and do not have excessive capacitive loading TMDS Signals In the HDMI DVI standard four differential pairs carry the TMDS signals In DVI three of these pairs are dedicated to carrying RGB video and sync data For HDMI audio data is interleaved with the video data the DVI sta
36. own The AD8197B is an HDMI DVI switch featuring equalized TMDS inputs and pre emphasized TMDS outputs It is in tended for use as a 4 1 switch in systems with long cable runs on both the input and or the output and is fully HDMI 1 3 receive compliant PINOUT The AD8197B is designed to have an HDMI DVI receiver pinout at its input and a transmitter pinout at its output This makes the AD8197B ideal for use in AVR type applications where a designer routes both the inputs and the outputs directly to HDMI DVI connectors as shown in Figure 31 When the AD8197B is used in receiver type applications it is necessary to change the order of the output pins on the PCB to align with the on board receiver One advantage of the AD8197B in an AVR type application is that all ofthe high speed signals can be routed on one side the topside of the board as shown in Figure 31 In addition to 12 dB of input equalization the AD8197B provides up to 6 dB of output pre emphasis that boosts the output TMDS signals and allows the AD8197B to precompensate when driving long PCB traces or output cables The net effect of the input equali zation and output pre emphasis of the AD8197B is that the AD8197B can compensate for the signal degradation of both input and output cables it acts to reopen a closed input data eye and transmit a full swing HDMI signal to an end receiver More information on the specific performance metrics of the AD8197B can be found in
37. rential TMDS input pair can be controlled by programming the appropriate RX TO bit in the receiver settings register Refer to Table 5 and Table 12 By default the input terminations are disabled switched open after reset The input terminations cannot be switched when programming the AD8197B through the parallel control interface This limits the usefulness of the parallel control interface Some systems require that the input terminations be switched on only for the one selected HDMI source The input termina tions for the three unselected HDMI sources require their input termination switches to be open The AD8197B can perform AD8197B this operation but it is not automatic To obtain this functionality the channel selection and the input termination status must be separately programmed via the I C serial control interface vri 07015 035 AVEE Figure 25 High Speed Input Simplified Schematic The input equalizer can be manually configured to provide two different levels of high frequency boost 6 dB or 12 dB The user can individually control the equalization level of the eight high speed input channels by selectively programming the associated RX EQ bits in the receive equalizer register through the serial control interface Alternately the user can globally control the equalization level of all eight high speed input channels by setting the PP EQ pin of the parallel control interface No specific cable length is sugg
38. s Input Termination RX EOIXI Corresponding Input TMDS Channel On Off Select Bit Bit O BO Table 10 RX TS Description Bit 1 B1 RX TS Description Bit 2 B2 0 All input terminations off switches open Bit 3 B3 1 Input termination resistor switch is controlled by Bit 4 AO RX_TO x control bits from Input Term Resistor Bit 5 A1 Control Registers 1 and 2 Bit 6 A2 Bit 7 A3 Bit 8 C3 Bit 9 C2 Bit 10 C1 Bit 11 CO Bit 12 D3 Bit 13 D2 Bit 14 D1 Bit 15 DO Rev 0 Page 19 of 28 AD8197B TRANSMITTER SETTINGS REGISTER TX PTO High Speed TMDS Output Termination On Off TX PE 1 0 High Speed TMDS Output Pre Emphasis Select Bit For All Channels Level Select Bus For All TMDS Channels Table 16 TX_PTO Description Table 15 TX_PE 1 0 Description TX_PTO Description TX PE 1 0 Description 0 Output termination off 00 No pre emphasis 0 dB 1 Output termination on 01 Low pre emphasis 2 dB i d Medi hasis 4 dB TX OCL High Speed TMDS Output Current Level Select S ium oae asis Bit For All Channels 11 High pre emphasis 6 dB Table 17 TX_OCL Description TX_OCL Description 0 Output current set to 10 mA 1 Output current set to 20 mA Rev 0 Page 20 of 28 PARALLEL INTERFACE CONFIGURATION REGISTERS The parallel interface configuration registers can be directly set using the PP EN PP CH 1 0 PP EQ PP PRE 1 0 PP OTO and PP OCL pins This interface is accessible only after the part is rese
39. s on the circuit board increase signal attenuation resulting in decreased signal swing and increased jitter through intersymbol interference ISI Controlling the Characteristic Impedance of a TMDS Differential Pair The characteristic impedance of a differential pair depends on a number of variables including the trace width the distance between the two traces the height of the dielectric material between the trace and the reference plane below it and the dielectric constant of the PCB binder material To a lesser extent the characteristic impedance also depends upon the trace thickness and the presence of solder mask There are many combinations that can produce the correct characteristic impedance Generally working with the PC board fabricator is required to obtain a set of parameters to produce the desired results One consideration is how to guarantee a differential pair with a differential impedance of 100 Q over the entire length of the trace One technique to accomplish this is to change the width of the traces in a differential pair based on how closely one trace is coupled to the other When the two traces of a differential pair are close and strongly coupled they should have a width that produces a 100 Q differential impedance When the traces split apart to go into a connector for example and are no AD8197B longer so strongly coupled the width of the traces should be increased to yield a differential impedance of 1
40. t and before any registers are accessed using the serial control interface Because most systems use serial control for the input termination resistors the parallel control interface is limited to controlling the AD8197B status after reset and before serial logic control The state of each pin is set by tying it to 3 3 V Logic 1 or 0 V Logic 0 Table 18 Parallel Interface Register Map AD8197B Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O High Speed Device High speed High speed source select Modes switch enable PP_EN 0 0 0 0 PP CH 1 PP CHI O Auxiliary Device Auxiliary switch Auxiliary switch source select Modes enable 1 0 0 0 0 PP CH 1 PP CHI O Receiver Settings Input term select terminations always open in parallel control mode 1 Input Termination Source A and Source B input termination select No parallel control termination always open Resistor Control 1 0 0 0 0 0 0 0 0 Input Termination Source C and Source D input termination select No parallel control termination always open Resistor Control 2 0 0 0 0 0 0 0 0 Receive Equalizer 1 Source A and Source B input equalization level select PP EQ PP EQ PP EQ PP EQ PP EQ PP EQ PP EQ PP EQ Receive Equalizer 2 Source C and Source D input equalization level select PP EQ PP EQ PP EQ PP EQ PP EQ PP EQ PP EQ PP EQ Transmitter Settings Output pre emphasis Output termination Output current level select
41. t termination for TMDS Channel X disconnected HS CH 1 0 High Speed TMDS Switch Source Select Bus 1 Input termination for TMDS Channel X connected Table 7 HS CH Mapping Table 12 RX_TO X Mapping HS CH 1 0 O 3 0 Description RX TOIX Corresponding Input TMDS Channel 00 A 3 0 High Speed Source A switched to output BIO BO 01 B 3 0 High Speed Source B switched to output Bit 1 B1 10 C 3 0 High Speed Source C switched to output Bit 2 B2 11 D 3 0 High Speed Source D switched to output Bit3 B3 AUXILIARY DEVICE MODES REGISTER Bit 4 AB AUX EN Auxiliary Low Speed Switch Enable Bit e de Table 8 AUX_EN Description Bit 7 A3 AUX_EN Description Bit 8 C3 0 Auxiliary switch off Bit 9 C2 1 Auxiliary switch on Bit 10 C1 Bit 11 CO AUX CH 1 0 Auxiliary Low Speed Switch Source Bit 12 D3 Select Bus Bit 13 D2 Table 9 AUX CH Mapping Bit 14 Di AUX CH 3 0 AUX COMI3 0 Description Bit 15 DO me aren ieee reer eet RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2 01 AUX B 3 0 Auxiliary Source B switched RX EQ X High Speed TMDS Input X Equalization Level to output Select Bit 10 AUX C 3 0 A C switched Table 13 RX_EQ X Description 11 AUX DI3 0 Auxiliary Source D switched RX EQIX Description to output 0 Low equalization 6 dB 1 High equalization 12 dB RECEIVER SETTINGS REGISTER Table 14 RX EQ X Mapping RX TS High Speed TMDS Channel
42. te data to the AD8197B register set an I C master such as a microcontroller needs to send the appropriate control signals to the AD8197B slave device The signals are controlled by the PC master unless otherwise specified For a diagram of the procedure see Figure 29 The steps for a write procedure are as follows 1 Senda start condition while holding the I2C SCL line high pull the I2C SDA line low 2 Send the AD8197B part address seven bits The upper four bits of the AD8197B part address are the static value 1001 and the three LSBs are set by Input Pin I2C_ADDR2 Input Pin 12C_ADDRI and Input Pin 12C_ADDRO LSB This transfer should be MSB first AD8197B Send the write indicator bit 0 Wait for the AD8197B to acknowledge the request Send the register address eight bits to which data is to be written This transfer should be MSB first Wait for the AD8197B to acknowledge the request Send the data eight bits to be written to the register whose address was set in Step 5 This transfer should be MSB first Wait for the AD8197B to acknowledge the request Perform one of the following 9a Senda stop condition while holding the I2C SCL line high pull the 12C_SDA line high and release control of the bus to end the transaction shown in Figure 29 9b Senda repeated start condition while holding the I2C SCL line high pull the 12C_SDA line low and continue with Step 2 in this procedure to perform anot
43. ted to the outputs In this state the AD8197B looks like a 100 Q resistor between the selected auxiliary inputs and the corresponding outputs as illustrated in Figure 27 The AD8197B does not buffer the auxiliary signals therefore the input traces output traces and the connection through the AD8197B all must be considered when designing a PCB to meet HDMI DVI specifications The unselected auxiliary inputs of the AD8197B are placed into a high impedance mode when the device is powered up To ensure that all of the auxiliary inputs of the AD8197B are in a high impedance mode when the device is powered off it is necessary to power the AMUXVCC supply as illustrated in Figure 28 In contrast to the auxiliary signals the AD8197B buffers the TMDS signals allowing a PCB designer to layout the TMDS inputs independently of the outputs Power Supplies The AD8197B has five separate power supplies referenced to two separate grounds The supply ground pairs are AVCC AV EE e VTTI AVEE e VTTO AVEE e DVCC DVEE e AMUXVCC DVEE The AVCC AVEE 3 3 V and DVCC DVEE 3 3 V supplies power the core of the AD8197B The VTTI AVEE supply 3 3 V powers the input termination see Figure 25 Similarly the VTTO AVEE supply 3 3 V powers the output termination see Figure 26 The AMUXVCC DVEE supply 3 3 V to 5 V powers the auxiliary multiplexer core and determines the maxi mum allowed voltage on the auxiliary lines For example if the DDC bus
44. the Typical Performance Characteristics section The AD8197B also provides a distinct advantage in receive type applications because it is a fully buffered HDMI DVI switch Although inverting the output pin order of the AD8197B on the PCB requires a designer to place vias in the high speed signal path the AD8197B fully buffers and electrically decouples the outputs from the inputs Therefore the effects of the vias placed on the output signal lines are not seen at the input of the AD8197B The programmable output terminations also improve signal quality at the output of the AD8197B The PCB designer there fore has significantly improved flexibility in the placement and routing of the output signal path with the AD8197B over other solutions CABLE LENGTHS AND EQUALIZATION The AD8197B offers two levels of programmable equalization for the high speed inputs 6 dB and 12 dB The equalizer of the AD8197B supports video data rates of up to 2 25 Gbps and as shown in Figure 14 it can equalize more than 20 meters of 24 AWG HDMI cable at 2 25 Gbps which corresponds to the video format 1080p with deep color Rev 0 Page 23 of 28 AD8197B The length of cable that can be used in a typical HDMI DVI application depends on a large number of factors including e Cable quality the quality of the cable in terms of conductor wire gauge and shielding Thicker conductors have lower signal degradation per unit length e Data rate the data rat
45. therwise noted Table 1 Parameter Conditions Comments Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Data Rate DR per Channel NRZ 2 25 Gbps Bit Error Rate BER PRBS 22 1 107 Added Deterministic Jitter DR x 2 25 Gbps PRBS 27 1 EQ 12 dB 25 ps p p Added Random Jitter 1 ps rms Differential Intrapair Skew At output 1 ps Differential Interpair Skew At output 40 ps EQUALIZATION PERFORMANCE Receiver Highest Setting Boost frequency 825 MHz 12 dB Transmitter Highest Setting Boost frequency 825 MHz 6 dB INPUT CHARACTERISTICS Input Voltage Swing Differential 150 1200 mV Input Common Mode Voltage Vicm AVCC 800 AVCC mV OUTPUT CHARACTERISTICS High Voltage Level Single ended high speed channel AVCC 10 AVCC 10 mV Low Voltage Level Single ended high speed channel AVCC 600 AVCC 400 mV Rise Fall Time 2096 to 8096 75 135 200 ps INPUT TERMINATION Resistance Single ended 50 Q AUXILIARY CHANNELS On Resistance Raux 100 Q On Capacitance Caux DC bias 2 5 V ac voltage 3 5 V f 100 kHz 8 pF Input Output Voltage Range DVEE AMUXVCC V POWER SUPPLY AVCC Operating range 3 3 3 3 6 V QUIESCENT CURRENT AVCC Outputs disabled 30 40 44 mA Outputs enabled no pre emphasis 52 60 66 mA Outputs enabled maximum pre emphasis 95 110 122 mA VTTI Input termination on 5 40 54 mA VTTO Output termination on no pre emphasis 35 40 46 mA Output termination on maximum pre emphasis 72 80 90 mA DVCC
46. tput 100 PP OTO Control High Speed Output Termination Selection Parallel Interface 1 HS high speed LS low speed input O output Rev 0 Page 8 of 28 AD8197B TYPICAL PERFORMANCE CHARACTERISTICS Ta 27 C AVCC 3 3 V VTTI 3 3 V VITO 3 3 V DVCC 3 3 V AMUXVCC 5 V AVEE 0 V DVEE 0 V differential input swing 1000 mV TMDS outputs terminated with external 50 Q resistors to 3 3 V pattern PRBS 27 1 data rate 2 25 Gbps unless otherwise noted HDMI CABLE DIGITAL O y PATTERN GENERATOR AD8197B SERIAL DATA EVALUATION BOARD ANALYZER SMA COAX CABLE REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07015 004 Figure 4 Test Circuit Diagram for Rx Eye Diagram 250mV DIV 250mV DIV 07015 005 07015 007 0 125UI DIV AT 2 25Gbps 0 125Ul DIV AT 2 25Gbps Figure 5 Rx Eye Diagram at TP2 Cable 2 meters 30 AWG Figure 7 Rx Eye Diagram at TP3 EQ 6 dB Cable 2 meters 30 AWG 250mV DIV 250mV DIV 07015 006 07015 008 0 125UI DIV AT 2 25Gbps 0 125UI DIV AT 2 25Gbps Figure 6 Rx Eye Diagram at TP2 Cable 20 meters 24 AWG Figure 8 Rx Eye Diagram at TP3 EQ 12 dB Cable 20 meters 24 AWG Rev 0 Page 9 of 28 AD8197B Ta 27 C AVCC 3 3 V VTTI 3 3 V VITO 3 3 V DVCC 3 3 V AMUXVCC 5 V AVEE 0 V DVEE 0 V differential input swing 1000 mV TMDS outputs terminated with external 50 Q resistors to 3 3 V pattern PRBS 27
47. trol interface or by setting the PP EN pin of the parallel control interface Larger wire ORed arrays can be constructed using the AD8197B in this mode Rev 0 Page 13 of 28 AD8197B VTTO DISABLE 2 AVEE 07015 025 Figure 26 High Speed Output Simplified Schematic The AD8197B requires output termination resistors when the high speed outputs are enabled Termination can be internal and or external The internal terminations of the AD8197B are enabled by programming the TX PTO bit of the transmitter settings register or by setting the PP OTO pin of the parallel control interface The internal terminations of the AD8197B default to the setting indicated by PP OTO upon reset External terminations can be provided either by on board resistors or by the input termination resistors of an HDMI DVI receiver If both the internal terminations are enabled and external termi nations are present set the output current level to 20 mA by programming the TX OCL bit of the transmitter settings register through the serial control interface or by setting the PP OCL pin of the parallel control interface The output current level defaults to the level indicated by PP OCL upon reset If only external terminations are provided if the internal terminations are disabled set the output current level to 10 mA by programming the TX_OCL bit of the transmitter settings register or by setting the PP_OCL pin of the parallel control interface The h
48. uration registers but the AD8197B does not physically update until the end of that register s delay window Writing new values during the delay window does not reset the window new values supersede the previously written values At the end of the delay window the AD8197B physically assumes the state indicated by the last set of values written to the configuration registers If the configuration registers are written after the delay window ends the AD8197B immediately updates and a new delay window begins Rev 0 Page 16 of 28 PARALLEL CONTROL INTERFACE The AD8197B can be partially controlled through the parallel interface using the PP EN PP CH 1 0 PP EQ PP PRE 1 0 PP OTO and PP OCL pins Logic levels for the parallel interface pins are set in accordance with the specifications listed in Table 1 Setting these pins updates the parallel control interface registers as listed in Table 18 Following a reset the AD8197B can be controlled through the parallel control interface until the first serial control event occurs As soon as any serial control event occurs the serial programming values override any prior parallel programming values and the parallel control interface is disabled until the part is subsequently reset The default serial programming values correspond to the state of the serial interface configuration registers as listed in Table 5 AD8197B Note that after changing the status of the channel selection PP C

ANALOG DEVICES AD8197B English products handbook Rev 0

Contents

Download Pdf Manuals

Related Search

Related Contents