ANALOG DEVICES AD5232 English products handbook Rev B
Contents
1. 3 Electrical Characteristics 10 50 100 Versions 3 Interface Timing 5 Absolute Maximum 7 Thermal Resistance 7 ESD ze esie ust 7 Pin Configuration and Function 8 Typical Performance Characteristics sse 9 Test CITCUITS ettet 2 12 14 Scratch Pad and 14 Basic Operation ite 14 EEMEM 14 REVISION HISTORY 09 11 Rev A to Rev Change to Resistor Noise Voltage Parameter in Table 1 4 10 09 Rev 0 to Rev Updated Form t c ere quet prie Universal Changes to Data Sheet Title sse 1 Changes to Features 1 Changes to Applications Section sse 1 Change to Wiper Resistance Parameter Table 1 3 Digital Input Output Configuration eee 14 Serial Data Interface eite one geistige 15 Daisy Chaining Operation sette 15 Advanced Control Modes sse 17 Using Additional Internal Nonvolatile EEMEM 18 Terminal Voltage Operating Range sse 18 Det2. 5 TEMPERATURE C 10 25 40 Figure 10 Icm vs Temperature See Figure 30 256 026 18 008 02618 009 026 18 010 HA 50 35 20 5 10 25 40 55 70 85 TEMPERATURE C Figure 11 loo vs Temperature 5 5 SDI 5 00 2 5 007 2 00ms CH3 5 00 10 00 Figure 12 loo vs Time Save Program Mode d T SDI Ipp CH1 5 00V CH2 5 00V M 2 00ms CH3 5 00V 10 00V SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION IF COMMAND INSTRUCTION 0 NOP IS EXECUTED IMMEDIATELY AFTER COMMAND INSTRUCTION 1 READ EEMEM Figure 13 loo vs Time Read Mode 026 18 011 N 3 gt lt 02618 012 M 2mA DIV 02618 013 12 500kHz R 10kO 6 45kHz R 100 42 f 95kHz R 50kO GAIN dB Vin 100mV rms 30 2 5V Vss 2 5V 36 1MO TA 25 C 1k 10k 100k 1M FREQUENCY Hz 02618 014 Figure 14 3 dB Bandwidth vs Resistance THD NOISE 02618 015 FREQUENCY Hz Figure 15 Total Harmonic Dist
3. ui 2 72 13 o Vpp 7 5 5V 100mV AC Vss Vp 5V VA MEASURE AT Vy WITH CODE 0x80 25 C 1k 10k 100k 1M FREQUENCY Hz Figure 20 PSRR vs Frequency 120 a 5 100 ul s 8 Rap 10 lt Rag 100 9 60 Rag 50 5 9 4 40 Vpp Vaz 2 75 2 Vss Vg2 2 75 5 Vin 5 p p 25 20 10 100 FREQUENCY kHz Figure 21 Analog Crosstalk vs Frequency See Figure 31 Rev B Page 11 of 24 02618 020 02618 021 TEST CIRCUITS Figure 22 to Figure 32 define the test conditions that are used in the Specifications section 02618 022 NC NO CONNECT Figure 22 Resistor Position Nonlinearity Error Rheostat Operation R INL R DNL 1LSB V 2N 02618 023 Figure 23 Potentiometer Divider Nonlinearity Error INL DNL lw Rw Vus Vus2l lw 02618 024 V Vpp 10 PSRR dB 20 LOG AVpp AVus Vus C PSS 02618 025 Figure 25 Power Supply Sensitivity PSS PSRR Rev B Page 12 of 24 Vout OFFSET BIAS Y Figure 26 Inverting Gain OFFSET BIAS Figure 27 Noninverting Gain DUT Isw A NC Vss TO 02618 029 Figure 29 Incremental On Resistance 02618 026 026 18 027 02618 028 02618 030 lt Figure 30 Leakage Cur
4. Rev B Page 16 of 24 ADVANCED CONTROL MODES The AD5232 digital potentiometer contains a set of user program ming features to address the wide variety of applications avail able to these universal adjustment devices Key programming features include the following e Independently programmable read and write to all registers e Simultaneous refresh of all RDAC wiper registers from corresponding internal EEMEM registers Increment and decrement command instructions for each RDAC wiper register e Left and right bit shift of all wiper registers to achieve 6 dB level changes Nonvolatile storage of the present scratch pad RDACx register values into the corresponding EEMEMx register e Fourteen extra bytes of user addressable electrical erasable memory Increment and Decrement Commands The increment and decrement command instructions Command Instruction 14 Command Instruction 15 Command Instruction 6 and Command Instruction 7 are useful for the basic servo adjust ment application These commands simplify microcontroller software coding by eliminating the need to perform a readback of the current wiper position and then add a 1 to the register contents using the microcontroller adder The microcontroller sends an increment command instruction Command Instruc tion 14 to the digital potentiometer which automatically moves the wiper to the next resistance segment position The master increment command
5. RDACI and RDAC2 registers the corresponding nonvolatile EEMEM1 and EEMEM2 registers and the 14 spare USER EEMEM registers that are available for constant storage The basic mode of adjustment is the increment and decrement command instructions that control the wiper position setting register RDACx An internal scratch pad RDACx register be moved up or down one step of the nominal resistance between Terminal A and Terminal B This step adjustment linearly changes the wiper to Terminal resistance by one position segment of the device s end to end resistance Ras For exponential logarithmic changes in wiper setting a left right shift command instruction adjusts the levels in 6 dB steps which can be useful for audio and light alarm applications The AD5232 is available in a thin 16 lead TSSOP package All parts are guaranteed to operate over the extended industrial temperature range of 40 C to 85 C An evaluation board EVAL AD5232 10EBZ is available One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2001 2011 Analog Devices Inc All rights reserved TABLE OF CONTENTS Features LU LE Mer 1 Applications venen be itane UR 1 Functional Block Diagram 1 General Description eec eee 1 REVISION HistoEy este sted asserts 2 Sp cifications E
6. 2 1 501 MSB IN B15 500 MSB OUT RDY NOTES 1 THIS EXTRA BIT IS NOT DEFINED BUT IT IS USUALLY THE MSB OF THE CHARACTER THAT WAS JUST RECEIVED 2 THE CPOL 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK 026 18 003 Figure 3 CPHA 0 Rev B Page 6 of 24 02618 002 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 3 Parameter Rating Voo to GND 0 3 7 Vss to GND 0 3V 7V to Vss 7V Va to GND Ax Bx Ax Wx Bx Wx Intermittent Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature max Storage Temperature Range Lead Temperature Soldering Vapor Phase 60 sec Infrared 15 sec Package Power Dissipation Vss 0 3 V Voo 0 3V 20 2 mA 0 3 V Voo 0 3 V 40 C to 85 C 150 C 65 C to 150 C 215 C 220 C max Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE is specified for the worst case conditions that
7. a device soldered in a circuit board for surface mount packages Table 4 Thermal Resistance Package Type Unit 16 Lead TSSOP RU 16 150 28 C W ESD CAUTION 1 Maximum terminal current is bounded by the maximum current handling of the switches maximum power dissipation of the package and maximum applied voltage across any two of the A B and W terminals at a given resistance 2 Includes programming of nonvolatile memory ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev B Page 7 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 500 3 05232 41 PR GND TOP VIEW WP 5 Not to Scale Vss 5 12 A1 6 2 w1 10 w2 9 B2 8 4 Table 5 Pin Function Descriptions Pin No Mnemonic Description 1 CLK Serial Input Register Clock Shifts in one bit at a time on positive clock edges 2 SDI Serial Data Input The MSB is loaded first 3 SDO Serial Data Output This open drain output requires an external pull up resistor Command Instruction 9 and Command Instruction 10 a
8. 40 50 60 70 80 90 100 110 Ty JUNCTION TEMPERATURE C Figure 44 Flash EE Memory Data Retention EVALUATION BOARD Analog Devices Inc offers a user friendly EVAL AD5232 10EBZ evaluation kit that can be controlled by a personal computer through a printer port The driving program is self contained no programming languages or skills are needed 02618 044 Rev B Page 21 of 24 OUTLINE DIMENSIONS Loos COPLANARITY 0 10 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO 153 AB Figure 45 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 Dimensions shown in millimeters ORDERING GUIDE Number of End to EndRas Temperature Package Package Ordering 5 Description Option Quantity Branding AD5232BRU10 2 10 40 C to 85 C 16 Lead TSSOP RU 16 96 5232B10 AD5232BRU10 REEL7 2 10 40 C to 85 C 16 Lead TSSOP RU 16 1 000 5232B10 AD5232BRUZ10 2 10 40 C to 85 C 16 Lead TSSOP RU 16 96 5232B10 AD5232BRUZ10 REEL7 2 10 40 C to 85 C 16 Lead TSSOP RU 16 1 000 5232B10 AD5232BRU50 2 50 40 C to 85 16 Lead TSSOP RU 16 96 5232B50 AD5232BRU50 REEL7 2 50 40 C to 85 C 16 Lead TSSOP RU 16 1 000 5232B50 AD5232BRUZ50 2 50 40 C to 85 16 Lead TSSOP RU 16 96 5232B50 AD5232BRUZ50 REEL7 2 50 40 C to 85 C 16 Lead TSSOP RU 16 1 000 5232B50 AD5232BRU100 2 100 40 C to 85 C 16 Lead TSSOP RU 16 96 5232BC AD5232BRU100 REEL7 2 100 40 C to 8
9. 0 4 V Input Current Vin OV or 2 5 Input Capacitance 4 pF POWER SUPPLIES Single Supply Power Range Voo Vss 0V 2 7 5 5 Dual Supply Power Range Voo Vss 2 25 2 75 V Positive Supply Current Ipp Vin or Vi GND 3 5 10 Programming Mode Current Vi GND 35 Read Mode Current Vpp or Vii GND 0 9 3 9 mA Negative Supply Current Iss Vin or Vi GND 42 5 V Vss 2 5 V 3 5 10 uA Power Dissipation Poiss Voo or Vi GND 0 018 0 05 mW Power Supply Sensitivity PSS 5 V 10 0 002 0 01 Rev B Page 3 of 24 Parameter Symbol Conditions Min Unit DYNAMIC CHARACTERISTICS 9 Bandwidth 3 dB BW 10 R 10 500 kHz Total Harmonic Distortion THDw Va 1 V rms Vs OV f 1 kHz Ras 10 0 022 Va 1 V rms Vs OV f 1 kHz Ras 50 100 0 045 Vw Settling Time ts Voo 5 V Vss OV Va Vs 0 65 3 6 us Vw 0 50 error band Code 0x00 to Code 0x80 for Ras 10 50 100 Resistor Noise Voltage Rwe 5 f 1 kHz 9 nV 4Hz Crosstalk Cwi Cw2 Cr Vs measure Vw with 5 adjacent VR making full scale code change Analog Crosstalk Cwi Cw2 measure Vwi with Vw2 70 5 V p p f 10 kHz Code 0x80 Code OxFF FLASH EE MEMORY
10. 2 typical distribution of internal channel to channel Rsa match Device to device matching is dependent on process lot and exhibits a 40 to 20 variation The change in Rea with temperature has a 600 ppm C temperature coefficient Rev Page 19 of 24 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage pro portional to the input voltage applied to a given terminal For example connecting Terminal A to 5 V and Terminal B to GND produces an output voltage at the wiper that can be any value from 0 V to 5 V Each LSB of voltage is equal to the voltage applied across Terminal A to Terminal B divided by the 2 position resolution of the potentiometer divider The general equation defining the output voltage with respect to ground for any given input voltage applied to Terminal A to Terminal B is Rip 0 Vs 3 where Rws D can be obtained from Equation 1 and Rwa D can be obtained from Equation 2 Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature Here the output voltage is dependent on the ratio of the internal resistors not the absolute value therefore the drift improves to 15 ppm C There is no voltage polarity restriction between Terminal A Terminal B and Wiper Terminal W as long as the terminal voltage stays within Vss
11. Pulse Width the 10 ns CS High to CS High tis 4 RDY Rise to CS Fall tu 0 ns CS Rise to RDY Fall Time tis 015 03 ms Store Read EEMEM Time 116 Applies to Command Instruction 2 Command 25 ms Instruction 3 and Command Instruction 9 CS Rise to Clock Rise Fall Setup ti 10 ns Preset Pulse Width Asynchronous terw Not shown in timing diagram 50 ns Preset Response Time to RDY High teresp PR pulsed low to refresh wiper positions 70 us 1 Guaranteed by design not subject to production test 2 See the Timing Diagrams section for the location of measured values 3 Typicals represent average readings at 25 C and 5 V 4 Propagation delay depends on the value of Voo and Ci 5 Valid for commands that do not activate the RDY pin 5 RDY pin low only for Command Instruction 2 Command Instruction 3 Command Instruction 8 Command Instruction 9 Command Instruction 10 and the PR hardware pulse CMD_8 1 ms 9 _10 0 12 ms and CMD_2 20 ms Device operation at Ta 40 C and lt 3 V extends the save time to 35 ms Rev B Page 5 of 24 Timing Diagrams CLK 1 SDI SDO RDY NOTES 1 1 24 15 EXTRA THAT IS DEFINED BUT IS USUALLY THE LSB OF THE CHARACTER THAT WAS PREVIOUSLY TRANSMITTED 2 THE CPOL 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK CLK 0
12. and the corresponding serial data output appearing at the serial data output SDO pin in hexadecimal format At system power on the scratch pad register is refreshed with the last value saved in the register The factory preset EEMEM value is midscale The scratch pad wiper register can be refreshed with the current contents of the nonvolatile EEMEMx register under hardware control by pulsing the PR pin The application programming example shown in Table 6 lists two digital potentiometers set to independent data values The wiper positions are then saved in the corresponding nonvolatile registers Table 6 Application Programming Example SDI SDO Action 0xB040 Loads 0x40 data into the RDAC1 register Wiper W1 moves to 1 4 full scale position 0 20 0xB040 Saves a copy of the RDAC1 register contents into the corresponding EEMEM1 register 0xB180 0 20 Loads 0x80 data into the RDAC2 register Wiper W2 moves to 1 2 full scale position 0 21 OxB180 Saves copy of the RDAC2 register contents into the corresponding EEMEM2 register Note that the PR pulse first sets the wiper at midscale when it is brought to Logic 0 Then on the positive transition to logic high it reloads the DAC wiper register with the contents of EEMEMx Many additional advanced programming commands are avail able to simplify the variable resistor adjust
13. instruction Command Instruction 15 moves all potentiometer wipers by one position from their present position to the next resistor segment position The direction of movement is referenced to Terminal B Thus each Command Instruction 15 moves the wiper tap position farther from Terminal B Logarithmic Taper Mode Adjustment Programming instructions allow decrement and increment wiper position control by an individual potentiometer or in a ganged potentiometer arrangement where both wiper positions are changed at the same time These settings are activated by the 6 dB decrement and 6 dB increment command instructions Command Instruction 4 and Command Instruction 5 and Command Instruction 12 and Command Instruction 13 respectively For example starting with the wiper connected to Terminal B executing nine increment instructions Command Instruction 12 moves the wiper in 6 dB steps from the 0 of the Raa Terminal B position to the 100 of the Rsa position of the AD5232 8 bit potentiometer The 6 dB increment instruction doubles the value of the RDACx register contents each time the command is executed When the wiper position is greater than midscale the last 6 dB increment command instruction causes the wiper to go to the full scale 255 code position Any addi tional 6 dB instruction does not change the wiper position from full scale RDACx register code 255 Figure 37 illustrates the operation of the 6 dB shifting function o
14. lt Vrerm lt OPERATION FROM DUAL SUPPLIES The AD5232 can be operated from dual supplies enabling control of ground referenced ac signals see Figure 42 for a typical circuit connection 02618 042 Figure 42 Operation from Dual Supplies The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs When configured as potentiometer divider the 3 dB bandwidth of the AD5232BRUI0 10 resistor measures 500 kHz at half scale Figure 14 provides the large signal BODE plot character istics of the three resistor versions 10 50 and 100 see Figure 43 for a parasitic simulation model of the RDAC circuit 02618 043 Figure 43 RDAC Circuit Simulation Model for RDACx 10 The following code provides a macro model net list for the 10 RDAC PARAM DW 255 RDAC 10E3 SUBCKT DPOT A W B 0 45E 12 RAW W 1 DW 256 RDAC 50 CW W 0 60E 12 RBW DW 256 RDAC 50 CB B 0 45E 12 ENDS DPOT APPLICATION PROGRAMMING EXAMPLES The command sequence examples shown in Table 14 to Table 18 have been developed to illustrate a typical sequence of events for the various features of the AD5232 nonvolatile digital poten tiometer Table 14 illustrates setting two digital potentiometers to independent data values Table 14 SDI SDO Action OxB140 Loads 0x40 data into the RDAC2
15. needed but only if these functions are in use A resistor value in the range of 1 to 10 optimizes the power and switching speed trade off Rev B Page 14 of 24 SERIAL DATA INTERFACE The AD5232 contains a 4 wire SPI compatible digital interface SDI SDO 25 CLK and uses 16 bit serial data word that is loaded MSB first The format of the SPI compatible word is shown in Table 7 The chip select CS pin must be held low until the complete data word is loaded into the SDI pin When CS returns high the serial data word is decoded according to the instructions in Table 8 The command bits Cx control the operation of the digital potentiometer The address bits Ax determine which register is activated The data bits Dx are the values that are loaded into the decoded register Table 9 provides an address map of the EEMEM locations The last command instruction executed prior to a period of no programming activity should be the no operation NOP command instruction Com mand Instruction 0 This instruction places the internal logic circuitry in a minimum power dissipation state COMMAND PROCESSOR COUNTER AND ADDRESS Ku DECODE RpULL UP gt SERIAL REGISTER 02618 033 Figure 33 Equivalent Digital Input Output Logic The AD5232 has an internal counter that counts a multiple of 16 bits per frame for proper operation For example the AD5232 works with a 16 bit or 32 bit word but it cannot work pr
16. register Wiper W2 moves to 1 4 full scale position 0 080 OxB140 Loads 0x80 data into the register Wiper W1 moves to 1 2 full scale position Table 15 illustrates the active trimming of one potentiometer followed by a save to nonvolatile memory calibrate Table 15 SDI SDO Action 0 040 Loads 0x40 data into the RDACI register Wiper W1 moves to 1 4 full scale position 0 040 Increments the register by 1 to 0x41 Wiper W1 moves one resistor segment away from Terminal B OxEOXX Increments the register by 1 to 0x42 Wiper W1 moves one more resistor segment away from Terminal B Continue until desired the wiper position is reached Ox20XX OxEOXX Saves the register data into the corresponding nonvolatile EEMEM1 memory ADDR 0x0 Rev B Page 20 of 24 Table 16 illustrates using the left shift by one to change circuit gain in 6 steps Table 16 SDI SDO Action OxC1XX Moves Wiper W2 to double the present data value contained in the RDAC2 register in the direction of Terminal A OxC1XX OxXXXX Moves Wiper W2 to double the present data value contained in the RDAC2 register in the direction of Terminal A Table 17 illustrates storing additional data in nonvolatile memory Table 17 SDI SDO Action 0x3280 OxXXXX Stores 0x80 data in s
17. 5 C 16 Lead TSSOP RU 16 1 000 5232BC AD5232BRUZ100 2 100 40 C to 85 C 16 Lead TSSOP RU 16 96 5232BC AD5232BRUZ100 RL7 2 100 40 C to 85 C 16 Lead TSSOP RU 16 1 000 5232BC EVAL AD5232 10EBZ 10 Evaluation Board 1 17 RoHS Compliant Part Line 1 contains the Analog Devices logo followed by the date code YYWW Line 2 contains the model number followed by the end to end resistance value Note that 100 OR Line 1 contains the model number Line 2 contains the Analog Devices logo followed by the end to end resistance value Line 3 contains the date code YYWW Rev B Page 22 of 24 NOTES Rev B Page 23 of 24 NOTES 2001 2011 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D02618 0 9 11 B DEVICES www analo g com Rev B Page 24 of 24
18. ANALOG DEVICES Nonvolatile Memory Dual 256 Position Digital Potentiometer FEATURES Dual channel 256 position resolution 10 50 and 100 nominal terminal resistance Nonvolatile memory maintenance of wiper settings Predefined linear increment decrement instructions Predefined 6 dB step log taper increment decrement instructions SPI compatible serial interface Wiper settings and EEMEM readback 3V to 5V single supply operation 2 5 V dual supply operation 14 bytes of general purpose user EEMEM Permanent memory write protection 100 year typical data retention T4 55 C APPLICATIONS Mechanical potentiometer replacement Instrumentation gain and offset adjustment Programmable voltage to current conversion Programmable filters delays and time constants Programmable power supply Low resolution DAC replacement Sensor calibration GENERAL DESCRIPTION The AD5232 device provides a nonvolatile dual channel digitally controlled variable resistor VR with 256 position resolution This device performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution solid state reliability and superior low temperature coefficient performance The versatile programming of the AD5232 per ormed via a microcontroller allows multiple modes of operation and adjustment In the direct program mode a predetermined setting ofthe RDAC registers RDACI and RDAC2 can be loaded dir
19. C ADDR to EEMEM 0 3 0 0 1 1 ADDR 07 06 05 D4 D2 DO Write contents of Serial Register Data Byte 0 to EEMEM ADDR 4 0 1 0 0 0 0 0 AO X X Decrement 6 dB right shift con tents of RDAC 0 Stops at all 05 5 0 1 0 1 X Decrement all 6 dB right shift contents of all RDAC registers Stops at all Os 6 0 1 1 0 0 0 0 AO X X Decrement contents of RDAC 0 by 1 Stops at all Os 7 0 1 1 1 X Decrement contents of all RDAC registers by 1 Stops at all Os 8 1 0 0 0 0 0 0 0 Reset Load all RDACs with their corresponding previously saved EEMEM values 9 1 0 0 1 ADDR Write contents of EEMEM ADDR to Serial Register Data Byte 0 10 1 0 1 0 0 0 0 AO X X X X X Write contents of RDAC 0 to Serial Register Data Byte 0 11 1 0 1 1 0 0 0 AO D7 D6 D5 D4 D3 D2 00 Write contents of Serial Register Data Byte 0 to RDAC 0 12 1 1 0 0 0 0 0 AO X Increment 6 dB left shift contents of RDAC 0 Stops at all 1s 13 1 1 0 1 Increment all 6 dB left shift contents of all RDAC registers Stops at all 18 14 1 1 1 0 0 0 0 AO X Increment contents of RDAC 0 by 1 Stops at all 1s 15 1 1 1 1 X Increment contents of all RDAC registers by 1 Stops at all 1s
20. CAL PERFORMANCE CHARACTERISTICS INL ERROR LSB DNL ERROR LSB R DNL LSB 5 2 00 1 75 1 50 1 25 1 00 0 75 0 50 0 25 0 0 25 0 50 0 75 1 00 1 25 1 50 1 75 2 00 INL TA 40 I INL TA 25 C NL TA 85 C 0 64 128 192 256 DIGITAL CODE Figure 5 INL vs Code Ta 40 C 25 C 85 C Overlay 2 00 1 75 1 50 1 25 1 00 0 75 0 50 0 25 0 0 25 0 50 0 75 1 00 1 25 1 50 1 75 2 00 DNL 25 C 128 DIGITAL CODE 192 256 Figure 6 DNL vs Code Ta 40 C 25 C 85 C Overlay 0 20 0 15 128 CODE Decimal 160 Figure 7 R DNL vs Code Ras 10 50 100 Overlay 02618 005 02618 006 02618 007 2000 4 4 RHEOSTAT ppm C POTENTIOMETER MODE TEMPCO ppm C Rev B Page 9 of 24 500 Vpp 5V 40 C 485 C VA NO CONNECT Rwg MEASURED 000 0 32 64 96 128 CODE Decimal 160 192 224 Figure 8 ARws AT vs Code Ras 10 Von 5 V Vpp 5V 40 C 485 C VA 2 Vp 0V 0 32 64 96 128 160 CODE Decimal 192 224 256 Figure 9 AVws AT vs Code Ras 10 Von 5 Vpp 2 5 Vss 2 5V
21. RELIABILITY Endurance 100 kCycles Data Retention 100 Years Typical parameters represent average readings at 25 and 5 V Resistor position nonlinearity R INL error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions R DNL measures the relative step change from ideal between successive tap positions Parts are guaranteed monotonic lw 50 HA Voo 2 7 V and lw 400 pA Voo 5 V for the Ras 10 version 50 pA for the Ras 50 version and lw 25 pA for the Ras 100 version see Figure 22 and DNL are measured at Vw with the RDACx configured as a potentiometer divider similar to a voltage output digital to analog converter Va Von and Vs Vss DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions see Figure 23 The A B and W resistor terminals have no limitations on polarity with respect to each other Dual supply operation enables ground referenced bipolar signal adjustment 5 Guaranteed by design not subject to production test Common mode leakage current is a measure of the dc leakage from any A B or W terminal to common mode bias level 2 7 Transfer mode current is not continuous Current is consumed while the EEMEMx locations are read and transferred to the RDACx register see Figure 13 8 is calculated from X Is
22. Right Shift 5 command execution contains an error only for the odd codes The even codes are ideal with the exception of zero right shift or greater than half scale left shift Figure 38 shows plots of Log Error that is 20 x log10 error code For example Code 3 Log Error 20 x 10210 0 5 3 15 56 dB which is the worst case The plot of Log Error 18 more signifi cant at the lower codes GAIN dB LOG ERROR CODE FOR 8 0 20 40 60 380 100 120 140 160 180 200 220 240 260 CODE FROM 1 TO 255 BY 2 Figure 38 Plot of Log Error Conformance for Odd Codes Only Even Codes Are Ideal 02618 038 Rev B Page 17 of 24 USING ADDITIONAL INTERNAL NONVOLATILE EEMEM The AD5232 contains additional internal user storage registers EEMEM for saving constants and other 8 bit data Table 9 provides an address map of the internal nonvolatile storage registers which are shown in the functional block diagram as EEMEM1 2 and bytes of USER EEMEM Note the following about EEMEM function RDAC data stored in EEMEM locations are transferred to their corresponding RDACx register at power on or when Command Instruction 1 and Command Instruction 8 are executed USERx refers to internal nonvolatile EEMEM registers that are available to store and retrieve constants by using Command Instruction 3 and Command Instruction 9 respectively The EEMEM locations are one byte each e
23. ailed Potentiometer Operation sss 18 Programming the Variable Resistor sss 19 Programming the Potentiometer Divider 20 Operation from Dual Supplies 20 Application Programming Examples sss 20 Equipment Customer Start up Sequence for a PCB Calibrated Unit with Protected Settings 21 Flash EEMEM 21 Evaluation Board 21 O tline Dimensions ierit bent 22 Ordering 4146 22 Changes to CS Rise to RDY Fall Time Parameter Table 2 5 Changes to Figure 2 and Figure 3 sse 6 Changes to Figure 24 tinens Rete 12 Added Figure 32 5 inb AE DE teta 13 Changes to Serial Data Interface Section 15 Changes to Programming the Variable Resistor Section 19 Changes to Ordering 22 10 01 Revision 0 Initial Version Rev B Page 2 of 24 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 10 50 100 VERSIONS 3 V 10 or 5 V 10 and Vss 0 V Va Vs 0 V 40 C lt lt 85 C unless otherwise noted Table 1 Parameter Symbol Conditions Min CHARACTERISTICS Specifications apply to all VRs RHEOSTAT MODE Resistor Differential Nonline
24. arity R DNL Rwe Va NC 1 1 2 1 LSB Resistor Nonlinearity R INL Rwe Va NC 0 4 0 4 5 Nominal Resistor Tolerance ARas 40 20 90 Resistance Temperature Coefficient 600 Wiper Resistance Rw 100 pA 5 5 V code Ox1E 50 100 Q 100 pA Voo 3 V code 200 Q POTENTIOMETER DIVIDER MODES Resolution N 8 Bits Differential Nonlinearity DNL 1 1 2 1 LSB Integral Nonlinearity INL 0 4 0 4 FS Voltage Divider Temperature AVw AT Code half scale 15 ppm C Coefficient Full Scale Error Vwese Code full scale 3 0 5 Zero Scale Error Vwzse Code zero scale 0 3 FS RESISTOR TERMINALS Terminal Voltage Range Va Vw Vss V Capacitance Ax Bx Ca f 1 MHz measured to GND code half scale 45 pF Capacitance Wx Cw f 1 MHz measured to GND code half scale 60 pF Common Mode Leakage Current gt 2 0 01 1 DIGITAL INPUTS AND OUTPUTS Input Logic High Vin With respect to GND Voo 5 V 2 4 Input Logic Low Vit With respect to GND Voo 5 V 0 8 Input Logic High Vin With respect to GND 2 1 Input Logic Low Vit With respect to GND 0 6 V Input Logic High With respect to GND 2 5 Vss 2 5 2 0 V Input Logic Low Vit With respect to GND Voo 2 5 V 2 5 V 0 5 V Output Logic High SDO and RDY Reurue 2 2 to 5 4 9 V Output Logic Low VoL 1 6 mA 5 V
25. bits of data that is refreshed at power on from the corresponding nonvol clocked into the serial register for daisy chain operation with atile register The increment decrement and shift the following exception after Command Instruction 9 or Com command instructions ignore the contents of Data Byte 0 in the mand Instruction 10 the selected internal register data is present shift register Execution of the operation noted in Table 8 occurs in Data Byte 0 The command instructions following Command when the CS strobe returns to logic high Execution of an NOP Instruction 9 and Command Instruction 10 must be full 16 bit instruction minimizes power dissipation Table 7 16 Bit Serial Data Word MSB LSB B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 BO 2 C1 2 1 0 07 06 05 04 03 02 D1 DO Table 8 Instruction Operation Truth Table Comm Instruction Byte 1 Data Byte 0 No C2 C1 CO 2 A1 AO 07 D6 D5 D4 02 ODO Operation 0 0 0 0 0 No operation NOP Do nothing 1 0 0 0 1 0 0 0 AO X Write contents 0 to the RDAC 0 register This com mand leaves the device in the read program power state To return the part to the idle state perform Command Instruction 0 NOP 2 0 0 1 0 0 0 0 AO X Save wiper setting Write contents of RDA
26. ctivate the SDO output see Table 8 Other commands shift out the previously loaded SDI bit pattern delayed by 16 clock pulses allowing daisy chain operation of multiple packages 4 GND Ground Logic Ground Reference 5 Vss Negative Power Supply Connect to 0 V for single supply applications 6 A1 Terminal A of RDAC1 7 W1 Wiper Terminal W of RDAC1 ADDR RDAC1 0x0 8 B1 Terminal B of RDAC1 9 B2 Terminal B of RDAC2 10 W2 Wiper Terminal W of RDAC2 ADDR RDAC2 0x1 11 A2 Terminal A of RDAC2 12 Voo Positive Power Supply 13 WP Write Protect When active low WP prevents any changes to the present register contents except PR Command Instruction 1 and Command Instruction 8 which refresh the RDACx register from EEMEM Execute NOP instruction Command Instruction 0 before returning WP to logic high 14 PR Hardware Override Preset Refreshes the scratch pad register with current contents of the register Factory default loads Midscale 0x80 until EEMEMx is loaded with a new value by the user PR is activated at the logic high transition 15 cs Serial Register Chip Select Active Low Serial register operation takes place when CS returns to logic high 16 RDY Ready This active high open drain output requires a pull up resistor Identifies completion of Command Instruction 2 Command Instruction 3 Command Instruction 8 Command Instruction 9 Command Instruction 10 and PR Rev B Page 8 of 24 TYPI
27. ectly from the microcontroller Another important mode of operation allows the RDACx register to be refreshed with the setting previously stored in the corresponding EEMEM register EEMEMI and EEMEM2 When changes are made to the RDACx register to establish a new wiper position the value of the setting can be saved into the register by executing an EEMEM save operation After the settings are saved in the register these values are automatically transferred to the RDACx register to set the wiper position at system power on Such operation is enabled by the internal preset strobe The preset strobe can also be accessed externally Rev B Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM Vpp ADDR 1 REGISTER SERIAL 2 REGISTER AD5232 D p mes P lie 14 BYTES USER EEMEM 02618 001 GND Vss Figure 1 All internal register contents can be read via the serial data output SDO This includes
28. ight bits Execution of Command Instruction 1 leaves the device in the read mode power consumption state When the final Command Instruction 1 is executed the user should perform an NOP Command Instruction 0 to return the device to the low power idle state Table 9 EEMEM Address Map 618 039 Vss 8 Figure 39 Maximum Terminal Voltages Set by Vpp and Vss Table 10 RDAC and Digital Register Address Map Register Address ADDR Name of Register 0000 RDAC1 0001 RDAC2 EEMEM Address EEMEM Contents of Each Device ADDR EEMEM ADDR 0000 RDAC1 0001 RDAC2 0010 USER 1 0011 USER 2 0100 USER 3 0101 USER 4 KKK xxx 1111 USER 14 TERMINAL VOLTAGE OPERATING RANGE The positive and negative Vss power supply of the digital potentiometer defines the boundary conditions for proper 3 terminal programmable resistance operations Signals present on Terminal A Terminal B and Wiper Terminal W that exceed or Vss clamped by a forward biased diode see Figure 39 The ground pin of the AD5232 device is used primarily as a digital ground reference that needs to be tied to the common ground of the PCB The digital input logic signals to the AD5232 must be referenced to the ground GND pin of the device and satisfy the minimum input logic high level and the maximum input logic low level that are defined in the Specifications section An internal level shift circuit between the digita
29. ion Version Version Version 8 Bit 78 10 390 5 781 0 PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistances of the RDACx between Terminal A and Terminal are available with values of 10 50 and 100 The final digits of the part number determine the nominal resistance value for example 10 10 100 100 The nominal resistance Ras of the AD5232 VR has 256 contact points accessed by Wiper Terminal W plus the Terminal B contact The 8 bit data word in the RDACXx latch is decoded to select one of the 256 possible settings The general transfer equation which determines the digitally programmed output resistance between Wx and Bx is D Rus D Ry 1 where Dis the decimal equivalent of the data contained in the RDACx register Raz is the nominal resistance between Terminal A and Terminal B Rw is the wiper resistance Table 12 lists the output resistance values that are set for the RDACx latch codes shown for 8 bit 10 potentiometers Table 12 Nominal Resistance Value at Selected Codes for Ras 10 100 EI a PERCENT OF NOMINAL END TO END RESISTANCE Rag e N a 0 64 128 192 258 CODE Decimal 02618 041 Figure 41 Symmetrical RDAC Operation When these terminals are used Terminal B should be tied to the wiper Setting the resistance value for Rwa starts at a maximum value of resistance and decreases as
30. is EEMEM save SCRATCH PAD AND EEMEM PROGRAMMING The scratch pad register RDACx register directly controls the position of the digital potentiometer wiper When the scratch pad register is loaded with all 0s the wiper is connected to Terminal B of the variable resistor When the scratch pad register is loaded with midscale code 1 2 of full scale position the wiper is connected to the middle of the variable resistor When the scratch pad is loaded with full scale code which is all 1s the wiper connects to Terminal A Because the scratch pad register is a standard logic register there is no restriction on the number of changes allowed The registers have a program erase write cycle limitation that is described in the Flash EEMEM Reliability section BASIC OPERATION The basic mode of setting the variable resistor wiper position by programming the scratch pad register is accomplished by loading the serial data input register with Command Instruc tion 11 which includes the desired wiper position data When the desired wiper position is found the user loads the serial data input register with Command Instruction 2 which copies the desired wiper position data into the corresponding non volatile register After 25 ms the wiper position is permanently stored in the corresponding nonvolatile EEMEM location Table 6 provides an application programming example listing the sequence of serial data input SDI words
31. l interface and the wiper switch control ensures that the common mode voltage range of the three terminals Terminal A Terminal B and Wiper Terminal W extends from Vss to Vpp The RDACx registers contain data that determines the position of the variable resistor wiper DETAILED POTENTIOMETER OPERATION The actual structure of the RDACx is designed to emulate the performance of a mechanical potentiometer The contains multiple strings of connected resistor segments with an array of analog switches that act as the wiper connection to several points along the resistor array The number of points is equal to the resolution of the device For example the AD5232 has 256 con nection points allowing it to provide better than 0 596 setability resolution Figure 40 provides an equivalent diagram of the con nections between the three terminals that make up one channel of the RDACx The SWa and SW switches are always on whereas only one of the SW 0 to SW 2 1 switches is on at a time depending on the resistance step decoded from the data bits The resistance contributed by Rw must be accounted for in the output resistance Rg Rag 2N NOTES 1 DIGITAL CIRCUITRY OMITTED FOR CLARITY Figure 40 Equivalent RDAC Structure 02618 040 Page 18 of 24 Table 11 Nominal Individual Segment Resistor Values 0 Segmented Resistor Size for Ras End to End Values Device 10 kQ 50 100 Resolut
32. ment process For example the wiper position can be changed one step at a time by using the software controlled increment decrement command instructions The wiper position can be also be changed 6 dB at a time by using the shift left right command instructions After an increment decrement or shift command instruction is loaded into the shift register subsequent CS strobes repeat this command instruction This is useful for push button control appli cations see the Advanced Control Modes section The SDO pin is available for daisy chaining and for readout of the internal register contents The serial input data register uses a 16 bit instruction address data word EEMEM PROTECTION The write protect WP pin disables any changes of the scratch pad register contents regardless of the software commands except that the EEMEM setting can be refreshed using Instruction Command 8 and PR Therefore the WP pin provides a hardware EEMEM protection feature Execute an NOP command Com mand Instruction 0 before returning WP to logic high DIGITAL INPUT OUTPUT CONFIGURATION All digital inputs are ESD protected high input impedance that can be driven directly from most digital sources The PR and WP pins which are active at logic low must be biased to if they are not being used No internal pull up resistors are present on any digital input pins The SDO and RDY pins are open drain digital outputs when pull up resistors are
33. n the individual RDACx register data bits for the 8 bit AD5232 example Each line going down the table represents a successive shift operation Note that the Left Shift 12 and Left Shift 13 com mand instructions were modified so that if the data in the RDACx register is equal to 0 and is left shifted it is then set to Code 1 In addition the left shift commands were modified so that if the data in the RDAC register is greater than or equal to midscale and is left shifted the data is then set to full scale This makes the left shift function as close to ideally logarithmic as possible The Right Shift 4 and Right Shift 5 command instructions are ideal only if the LSB is 0 that is ideal logarithmic with no error If the LSB is a 1 the right shift function generates a linear half LSB error that translates to a code dependent logarithmic error for odd codes only as shown in Figure 38 The plot shows the errors of the odd codes LEFT SHIFT RIGHT SHIFT 0000 0000 1111 1111 0000 0001 0111 1111 0000 0010 0011 1111 0000 0100 0001 1111 LEFT SHIFT 0000 1000 0000 0111 RIGHT SHIFT 6dB 0001 0000 0000 0011 6dB 0010 0000 0000 0001 0100 0000 0000 0000 1000 0000 0000 0000 1111 1111 0000 0000 1111 1111 0000 0000 02618 037 Figure 37 Detail Left and Right Shift Function Actual conformance to a logarithmic curve between the data contents in the RDACx register and the wiper position for each Right Shift 4 and
34. operly with a 15 bit or 17 bit word To prevent data from mislocking due to noise for example the counter resets if the count is not a multiple of 4 when 8 goes high but the data remains in register if the count is a multiple of 4 In addition the AD5232 has a subtle feature whereby if CS is pulsed without CLK and SDI the part repeats the previous command except during power up As a result care must be taken to ensure that no excessive noise exists in the CLK or CS line that may alter the effective number of bits pattern The equivalent serial data input and output logic is shown in Figure 33 The open drain SDO is disabled whenever CS is logic high The SPI interface can be used in two slave modes CPHA 1 CPOL 1 and CPHA 0 CPOL 0 CPHA and CPOL refer to the control bits that dictate SPI timing in the following micro processors and MicroConverter devices the ADuC812 and ADuC824 the M68HC11 and the MC68HC16R1 916R1 ESD protection of the digital inputs is shown in Figure 34 and Figure 35 02618 034 Figure 34 Equivalent ESD Digital Input Protection INPUTS 3000 05232 02618 035 GND Figure 35 Equivalent WP Input Protection DAISY CHAINING OPERATION The SDO pin serves two purposes it can be used to read back the contents of the wiper setting and the EEMEM using Command Instruction 9 and Command Instruction 10 see Table 8 or it can be used for daisy chaining multiple de
35. ortion Noise vs Frequency 110 100 90 80 70 60 Rw 0 50 40 30 20 10 02618 016 CODE Decimal Figure 16 Wiper On Resistance vs Code Rev B Page 10 of 24 GAIN dB GAIN dB GAIN dB 0x80 6 0 40 12 0 20 0 10 24 0 08 0 0 04 36 0 02 42 0 01 48 2 7 _ Vss 2 7V 3 Rag 10 54 100mV rms 25 C 60 1k 10k 100k 1M FREQUENCY Hz Figure 17 Gain vs Frequency vs Code Ras 10 0 0 80 6 0 40 12 0 20 0 10 24 0 08 30 0 04 36 0 02 42 0 01 48 2 7 ss 2 7V Rag 50 5458 100 rms AB 25 C 60 1k 10k 100k 1M FREQUENCY Hz Figure 18 Gain vs Frequency vs Code Ras 50 0 45 0 80 0 40 0 20 0 10 24 0 08 0 0 04 36 22 0 02 0x01 48 2 7 _54 Vss 2 7V Rag 100kO 100mV rms o 25 C 1k 10k 100k 1M FREQUENCY Hz Figure 19 vs Frequency vs Code Ras 100 02618 017 026 18 018 02618 019 a 5
36. pare EEMEM location USER1 0x3340 OxXXXX Stores 0x40 data in spare EEMEM location USER2 Table 18 illustrates reading back data from various memory locations Table 18 SDI SDO Action Ox94XX OxXXXX Prepares data read from USER3 location USER3 is already loaded with 0x80 0 00 OxXX80 Instruction 0 NOP sends 16 bit word out of SDO where the last eight bits contain the contents of USER3 location The NOP command ensures that the device returns to the idle power dissipation state EQUIPMENT CUSTOMER START UP SEQUENCE FOR A PCB CALIBRATED UNIT WITH PROTECTED SETTINGS l Forthe PCB setting tie WP to GND to prevent changes in the PCB wiper set position 2 Set power Vp and Vss with respect to GND 3 As an optional step strobe PR pin to ensure full power on preset of the wiper register with EEMEM contents in unpredictable supply sequencing environments FLASH EEMEM RELIABILITY The Flash EE memory array on the AD5232 is fully qualified for two key Flash EE memory characteristics namely Flash EE memory cycling endurance and Flash EE memory data retention Endurance quantifies the ability of the Flash EE memory to be cycled through many program read and erase cycles In real terms a single endurance cycle is composed of four independent sequential events These events are defined as follows 1 Initial page erase sequence 2 Read verify sequence 3 Byte program seq
37. rent 20 LOG NC NO CONNECT 026 18 031 Figure 31 Analog Crosstalk Rev B Page 13 of 24 MIN OR OUTPUT 5 1 THE DIODE BRIDGE TEST CIRCUIT IS EQUNALENT THE APPLICATION CIRCUIT WITH OF 2 2kQ Figure 32 Load Circuit for Measuring and 02618 032 THEORY OF OPERATION The AD5232 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of Vss lt lt The basic voltage range is limited to a Vpp Vss lt 5 5 V The digital potentiometer wiper position is determined by the RDACx register contents The RDACx register acts as a scratch pad register allowing as many value changes as necessary to place the poten tiometer wiper in the correct position The scratch pad register can be programmed with any position value using the standard SPI serial interface mode by loading the complete representative data word When a desirable position is found this value can be saved into a corresponding register Thereafter the wiper position is always set at that position for any future on off on power supply sequence The EEMEM save process takes approx imately 25 ms During this time the shift register is locked preventing any changes from taking place The RDY pin indicates the completion of th
38. s Vss dynamic characteristics use Voo 2 5 V and Vss 2 5 V unless otherwise noted 10 Endurance is qualified to 100 000 cycles per Std 22 Method A117 and measured at 40 C 25 C and 85 C Typical endurance at 25 C is 700 000 cycles The retention lifetime equivalent at junction temperature 55 C as Std 22 Method A117 Retention lifetime based on an activation energy of 0 6 eV derates with junction temperature as shown in Figure 44 in the Flash EEMEM Reliability section The AD5232 contains 9 646 transistors Die size 69 mil x 115 mil 7 993 sq mil 4 0124 INTERFACE TIMING CHARACTERISTICS All input control voltages are specified with tr tr 2 5 ns 10 to 90 of 3 V and are timed from a voltage level of 1 5 V Switching characteristics are measured using both Vpp 3 V and Vpp 5 V Table 2 Parameter 2 Symbol Conditions Min Typ Clock Cycle Time tcyc 20 ns CS Setup Time t 10 ns CLK Shutdown Time to CS Rise 1 Input Clock Pulse Width ta ts Clock level high or low 10 ns Data Setup Time te From positive CLK transition 5 ns Data Hold Time t From positive CLK transition 5 ns CS to SDO SPI Line Acquire ts 40 ns CS to SDO SPI Line Release to 50 ns CLK to SDO Propagation Delay tio Re 2 2 lt 20 pF 50 ns CLK to SDO Data Hold Time tu 2 2 lt 20 pF 0 ns CS High
39. the data loaded in the latch is increased in value The general transfer equation for this operation is 256 Rya D x Rag 2 where D is the decimal equivalent of the data contained in the RDAC register Rasis the nominal resistance between Terminal and Terminal Rwis the wiper resistance Table 13 lists the output resistance values that are set for the RDACX latch codes shown for 8 bit 10 potentiometers Table 13 Nominal Resistance Value at Selected Codes for Ras 10 D Rws D Output State 255 10011 Full scale 128 5050 Midscale 1 89 1 LSB 0 50 Zero scale wiper contact resistance Note that in the zero scale condition a finite wiper resistance of 50 18 D Dec 0 Output State 255 89 Full scale 128 5050 Midscale 1 10011 1 LSB 0 10050 Zero scale present Care should be taken to limit the current flow between Wx and Bx in this state to a maximum continuous value of 2 mA to avoid degradation or possible destruction of the internal switch metallization Intermittent current operation to 20 mA is allowed Like the mechanical potentiometer that the RDACx replaces the AD5232 parts are totally symmetrical The resistance between the Wiper Terminal W and Terminal A also produces a digitally controlled resistance Rwa Figure 41 shows the symmetrical programmability of the various terminal connections The multichannel AD5232 has a 0
40. uence 4 Second read verify sequence During reliability qualification Flash EE memory is cycled from 0x00 to OxFF until a first fail is recorded signifying the endurance limit of the on chip Flash EE memory As indicated in the Specifications section the AD5232 Flash EE memory endurance qualification has been carried out in accor dance with JEDEC Std 22 Method A117 over the industrial temperature range of 40 C to 85 C The results allow the specification of a minimum endurance figure over supply and temperature of 100 000 cycles with an endurance figure of 700 000 cycles being typical of operation at 25 C Retention quantifies the ability of the Flash EE memory to retain its programmed data over time Again the AD5232 has been qualified in accordance with the formal JEDEC Retention Lifetime Specifi cation A117 at a specific junction temperature of T 55 C As part of this qualification procedure the Flash EE memory is cycled to its specified endurance limit as described previously before data retention is characterized This means that the Flash EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash EE memory is repro grammed It should also be noted that retention lifetime based on an activation energy of 0 6 eV derates with as shown in Figure 44 ADI TYPICAL PERFORMANCE RETENTION Years
41. vices The remaining com mand instructions are valid for daisy chaining multiple devices in simultaneous operations Daisy chaining minimizes the number of port pins required from the controlling IC see Figure 36 The SDO pin contains an open drain N channel FET that requires a pull up resistor if this function is used As shown in Figure 36 users must tie the SDO pin of one package to the SDI pin of the next package Users may need to increase the clock period because the pull up resistor and the capacitive loading at the SDO to SDI interface may require additional time delay between subsequent packages If two AD5232s are daisy chained 32 bits of data are required The first 16 bits go to U2 and the second 16 bits with the same format go to U1 The 16 bits are formatted to contain the 4 bit instruction followed by the 4 bit address followed by the eight bits of data The CS pin should be kept low until all 32 bits are locked into their respective serial registers The cs pin is then pulled high to complete the operation MicroConverter AD5232 01 02618 036 Figure 36 Daisy Chain Configuration Using the 520 Rev B Page 15 of 24 Command bits are identified as Cx address bits are Ax and data words to completely clock out the contents of the serial data bits are Dx The command instruction codes are defined register The RDACx register is a volatile scratch pad register in Table 8 The SDO output shifts out the last eight
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ANALOG DEVICES AD5232 English products handbook Rev B