ANALOG DEVICES AD5161 English products handbook
Contents
1. 510 110 1 110 AD RS SD D7 D6 D5 04 D3 02 D1 Slave Address Byte Instruction Byte Data Byte Table 8 Read Mode 5 0 1 0 1 1 0 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Data Byte S Start Condition R Read P Stop Condition RS Reset wiper to Midscale 80 Acknowledge SD Shutdown connects wiper to B terminal and open circuits X Dort Care A terminal It does not change contents of wiper register W Write D7 06 D5 D4 D3 D2 D1 Data Bits SCL ee ae SALER EE ads START BY MASTER ACK BY ACK BY ACK BY AD5161 AD5161 AD5161 FRAME 1 FRAME 2 FRAME 3 STOP BY SLAVE ADDRESS INSTRUCTION BYTE DATA BYTE MASTER Figure 40 Writing to the RDAC Register SCL s 19 1 1 07 ACK BY NO ACK AD5161 BY MASTER START BY FRAME 1 FRAME 2 STOPBY MASTER SLAVE ADDRESS BYTE RDAC REGISTER MASTER Figure 41 Reading Data from a Previously Selected RDAC Register in Write Mode Rev A Page 14 of 20 THEORY OPERATION The AD5161 is a 256 position digitally controlled variable resistor VR device An internal power on preset places the wiper at midscale during power on which simplifies the fault condition recovery at power up PROGRAMMING THE VARIABLE RESISTOR Rh2. 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 CODE Decimal CODE Decimal Figure 6 INL vs Code Vpp 5 V Figure 9 DNL vs Code vs Supply Voltages Rev A Page 8 of 20 RHEOSTAT MODE INL 158 RHEOSTAT MODE DNL LSB FSE FULL SCALE ERROR LSB 0 32 64 96 128 160 192 224 256 CODE Decimal Figure 10 R INL vs Code Voo 5 CODE Decimal Figure 11 R DNL vs Code Voo 5 V 2 5 P a e a 40 0 40 80 120 TEMPERATURE C Figure 12 Full Scale Error vs Temperature Rev A Page 9 of 20 SUPPLY CURRENT ZSE ZERO SCALE ERROR uA la SHUTDOWN CURRENT nA TEMPERATURE C Figure 13 Zero Scale Error vs Temperature TEMPERATURE C Figure 14 Supply Current vs Temperature 40 0 40 80 120 TEMPERATURE C Figure 15 Shutdown Current vs Temperature RHEOSTAT MODE TEMPCO ppm C POTENTIOMETER MODE 60 96 CODE Decimal 128 160 256 Figure 16 Rheostat Mode Tempco ARws AT vs Code 160 140 120 100 80 60 40 20 0 20 0 32 64 96 128 160 192 224 256 CODE Decimal Figure 17 Potentiometer Mode Tempco AVws AT
3. 1 Functional Block Diagram senten 1 Pin Configuration 1 Revision History e ERRARE ERR 2 Electrical Characteristics 5 3 Electrical Characteristics 10 50 100 Versions 4 Timing Characteristics 5 10 50 100 Versions 5 Absolute Maximum Ratings 6 ESD 6 Pin Configuration and Function 7 Typical Performance Characteristics CITCUILS REVISION HISTORY 4 09 Rev 0 to Rev Changes to Ordering Guide 19 5 03 Revision 0 Initial Version SPI Interfacen u 13 EC a a Su tes 14 Theory of Operation u s a pP eite ted 15 Programming the Variable Resistor sess 15 Programming the Potentiometer 16 Pin Selectable Digital Interface ses 16 Level Shifting for Bidirectional Interface 18 ESD Protection 18 Terminal Voltage Operating Range 18 Power Up Sequence RE Ie ERES 18 Layout and Power Supply Bypassing 18 Outlin Dimensions detener tpe diete tiene sane 19 Ordering Guide ede bett Re ee s 19 Rev A Page 2 of 20
4. Figure 28 Test Circuit for Potentiometer Divider Nonlinearity Error INL DNL NO CONNECT Figure 29 Test Circuit for Resistor Position Nonlinearity Error Rheostat Operation R INL R DNL lw Vpp RNouiNAL Vuszl lw Vpp 10 PSRR dB 20 LOG AV Woo 5 PSS OFFSET our GND L OFFSET i BIAS Figure 32 Test Circuit for Inverting Gain Rev A Page 12 of 20 5V O Vour OFFSET GND A DUT OFFSET l BIAS Figure 33 Test Circuit for Noninverting Gain OFFSET GND Figure 34 Test Circuit for Gain vs Frequency 0 1V Rsw 5 DUT sw CODE 0x00 gt CONNECT Figure 36 Test Circuit for Common Mode Leakage current SPI INTERFACE SDI ps X eo Table 6 AD5161 Serial Data Word Format 1 0 B7 Be 85 B2 BO 07 06 05 D4 D3 D2 D1 D0 RDAC REGISTER LOAD N MSB LSB 27 20 VOUT N Figure 37 SPI Interface Timing Diagram VA 5 V Vs 0 V Vw Vour SDI DATA IN VOUT 1LSB Figure 38 SPI Interface Detailed Timing Diagram Va 5 V Vs 0 V Vw Vour Rev A Page 13 of 20 INTERFACE Table 7 Write Mode
5. 1096 or 3V 10 Va Vp 0 V 40 C lt lt 125 unless otherwise noted Table 3 Parameter Symbol Conditions Min Typ Max Unit SPI INTERFACE TIMING CHARACTERISTICS Specifications Apply to All Parts Clock Frequency fax 25 MHz Input Clock Pulsewidth tcu tc Clock level high or low 20 ns Data Setup Time tps 5 ns Data Hold Time 5 ns CS Setup Time tcss 15 ns CS High Pulsewidth tcsw 40 ns CLK Fall to CS Fall Hold Time testo 0 ns CLK Fall to CS Rise Hold Time 0 ns CS Rise to Clock Rise Setup tcsi 10 ns INTERFACE TIMING CHARACTERISTICS Specifications Apply to Parts SCL Clock Frequency 400 kHz Bus Free Time between STOP and START ti 1 3 us tupsra Hold Time Repeated START t After this period the first clock pulse is 0 6 us generated tiow Low Period of SCL Clock t3 1 3 us tuich High Period of SCL Clock t4 0 6 50 us tsu sta Setup Time for Repeated START Condition ts 0 6 us Data Hold Time te 0 9 us tsu par Data Setup Time t7 100 ns tr Fall Time of Both SDA and SCL Signals ts 300 ns tr Rise Time of Both SDA and SCL Signals to 300 ns tsusro Setup Time for STOP Condition tio 0 6 us NOTES 1 Typical specifications represent average readings at 25 C and 5 V Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance
6. IDIV 0 500dB 1 026 MHz 511 MHz 50kO 101 MHz 100 54 MHz 6 0 50kQ 5 0 10kQ 100 10 0 10 5 10k START 1 000 000Hz 1M 10M STOP 1 000 000 000Hz 100k Figure 22 3 dB Bandwidth Code 0x80 60 771 CODE 0x80 Va Vpp Vp OV 40 a x PSRR Q 3V DC 10 p p AC amp 20 PSRR Vpp 5V DC 10 p p AC 0 100 1k 10k 100k 1M FREQUENCY Hz Figure 23 PSRR vs Frequency Ipp 10M 100k FREQUENCY Hz Figure 24 loo vs Frequency Rev A Page 11 of 20 gt w ee _ CLK Ch 1 200mV By Ch2 5 00 VvBw M 100ns A CH2 73 00 V Figure 25 Digital Feedthrough gt w ts CH1 152mV 5 00 V By M 200ns Ch 1 100mV 2 Figure 26 Midscale Glitch Code 0 80 0 7 Ch 1 Ch2 200 5 CH1 3 00 5 00 BW 5 00V Bw Figure 27 Large Signal Settling Time Code OXFF 0x00 TEST CIRCUITS Figure 28 to Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables V Vpp 1158 V 2N
7. 1 LSB Voltage Divider Temperature Coefficient AVw AT Code 0x80 15 Full Scale Error Vwese Code OxFF 3 1 0 LSB Zero Scale Error Vwzse Code 0x00 0 1 3 LSB RESISTOR TERMINALS Voltage Range GND V A CAB f 1 MHz measured to 45 pF GND Code 0x80 Capacitance W Cw f 1 MHz measured to 60 pF GND Code 0x80 Shutdown Supply Current 50 5 5 V 0 01 1 uA Common Mode Leakage Vs 2 1 DIGITAL INPUTS AND OUTPUTS Input Logic High 2 4 V Input Logic Low Vi 0 8 V Input Logic High 2 1 V Input Logic Low Vi 0 6 V Input Current li Vin OVor5V 1 uA Input Capacitance 5 pF POWER SUPPLIES Power Supply Range RANGE 2 7 5 5 V Supply Current 5 3 8 uA Power Dissipation Poiss 5 0 2 mW 5 V Power Supply Sensitivity PSS 5 V 1096 0 02 0 05 Code Midscale DYNAMIC CHARACTERISTICS Bandwidth 3dB BW 10 50 100 600 100 40 kHz Code 0x80 Total Harmonic Distortion THDw 1 V rms Vs 0 05 1 kHz Ras 10 Vw Settling Time 10 50 100 ts 5 OV 2 us 1 LSB error band Resistor Noise Voltage Density 5 RS 0 9 nV 4Hz Rev A Page 4 of 20 TIMING CHARACTERISTICS 5 10 50 100 VERSIONS 5V
8. GND V other conditions above those indicated in the operational A VB VW DD E c 2 420 mA section of this specification is not implied Exposure to absolute MAX US maximum rating conditions for extended periods may affect Digital Inputs and Output Voltage to GND OV to 7 ie 5 5 2 2 device reliability Operating Temperature Range 40 C to 125 C Maximum Junction Temperature Tmax 150 C Storage Temperature Range 65 C to 150 C ESD CAUTION Lead Temperature 10 sec 300 ESD electrostatic discharge sensitive device Thermal Resistance Charged devices and circuit boards can discharge 10 Lead 5 200 C W without detection Although this product features NOTES patented or proprietary protection circuitry damage 1 Maximum terminal current is bounded by the maximum current handling of occur devices subjected to high energy ESD the switches maximum power dissipation of the package and maximum Therefore proper ESD precautions should be taken to applied voltage across any two of the A B and W terminals at a given avoid performance degradation or loss of functionality resistance 2Package power dissipation Tmax Rev A Page 6 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SDO NC 4 Not to Scale GND SDVSDA 5 6 CLK SCL Figure 3 Pin Configuration Table 5 Pin Function Description Pin No Mnemonic Descr
9. vs Code REF LEVEL 0 000dB DIV 6 000dB MARKER 1 000 000 000Hz MAG A R 8 918dB 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 1k START 1 000 000Hz 10k 100k 1M STOP 1 000 000 000Hz Figure 18 Gain vs Frequency vs Code Ras 5 Rev A Page 10 of 20 REF LEVEL 0 000dB DIV 6 000dB MARKER 510 634 725Hz MAG A R 9 049dB 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 1k START 1 000 000Hz 10k 100k 1M STOP 1 000 000 000Hz Figure 19 Gain vs Frequency vs Code Ras 10 REF LEVEL 0 000dB DIV 6 000dB MARKER 100 885 289Hz MAG 9 014dB 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 1k START 1 000 000Hz 10k 100k 1M STOP 1 000 000 000Hz Figure 20 Gain vs Frequency vs Code Ras 50 REF LEVEL 0 000dB DIV 6 000dB MARKER 54 089 173Hz 9 052dB 0 80 40 20 0x10 0x08 0x04 0x02 0x01 1k START 1 000 000Hz 10k 100k 1M STOP 1 000 000 000Hz Figure 21 Gain vs Frequency vs Code Ras 100 kQ REF LEVEL 5 000dB 5 5
10. 0 C to 125 C 10 Lead MSOP RM 10 D0D AD5161BRM50 50k 40 C to 125 C 10 Lead MSOP RM 10 DOE AD5161BRM50 RL7 50k 40 C to 125 C 10 Lead MSOP RM 10 DOE AD5161BRMZ50 50k 40 C to 125 C 10 Lead MSOP RM 10 DOE AD5161BRMZ50 RL7 50k 40 C to 125 C 10 Lead MSOP RM 10 DOE AD5161BRM100 100k 40 C to 125 C 10 Lead MSOP RM 10 DOF AD5161BRM100 RL7 100k 40 to 125 C 10 Lead MSOP RM 10 DOF AD5161BRMZ100 100k 40 C to 125 C 10 Lead MSOP RM 10 DOF AD5161BRMZ100 RL7 100k 40 C to 125 C 10 Lead MSOP RM 10 D0F AD5161EVAL2 See Note 2 Evaluation Board 1 Z RoHS Compliant Part denotes RoHS compliant part may be top or bottom marked The evaluation board is shipped with the 10 kO Ras resistor option however the board is compatible with all available resistor value options The AD5161 contains 2532 transistors Die size 30 7 mil x 76 8 mil 2358 sq mil Rev A Page 19 of 20 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components in an system provided that the system conforms to the Standard Specification as defined by Philips 2003 2009 Analog Devices Inc rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners Or iver DEVICES Rev A Page 20 of 20 www analog com
11. ANALOQ DEVICES 256 Position SPI l C Selectable Digital Potentiometer FUNCTIONAL BLOCK DIAGRAM Vpp SDO NC FEATURES 256 position End to end resistance 5 10 50 100 Compact 5 10 3 mm x 4 9 mm package Pin selectable SPI I C compatible interface Extra package address decode pin AD0 Full read write of wiper register Power on preset to midscale Single supply 2 7 V to 5 5 V Low temperature coefficient 45 ppm C Low power lbp 8 pA Wide operating temperature 40 C to 125 C SDO output allows multiple device daisy chaining Evaluation board available APPLICATIONS Mechanical potentiometer replacement in new designs Transducer adjustment of pressure temperature position chemical and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment GENERAL DESCRIPTION The AD5161 provides a compact 3 mm x 4 9 mm packaged solution for 256 position adjustment applications These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors with enhanced resolution solid state reliability and superior low temperature coefficient performance The wiper settings are controllable through a pin selectable SPI or compatible digital interface which can also be used to read back the wiper register content When the SPI mode is used the device can be daisy chained SDO to SDI allowing several pa
12. ELECTRICAL CHARACTERISTICS 5 VERSION Vpp 5 V 1096 3 V 10 Va Vpp Vs 0 V 40 lt lt 125 C unless otherwise noted Table 1 Parameter Symbol Conditions Min Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity2 R DNL Rwe Va no connect 1 5 0 1 1 5 LSB Resistor Integral Nonlinearity R INL Rws Va no connect 4 0 75 4 LSB Nominal Resistor Tolerance ARAB Ta 25 30 30 Resistance Temperature Coefficient ARas AT Vas Wiper no connect 45 ppm C Wiper Resistance Rw 50 120 Q DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution N 8 Bits Differential Nonlinearity DNL 1 5 0 1 1 5 LSB Integral Nonlinearity INL 1 5 0 6 41 5 LSB Voltage Divider Temperature Coefficient AVw AT Code 0x80 15 ppm C Full Scale Error Vwese Code OxFF 6 2 5 0 LSB Zero Scale Error VwzsE Code 0x00 0 2 6 158 RESISTOR 5 Voltage Range Vasw GND V A Cap f 1 MHz measured to GND 45 pF Code 0x80 Capacitance W Cw f 1 MHz measured to GND 60 pF Code 0x80 Shutdown Supply Current Ipp sp Voo 5 5 V 0 01 1 pA Common Mode Leakage Vs 2 1 DIGITAL INPUTS AND OUTPUTS Input Logic High 2 4 V Input Logic Low Vi 0 8 V Input Logic High 2 1 V Input Logic Low Vi 3 0 6 V Input Current li Vin O
13. Vor5V 1 uA Input Capacitance 5 pF POWER SUPPLIES Power Supply Range 2 7 5 5 V Supply Current 5 0 3 8 Power Dissipation Ppiss 5VorVi OV Voo 5 V 0 2 mW Power Supply Sensitivity PSS 5 V 10 0 02 0 05 Code Midscale DYNAMIC CHARACTERISTICS Bandwidth 3dB BW_5K 5 kO Code 0x80 1 2 MHz Total Harmonic Distortion THDw 1V rms Vs OV f 1 kHz 0 05 Vw Settling Time ts Va 5V Vs 0V 1 LSB error band 1 us Resistor Noise Voltage Density Rwe 2 5 RS 0 6 nV 4Hz Rev A Page 3 of 20 ELECTRICAL CHARACTERISTICS 10 50 100 VERSIONS Vpp 5 V 1096 3 V 10 Von Vs 0 40 C lt lt 125 C unless otherwise noted Table 2 Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity R DNL Rwe VA no connect 1 0 1 1 LSB Resistor Integral Nonlinearity2 R INL no connect 2 0 25 2 LSB Nominal Resistor Tolerance ARAB Ta 25 30 30 Resistance Temperature Coefficient Vas 45 ppm C Wiper no connect Wiper Resistance Rw 5 V 50 120 Q DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution N 8 Bits Differential Nonlinearity DNL 1 0 1 1 LSB Integral Nonlinearity INL 1 0 3
14. and the terminal open circuited the following output resistance will set for the indicated RDAC latch codes Table 10 Codes and Corresponding Rwa Resistance D Dec Rwa Q Output State 255 99 Full Scale 128 5 060 Midscale 1 9 961 1158 0 10 060 Zero Scale Typical device to device matching is process lot dependent and may vary by up to 30 Since the resistance element is processed in thin film technology the change in Ras with temperature has a very low 45 ppm C temperature coefficient Rev A Page 15 of 20 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper to B and wiper to A proportional to the input voltage at A to B Unlike the polarity of to GND which must positive voltage across A B W A and W B can be at either polarity If ignoring the effect of the wiper resistance for approximation connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper to B starting at 0 V up to 1 LSB less than 5 V Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 256 positions of the potentiometer divider The general equation defining the output voltage at Vw with respect to ground for any valid input voltage applied to terminals A and B is D V 256 D Vs w D 256 4 256 For a more accurate calculation which includes the effect
15. ave low resistance and low inductance Similarly it is also a good practice to bypass the power supplies with quality capacitors for optimum stability Supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0 01 uF to 0 1 uF Low ESR 1 uF to 10 pF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple see Figure 49 Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce 05161 im ed ERE ES ul Figure 49 Power Supply Bypassing Rev A Page 18 of 20 OUTLINE DIMENSIONS 0 00 4 90 BSC r 1 10 MAX SHUT 015 057 elle N SEATING 0 17 PLANE COPLANARITY 0 10 COMPLIANT TO JEDEC STANDARDS MO 187BA Figure 50 10 Lead Mini Small Outline Package MSOP RM 10 Dimensions shown in millimeters ORDERING GUIDE Model Ras Q Temperature Package Description Package Option Branding AD5161BRM5 5k 40 C to 125 C 10 Lead MSOP RM 10 DOC AD5161BRM5 RL7 5k 40 C to 125 C 10 Lead MSOP RM 10 DOC AD5161BRMZ5 5k 40 C to 125 C 10 Lead MSOP RM 10 D0C AD5161BRMZ5 RL7 5k 40 C to 125 C 10 Lead MSOP RM 10 D0C AD5161BRM10 10k 40 C to 125 C 10 Lead MSOP RM 10 DOD AD5161BRM10 RL7 10k 40 C to 125 C 10 Lead MSOP RM 10 DOD AD5161BRMZ10 10k 40 C to 125 C 10 Lead MSOP RM 10 D0D AD5161BRMZ10 RL7 10k 4
16. d to the internal RDAC register when the CS line returns to logic high Extra MSB bits are ignored Daisy Chain Operation The serial data output SDO pin contains an open drain N channel FET This output requires a pull up resistor in order to transfer data to the next packages SDI pin This allows for daisy chaining several RDACs from a single processor serial data line The pull up resistor termination voltage can be larger than the supply voltage It is recommended to increase the clock period when using a pull up resistor to the SDI pin of the following device because capacitive loading at the daisy chain node SDO SDI between devices may induce time delay to subsequent devices Users should be aware of this potential problem to achieve data transfer successfully see Figure 43 If two AD5161s are daisy chained a total of at least 16 bits of data is required The first eight bits complying with the format shown in Table 6 go to U2 and the second eight bits with the same format go to Ul CS should be kept low until all 16 bits are clocked into their respective serial registers After this CS is pulled high to complete the operation and load the RDAC latch If the data word during the CS low period is greater than 16 bits any additional MSBs will be discarded Figure 43 Daisy Chain Configuration Compatible 2 Wire Serial Bus DIS 1 The AD5161 can also be controlled via an compatible serial bus with DIS tied hi
17. ddress instruction and data byte Similarly a repeated read function of the RDAC is also allowed Readback RDAC Value The AD5161 allows the user to read back the RDAC values in the read mode Refer to Table 7 and Table 8 for the programming format Multiple Devices on One Bus Figure 44 shows two AD5161 devices on the same serial bus Each has a different slave address since the states of their ADO pins are different This allows each RDAC within each device to be written to or read from independently The master device output bus line drivers are open drain pull downs in a fully compatible interface SDA SCL Figure 44 Multiple AD5161 Devices on One FC Bus Rev A Page 17 of 20 LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE While most legacy systems may be operated at one voltage a new component may be optimized at another When two systems operate the same signal at two different voltages proper level shifting is needed For instance one can use a 3 3 V E PROM to interface with a 5 V digital potentiometer level shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E PROM Figure 45 shows one of the implementations M1 and 2 can be any N channel signal FETs or if Vp falls below 2 5 V low threshold FETs such as the FDV301N 3 3V 5V AD5161 Figure 45 Level Shifting for Operation a
18. eostat Operation The nominal resistance of the RDAC between terminals A and B is available in 5 10 50 and 100 The final two or three digits of the part number determine the nominal resistance value e g 10 10 50 50 The nominal resistance Ras of the VR has 256 contact points accessed by the wiper terminal plus the B terminal contact The 8 bit data in the RDAC latch is decoded to select one of the 256 possible settings Assume a 10 part is used the wiper s first connection starts at the B terminal for data 0x00 Since there is a 60 wiper contact resistance such connection yields a minimum of 60 resistance between Terminals W and B The second connection is the first tap point which corresponds to 99 Ras 256 Rw 39 Q 60 for data 0x01 The third connection is the next tap point representing 177 2 x 39 60 0 for data 0x02 and so on Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 9961 Ras 1158 Rw Figure 42 shows a simplified diagram of the equivalent RDAC circuit where the last resistor string will not be accessed therefore there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance Figure 42 AD5161 Equivalent RDAC Circuit The terms digital potentiometer VR and RDAC are used interchangeably The general equation determining the digitally program
19. f nine clock pulses a slight difference with the write mode where there are eight data bits followed by an acknowledge bit Similarly the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL see Figure 41 5 When all data bits have been read or written a STOP condition is established by the master A STOP condition is defined as a low to high transition on the SDA line while SCL is high In write mode the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition see Figure 40 In read mode the master will issue a No Acknowledge for the ninth clock pulse i e the SDA line remains high The master will then bring the SDA line low before the tenth clock pulse which goes high to establish a STOP condition see Figure 41 A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once During the write cycle each data byte will update the RDAC output For example after the RDAC has acknowledged its slave address and instruction bytes the RDAC output will update after these two bytes If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction this byte will update the output of the selected slave device If different instructions are needed the write mode has to start again with a new slave a
20. gh The RDACs are connected to this bus as slave devices The first byte of the AD5161 is a slave address byte see Table 7 and Table 8 It has a 7 bit slave address and a R W bit The six MSBs of the slave address are 010110 and the following bit is determined by the state of the ADO pin of the device ADO allows the user to place up to two of the PC compatible devices on one bus The 2 wire serial bus protocol operates as follows 1 The master initiates data transfer by establishing a START condition which is when a high to low transition on the SDA line occurs while SCL is high see Figure 40 The following byte is the slave address byte which consists of the 7 bit slave address followed by an R W bit this bit determines whether data will be read from or written to the slave device Rev A Page 16 of 20 slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse this is termed the acknowledge bit At this stage all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register If the R W bit is high the master will read from the slave device On the other hand if the R W bit is low the master will write to the slave device write operation contains an extra instruction byte that a read operation does not contain Such an instruction byte in write mode follows the slave addres
21. iption 1 A A Terminal 2 B B Terminal 3 CS ADO Chip Select CS Input Active Low When CS returns high data will be loaded into the DAC register Programmable address bit 0 ADO for multiple package decoding 4 SDO NC Serial Data Output SDO Open drain transistor requires pull up resistor No Connect NC 5 SDI SDA Serial Data Input SDI Serial Data Input Output SDA 6 CLK SCL Serial Clock Input Positive edge triggered 7 GND Digital Ground 8 DIS Digital Interface Select SPI I C Select SPI when DIS 0 when DIS 1 9 Positive Power Supply 10 w W Terminal Rev A Page 7 of 20 TYPICAL PERFORMANCE CHARACTERISTICS 0 8 5V 3V amp 0 6 i s 8 04 w E E 02 ul 8 a 0 K t lt 02 ui 04 a E 0 6 0 8 1 0 0 32 64 96 128 160 192 224 256 CODE Decimal CODE Decimal Figure 4 R INL vs Code vs Supply Voltages Figure 7 DNL vs Code Vop 5 V RHEOSTAT MODE DNL LSB POTENTIOMETER MODE INL LSB 0 32 64 96 128 160 192 224 256 CODE Decimal CODE Decimal Figure 5 R DNL vs Code vs Supply Voltages Figure 8 INL vs Code vs Supply Voltages POTENTIOMETER MODE DNL LSB POTENTIOMETER MODE INL LSB
22. med output resistance between W and B is D Ryg D cxR ap R 1 we D 256 AB W 1 where D is the decimal equivalent of the binary code loaded in the 8 bit register is the end to end resistance and Rwis the wiper resistance contributed by the on resistance of the internal switch In summary if Ras 10 and the A terminal is open circuited the following output resistance Rws will be set for the indicated RDAC latch codes Table 9 Codes and Corresponding Rws Resistance D Rw Q Output State 255 9 961 Full Scale Ras 1 LSB Rw 128 5 060 Midscale 1 99 1LSB 0 60 Zero Scale Wiper Contact Resistance Note that in the zero scale condition a finite wiper resistance of 60 is present Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA Otherwise degradation or possible destruction of the internal switch contact can occur Similar to the mechanical potentiometer the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance When these terminals are used the B terminal can be opened Setting the resistance value for Rwa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value The general equation for this operation is 256 D Rw 2 For Ras 10
23. of wiper resistance Vw can be found as R D R D WB WA V 256 256 3 D B 4 Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature Unlike the rheostat mode the output voltage is dependent mainly on the ratio of the internal resistors Rwa and Rws and not the absolute values Therefore the temperature drift reduces to 15 ppm C PIN SELECTABLE DIGITAL INTERFACE The AD5161 provides the flexibility of a selectable interface When the digital interface select DIS pin is tied low the SPI mode is engaged When the DIS pin is tied high the mode is engaged SPI Compatible 3 Wire Serial Bus DIS 0 The AD5161 contains a 3 wire SPI compatible digital interface SDI CS and CLK The 8 bit serial word must be loaded MSB first The format of the word is shown in Table 6 The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register Standard logic families work well If mechanical switches are used for product evaluation they should be debounced by a flip flop or other suitable means When CS is low the clock loads data into the serial register on each positive clock edge see Figure 37 The data setup and data hold times in the specification table determine the valid timing requirements The AD5161 uses an 8 bit serial input data register word that is transferre
24. rts to share the same control lines In the mode address pin AD0 can be used to place up to two devices on the same bus In this same mode command bits are available to reset the wiper position to midscale or to shut down the device into a state of zero power consumption Operating from a 2 7 V to 5 5 V power supply and consuming less than 5 uA allows for usage in portable battery operated applications Rev A sD SDA a CLK SCL Il SPI IPC INTERFACE ps CS Abo WIPER B REGISTER GND Figure 1 PIN CONFIGURATION 5 topview 81015 SDO NC 4 Not to Scale 7 GND SDI SDA 5 6 CLK SCL Figure 2 Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2003 2009 Analog Devices Inc All rights reserved TABLE OF CONTENTS Features asqa sm amy w Sa hap asua 1 Applications app aaa ires AR CURIE 1 General Description et
25. s byte The first bit MSB of the instruction byte is a don t care The second MSB RS is the midscale reset A logic high on this bit moves the wiper to the center tap where This feature effectively writes over the contents of the register and thus when taken out of reset mode the RDAC will remain at midscale The third MSB SD is a shutdown bit A logic high causes an open circuit at terminal A while shorting the wiper to terminal B This operation yields almost 0 in rheostat mode or 0 V in potentiometer mode It is important to note that the shutdown operation does not disturb the contents of the register When brought out of shutdown the previous setting will be applied to the RDAC Also during shutdown new settings can be programmed When the part is returned from shutdown the corresponding VR setting will be applied to the RDAC The remainder of the bits in the instruction byte are don t cares see Table 7 After acknowledging the instruction byte the last byte in write mode is the data byte Data is transmitted over the serial bus in sequences of nine clock pulses eight data bits followed by an acknowledge bit The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL see Table 7 In the read mode the data byte follows immediately after the acknowledgment of the slave address byte Data is transmitted over the serial bus in sequences o
26. t Different Potentials ESD PROTECTION All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 46 and Figure 47 This applies to the digital input pins SDI SDA CLK SCL and CS ADO Figure 47 ESD Protection of Resistor Terminals TERMINAL VOLTAGE OPERATING RANGE The AD5161 Vp and GND power supply defines the boundary conditions for proper 3 terminal digital potentiometer operation Supply signals present on terminals A B and W that exceed or GND will be clamped by the internal forward biased diodes see Figure 48 Vpp Vss Figure 48 Maximum Terminal Voltages Set by Vpp and Vss POWER UP SEQUENCE Since the ESD protection diodes limit the voltage compliance at terminals A B and W see Figure 48 it is important to power Vpp GND before applying any voltage to terminals B and W otherwise the diode will be forward biased such that Vo will be powered unintentionally and may affect the rest of the user s circuit The ideal power up sequence is in the following order GND digital inputs and then V sw The relative order of powering Va Vs Vw and the digital inputs is not important as long as they are powered after Vpp GND LAYOUT AND POWER SUPPLY BYPASSING Itis a good practice to employ compact minimum lead length layout design The leads to the inputs should be as direct as possible with a minimum conductor length Ground paths should h
27. wiper positions R DNL measures the relative step change from ideal between successive tap positions Parts are guaranteed monotonic Wiper Vw no connect 51 and DNL are measured at Vw with the RDAC configured as a potentiometer divider similar to a voltage output D A converter Voo and Vs 0 V DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions 5 Resistor terminals A B W have no limitations on polarity with respect to each other Guaranteed by design and not subject to production test 7 Measured at the A terminal The A terminal is open circuited in shutdown mode 8 is calculated from lbo CMOS logic level inputs result in minimum power dissipation dynamic characteristics use 5 V 10 See timing diagram for location of measured values All input control voltages are specified with ta tc 2 ns 10 to 90 of 3 V and timed from a voltage level of 1 5 V 11 See timing diagrams for locations of measured values Rev A Page 5 of 20 ABSOLUTE MAXIMUM RATINGS 25 C unless otherwise noted Stresses above those listed under Absolute Maximum Ratings Table 4 may cause permanent damage to the device This is a stress Parameter Value Ehe deiceatth rating only functional operation of the device at these or an to GND 0 3 Vto 7 V BOR a Ve Vw to
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ANALOG DEVICES AD5161 English products handbook