ANALOG DEVICES AD5246 English products handbook Rev B
Contents
1. 0 16 32 48 64 80 96 112 CODE Decimal Figure 3 R INL vs Code vs Supply Voltages 03875 020 128 CODE Decimal Figure 4 R DNL vs Code vs Supply Voltages T4 40 C T4 25 C TA 85 C TA 125 0 16 32 48 64 80 96 112 CODE Decimal Figure 5 R INL vs Code vs Temperature 12 03875 021 03875 022 Rev C Page 8 of 16 RHEOSTAT MODE DNL LSB FSE FULL SCALE ERROR LSB ZSE ZERO SCALE ERROR LSB Vpp 27V Rap 10 25 C 85 C 125 C 03875 023 0 16 32 48 64 80 96 112 128 CODE Decimal Figure 6 R DNL vs Code vs Temperature 03875 024 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 7 Full Scale Error vs Temperature 1 50 1 25 1 00 0 75 0 50 0 25 03875 025 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 8 Zero Scale Error vs Temperature GAIN dB 100 DIGITAL INPUTS2. Data Hold Time 6 0 9 us tsu pat Data Setup Time t 100 ns tr Fall Time of Both SDA and SCL Signals ts 300 ns tr Rise Time of Both SDA and SCL Signals to 300 ns tsusro Setup Time for STOP Condition tio 0 6 us 1 Typical specifications represent average readings at 25 C and Von 5 V Guaranteed by design not subject to production test 3 timing diagrams Figure 26 Figure 27 and Figure 28 for locations of measured values Specifications apply to all parts Rev C Page 5 of 16 AD5246 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 4 Parameter Value Voo to GND 0 3Vto 47V Va Vw to GND Voo Terminal Current A B A W B W Pulsed 20 mA Continuous 5 mA Digital Inputs and Output Voltage to GND O V to Voo 0 3 V Operating Temperature Range 40 C to 125 C Maximum Junction Temperature Tmax 150 C Storage Temperature 65 C to 150 C Lead Temperature Soldering 10 sec 300 C Thermal Resistance SC70 6 340 C W Maximum terminal current is bounded by the maximum current handling of the switches maximum power dissipation of the package and maximum applied voltage across any two of the A B and W terminals at a given resistance 2 Package power dissipation Tmax Ta Oua ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment
3. 14 Terminal Voltage Operating Range sse 14 Maximum Operating Current sssseeeeee 14 Power Up Sequerice eee eder e eite 14 Layout and Power Supply Bypassing sss 15 Constant Bias to Retain Resistance 15 Outline Dimensions nsei 16 Ordering G lde coste et 16 Rev Page 2 of 16 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 5 VERSION Voo 5 1096 or 3 V 10 Va 40 C lt Ta lt 125 C unless otherwise noted AD5246 Table 1 Parameter Symbol Conditions Min Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity R DNL Rws 1 5 01 41 5 LSB Resistor Integral Nonlinearity R INL Rws 4 075 4 15 Nominal Resistor Tolerance ARas Ta 25 C 30 30 Resistance Temperature Coefficient ARas Ras AT Wiper no connect 45 ppm C Rwe Rws Code 0x00 Von 5 V 75 150 Q Code 0x00 Voo 2 7 V 150 400 Q RESISTOR TERMINALS Voltage Range Vs w GND Voo V Capacitance B f 1 MHz measured to GND code 0x40 45 pF Capacitance W Cw f 1 MHz measured to GND code 0x40 60 pF Common Mode Leakage Icm 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High Von 5V 24 V Input Logic Low Vit Vop 5V 0 8 V Input Logic High Von 23V 2 1 V Input Logic Low Vit Voo 3 V 0 6 V Input Current lit Vin OVor5V 1 uA Input Capacitance Ci 5 pF POWER SUPPLIES
4. 0V CODE 0x40 z 10 5 5V E DD z gt 1 o gt 5 o d 01 2 0 01 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 9 Supply Current vs Temperature 1 00 lwg 2000A _ 90 2 7V Rap 10kQ o amp 70 o n 2 60 50 2 40 30 20 10 0 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 CODE Decimal Figure 10 Rheostat Mode Tempco ARws AT vs Code 03875 028 1k 10k 100k FREQUENCY Hz 1M 10 Figure 11 Gain vs Frequency vs Code Ras 5 03875 026 03875 027 Rev C Page 9 of 16 GAIN dB GAIN dB GAIN dB AD5246 0 amp 0 40 12 0x20 ES 0x10 0x08 24 0x04 30 0x02 25 0x01 42 48 54 amp 60 5 1k 10k 100k 1M 10M FREQUENCY Hz Figure 12 Gain vs Frequency vs Code Ras 10 0 4l 6 0x40 0x20 18 0x10 ET 0x08 0x04 30 0x02 36 0x01 42 48 54 8 60 E 1k 10k 100k 1M 10M FREQUENCY Hz Figure 13 Gain vs Frequency v
5. Power Supply Range Vp RANGE 2 7 5 5 V Supply Current Voo 5 5 V Vin Voo or Vi GND 3 7 Voo 5 V Vin Voo or Vi GND 2 5 5 2 Voo 3 3 V Voo or Vii GND 0 9 2 Power Dissipation Poiss Vi 5 V or Vu O0 V Voo 5 V 40 uW Power Supply Sensitivity PSSR Voo 5 V 10 code midscale 0 01 0 025 DYNAMIC CHARACTERISTICS 7 Bandwidth 3 dB BW 5K Ras 5 code 0x40 1 2 MHz Total Harmonic Distortion THDw Va 1 V rms Vs O V f 1 kHz 0 05 Vw Settling Time ts Va 5 V 1 LSB error band 1 us Resistor Noise Voltage Density Rwe 2 5 lt 00 6 nV 4Hz 1 Typical specifications represent average readings at 25 C Voo 5 V Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions R DNL measures the relative step change from ideal between successive tap positions Parts are guaranteed monotonic 3 Code Ox7F Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other 5 Guaranteed by design not subject to production test 6 is calculated from loo x Voo CMOS logic level inputs result in minimum power dissipation 7Mpp 5 V Rev Page 3 of 16 AD5246 ELECTRICAL CHARACTERISTICS 10 50 100 VERSIONS Vpp 5 V 1096 or 3 V 10 Va Von 40 C lt Ta lt 125 C unl
6. Rev Page 16 of 16
7. 0 40 120 1 10 040 0 90 0 70 080 um des D HE t 0 46 0 10 MAX 036 SEATING 022 0 30 PLANE 0 0 COPLANARITY 015 0 26 0 10 072809 A COMPLIANT TO JEDEC STANDARDS MO 203 AB Figure 36 6 Lead Thin Shrink Small Outline Transistor Package SC70 KS 6 Dimensions shown in millimeters ORDERING GUIDE Model Ras kQ Temperature Range Package Description Package Option Branding AD5246BKSZ5 RL7 5 40 C to 125 C 6 lead SC70 KS 6 D93 AD5246BKSZ10 R2 10 40 C to 125 C 6 lead SC70 KS 6 D92 AD5246BKSZ10 RL7 10 40 C to 125 C 6 lead SC70 KS 6 D92 AD5246BKSZ50 RL7 50 40 C to 125 6 lead SC70 KS 6 D94 AD5246BKSZ100 R2 100 40 C to 125 C 6 lead SC70 KS 6 D9D AD5246BKSZ100 RL7 100 40 C to 125 C 6 lead SC70 KS 6 D9D EVAL AD5246DBZ Evaluation Board 17 RoHS Compliant Part The evaluation board is shipped with the 10 kO Ras resistor option however the board is compatible with all available resistor value options Purchase of licensed C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent Rights to use these components in an 2 system provided that the system conforms to the I C Standard Specification as defined by Philips 2003 2012 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www analo g com Id DEVICES
8. Typical Performance Characteristics sees 8 Test Circuits 11 este RC RR o 12 Operation iet A e I Pe PEN ERI 13 REVISION HISTORY 5 12 Rev B to Rev C Changes to Features and General Description Sections 1 Changes to Ipp Parameters Table 1 ss 3 Changes to Ip Parameters Table 2 sss 4 Changes to Figure ette etta eere 9 Removed Evaluation Board Section sss 15 Changes to Ordering Guide ses 16 8 09 Rev A to Rev B Changes to Power Supply Sensitivity Parameter 3 Updated Outline 2516 Changes to Ordering Guide sss 16 7 05 Rev 0 to Rev A Changes to Table etes 3 Changes to Table2 dye eerte te eth ee ette 4 Changes to Absolute Maximum Ratings eee 6 Moved Pin Configuration and Function Descriptions 7 Deleted Table 7 eee oiei 12 Changes to Operation Section sss 13 Deleted Figure 31 e RE a ent 14 Changes to Figure 30 and Figure 32 sss 14 9 03 Revision 0 Initial Version Programming the Variable Resistor sss 13 Compatible 2 Wire Serial Bus ss 13 Level Shifting for Bidirectional Interface 14 ESD Protection
9. desire nonvolatility but cannot justify the addi tional cost for the EEMEM the AD5246 may be considered as a low cost alternative by maintaining a constant bias to retain the wiper setting The AD5246 was designed specifically with low power in mind which allows low power consumption even in battery operated systems The graph in Figure 35 demonstrates the power consumption from a 3 4 V 450 mA hr Li ion cell phone battery which is connected to the AD5246 AD5246 The measurement over time shows that the device draws approximately 1 3 uA and consumes negligible power Over a course of 30 days the battery was depleted by less than 296 the majority of which is due to the intrinsic leakage current of the battery itself BATTERY LIFE DEPLETED 03875 035 0 5 10 15 20 25 30 DAYS Figure 35 Battery Operating Life Depletion This demonstrates that constantly biasing the pot is not an impractical approach Most portable devices do not require the removal of batteries for the purpose of charging Although the resistance setting of the AD5246 will be lost when the battery needs replacement such events occur rather infrequently so that this inconvenience is justified by the lower cost and smaller size offered by the AD5246 If and when total power is lost the user should be provided with a means to adjust the setting accordingly Rev Page 15 of 16 AD5246 OUTLINE DIMENSIONS 1 00
10. no more than 20 mA Otherwise degradation or possible destruction of the internal switch contact can occur Typical device to device matching is process lot dependent and may vary by up to 30 Since the resistance element is proc essed in thin film technology the temperature coefficient of Ras is only 45 ppm C PC COMPATIBLE 2 WIRE SERIAL BUS The first byte of the AD5246 is a slave address byte see Table 6 and Table 7 It has a 7 bit slave address and an R W bit The seven MSBs of the slave address are 0101110 followed by 0 for a write command or 1 to place the device in read mode The 2 wire serial bus protocol operates as follows 1 master initiates data transfer by establishing a START condition which is when a high to low transition on the SDA line occurs while SCL is high see Figure 27 The following byte is the slave address byte which consists of the 7 bit slave address followed by an R W bit this bit determines whether data will be read from or written to the slave device The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse this is termed the acknowledge bit At this stage all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register If the R W bit is high the master reads from the slave device Conversely if the R W bit is low the master writes to
11. the part only once For example after the RDAC has acknowledged its slave address in write mode the RDAC output updates on each succes sive byte If different instructions are needed the write read mode has to start again with a new slave address and data byte Similarly a repeated read function of the RDAC is also allowed LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE While most legacy systems may be operated at one voltage a new component may be optimized at another When two systems operate the same signal at two different voltages proper level shifting is needed For instance one can use a 1 8 V to interface with a 5 V digital potentiometer A level shifting scheme is needed to enable a bidirectional communi cation so that the setting of the digital potentiometer can be stored to and retrieved from the E PROM Figure 30 shows one of the implementations M1 and M2 can be any N channel signal FETs or if Vp falls below 2 5 V M1 and M2 can be low threshold FETs such as the FDV301N Vpp1 1 8V SDA1 SCL1 5V 03875 011 AD5246 Figure 30 Level Shifting for Operation at Different Potentials ESD PROTECTION All digital inputs are protected with a series input resistor and parallel Zener ESD structures as shown in Figure 31 This applies to the digital input pins SDA and SCL 3409 O LOGIC V GND 03875 002 Figure 31 ESD Protection of Digital Pins TERMINAL VOLTAGE OPERATING RANGE The AD524
12. the slave device 2 In write mode after acknowledgement of the slave address byte the next byte is the data byte Data is transmitted over the serial bus in sequences of nine clock pulses eight data bits followed by an acknowledge bit The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL see Table 6 3 Inread mode after acknowledgment of the slave address byte data is received over the serial bus in sequences of nine clock pulses a slight difference from the write mode where eight data bits are followed by an acknowledge bit Similarly the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL see Figure 28 4 When all data bits have been read or written a STOP condition is established by the master A STOP condition is defined as a low to high transition on the SDA line while SCL is high In write mode the master pulls the SDA line high during the tenth clock pulse to establish a STOP condition see Figure 27 In read mode the master issues a No Acknowledge for the ninth clock pulse that is the SDA line remains high The master then brings the SDA line low before the tenth clock pulse which goes high to establish a STOP condition see Figure 28 Rev C Page 13 of 16 AD5246 A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing
13. 0 0 05 Vw Settling Time 10 50 100 ts 5 1 LSB error band 2 us Resistor Noise Voltage Density Rwe 5 Rs 0 9 nV VHz 1 Typical specifications represent average readings at 25 C and Voo 5 V Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions R DNL measures the relative step change from ideal between successive tap positions Parts are guaranteed monotonic 3 Code Ox7F 4 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other 5 Guaranteed by design not subject to production test 6 is calculated from loo x Voo CMOS logic level inputs result in minimum power dissipation 7 All dynamic characteristics use Voo 5 V Rev C Page 4 of 16 TIMING CHARACTERISTICS Voo 5 V 10 or 3 V 1096 Va 40 C lt Ta lt 125 C unless otherwise noted AD5246 Table 3 Parameter Symbol Conditions Min Max Unit INTERFACE TIMING CHARACTERISTICS 3 4 SCL Clock Frequency 400 kHz tsur Bus Free Time Between STOP and START t 1 3 us tup srA Hold Time Repeated START t After this period the first clock pulse is generated 0 6 us trow Low Period of SCL Clock ts 1 3 us High Period of SCL Clock t4 0 6 50 us tsusrA Setup Time for Repeated START Condition ts 0 6 us
14. 3 V allows for usage in portable battery operated applications 1 The terms digital potentiometer VR and are used interchangeably in this document Rev C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 128 Position I C Compatible Digital Resistor 05246 FUNCTIONAL BLOCK DIAGRAM Vpp SCL 12C INTERFACE SDA WIPER REGISTER 03875 001 GND Figure 1 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2003 2012 Analog Devices Inc All rights reserved AD5246 TABLE OF CONTENTS SpecifiCatioris iin ede e Rt e IER Ee ede 3 Electrical Characteristics 5 kQ Version eee 3 Electrical Characteristics 10 50 100 Versions 4 Timing Characteristics seeeeeeentetete tentent 5 Absolute Maximum Ratings sse 6 ESD GAUSEION ctetu C ERE D eI 6 Pin Configuration and Function 7
15. 6 and GND power supply defines the boundary conditions for proper 3 terminal digital potentiometer operation Supply signals present on Terminal B and Terminal W that exceed Vp or GND are clamped by the internal forward biased diodes see Figure 32 Vpp 03875 016 GND Figure 32 Maximum Terminal Voltages Set by Vop and GND MAXIMUM OPERATING CURRENT At low code values the user should be aware that due to low resistance values the current through the RDAC may exceed the 5 mA limit In Figure 33 a 5 V supply is placed on the wiper and the current through Terminal W and Terminal B is plotted with respect to code A line is also drawn denoting the 5 mA current limit Note that at low code values particularly for the 5 and 10 options the current level increases significantly Care should be taken to limit the current flow between W and B in this state to a maximum continuous current of 5 mA and a maximum pulse current of no more than 20 mA Otherwise degradation or possible destruction of the internal switch contacts can occur 100 10 LI 5mA CURRENT LIMIT Rag 5kQ 1 5 Rag 10kO m Rag 50kQ 0 1 Rap 100kQ 0 01 3 0 16 32 48 64 80 96 112 12 CODE Decimal Figure 33 Maximum Operating Current POWER UP SEQUENCE Since the E
16. ANALOG DEVICES FEATURES 128 position End to end resistance 5 10 50 100 Ultracompact SC70 6 2 mm x 2 1 mm package PC compatible interface Full read write of wiper register Power on preset to midscale Single supply 2 7 V to 5 5 V Rheostat mode temperature coefficient 45 ppm C Low power 0 9 pA at 3 3 V typical Wide operating temperature 40 C to 125 APPLICATIONS Mechanical potentiometer replacement in new designs Transducer adjustment of pressure temperature position chemical and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment GENERAL OVERVIEW The AD5246 provides a compact 2 mm x 2 1 mm packaged solution for 128 position adjustment applications This device performs the same electronic adjustment function as a variable resistor Available in four different end to end resistance values 5 10 50 100 kQ these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments The wiper settings are controllable through the compatible digital interface which can also be used to read back the present wiper register control word The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC latch Operating from a 2 7 V to 5 5 V power supply and consuming 0 9 uA 3
17. SD protection diodes limit the voltage compliance at Terminal B and Terminal W see Figure 32 it is important to power Vpp GND before applying any voltage to Terminal B and Terminal W otherwise the diode is forward biased such that Vpp is powered unintentionally and may affect the rest of the user s circuit The ideal power up sequence is in the follow ing order GND Von digital inputs and then Vs Vw The relative order of powering V and Vw and the digital inputs is not important providing they are powered after Vpp GND Rev C Page 14 of 16 LAYOUT AND POWER SUPPLY BYPASSING It is a good practice to use a compact minimum lead length layout design The leads to the inputs should be as direct as possible with a minimum conductor length Ground paths should have low resistance and low inductance Similarly it is good practice to bypass the power supplies with quality capacitors for optimum stability Supply leads to the device should be bypassed with 0 01 uF to 0 1 uF disc or chip ceramic capacitors Low ESR 1 uF to 10 uF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple see Figure 34 Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce AD5246 03875 017 Figure 34 Power Supply Bypassing CONSTANT BIAS TO RETAIN RESISTANCE SETTING For users who
18. TS Figure 21 to Figure 25 define the test conditions used in the product Specification tables Rsw 4 DUT DUT 5 lw CODE 0x00 IL O CU Vms 5 V B Vpp TO GND 5 Figure 21 Test Circuit for Resistor Position Nonlinearity Error Figure 24 Test Circuit for Incremental On Resistance Rheostat Operation R INL R DNL DUT Ve Vpp 10 PSRR dB 20 LOG us 5 AV ms PSS Pee DD Vms 8 E P NO CONNECT 8 Figure 22 Test Circuit for Power Supply Sensitivity PSS PSSR Figure 25 Test Circuit for Common Mode Leakage Current d c lt H 03875 010 Figure 23 Test Circuit for Gain vs Frequency Rev Page 11 of 16 AD5246 l C INTERFACE Table 6 Write Mode S 0 1 0 1 1 1 0 Ww A X D6 D5 D4 D3 D2 D1 DO A Slave Address Byte Data Byte Table 7 Read Mode S 0 1 0 1 1 1 0 R A 0 D6 D5 D4 D3 D2 D1 DO A Slave Address Byte Data Byte S Start Condition W Write P Stop Condition R Read A Acknowledge D6 D5 D4 D3 D2 D1 DO Data Bits X Dont Care SCL 4 03875 019 Figure 26 PC Interface Detailed Timing Diagram SCL AUS AA SEE Hm f CDC CCS C CR ACK BY ACK BY 1 2 FRAME 2 AD5246 stop By TART BY pa 2 MASTER SLAVE ADDRESS BYTES DATA BYTE MASTER Fi
19. and can discharge without detection Although this product features Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability WARNING S proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Sprit Ate electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev C Page6 of 16 AD5246 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 5 AD5246 GND 2 5 W Not to Scale Sc 3 2 50 03875 018 Figure 2 Pin Configuration Table 5 Pin Function Descriptions Pin No Mnemonic Description 1 Voo Positive Power Supply 2 GND Digital Ground 3 SCL Serial Clock Input Positive edge triggered 4 SDA Serial Data Input Output 5 W Terminal 6 B B Terminal Rev C Page 7 of 16 AD5246 TYPICAL PERFORMANCE CHARACTERISTICS RHEOSTAT MODE INL LSB RHEOSTAT MODE DNL LSB RHEOSTAT MODE INL LSB 1 0 0 8 0 6 0 4 0 2 25 C Rap 10
20. ess otherwise noted Table 2 Parameter Symbol Conditions Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity R DNL Rwe Va no connect 1 0 1 1 LSB Resistor Integral Nonlinearity R INL Rwe Va no connect 2 0 25 2 LSB Nominal Resistor Tolerance ARas Ta 25 20 20 Resistance Temperature Coefficient ARag Rag AT Wiper no connect 45 ppm C Rwe Rwe Code 0x00 Von 5 V 75 150 Code 0x00 Voo 2 7 V 150 400 Q RESISTOR TERMINALS Voltage Range Vs w GND Voo V Capacitance B Cs f 1MHz measured to GND code 0x40 45 pF Capacitance W Cw f 1 MHz measured to GND code 0x40 60 pF Common Mode Leakage Icm 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High Voo 5V 2 4 V Input Logic Low Vit Vpp 5V 0 8 V Input Logic High Vop 2 3V 2 1 V Input Logic Low Vit Vpp 3 V 0 6 V Input Current li Vin OVor5V 1 uA Input Capacitance Ci 5 pF POWER SUPPLIES Power Supply Range VDD RANGE 2 7 5 5 V Supply Current Voo 5 5 V Voo or Vi GND 3 7 yA Voo 5 V Voo or Vi GND 2 5 5 2 Voo 3 3 V Vu Voo or Vi GND 0 9 2 Power Dissipation Poiss 5 V or Ve 0V Voo 5 40 uW Power Supply Sensitivity PSSR Voo 5 V 10 code midscale 0 01 0 02 DYNAMIC CHARACTERISTICS 7 Bandwidth 3 dB BW Ras 10 50 100 code 0x40 600 100 40 kHz Total Harmonic Distortion THDw Va 1 V rms f 1 kHz Ras 1
21. gure 27 Writing to the RDAC Register A ANASA e fA _ EEEE ACK BY NO ACK AD5246 BY MASTER 5 START BY FRAME 1 FRAME 2 gt STOPBY MASTER SLAVE ADDRESS BYTE RDAC REGISTER MASTER 2 Figure 28 Reading from the RDAC Register Rev Page 12 of 16 AD5246 OPERATION The AD5246 is a 128 position digitally controlled variable resistor VR device PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminal A and Terminal is available in 5 10 50 and 100 The final two or three digits of the part number determine the nominal resistance value that is 10 kQ 10 50 kQ 50 The nominal resistance Ras of the VR has 128 contact points accessed by the wiper terminal The 7 bit data in the RDAC latch is decoded to select one of the 128 possible settings The general equation determining the digitally programmed output resistance between W and B is D Ry D Ras 2 Ry 1 where D is the decimal equivalent of the binary code loaded in the 7 bit RDAC register Ras is the end to end resistance Rwis the wiper resistance contributed by the on resistance of each internal switch 03875 015 Figure 29 AD5246 Equivalent RDAC Circuit Note that in the zero scale condition there is a relatively small finite wiper resistance Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of
22. s Code Ras 50 0 4 0x40 e 0x20 18 0x10 24 0x08 30 0x04 36 0x02 1 42 0x0 48 54 8 60 5 1k 10k 100k 1M 10M FREQUENCY Hz Figure 14 Gain vs Frequency vs Code Ras 100 kQ AD5246 GAIN dB Ipp uA 0 6 5kQ 12 10kO 18 100kQ 24 50kQ 30 36 42 48 54 S 60 z 1k 10k 100k 1M 10M FREQUENCY Hz Figure 15 3 dB Bandwidth Code 0x80 0 30 A Vpp 5 5V Ty 25 C CODE 0x55 0 257 Vpp 5 5V CODE 0 7 0 20 C Vpp 2 7V CODE 0x55 0 15 D Vpp 2 7V CODE 0x7F 0 10 A B 0 05 H 0 2 1k 10k 100k 1M FREQUENCY Hz Figure 16 loo vs Frequency 360 300 240 180 120 60 25 C Rap 50 CODE 0x00 0 03875 008 05 10 15 20 25 30 35 40 45 50 55 Veias V Figure 17 Rws vs Veias VS Voo 25 C Rap 10k 100kHz CLK 03875 006 ius DIV Figure 18 Digital Feedthrough Vpp 5 5V TA 25C Vp OV Rap 10kQ CODE 0x40 to 0x3F 03875 007 200ns DIV Figure 19 Midscale Glitch Code 0x40 to Ox3F Vpp 5 5V Vp 0V CODE 00 7Fy 03875 005 40us DIV Figure 20 Large Signal Settling Time Rev Page 10 of 16 AD5246 TEST CIRCUI
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ANALOG DEVICES AD5246 English products handbook Rev B