ANALOG DEVICES AD558 English products handbook
Contents
1. 0 V to 7 0 V VOUE Sar ee oe ee re ee ee Indefinite Short to Ground Momentary Short to Vcc Power Dissipation 0 0 cece eee eens 450 mW Storage Temperature Range N P Plastic Packages 25 C to 100 C D Ceramic Package 55 C to 150 C Lead Temperature soldering 10 sec 300 C Thermal Resistance Junction to Ambient Junction to Case D Ceramic Package 100 C W 30 C W N P Plastic Packages 140 C W 55 C W Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability AD558 METALIZATION PHOTOGRAPH TOP VIEW Not to Scale REV A Dimensions is in cae and mm 7 E 0 112 2 8 e Model Temperature AD558JN 0 C to 70 C AD558JP 0 C to 70 C AD558JD 0 C to 70 C AD558KN 0 C to 70 C AD558KP 0 C to 70 C AD558KD 0 C to 70 C AD558SD 55 C to 125 C AD558TD 55 C to 125 C NOTES ORDERING GUIDE Relative Accuracy Error Max Tmn to Tmax 1 2 LSB 1 2 LSB 1 2 LSB 1 4 LSB 1 4 LSB 1 4 LSB 3 4 LSB 3 8 LSB Full Scale Error Max2. L input register and fully microprocessor compatible control logic allow the AD558 to be directly connected to 8 or 16 bit data buses and operated with standard control signals The latch may be disabled for direct DAC interfacing 2 The laser trimmed on chip SiCr thin film resistors are calibrated for absolute accuracy and linearity at the factory Therefore no user trims are necessary for full rated accuracy over the operating temperature range 3 The inclusion of a precision low voltage bandgap reference eliminates the need to specify and apply a separate refer ence source 4 The voltage switching structure of the AD558 DAC section along with a high speed output amplifier and laser trimmed resistors give the user a choice of 0 V to 2 56 V or 0 V to 10 V output ranges selectable by pin strapping Circuitry is internally compensated for minimum settling time on both ranges typically settling to 1 2 LSB for a full scale 2 55 volt step in 800 ns 5 The AD558 is designed and specified to operate from a single 4 5 V to 16 5 V power supply 6 Low digital input currents 100 UA max minimize bus load ing Input thresholds are TTL low voltage CMOS compat ible over the entire operating Vcc range 7 All AD558 grades are available in chip form with guaranteed specifications from 25 C to Tmax MIL STD 883 Class B visual inspection is standard on Analog Devices bipolar chips Contact the factory for additional chip informatio
3. The 0 V to 10 V range requires a power supply of 11 4 V to 16 5 V OUTPUT OUTPUT Vout Vout Vout SENSE Vout SENSE Vour SELECT Vour SELECT GND GND a 0 V to 2 56 V Output Range b 0 V to 10 V Output Range Figure 3 Connection Diagrams Because of its precise factory calibration the AD558 is intended to be operated without user trims for gain and offset therefore no provisions have been made for such user trims If a small in crease in scale is required however it may be accomplished by slightly altering the effective gain of the output buffer A resistor in series with Voy SENSE will increase the output range For example if a 0 V to 10 24 V output range is desired 40 mV 1 LSB a nominal resistance of 850 Q is required It must be remembered that although the internal resistors all ratio match and track the absolute tolerance of these resistors is typically 20 and the absolute TC is typically 50 ppm C 0 to 100 ppm C That must be considered when rescaling is performed Figure 4 shows the recommended circuitry for a full scale output range of 10 24 volts Internal resistance values shown are nominal REV A Applications AD558 Figure 4 10 24 V Full Scale Connection NOTE Decreasing the scale by putting a resistor in series with GND will not work properly due to the code dependent currents in GND Adjusting offset by injecting dc at GND 1s not recommended for the same reason GROUNDING AND BY
4. Transparent 0 g 0 Latching 1 g 0 Latching 0 0 g Latching 1 0 g Latching X 1 X Previous Data Latched X X 1 Previous Data Latched NOTES X Does not matter g Logic Threshold at Positive Going Transition CE DAC DATA Figure 6 AD558 Control Logic Function In a level triggered latch such as that in the AD558 there is an interaction between data setup and hold times and the width of the enable pulse In an effort to reduce the time required to test all possible combinations in production the AD558 is tested with tps tw 200 ns at 25 C and 270 ns at Twin and Tmax with tpy 10 ns at all temperatures Failure to comply with these specifications may result in data not being latched properly Figure 7 shows the timing for the data and control signals CE and CS are identical in timing as well as in function AD558 1 2 LSB DAC V OUTPUT tseTTLING tw STORAGE PULSE WIDTH 200ns MIN toy DATA HOLD TIME 10ns MIN tbs DATA SETUP TIME 200ns MIN tseTTLING DAC OUTPUT SETTLING TIME TO 1 2 LSB Figure 7 AD558 Timing USE OF Vour SENSE Separate access to the feedback resistor of the output amplifier allows additional application versatility Figure 8a shows how I x R drops in long lines to remote loads may be cancelled by putting the drops inside the loop Figure 8b shows how the separate sense may be used to provide a higher output current by feeding back around a simple
5. current booster Vout OV TO 10V RL a Compensation for I x R Drops in Output Lines Vec 2N2222 Vout SENSE y OUT OV TO 2 56V RL b Output Current Booster Figure 8 Use of Vour Sense OPTIMIZING SETTLING TIME In order to provide single supply operation and zero based output voltage ranges the AD558 output stage has a passive pull down to ground As a result settling time for negative going output steps may be longer than for positive going output steps The relative difference depends on load resistance and capacitance If a negative power supply is available the negative going settling time may be improved by adding a pull down resistor from the output to the negative supply as shown in Figure 9 The value of the resistor should be such that at zero voltage out current through that resistor is 0 5 mA max BIPOLAR OUTPUT RANGES The AD558 was designed for operation from a single power supply and is thus capable of providing only unipolar 0 V to 2 56 V and 0 V to 10 V output ranges If a negative supply is Z Vow SENSE NEGATIVE SUPPLY RP D 2x VEE VEE in KQ Figure 9 Improved Settling Time available bipolar output ranges may be achieved by suitable output offsetting and scaling Figure 10 shows how a 1 28 volt output range may be achieved when a 5 volt power supply is available The offset 1s provided by the AD589 precision 1 2 volt reference which will operate
6. from a 5 volt supply The AD544 output amplifier can provide the necessary 1 28 volt output swing from 5 volt supplies Coding is complementary offset binary 5kQ A 7kO 00000000 128V COTE 10000000 ov 11111111 1 27V Figure 10 Bipolar Operation of AD558 from 5 V Supplies MEASURING OFFSET ERROR One of the most commonly specified endpoint errors associated with real world nonideal DACs is offset error In most DAC testing the offset error is measured by applying the zero scale code and measuring the output deviation from 0 volts There are some DACs like the AD558 where offset errors may be present but not observable at the zero scale because of other circuit limitations such as zero coinciding with single supply ground so that a nonzero output at zero code cannot be read as the offset error Factors like this make testing the AD558 a little more complicated By adding a pulldown resistor from the output to a negative supply as shown in Figure 11 we can now read offset errors at zero code that may not have been observable due to circuit limitations The value of the resistor should be such that at zero voltage out current through the resistor is 0 5 mA max OUTPUT a 0 V to 2 56 V Output Range 6 REV A b 0 V to 10 V Output Range Figure 11 Offset Connection Diagrams INTERFACING THE AD558 TO MICROPROCESSOR DATA BUSES The AD558 is configured to act like a write only location in memory
7. that may be made to coincide with a read only memory location or with a RAM location The latter case allows data previously written into the DAC to be read back later via the RAM Address decoding is partially complete for either ROM or RAM Figure 12 shows interfaces for three popular micropro cessor systems ADDRESS BUS VOUT AD558 R W DB0 DB7 8 8 DATA BUS RW gt CE GATED DECODED ADDRESS CS a 6800 AD558 Interface ADDRESS SELECT PULSE LOGIC AD558 DBO DB7 DATA BUS MEMW CE DECODED ADDRESS SELECT PULSE gt S b 8080A AD558 Interface ADDRESS BUS ADDRESS mm Lote mm Lote DBO DB7 DATA BUS CDP 1802 MWR gt CE DECODED ADDRESS SELECT PULSE CS c 1802 AD558 Interface Figure 12 Interfacing the AD558 to Microprocessors Performance typical 25 C Vec 5 V to 15 V unless otherwise noted LSB ALL AD558 1 00 AD5589 T ERROR 0 25 0 50 0 75 1 00 55 25 O 25 50 75 100 125 OC 1LSB 0 39 OF FULL SCALE Figure 13 Full Scale Accuracy vs Temperature Performance of AD558 REV A ALL AD558 AD558S T 55 25 0 25 50 75 100 125 C 1 2 1LSB 0 39 OF FULL SCALE Figure 14 Zero Drift vs Temperature Performance of AD558 AD558 18 VOLTS Figure 15 Quiescent Current vs Power Supply Voltage for AD558 DATA INPUT TTL LEVELS HORIZONTAL 200ns DIV Figure 16 AD558 Set
8. 4 0 to 2 56 0 to 10 5 Internal Passive Pull Down to Ground 1 2 1 125 375 55 125 5 55 AD558T Min Typ Max 0 to 2 56 0 to 10 Internal Passive Pull Down to Ground The AD558 S amp T grades are available processed and screened lo MIL STD 883 Class B Consult Analog Devices Military Databook for details Relative Accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the offset to the full scale of the device See Measuring Offset Error gt Operation of the 0 volt to 10 volt output range requires a minimum supply voltage of 11 4 volts Passive pull down resistance is 2 KQ for 2 56 volt range 10 kQ for 10 volt range Settling time is specified for a positive going full scale step to 1 2 LSB Negative going steps to zero are slower but can be improved with an external pull down The full range output voltage for the 2 56 range is 2 55 V and is guaranteed with a 5 V supply for the 10 V range it is 9 960 V guaranteed with a 15 V supply 7A monotonic converter has a maximum differential linearity error of 1 LSB 8See Figure 7 Specifications shown in boldface are tested on all production units at final electrical test Specifications subject to change without notice LSB LSB LSB LSB C REV A ABSOLUTE MAXIMUM RATINGS Vice tO Ground 2 4 0 ooo ae ead Sa bas OVto 18 V Digital Inputs Pins 1 10
9. ANALOG DEVICES DACPORT Low Cost Complete uP Compatible 8 Bit DAC AD938 FEATURES Complete 8 Bit DAC Voltage Output 2 Calibrated Ranges Internal Precision Bandgap Reference Single Supply Operation 5 V to 15 V Full Microprocessor Interface Fast 1 ws Voltage Settling to 1 2 LSB Low Power 75 mW No User Trims Guaranteed Monotonic Over Temperature All Errors Specified Tin to Tmax Small 16 Pin DIP and 20 Pin PLCC Packages Single Laser Wafer Trimmed Chip for Hybrids Low Cost MIL STD 883 Compliant Versions Available PRODUCT DESCRIPTION The AD558 DACPORT is a complete voltage output 8 bit digital to analog converter including output amplifier full microprocessor interface and precision voltage reference on a single monolithic chip No external components or trims are required to interface with full accuracy an 8 bit data bus to an analog system The performance and versatility of the DACPORT 1s a result of several recently developed monolithic bipolar technologies The complete microprocessor interface and control logic is imple mented with integrated injection logic PL an extremely dense and low power logic structure that 1s process compatible with linear bipolar fabrication The internal precision voltage reference is the patented low voltage bandgap circuit which permits full accuracy performance on a single 5 V to 15 V power supply Thin film silicon chromium resistors provide the stability re quired fo
10. NTED IN U S A
11. PASSING All precision converter products require careful application of good grounding practices to maintain full rated performance Because the AD558 is intended for application in microcom puter systems where digital noise is prevalent special care must be taken to assure that its inherent precision is realized The AD558 has two ground common pins this minimizes ground drops and noise in the analog signal path Figure 5 shows how the ground connections should be made OUTPUT TO SYSTEM GND TO SYSTEM GND 0 1uF SEE TEXT TO SYSTEM Vec Figure 5 Recommended Grounding and Bypassing It is often advisable to maintain separate analog and digital grounds throughout a complete system tying them common in one place only If the common tie point is remote and acciden tal disconnection of that one common tie point occurs due to card removal with power on a large differential voltage between the two commons could develop To protect devices that inter face to both digital and analog parts of the system such as the AD558 it is recommended that common ground tie points should be provided at each such device If only one system ground can be connected directly to the AD558 it is recom mended that analog common be selected POWER SUPPLY CONSIDERATIONS The AD558 is designed to operate from a single positive power supply voltage Specified performance is achieved for any supply voltage between 4 5 V and 16 5 V This mak
12. Tmn to Tmax 2 5 LSB 2 5 LSB 2 5 LSB 1 LSB 1 LSB 1 LSB 2 5 LSB 1 LSB TOP VIEW GND 5 Not to Scale 2 18 VourSELECT GND 16 NC 15 GND Voc NC NO CONNECT Figure 1b AD558 Pin Configuration PLCC and LCC Package Option Plastic N 16 PLCC P 20A TO 116 D 16 Plastic N 16 PLCC P 20A TO 116 D 16 TO 116 D 16 TO 116 D 16 lFor details on grade and package offerings screened in accordance with MIL STD 883 refer to the Analog Devices Military Products Databook or current AD558 883B data sheet D Ceramic DIP N Plastic DIP P Plastic Leaded Chip Carrier 3 AD998 CIRCUIT DESCRIPTION The AD558 consists of four major functional blocks fabricated on a single monolithic chip see Figure 2 The main D to A converter section uses eight equally weighted laser trimmed current sources switched into a silicon chromium thin film R 2R resistor ladder network to give a direct but unbuffered 0 mV to 400 mV output range The transistors that form the DAC switches are PNPs this allows direct positive voltage logic interface and a zero based output range DIGITAL INPUT DATA CONTROL INPUTS Vcc GND GND Iy OUTPUT 8 BIT VOLTAGE SWITCHING AMP i D TO A CONVERTER CONTROL AMP Figure 2 AD558 Functional Block Diagram Vout Vout SENSE Vout SELECT The high speed output buffer amplifier is operated in the non inverting mode with gain determined b
13. es the AD558 ideal for battery operated portable automotive or digital main frame applications For additional insight An IC Amplifier Users Guide to Decoupling Grounding and Making Things Go Right For A change is available at no charge from any Analog Devices Sales Office REV A The only consideration in selecting a supply voltage is that in order to be able to use the 0 V to 10 V output range the power supply voltage must be between 11 4 V and 16 5 V If how ever the 0 V to 2 56 V range is to be used power consumption will be minimized by utilizing the lowest available supply voltage above 4 5 V TIMING AND CONTROL The AD558 has data input latches that simplify interface to 8 and 16 bit data buses These latches are controlled by Chip Enable CE and Chip Select CS inputs CE and CS are inter nally NORed so that the latches transmit input data to the DAC section when both CE and CS are at Logic 0 If the ap plication does not involve a data bus a 00 condition allows for direct operation of the DAC When either CE or CS go to Logic 1 the input data is latched into the registers and held until both CE and CS return to 0 Unused CE or CS inputs should be tied to ground The truth table is given in Table I The logic function is also shown in Figure 6 Table I AD558 Control Logic Truth Table Latch Input Data CE CS DAC Data Condition 0 0 0 Transparent 1 0 0
14. n 8 The AD558 is available in versions compliant with MIL STD 883 Refer to Analog Devices Military Products Data book or current AD558 883B data sheet for detailed specifications One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 AD558 SPEC F CATI 0 NS Ta 25 C Vec 9 V to 15 V unless otherwise noted Min Typ Max Min a a Model RESOLUTION RELATIVE ACCURACY 0 C to 70 C 55 C to 125 C OUTPUT Ranges Current Source Sink OUTPUT SETTLING TIME 0 to 2 56 Volt Range 0 to 10 Volt Range FULL SCALE ACCURACY 25 C Tyr to Tmax ZERO ERROR 25 C Tmn to Tmax MONOTONICITY Tmn to Tmax DIGITAL INPUTS Tmn to Tmax Input Current Data Inputs Voltage Bit On Logic 1 Bit On Logic 0 Control Inputs Voltage On Logic 1 On Logic 0 Input Capacitance TIMING tw Strobe Pulse Width Tyr to Tmax tpu Data Hold Time Tmn to Tmax tps Data Set Up Time Tmn to Tmax POWER SUPPLY Operating Voltage Range Vcc 2 56 Volt Range 10 Volt Range Current Icc Rejection Ratio POWER DISSIPATION Vec 5 V Vec 15 V OPERATING TEMPERATURE RANGE 0 NOTES AD558J Min Typ Max 5 1 2 0 to 2 56 0 to 10 Internal Passive Pull Down to Ground 0 to 2 56 0 to 10 Internal Passive Pull Down to Ground 2 0 3 0 0 5 1 1 2 1 75 125 225 375 AD558S Typ Max 1 2 3
15. r guaranteed monotonic operation over the entire oper ating temperature range all grades while recent advances in laser wafer trimming of these thin film resistors permit absolute calibration at the factory to within 1 LSB thus no user trims for gain or offset are required A new circuit design provides voltage settling to 1 2 LSB for a full scale step in 800 ns The AD558 is available in four performance grades The AD558J and K are specified for use over the 0 C to 70 C temperature range while the AD558S and T grades are specified for 55 C to 125 C operation The J and K grades are available either in 16 pin plastic N or hermetic ceramic D DIPS They are also available in 20 pin JEDEC standard PLCC pack ages The S and T grades are available in the 16 pin her metic ceramic DIP package DACPORT is a registered trademark of Analog Devices Inc REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM CONTROL INPUTS DIGITAL INPUT DATA BUS 8 BIT VOLTAGE SWITCHING D TO A CONVERTER C Vout VouTSENSE A VoytSELECT GND V PRODUCT HIGHLIGHTS 1 The 8 bit I
16. signed with these ap plications in mind The hermetically sealed low profile DIP package takes up a fraction of the space required by equivalent modular designs and protects the chip from hazardous environ ments To further ensure reliability military temperature range AD558 grades S and T are available screened to MIL STD 883 For more complete data sheet information consult the Analog Devices Military Databook CHIP AVAILABILITY The AD558 is available in laser trimmed passivated chip form AD558J and AD558T chips are available Consult the factory for details Input Logic Coding Digital Input Code Output Voltage 2 56 V Range 10 000 V Range 0000 0000 0000 0001 0000 0010 0000 1111 0001 0000 0111 1111 1000 0000 1100 0000 1111 1111 CONNECTING THE AD558 The AD558 has been configured for ease of application All ref erence output amplifier and logic connections are made inter nally In addition all calibration trims are performed at the factory assuring specified accuracy without user trims The only connection decision that must be made by the user is a single jumper to select output voltage range Clean circuit board lay out is facilitated by isolating all digital bit inputs on one side of the package analog outputs are on the opposite side Figure 3 shows the two alternative output range connections The 0 V to 2 56 V range may be selected for use with any power supply between 4 5 V and 16 5 V
17. tling Characteristics Detail 0 V to 2 56 V Output Range Full Scale Step DATA INPUT TTL LEVELS VouT 1 2LSB DIV HORIZONTAL 500ns DIV Figure 17 AD558 Settling Characteristic Detail 0 V to 10 V Output Range Full Scale Step O N Tp e CS AND CE STROBE PULSE DATA IN ALL BITS VOUT OV TO 2 56V fies esos esl es pee RANGE oe HORIZONTAL 100ns DIV Figure 18 AD558 Logic Timing OUTLINE DIMENSIONS Dimensions shown in inches and mm N Plastic Package 22 1 MAX F 0 25 0 31 6 35 7 87 0 035 0 89 7 cs se A Sg Se 7 62 0 018 0 46 0 033 0 84 0 1 2 54 D Ceramic Package as an 0 922 0 040R 0 265 0 290 0 010 0 310 0 01 6 73 7 37 40 254 7 874 0 254 p 0 800 0 010 i 20 32 0 254 0 035 0 01 0 095 2 41 a 0 035 0 01 0 889 0 254 _ ise AT 0 co 2 159 180 0 03 is 57 0 taal 125 01256 175 MIN pe 0 002 0 254 0 05 1 ME 20 481 D 4 0 Topsa en _0 017 8 093 017 J 0 43 a 076 0 700 17 78 BSC P PLCC Package 0 173 0 008 4 385 0 185 0 390 0 005 sq 9 905 0 125 7 0 105 0 015 2 665 0 375 0 020 MIN 0 353 003 8 966 0 076 Sa 0 51 F w p 0 035 0 01 at R 9 89 0 25 0 045 0 003 1 143 0076 0 020 0 0 0 51 0 432 0 101 MAX F gm 0 025 of le io 64 NN 0 02 0 0 51 MAX 1 27 0 060 MIN 1 53 8 REV A C558f 2 1 8 87 PRI
18. y the user connections at the output range select pin The gain setting application resistors are thin film laser trimmed to match and track the DAC resistors and to assure precise initial calibration of the two output ranges 0 V to 2 56 V and 0 V to 10 V The amplifier output stage is an NPN transistor with passive pull down for zero based output capability with a single power supply The internal precision voltage reference is of the patented bandgap type This design produces a reference voltage of 1 2 volts and thus unlike 6 3 volt temperature compensated Zeners may be operated from a single low voltage logic power supply The microprocessor interface logic consists of an 8 bit data latch and control circuitry Low power small geometry and high speed are advantages of the I L design as applied to this section I L is bipolar process compatible so that the performance of the ana log sections need not be compromised to provide on chip logic capabilities The control logic allows the latches to be operated from a decoded microprocessor address and write signal If the application does not involve a uP or data bus wiring CS and CE to ground renders the latches transparent for direct DAC access MIL STD 883 The rigors of the military aerospace environment temperature extremes humidity mechanical stress etc demand the utmost in electronic circuits The AD558 with the inherent reliability of integrated circuit construction was de
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ANALOG DEVICES AD558 English products handbook