ANALOG DEVICES AD7528 English products handbook Rev B
Contents
1. 0 66 0 02 51 MAX La e 0 025 0 64 0 02 0 51 MIN MAX 0 060 1 53 MIN REV B C681e 0 9 98 PRINTED IN U S A2. stereo audio and telephone signal level control applications Table IV gives input codes vs attenuation for a 0 dB to 15 5 dB range Attenuation dB Input Code 256 X 10 exp CET SUGGESTED OP AMP AD644 Figure 15 Digitally Controlled Dual Telephone Attenuator Table IV Attenuation vs DAC A DAC B Code for the Circuit of Figure 15 Attn DAC Input CodeIn Attn DAC Input Code In dB Code Decimal dB Code Decimal 0 0 11111111 255 80 01100110 102 0 5 11110010 242 85 01100000 96 1 0 11100100 228 9 0 01011011 91 1 5 11010111 215 95 01010110 86 2 0 11001011 203 10 0 01010001 81 2 5 11000000 192 10 5 01001100 76 3 0 10110101 181 11 0 01001000 72 3 5 10101011 171 11 5 01000100 68 4 0 10100010 162 12 0 01000000 64 4 5 10011000 152 125 00111101 61 5 0 10010000 144 13 0 00111001 57 5 5 10001000 136 13 5 00110110 54 6 0 10000000 128 14 0 00110011 51 6 5 01111001 121 14 5 00110000 48 7 0 01110010 114 15 0 00101110 46 7 5 01101100 108 15 5 00101011 43 For further applications information the reader is referred to Analog Devices Application Note on the AD7528 OUTLINE DIMENSIONS Dimensions shown in inches and mm 20 Lead Cerdip Q 20 F 0 28 7 11 0 24 6 1 0 32 8 128 0 97 24 64 pane r 0 935 23 75 029 7 366 0 20 5 0 0 14 3 56 0 14 3 56 0 125 3 17 paseo X seatine 0 125 3 18 gt e e PLANE 0 011 0 28 0 07 1 78 0 0
3. 1 LSB Q 20 AD7528SQ 55 C to 125 C 1 LSB 4 LSB Q 20 AD7528TQ 55 C to 125 C 1 2 LSB 2 LSB Q 20 AD7528UQ 55 C to 125 C 1 2 LSB 1 LSB Q 20 NOTES Analog Devices reserves the right to ship side brazed ceramic in lieu of cerdip Parts will be marked with cerdip designator Q Processing to MIL STD 883C Class B is available To order add suffix 883B to part number For further information see Analog Devices 1990 Military Products Databook 3N Plastic DIP P Plastic Leaded Chip Carrier Q Cerdip R SOIC One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1998 AD7528 SPEC CATI NS Veer Veer B 10 V OUT A OUT B 0 V unless otherwise noted 5 Vpp 15 V Parameter Version Ta 25 C Tmax Ta7 25 Tum Tmax Units Test Conditions Comments STATIC PERFORMANCE Resolution All 8 8 8 8 Bits Relative Accuracy J A 8 1 1 1 1 LSB max This is an Endpoint Linearity Specification K B T t1 2 t1 2 t1 2 t1 2 LSB max L C U 1 2 1 2 1 2 1 2 LSB max Differential Nonlinearity t1 1 1 1 LSB max All Grades Guaranteed Monotonic Over Full Operating Temperature Range Gain Error LAS t4 6 4 5 LSB max Measured Using Internal Rfg and Rfg K B T 2 4 2 t3 LSB max Both DAC Latches Loaded with 11111111
4. 2 0 5 0 11 2 79 15 0 009 0 23 0 05 1 27 0 016 0 41 0 09 2 28 0 LEAD NO 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42 20 Lead SOIC R 20 0 5118 13 00 0 4961 12 60 20 11 0 2992 7 60 0 2914 7 40 0 4193 10 65 1 10 0 3937 10 00 mn PIN 1 0 1043 2 65 0291 0 74 0 0926 2 35 20291 0 74 0 0098 0 25 45 T 0 0118 0 30 0 0500 0 0192 0 49 T i i 49 SEATING 0 0500 1 27 apaninim 1 27 90138 0 45 0 0125 0 32 0 0040 0 10 20 0 0138 0 35 PLANE 10 23 0 0157 0 40 20 Lead Plastic DIP N 20 4 1 07 27 18 MAX 07 27 18 WWE Do 11 1 0 255 6 477 m 0 32 8 128 4 0 30 7 62 0 145 3 683 0 135 3 429 t MIN 0 125 3 17 0 125 2 175 Ey MIN SEATING bami ioe be 0 011 0 28 0 021 0 533 0 11 2 79 0 065 1 66 PLANE 15 0003 023 0 015 0 381 0 09 2 28 0 045 1 15 0s LEAD NO 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42 20 Lead Plastic Leaded Chip Carrier P 20A 0 180 4 47 0 395 10 02 0 165 4 19 0 385 9 78 ls 0 12 3 05 0 356 9 04 0 09 2 29 0 350 8 89 it gt 0 020 0 51 MIN 0 048 1 21 0 042 1 07 4 0 021 0 53 FOA Nes Hio F 0 013 0 33 TOP VIEW PINS DOWN 0 032 0 81 y 0 026
5. AC A and DAC B is inherent The AD7528 s matched CMOS DACs make a whole new range of applications circuits possible particularly in the audio graphics and process control areas 2 Small package size combining the inputs to the on chip DAC latches into a common data bus and adding a DAC A DAC B select line has allowed the AD7528 to be packaged in either a small 20 lead DIP SOIC or PLCC REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ORDERING GUIDE Temperature Relative Gain Package Model Ranges Accuracy Error Options AD7528 N 40 to 85 C 1 LSB 4 LSB N 20 AD7528KN 40 C to 85 C 1 2 LSB 2 LSB N 20 AD7528LN 40 C to 85 C 1 2 LSB 1 LSB N 20 AD7528JP 40 C to 85 C 1 LSB 4 LSB P 20A AD7528KP 40 C to 85 C 1 2 LSB 2 LSB P 20A AD75281P 40 C to 85 C 1 2 LSB 1 LSB P 20A AD7528 R 40 to 85 C 1 LSB 4 LSB R 20 AD7528KR 40 C to 85 C 1 2 LSB 2 LSB R 20 AD7528LR 40 C to 85 C 1 2 LSB 1 LSB R 20 AD7528AQ 40 C to 85 C 1 LSB 4 LSB Q 20 AD7528BQ 40 C to 85 C 1 2 LSB 2 LSB Q 20 AD7528CQ 40 C to 85 C 1 2 LSB
6. ANALOG DEVICES CMOS Dual 8 Bit Buffered Multiplying DAC AD7528 FUNCTIONAL BLOCK DIAGRAM FEATURES On Chip Latches for Both DACs 5 V to 15 V Operation DACs Matched to 1 Four Quadrant Multiplication TTL CMOS Compatible Latch Free Protection Schottkys not Required APPLICATIONS Digital Control of Gain Attenuation Filter Parameters Stereo Audio Circuits X Y Graphics GENERAL DESCRIPTION The AD7528 is a monolithic dual 8 bit digital analog converter featuring excellent DAC to DAC matching It is available in skinny 0 3 wide 20 lead DIPs and in 20 lead surface mount packages Separate on chip latches are provided for each DAC to allow easy microprocessor interface Data is transferred into either of the two DAC data latches via a common 8 bit T TL CMOS compatible input port Control input DAC A DAC B determines which DAC is to be loaded The AD7528 s load cycle is similar to the write cycle of a ran dom access memory and the device is bus compatible with most 8 bit microprocessors including 6800 8080 8085 Z80 The device operates from a 5 V to 15 V power supply dis sipating only 20 mW of power Both DACSs offer excellent four quadrant multiplication charac teristics with a separate reference input and feedback resistor for each DAC PRODUCT HIGHLIGHTS 1 DAC to DAC matching since both of the AD7528 DACs are fabricated at the same time on the same chip precise match ing and tracking between D
7. GRAMMABLE STATE VARIABLE FILTER In this state variable or universal filter configuration Figure 14 DACs AI and control the gain and Q of the filter character istic while DACs A2 and B2 control the cutoff frequency fc DACSs A2 and B2 must track accurately for the simple expres sion for fc to hold This is readily accomplished by the AD7528 Op amps are 2 x AD644 C3 compensates for the effects of op amp gain bandwidth limitations R DAC A DAC B Figure 14 Digitally Controlled State Variable Filter REV B In the circuit of Figure 13 the AD7528 is used to implement a programmable window comparator DACs A and B are loaded with the required upper and lower voltage limits for the test respectively If the test input is not within the programmed limits the pass fail output will indicate a fail logic zero The filter provides low pass high pass and band pass outputs and is ideally suited for applications where microprocessor control of filter parameters is required e g equalizer tone controls etc Programmable range for component values shown is fc 0 kHz to 15 kHz and Q 0 3 to 4 5 CIRCUIT EQUATIONS C1 C2 R1 R2 R5 1 fe 3XRICI DAC Equivalent Resistance Equals 256 x DAC Ladder Resistance DAC Digital Code AD7528 DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR In this configuration the AD7528 functions as a 2 channel digi tally controlled attenuator Ideal for
8. L C U 1 3 1 1 LSB max Gain Error is Adjustable Using Circuits of Figures 4 and 5 Gain Temperature Coefficient AGain ATemperature All 0 007 0 007 0 0035 0 0035 C max Output Leakage Current OUT A Pin 2 All 50 400 50 200 nA max DAC Latches Loaded with 00000000 OUT B Pin 20 All 50 400 50 200 nA max Input Resistance Vnggr A Vngr B All 8 8 8 8 kQ min Input Resistance TC 300 ppm C Typical 15 15 15 15 kQ max Input Resistance is 11 Vrer A Vgrgr Input Resistance Match All 1 1 1 1 max DIGITAL INPUTS Input High Voltage TH All 2 4 2 4 13 5 13 5 V min Input Low Voltage Vit All 0 8 0 8 1 5 15 V max Input Current Ix I 10 1 10 uA max Vin 0 or Vpp Input Capacitance DB0 DB7 10 10 10 10 pF max WR CS DAC A DAC B 15 15 15 15 SWITCHING CHARACTERISTICS See Timing Diagram Chip Select to Write Set Up Time tcs 90 100 60 80 ns min Chip Select to Write Hold Time tcu All 0 0 10 15 ns min DAC Select to Write Set Up Time tas All 90 100 60 80 ns min DAC Select to Write Hold Time tay All 0 0 10 15 ns min Data Valid to Write Set Up Time tps 80 90 30 40 ns min Data Valid to Write Hold Time toy All 0 0 0 0 ns min Write Pulsewidth twr All 90 100 60 80 ns min POWER SUPPLY See Figure 3 Ipp All 2 2 2 2 mA max All Digital Inputs or All 100 500 100 500 uA max All Digital Inputs 0 V or Vpp AC PERFORMANCE CHARACTERISTICS Measured Using Recomm
9. ended P C Board Layout Figure 7 and AD644 as Output Amplifiers Vpp 5 V Vpp 15 V Parameter Version T 25 Tygys Ta 25 Tags Tmax Units Test Conditions Comments DC SUPPLY REJECTION AGAIN AVpp All 0 02 0 04 0 01 0 02 per max AVpp 5 CURRENT SETTLING TIME All 350 400 180 200 ns max To 1 2 LSB OUT A OUT B Load 100 Q WR CS 0 V DBO DB7 0 V to Vpp or Vpp to 0 V PROPAGATION DELAY From Digital In Veer Vggp B 10 V put to 90 of Final Analog Output Current All 220 270 80 100 ns max OUT A OUT B Load 100 Q 13 pF WR CS 0 V DBO DB7 0 V to Vpp or Vpp to 0 V DIGITAL TO ANALOG GLITCH IMPULSE 160 440 nV sec typ For Code Transition 00000000 to 11111111 OUTPUT CAPACITANCE 50 50 50 50 pF DAC Latches Loaded with 00000000 50 50 50 50 pF CourA 120 120 120 120 pF max DAC Latches Loaded with 11111111 CourB 120 120 120 120 pF max AC FEEDTHROUGH A to OUT A All 70 65 70 65 dB max Vrer Vngr B 20 V p p Sine Wave Vrer B to OUT B 10 65 70 65 dB max 100 kHz REV 07528 Vpp 5 Vpp 15 V Parameter Version Ta 25 C Tmn Tmax Ta 25 C Tmn Tmax Units Test Conditions Comments CHANNEL TO CHANNEL ISOLATION Both DAC Latches Loaded with 11111111 Vrer A to OUT B All 77 77 dB typ Vrer 20 V p p Sine Wave 100 kHz Vrer B 0 V see F
10. igure 6 Vrer B to OUT A 77 77 dB typ Vrer A 20 V p p Sine Wave 100 kHz Vrer 0 V see Figure 6 DIGITAL CROSSTALK All 30 60 nV sec typ Measured for Code Transition 00000000 to 11111111 HARMONIC DISTORTION 85 85 dB typ Vin 6 V rms 1 kHz NOTES l Temperature Ranges are J K L Versions 40 C to 85 B C Versions 40 C to 85 S T U Versions 55 C to 125 Specifications applies to both DACs in AD7528 5Guaranteed by design but not production tested Logic inputs are MOS Gates Typical input current 25 C is less than 1 nA These characteristics are for design guidance only and are not subject to test Feedthrough can be further reduced by connecting the metal lid on the ceramic package suffix D to DGND Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Vpp to AGND b eas Tee 0V 317 V Vppto DGND na see ERE HN 0V 417 V AGND to DGND Vpp 0 3 V DGND to AGND Vpp 0 3 V Digital Input Voltage to DGND 0 3 V Vpp 0 3 V Veins to AGND 0 3 V Vpp 0 3V Vrer Vagg to AGND 25 V Vggp Vreg to AGND 25 V Power Dissipation Any Package to 75 450 mW Derates above 75 C by 6 mW C Operating Temperature Range Commercia
11. l J K L Grades Industrial A B C Grades Extended S T U Grades Storage Temperature Lead Temperature Soldering 10 secs 40 C to 85 C 40 C to 85 C 55 C to 125 C 65 to 150 C CAUTION 1 ESD sensitive device The digital control inputs are diode protected however permanent damage may occur on uncon nected devices subjected to high energy electrostatic fields Unused devices must be stored in conductive foam or shunts 2 Do not insert this device into powered sockets Remove power before insertion or removal TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB max over the operating temperature range ensures monotonicity Gain Error Gain error or full scale error is a measure of the output error between an ideal DAC and the actual device output For the REV AD7528 ideal maximum output is 1 LSB Gain error of both DACs is adjustable to zero with external resistance Output Capacitance Capacitance fr
12. nd 0 8 V into CMOS logic levels When Vy is in the region of 2 0 volts to 3 5 volts the input buffers operate in their linear region and pass a quiescent current see Figure 3 To minimize power supply currents it is recommended that the digital input voltages be as close to the supply rails Vpp and DGND as is practically possible The AD7528 may be operated with any supply voltage in the range 5 Vpp 15 volts With Vpp 15 V the input logic levels are CMOS compatible only i e 1 5 V and 13 5 V 9 800 Vpp 15V Ty 25 8 200 ALL DIGITAL INPUTS TIED TOGETHER 600 6 500 5 gt gt 400 42 i E 900 5V st 200 27 100 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Vin Volts Figure 3 Typical Plots of Supply Current Ipp vs Logic Input Voltage for 5 V and 15 V 4 REV B AD7528 Table I Unipolar Binary Code Table DAC Latch Contents Analog Output MSB LSB DAC A or DAC B 255 11111111 va y 129 10000001 IN 556 128 Vin 10000000 v 18 127 01111111 t 1 00000001 Valz 0 00000000 5 0 NOTES R1 R2 AND R3 R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED 1 SEE TABLE Ill FOR RECOMMENDED VALUES Note 1 LSB 2 356 V 2C1 C2 PHASE COMPENSATION 10pF 15pF IS REQUIRED WHEN USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION Figure 4 Dual DAC Unipola
13. olation PIN 8 OF TO 5 CAN AD644 2 AD644 AD644 AD7528 PIN 1 C2 LOCATION NOTE INPUT SCREENS 9 A TO REDUCE DGND FEEDTHROUGH LAYOUT SHOWS o DAC A DAC B COPPER SIDE LSB o MSB i e BOTTOM VIEW Figure 7 Suggested PC Board Layout for AD7528 with AD644 Dual Op Amp 6 ship between input frequency and channel to channel isolation Figure 7 shows a printed circuit layout for the AD7528 and the AD644 dual op amp which minimizes feedthrough and crosstalk SINGLE SUPPLY APPLICATIONS The AD7528 DAC R 2R ladder termination resistors are con nected to AGND within the device This arrangement is par ticularly convenient for single supply operation because AGND may be biased at any voltage between DGND and Vpp Figure 8 shows a circuit which provides two 5 V to 8 V analog out puts by biasing AGND 5 V up from DGND The two DAC reference inputs are tied together and a reference input voltage is obtained without a buffer amplifier by making use of the constant and matched impedances of the DAC A and DAC B reference inputs Current flows through the two DAC R 2R ladders into R1 and R1 is adjusted until the and Vrgr B inputs are at 2 V The two analog output voltages range from 5 V to 8 V for DAC codes 00000000 to 11111111 Figure 8 AD7528 Single Supply Operation Figure 9 shows DAC A of the AD7528 connected in a positive reference voltage switching mode This configurati
14. om OUT A or OUT B to AGND Digital to Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state This is normally specified as the area of the glitch in either pA secs or nV secs depending upon whether the glitch is measured as a current or voltage signal Glitch impulse is measured with Vpgr Vnggr AGND Propagation Delay This is a measure of the internal delays of the circuit and is defined as the time from a digital input change to the analog output current reaching 90 of its final value Channel to Channel Isolation The proportion of input signal from one DAC s reference input which appears at the output of the other DAC expressed as a ratio in dB Digital Crosstalk The glitch energy transferred to the output of one converter due to a change in digital input code to the other converter Speci fied in nV secs PIN CONFIGURATIONS PLCC m m u 19 n OUT A AGND s OUT B a u 3 PIN 1 VREF IDENTIFIER Vrer B DGND Vpp oo AD7528 00 DAC A DAC SOR VIEW WR MSB DB7 Not to Scale ts DB6 DBO LSB EON DIP SOIC O nner d m m AGND 1 e OUT A 2 Reg A 3 Veer A 4 DGND 5 AD7528 TOP VIEW DAC A DAC B a Not to Scale MSB DB7 DB6 8 DB5 9 DB4 10 AD7528 INTERFACE LOGIC INFORMATION DAC Selection Both DAC latches share a common 8 bit input po
15. omplex systems where the AGND DGND intertie is on the backplane it is recommended that diodes be connected in inverse parallel between the AD7528 AGND and DGND pins 1N914 or equivalent 2 OUTPUT AMPLIFIER OFFSET CMOS DACs exhibit a code dependent output resistance which in turn causes a code dependent amplifier noise gain The effect is a code dependent differential nonlinearity term at the amplifier output which depends on Vos Vos is amplifier input offset voltage This differential nonlinearity term adds to the R 2R differential nonlinearity To maintain monotonic operation it is recommended that amplifier Vos be no greater than 10 of 1 LSB over the temperature range of interest 3 HIGH FREQUENCY CONSIDERATIONS The output capacitance of a CMOS DAC works in conjunction with the amplifier feedback resistance to add a pole to the open loop response This can cause ringing or oscillation Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor DYNAMIC PERFORMANCE The dynamic performance of the two DACs in the AD7528 will depend upon the gain and phase characteristics of the output amplifiers together with the optimum choice of the PC board layout and decoupling components Figure 6 shows the relation 25 C 90 Vpp 15V Vin 20V PEAK TO PEAK 20k 50k 100k 200k 500k 1M INPUT FREQUENCY Hz Figure 6 Channel to Channel Is
16. on is useful in that Vour is the same polarity as allowing single supply operation However to retain specified linearity must be in the range 0 V to 2 5 V and the output buffered or loaded with a high impedance see Figure 10 Note that the input voltage is connected to the DAC OUT A and the output voltage is taken from the DAC A pin Vin OV TO 2 5V OUT LINEARITY ERROR LSB ERENTIAL LINEARITY 25 3 35 4 45 5 55 6 65 7 75 VinA Volts Figure 10 Typical AD7528 Performance in Single Supply Voltage Switching Mode K B T L C U Grades REV AD7528 MICROPROCESSOR INTERFACE ADDRESS P DECODE gt wg AD7528 DACB DATA BUS ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY A DECODED 7528 ADDR DAC A A 1 DECODED 7528 ADDR DAC B Figure 11 AD7528 Dual DAC to 6800 CPU Interface DRESS P DAC A DAC B DECODE UWS Se h Jie WR AD7528 DAC B ADDRESS BUS ADDR DATA BUS ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY DECODED 7528 ADDR DAC A A 1 DECODED 7528 ADDR DAC B NOTE 8085 INSTRUCTION SHLD STORE H amp L DIRECT CAN UPDATE BOTH DACs WITH DATA FROM H AND L REGISTERS Figure 12 AD7528 Dual DAC to 8085 CPU Interface PROGRAMMABLE WINDOW COMPARATOR TEST INPUT 0 TO Vper O Figure 13 Digitally Programmable Window Comparator Upper and Lower Limit Detector PRO
17. r Binary Operation 2 Quadrant Multiplication See Table 1 du Table II Bipolar Offset Binary Code Table DAC Latch Contents Analog Output MSB LSB DAC A or DAC B OVout A 127 11111111 e t INPUTS 10000001 10000000 0 1 01111111 is 127 00000001 Va 15g 128 OVorB 00000000 Va 15g Note 1 LSB 27 Vs is Vos 10V V AGND NOTES 1R1 R2 AND R3 R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED SEE TABLE Ill FOR RECOMMENDED VALUES ADJUST R1 FOR WITH CODE 10000000 IN DAC A LATCH ADJUST FOR Voy WITH CODE 10000000 IN DAC B LATCH 2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS Table III Recommended Trim Resistor R6 R7 AND R9 R10 Val Grad 3c1 C2 PHASE COMPENSATION 10pF 15pF MAY BE REQUIRED alues vs trade IF A1 A3 IS A HIGH SPEED AMPLIFIER Trim Figure 5 Dual DAC Bipolar Operation Resi t IAIS K B T LIC JU 4 Quadrant Multiplication See Table II ae J R1 R3 lk 500 200 R2 R4 330 150 82 REV B b AD7528 APPLICATIONS INFORMATION Application Hints To ensure system performance consistent with AD7528 specifi cations careful attention must be given to the following points 1 GENERAL GROUND MANAGEMENT AC or transient voltages between the AD7528 AGND and DGND can cause noise injection into the analog output The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7528 In more c
18. rcuit for DAC A is shown in DAC A DATA LATCHES AND DRIVERS Figure 1 Simplified Functional Circuit for DAC A Figure 1 An inverted R 2R ladder structure is used that is bi nary weighted currents are switched between the DAC output and AGND thus maintaining fixed currents in each ladder leg independent of switch state EQUIVALENT CIRCUIT ANALYSIS Figure 2 shows an approximate equivalent circuit for one of the AD7528 s D A converters in this case DAC A A similar equivalent circuit can be drawn for DAC B Note that AGND Pin 1 is common for both DAC A and DAC B The current source I gaxagg is composed of surface and junc tion leakages and as with most semiconductor devices approxi mately doubles every 10 The resistor Ro as shown in Figure 2 is the equivalent output resistance of the device which varies with input code excluding all 0s code from 0 8 to 2 R R is typically 11 Cour is the capacitance due to the N channel switches and varies from about 50 pF to 120 pF depending upon the digital input g Vngg N is the Thevenin equivalent voltage generator due to the reference input voltage Vggr and the transfer function of the R 2R ladder 9 Vngr AGND Figure 2 Equivalent Analog Output Circuit of DAC A CIRCUIT INFORMATION DIGITAL SECTION The input buffers are simple CMOS inverters designed such that when the AD7528 is operated with Vpp 5 V the buffer converts T TL input levels 2 4 V a
19. rt The con trol input DAC A DAC B selects which DAC can accept data from the input port Mode Selection _ Inputs CS and WR control the operating mode of the selected DAC See Mode Selection Table below Write Mode When CS and WR are both low the selected DAC is in the write mode The input data latches of the selected DAC are transpar ent and its analog output responds to activity on DBO DB7 Hold Mode The selected DAC latch retains the data which was present on DBO DB7 just prior to CS WR assuming a high state Both analog outputs remain at the values corresponding to the data in their respective latches Mode Selection Table DAC A DAC B cs WR DACA DACB L L L WRITE HOLD H L L HOLD WRITE X H X HOLD HOLD X X H HOLD HOLD L Low State H High State X Don t Care WRITE CYCLE TIMING DIAGRAM gt t Wu tcs 7 Vpp CHIP SELECT 0 gt tay it tas Vpp DAC A DAC B 0 twr Vpp WRITE 0 tps ton Vi DATA IN V NOTES 1 ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10 TO 90 OF Vpp Vpp 45V t t 20ns Vpp 15V ty t 40ns Vin Vit 2 TIMING MEASUREMENT REFERENCE LEVEL IS 2 CIRCUIT INFORMATION D A SECTION The AD7528 contains two identical 8 bit multiplying D A con verters DAC A and DAC B Each DAC consists of a highly stable thin film R 2R ladder and eight N channel current steer ing switches A simplified D A ci
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ANALOG DEVICES AD7528 English products handbook Rev B