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ANALOG DEVICES AD7549 English products handbook

1. AD7549 PIN FUNCTION DESCRIPTION 1 DB3 Data Bit 3 Data Bit 7 or Data Bit 11 MSB 2 DB2 Data Bit 2 Data Bit 6 or Data Bit 10 3 DB1 Data Bit 1 Data Bit 5 or Data Bit 9 4 DBO Data Bit 0 Data Bit 4 or Data Bit 8 5 UPD Updates DAC Registers from 4 bit input registers DAC A and DAC B both updated simultaneously 6 A2 Address line 2 7 Al Address line 1 8 AO Address line 0 9 CS Chip Select Input Active low 10 WR Write Input Active low l1 CLR Clear Input Active High Clears all registers 12 DGND Digital Ground 13 VREFB Voltage reference input to DAC B 14 Ress Feedback resistor of DAC B 15 lours Current output terminal of DAC B 16 AGND Analog ground 17 loura Current output terminal of DAC A 18 Resa Feedback resistor of DAC A 19 VREFA Voltage reference input to DAC A 20 VDD 15V supply input No data transfer No data transfer All registers cleared DAC A LOW NIBBLE REGISTER loaded from Data Bus DAC A MID NIBBLE REGISTER loaded from Data Bus DAC A HIGH NIBBLE REGISTER loaded from Data Bus DAC A Register loaded from Input Registers DAC B LOW NIBBLE REGISTER loaded from Data Bus DAC B MID NIBBLE REGISTER loaded from Data Bus DAC B HIGH NIBBLE REGISTER loaded from Data Bus DAC B Register loaded from Input Registers DAC A DAC B Registers updated simultaneously from Input Registers Table AD7549 Truth Table dodge edd g dsx NOTE X Don t Care REV A 5
2. ANALOG LC MOS DEVICES Dual 12 Bit j P Compatible DAC AD7949 FEATURES FUNCTIONAL BLOCK DIAGRAM Two Doubled Buffered 12 Bit DACs 4 Quadrant Multiplication Low Gain Error 3LSBs max DAC Ladder Resistance Matching 1 Space Saving Skinny DIP and Surface Mount Packages Latch Up Proof Extended Temperature Range Operation APPLICATIONS Programmable Filters Automatic Test Equipment Microcomputer Based Process Control Audio Systems DAC A REGISTER Programmable Power Supplies a Synchro Applications ai Ao 3 cs 9 GENERAL DESCRIPTION The AD7549 is a monolithic dual 12 bit current output D A converter It is packaged in both 0 3 wide 20 pin DIPs and in 20 terminal surface mount packages Both DACs provide four quadrant multiplication capabilities with a separate reference input and feedback resistor for each DAC The monolithic construction ensures excellent thermal tracking and gain error tracking between the two DACs The DACs in the AD7549 are each loaded in three 4 bit nibbles The control logic is designed for easy processor interfacing PRODUCT HIGHLIGHTS Input and DAC register loading is accomplished using address 1 Small package size the loading structure adopted for the lines AO Al A2 and CS WR lines A logic high level on the AD7549 enables two 12 Bit DACs to be packaged in either a CLR input clears all registers Both DACs may be simultaneously small 20 pin 0 3 DIP or in 20 termin
3. Typical value is 1 ppm C DAC A Register loaded with all 0 s DAC B Register loaded with all 0 s Typical Input Resistance 11k9 Vrera Vrers Input Resistance Match DIGITAL INPUTS Vin Input High Voltage Vr Input Low Voltage Iin Input Current 25 C T min tO T nax Cry Input Capacitance POWER SUPPLY Ipp AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance only and are not subject to test Voo 15V Viera Voes 10V loura loum AGND OV Output Amplifiers are AD644 except where stated Parameter Ta Tun Tmax a Test Conditions Comments Typically 1 Vin Vpp Output Current Settling Time To 0 01 of full scale range Int load 1009 Cexr 13pF DAC output measured from falling edge of WR Typical value of Settling Time is 0 8ps Digital to Analog Glitch Measured with Vrerra Vreg OV Touta louts load 1000 Cext L3pF Impulse DAC registers alternately loaded with all 0 s and all 1 s AC Feedthrough Vrera to louta Vrera gt Vrern 20V p p 10kHz sine wave Vrers to louts DAC registers loaded with all 0s Power Supply Rejection AGain AVpp AVpp 5 Output Capacitance Couta DAC A DACB loaded with all 0 s Couts Couta DAC A DACB loaded with all 1 s Coure Channel to Channel Isolation Vrera t0louts Vrera 20V p p 100kHz sine wave Vrerp 0V Vrere tolouta Vrere 20V p p 100kHz sine wave Vrera 0V Digital Crosstalk Measured for a Code Tran
4. applications with low bandwidth requirements it has extremely low offset 504V and in most applications will not require an offset trim The AD544L has a much wider bandwidth and higher slew rate and is recommended for multiplying and other applications requiring fast settling An offset trim on the AD544L may be necessary in some circuits Temperature Coefficients The gain temperature coefficient of the AD7549 has a maximum value of Sppm C and typical value of lppm C This corresponds to worst case gain shifts of 2LSBs and 0 4LSBs respectively over a 100 C temperature range When trim resistors R1 R3 and R2 R4 are used to adjust full scale range the temperature coefficient of R1 R3 and R2 R4 should also be taken into account High Frequency Considerations AD7549 output capacitance works in conjunction with the amplifier feedback resistance to add a pole to the open loop response This can cause ringing or oscillation Stability can be restored by adding a phase compen sation capacitor in parallel with the feedback resistor Feedthrough The dynamic performance of the AD7549 depends upon the gain and phase stability of the output amplifier together with the optimum choice of PC board layout and decoupling components A suggested printed circuit layout for Figure 2 is shown in Figure 4 which minimizes feedthrough from VREFA Vrers to the output in multiplying applications Vrere Vrera Vopn PIN 1 AD7549 y2 2 KEUNA PIN 8 AD644
5. 40 C to 85 C Vaera gt Vrere Pins 19 13 to AGND 25V Industrial A B Versions ee ee ee 40 C to 85 C Varpa Vrrer Pins 18 14 to AGND 25V Extended S T Versions 55 C to 125 C Digital Input Voltage Pins 1 11 Storage Temperature 65 C to 150 C toDGND HSV tisy A Temperance Soene Tse a mei Toone Vemiss Vprmi7 to DGND 0 3V Vpp 0 3V Stresses above those listed under Absolute Maximum Ratings may AGND toDGND 0 3V Vpp 0 3V cause permanent damage to the device This is a stress rating only and Power Dissipation Any Package functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not To 75 C 2 ee ee ee ee 450mW implied Exposure to absolute maximum rating conditions for extended Derates above 75 2 we ee ee 6mW C periods may affect device reliability CAUTION ESD electrostatic discharge sensitive device The digital control inputs are diode protect WARNING a ed however permanent damage may occur on unconnected devices subject to high energy electrostatic fields Unused devices must be stored in conductive foam or shunts The protective SRAT 4 foam should be discharged to the destination socket before devices are removed ESD SENSITIVE DEVICE REV A 3 AD7549 ORDERING GUIDE AD7549JN 40 Ct
6. AD7549 UNIPOLAR BINARY OPERATION 2 QUADRANT MULTIPLICATION Figure 2 shows the circuit diagram for unipolar binary operation With an ac input the circuit performs 2 quadrant multiplication The code table for Figure 2 is given in Table II Operational amplifiers Al and A2 can be in a single package i e AD644 or separate packages AD544 Capacitors C1 and C2 provide phase compensation to help prevent overshoot and ringing when high speed op amps are used For zero offset adjustment the appropriate DAC register is loaded with all O s and amplifier offset adjusted so that Voutra or Vours is at a minimum i e 1204 V Full scale trimming is accomplished by loading the DAC register with all 1 s and adjusting R1 R3 so that VouTa Vouts Vin 4095 4096 In fixed reference applications full scale can also be adjusted by omitung R1 R2 R3 R4 and trimming the reference voltage magnitude Figure 2 AD7549 Unipolar Binary Operation Binary Number in DAC Register Analog Output Voura or Vouts MSB 1111 LSB 1111 1111 1000 0000 0000 0000 0000 0001 0000 0000 0000 Table Il Unipolar Binary Code Table for Circuit of Figure 2 BIPOLAR OPERATION 4 QUADRANT MULTIPLICATION The recommended circuit diagram for bipolar operation is shown in Figure 3 Offset binary coding is used With the appropriate DAC register loaded to 1000 0000 0000 adjust R1 R3 so that Voura Vours OV Alt
7. Le o 3 EN UU o Piss Voute e o COPPER TRACKS ARE ON COMPONENT SIDE DGND OF PRINTED CIRCUIT BOARD Figure 4 Suggested Layout for AD7549 with AD644 Dual Op Amp REV A AD7549 8085A INTERFACE A typical interface circuit for the AD7549 and the 8085A micro processor is given in Figure 5 Only the bottom 4 bits of the microprocessor data bus are used The address decoder provides both the CS and UPD signals for the DAC Address lines AO Al A2 select one of six DAC Input Registers for accepting data In applications where simultaneous loading of the DACs is required then the UPD pin must be used to strobe both DAC registers Otherwise UPD may be tied high and address lines A0 A2 in conjunction with CS and WR signals will select each DAC register separately see Pin Function Description ADDRESS BUS A2 A0 ADDRESS eal cS DECODE A UPD AD7549 DBO DB3 LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 5 AD7549 8085A Interface AD7549 Z80 INTERFACE Figure 6 shows the AD7549 connected to the Z80 microprocessor The interface structure is similar to that for the 8085A ADDRESS BUS DECODE FROM SYSTEM RESET DATA BUS LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 6 AD7549 Z80 Interface ly 2 AD7549 AD7549 8048 INTERFACE The AD7549 can be interfaced to the 8048 single component microcomputer using the circuit of Figure 7 A minimum number of I O lines are needed Th
8. S PN 0 150 0 200 5 05 N 3 81 I 0 015 0 381 0 150 3 81 MIN 0 010 0 002 0 125 3 18 MIN jf opoa 10 204 oe or 0 254 0 051 o a gt je gt ja gt e 0 022 0 558 0 100 2 54 0 070 1 77 SEATING 0 020 0 51 0 100 2 54 0 05 1 27 0 074 0 356 BSC 0 045 1 15 PLANE 0 016 0 41 TYP TYP 20 Terminal Plastic Leaded Chip Carrier E 20 P 20A LCCC E Package l 0 042 1 07 0 042 1 07 ie 0 048 1 21 pa 0 056 1 42 0 358 9 09 EE 0 342 8 69 0 040 1 02 x x 45 REF 3 PLCS Ja _1 PIN 1 0 050 1 27 ee Y 0 028 0 71 0 042 1 07 0 350 8 89 BSC 0 022 0 56 0 048 1 21 re 356 9 04 ry Maas 7 37 E Top View 0 985 9 78 0 013 0 33 0 330 8 38 BOTTOM VIEW 0 393 10 92 0 021 0 53 0 050 1 27 0 026 0 66 ee BSC g 0 032 0 81 A O 5 _ 0 020 0 51 0 015 0 38 x 45 REF eT 9 04 0 025 0 63 0 385 9 78 0 025 0 64 4 0 395 EE 02 0 040 1 01 0 100 2 54 0 085 2 16 0 064 1 63 1 110 2 79 3 A aO EST T FI roa REV A
9. al surface mount updated using the UPD input packages The AD7549 is manufactured using the Linear Compatible 2 DAC to DAC matching since both DACs are fabricated on CMOS LC MOS process It is speed compatible with most the same chip precise matching and tracking is inherent microprocessors and accepts TTL 74HC or 5V CMOS logic This opens up applications which otherwise would not be level inputs considered i e Programmable Filters Audio Systems etc REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A which may result from its use No license is granted by implication or Tel 617 329 4700 Fax 617 326 8703 Twx 710 394 6577 otherwise under any patent or patent rights of Analog Devices Telex 924491 Cable ANALOG NORWOODMASS AD7549 SPECIFICATIONS Yargi ton i m 10 ACCURACY Resolution Relative Accuracy Differential Nonlinearity All grades guaranteed monotonic over temperature Full Scale Error Measured using internal Rpg and includes effects of leakage current and gain TC Gain Temperature Coefficient AGain ATemperature Output Leakage Current loura Pin 17 25 C T min tO T max Touts Pin 15 25 C T min tO T max REFERENCE INPUT Input Resistance Pin 19 Pin 13
10. e system is easily expanded by using extra port lines to provide Chip Selects for more AD7549 s The advantage of this interface lies in its simplicity In either single or multiple DAC applications both the software and chip select decoding are simplified over what would be required if the devices were memory mapped in a conventional manner The combination of 8048 system and AD7549 is particularly suitable for dedicated control applications By adding reference and output circuitry a complete control system can be configured with a minimum number of components AD7549 MC6809 INTERFACE Figure 8 is the interface circuit for the popular MC6809 8 bit microprocessor CS and UPD signals are decoded from the address for the simultaneous update facility while the WR pulse is provided by inverting the microprocessor clock E A0 A15 ADDRESS BUS MC6809 AD7549 ADDRESS as DECODE LINEAR CIRCUITRY OMITTED FOR CLARITY LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 7 AD7549 8048 Interface Figure 8 AD7549 MC6809 Interface OUTLINE DIMENSIONS Dimensions shown in inches and mm 20 Pin Plastic DIP N 20 20 Pin Cerdip Q 20 0 280 7 11 0 240 6 10 i PIN 1 Aeree LAH IDENTIFIER z 0 325 8 25 1 052 0 011 0 300 7 62 Le i 0 300 7 62 be a su As REF pea 0 925 23 50 es 1 52 al i E E cca 0 508 0 127 REF 0 210 0 015 0 38 0 195 4 95 0 175 4 45 amet 0 115 2 93 MAX NTN EN NN N
11. ernatively R1 R2 R3 R4 may be omitted and the ratios of R6 R7 R9 10 varied for Vouta Vours OV Full scale trimming can be accomplished by adjusting the amplitude of Vw or by varying the value of R5 R8 Resistors R5 R6 R7 R8 R9 R10 must be ratio matched to 0 01 When operating over a wide temperature range it is important that the resistors be of the same type so that their temperature coefficients match The code table for Figure 3 is given in Table III R5 20ki2 Figure 3 Bipolar Operation Offset Binary Coding Binary Number in DAC Register Analog Output Voura or Vouts MSB LSB 1111 1111 1111 2048 1000 0000 0001 Vm za 1000 0000 0000 jov 0111 1111 1111 Vin sg 0000 0000 0000 Table Ill Bipolar Code Table for Offset Binary Circuit of Figure 3 REV A AD7549 APPLICATION HINTS Output Offset CMOS D A converters in circuits such as Figures 2 and 3 exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the amplifier The maximum amplitude of this offset which adds to the D A converter nonlinearity depends on Vos where Vos is the amplifier input offset voltage To maintain mono tonic operation it is recommended that Vos be no greater than 25 x 10 Vrer over the temperature range of operation Suitable op amps are AD644L AD517L and ADS44L The AD517L is best suited for fixed reference
12. o 85 C AD7549KN 40 Cto 85 C AD7549JP 40 C to 85 C AD7549KP 40 Cto 85 C AD7549AQ 40 Cto 85 C AD7549BQ 40 Cto 85 C AD7549SQ 55 Cto 125 C AD7549TQ 55 Cto 125 C AD7549SE 55 Cto 125 C AD7549TE NOTES To order MIL STD 883 Class B process parts add 883B to part number Contact your local sales office for military data sheet 2E Leadless Ceramic Chip Carrier N Plastic DIP P Plastic Leaded Chip Carrier Q Cerdip TERMINOLOGY RELATIVE ACCURACY Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function It is measured after adjusting for zero error and full scale error and is normally expressed in Least Significant Bits or as a percentage of full scale reading DIFFERENTIAL NONLINEARITY Differential nonlinearity is the difference between the measured change and the ideal 1LSB change between any two adjacent codes A specified differential nonlinearity of 1LSB max over the operating temperature range ensures montonicity FULL SCALE ERROR Full scale error or gain error is a measure of the output error between an ideal DAC and the actual device output Full scale error is adjustable to zero OUTPUT CAPACITANCE This is the capacitance from Ioyra or lours to AGND DIGITAL TO ANALOG GLITCH IMPULSE The amount of charge injected into the analog output when
13. sition of all 0 s to ail 1 s Output Noise Voltage Density 10Hz 100kHz Measured between Rraa and outa or Repp and lours Harmonic Distortion Vm 6V rms lkHz NOTES Temperature range as follows J K Versions 40 C to 85 C A B Versions 40 C to 85 C S T Versions 55 C to 125 C 2At Vip 5V the device is fully functional with degraded performance Guaranteed by Product Assurance testing j Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND Specifications subject to change without notice 92 REV A AD7549 TIMING CHARACTERISTICS w 15V Vacs Vars 10 bam larg AGND OV unless otherwise stated Limit at Ta 55 C to 125 C Limit at Ta 40 C to 85 C Test Conditions Comments Address Valid to Write Setup Time Address Valid to Write Hold Time Data Setup Time Data Hold Time Chip Select or Update to Write Setup Time Chip Select or Update to Write Hold Time Write Pulse Width Clear Pulse Width Specifications subject to change without notice ty eer amp tz Ao A2 LL A TT MLLILLLILL N me 1 All INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10 TO 90 OF 5V t t 20ns 2 TIMING MEASUREMENT REFERENCE LEVEL IS M ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Operating Temperature Range Vpn Pin 20 to DGND 0 3V 17V Commercial J K Versions
14. the inputs change state is called Digital to Analog Glitch Impulse 55 Cto 125 C Temperature Relative Range Accuracy 1LSB 1 2LSB N 20 1LSB P 20A 1 2LSB P 20A 1LSB Q 20 1 2LSB Q 20 1LSB Q 20 1 2LSB Q 20 1LSB 1 2LSB This is normally specified as the area of the glitch in either pA secs or nV secs depending upon whether the glitch is measured as a current or voltage signal Digital charge injection is measured with VRrera and VREFB equal to AGND OUTPUT LEAKAGE CURRENT Output Leakage Current is current which appears at loura or Ioutrr with the DAC registers loaded to all zeros MULTIPLYING FEEDTHROUGH ERROR This is the error due to capacitive feedthrough from Vrera to Iouta OF Vrers to Iourg with the DAC registers loaded to all zeros CHANNEL TO CHANNEL ISOLATION Channel to Channel Isolation refers to the proportion of input signal from one DAC s reference input which appears at the output of the other DAC expressed as a ratio in dB DIGITAL CROSSTALK The ghtch impulse transferred to the output of one converter due to a change in digital input code to the other converter is defined as Digital Crosstalk and is specified in nV secs PIN CONFIGURATIONS DIP LCCC MSB DB3 g Saoaa amp DBZ Goa G gt gt 3 2 1 20 19 AD7549 TOP VIEW Not to Scale aout g 5 ts ty bead AD7549 TOP VIEW Not to Scale AD7549 TOP VIEW Not to Scale REV A

ANALOG DEVICES AD7549 English products handbook

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