ANALOG DEVICES AD8300 English products handbook
Contents
1. Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE Resolution N Note 1 12 Bits Relative Accuracy INL 2 1 2 2 LSB Differential Nonlinearity DNL Monotonic 1 t1 2 1 LSB Zero Scale Error Vzsk Data 000g 11 2 3 mV Full Scale Voltage Ves Data FFFy 2 039 2 0475 2 056 Volts Full Scale Tempco TCVzs Notes 3 4 16 ppm C ANALOG OUTPUT Output Current Source lour Data 800g AVour 5 LSB 5 mA Output Current Sink lour Data 8004 AVour 5 LSB 2 mA Load Regulation LazG Ry 200 Q to Data 800g 1 5 5 LSB Output Resistance to GND Rout Data 000g 30 Q Capacitive Load CL No Oscillation 500 pF LOGIC INPUTS Logic Input Low Voltage Vir 0 6 V Logic Input High Voltage Vin 2 1 V Input Leakage Current In 10 uA Input Capacitance Cir 10 pF INTERFACE TIMING SPECIFICATIONS Clock Width High tcu 40 ns Clock Width Low tcr 40 ns Load Pulsewidth trpyw 50 ns Data Setup tps 15 ns Data Hold toy 15 ns Clear Pulsewidth tctrw 40 ns Load Setup tipi 15 ns Load Hold tr po 40 ns Select tcss 40 ns Deselect tcsH 40 ns AC CHARACTERISTICS Voltage Output Settling Time ts To 0 2 of Full Scale 7 us To 1 LSB of Final Value 14 us Output Slew Rate SR Data 000g to FFFy to 000g 2 0 V us DAC Glitch 15 nV s Digital Feedthrough 15 nV s SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE DNL lt 1 LSB 2 7 5 5 V Positive Supply Current Ipp Vpp 3 V Vg 0 V Data 000g 1 2 1 7 mA Vpp 3 6 V Vin 2 3 V Data FF2. C Figure 18 Full Scale Output Tempco Histogram REV A AD8300 Table I Control Logic Truth Table cs CLK CLR LD Serial Shift Register Function DAC Register Function H X H H No Effect Latched L L H H No Effect Latched L H H H No Effect Latched L T H H Shift Register Data Advanced One Bit Latched T L H H No Effect Latched H X H l No Effect Updated with Current Shift Register Contents H X H L No Effect Transparent H X L X No Effect Loaded with All Zeros H X T H No Effect Latched All Zeros NOTES 1 T Positive Logic Transition Negative Logic Transition X Don t Care 2 Do not clock in serial data while LD is LOW 3 Data loads MSB first OPERATION The AD8300 is a complete ready to use 12 bit digital to analog converter Only one 3 V power supply is necessary for opera tion It contains a 12 bit laser trimmed digital to analog converter a curvature corrected bandgap reference rail to rail output op amp serial input register and DAC register The serial data interface consists of a serial data input SDI clock CLK and load strobe pins LD with an active low CS strobe In addition an asynchronous CLR pin will set all DAC register bits to zero causing the Voyr to become zero volts This func tion is useful for power on reset or system failure recovery to a known state D A CONVERTER SECTION The internal DAC is a 12 bit device with an output that swings from GND potential to 0
3. output schematic of the rail to rail amplifier with its N channel pull down FETs that will pull an output load directly to GND The output sourcing current is provided by a P channel pull up device that can source current to GND terminated loads Figure 21 Equivalent Analog Output Circuit The rail to rail output stage achieves the minimum operating supply voltage capability shown in Figure 2 The N channel output pull down MOSFET shown in Figure 21 has a 35 Q on resistance which sets the sink current capability near ground In addition to resistive load driving capability the amplifier has also been carefully designed and characterized for up to 500 pF capacitive load driving capability REFERENCE SECTION The internal curvature corrected bandgap voltage reference is laser trimmed for both initial accuracy and low temperature coefficient Figure 18 provides a histogram of total output per formance of full scale vs temperature which is dominated by the reference performance POWER SUPPLY The very low power consumption of the AD8300 is a direct result of a circuit design optimizing use of a CBCMOS process By using the low power characteristics of the CMOS for the logic and the low noise tight matching of the complementary bipolar transistors good analog accuracy is achieved For power consumption sensitive applications it is important to note that the internal power consumption of the AD8300 is strongly dependent on the actual l
4. 4 volt generated from the internal band gap voltage see Figure 20 It uses a laser trimmed segmented R 2R ladder which is switched by N channel MOSFETs The output voltage of the DAC has a constant resistance indepen dent of digital input code The DAC output is internally con nected to the rail to rail output op amp AMPLIFIER SECTION The internal DAC s output is buffered by a low power con sumption precision amplifier This low power amplifier contains a differential PNP pair input stage that provides low offset volt age and low noise as well as the ability to amplify the zero scale DAC output voltages The rail to rail amplifier is configured with a gain of approximately five in order to set the 2 0475 volt full scale output 0 5 mV LSB See Figure 20 for an equivalent circuit schematic of the analog section 12 BIT DAC i rin Figure 20 Equivalent AD8300 Schematic of Analog Portion The op amp has a 2 us typical settling time to 0 4 of full scale There are slight differences in settling time for negative slewing signals versus positive Also negative transition settling time to within the last 6 LSB of zero volts has an extended settling time See the oscilloscope photos in the typical performances section of this data sheet REV A OUTPUT SECTION The rail to rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply Figure 21 shows an equivalent
5. ANALOG DEVICES 3 Volt Serial Input Complete 12 Bit DAC AD8300 FEATURES Complete 12 Bit DAC No External Components Single 3 Volt Operation 0 5 mV Bit with 2 0475 V Full Scale 6 ps Output Voltage Settling Time Low Power 3 6 mW Compact SO 8 1 5 mm Height Package APPLICATIONS Portable Communications Digitally Controlled Calibration Servo Controls PC Peripherals GENERAL DESCRIPTION The AD8300 is a complete 12 bit voltage output digital to analog converter designed to operate from a single 3 volt sup ply Built using a CBCMOS process this monolithic DAC offers the user low cost and ease of use in single supply 3 volt systems Operation is guaranteed over the supply voltage range of 2 7 V to 5 5 V making this device ideal for battery oper ated applications The 2 0475 V full scale voltage output is laser trimmed to maintain accuracy over the operating temperature range of the device The binary input data format provides an easy to use one half millivolt per bit software programmability The voltage outputs are capable of sourcing 5 mA 3 0 N P MINIMUM SUPPLY VOLTAGE Volts N eo 0 01 0 1 1 0 10 OUTPUT LOAD CURRENT mA Figure 1 Minimum Supply Voltage vs Load REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements o
6. EQUENCY N e eo 1 0 1 2 3 4 5 6 TOTAL UNADJUSTED ERROR mV Figure 13 Total Unadjusted Error Histogram 1 5 1 0 0 5 Vour DRIFT mV o L a 1 0 p 1 5 55 35 15 5 25 45 65 85 105 125 TEMPERATURE C Figure 16 Full Scale Voltage Drift vs Temperature 15 NO LOAD 1 0 ss 300 UNITS NORMALIZED TO 25 C gt E 0 5 it Vpp 5V u c 0 a m 3 gt 0 5 Vpp 2 7V 1 0 1 5 755 35 15 5 25 45 65 85 105 125 TEMPERATURE C Figure 14 Zero Scale Voltage Drift vs Temperature NOISE DENSITY pV Hz 1 10 100 1k 10k 100k FREQUENCY Hz Figure 17 Output Voltage Noise Density vs Frequency N R 2 7V 35 UNITS N o o SCALE DATA FFFH NOMINAL VOLTAGE CHANGE mV ZERO SCALE DATA 0004 0 100 200 300 400 500 600 HOURS OF OPERATION AT 150 C Figure 19 Long Term Drift Accelerated by Burn In Ipp SUPPLY CURRENT mA FREQUENCY 3 0 1 0 60 20 20 60 100 140 TEMPERATURE C Figure 15 Supply Current vs Temperature 0 50 40 30 20 10 0 10 20 30 40 TEMPERATURE COEFFICIENT ppm
7. Fy 1 9 3 0 mA Power Dissipation Ppiss Vpp 3 V Vy 0 V Data 000g 3 6 5 1 mW Power Supply Sensitivity PSS AVpp 596 0 001 0 005 NOTES LSB 0 5 mV for 0 V to 2 0475 V output range The first two codes 0005 0015 are excluded from the linearity error measurement 3Includes internal voltage reference error These parameters are guaranteed by design and not subject to production testing gt All input control signals are specified with tg tp 2 ns 10 to 90 of 3 V and timed from a voltage level of 1 6 V The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground Some devices exhibit double the typical settling time in this 6 LSB region Specifications subject to change without notice REV A 5 V OPERATION Von 5 V 10 40 C lt T lt 85 C unless otherwise noted AD8300 Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE Resolution N Note 1 12 Bits Relative Accuracy INL 2 1 2 2 LSB Differential Nonlinearity DNL Monotonic 1 1 2 1 LSB Zero Scale Error Vzsk Data 000g 1 2 3 mV Full Scale Voltage Ves Data FFFy 2 039 2 0475 2 056 Volts Full Scale Tempco TCVegs Notes 3 4 16 ppm C ANALOG OUTPUT Output Current Source lour Data 800g AVour 5 LSB 5 mA Output Current Sink Iour Data 800p AVour 5 LSB 2 mA Load Regulation Lrec Ry 200 Q to Data 800g 1 5 5 LSB O
8. f patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM LR LD m 12 cs Q GND CLK P SERIAL SDI REGISTER AD8300 A double buffered serial data interface offers high speed three wire DSP and microcontroller compatible inputs using data in SDI clock CLK and load strobe LD pins A chip select CS pin simplifies connection of multiple DAC packages by enabling the clock input when active low Additionally a CLR input sets the output to zero scale at power on or upon user demand The AD8300 is specified over the extended industrial 40 C to 85 C temperature range AD8300s are available in plastic DIP and low profile 1 5 mm height SO 8 surface mount packages 1 00 0 75 Vpp 2 7V m TA 40 C 25 C 125 C 1 0 50 a Q 0 25 tc ul gt 0 00 c E X 0 25 zZ 1 0 50 1 2 HH 40 C 0 75 H BRE 25 C Il 125 C 1 00 0 1024 2048 3072 4096 DIGITAL INPUT CODE Decimal Figure 2 Linearity Error vs Digital Code and Temperature One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1999 AD8300 SPECIFICATIONS 3 V OPERATION Q Vi 5 V 10 40 C lt T x 85 C unless otherwise noted
9. his operation is shown in Table II APPLICATIONS INFORMATION See DAC8512 data sheet for additional application circuit ideas Table II Unipolar Code Table Hexadecimal Decimal Number in Number in Analog Output DAC Register DAC Register Voltage V FFF 4095 2 0475 801 2049 1 0245 800 2048 1 0240 EF 2047 1 0235 000 0 0 0000 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Lead SOIC SO 8 0 1968 5 00 0 1890 am 8 5 0 1574 4 00 L 0 2440 6 20 0 1497 3 80 0 2284 5 80 A piu 1 8 M E 0 0500 1 27 0 0196 0 80 BSC 0 0099 0 25 0 0688 1 75 0 0098 0 25 _ 0 0532 1 35 _ 0 0040 0 10 gt e 8 0 0192 0 49 T 0 0500 1 27 SEATING 0 0192 0 49 0 0098 0 25 0 0 0500 1 27 PLANE 0 0138 0 35 00075 0 19 0 0160 0 41 0 160 4 06 0 115 2 93 le 0 022 0 558 0 070 1 77 SEATING 0 014 0 356 0 045 1 15 PLANE 8 Lead Plastic DIP N 8 0 430 10 92 F 0 280 7 11 0 240 6 10 0 325 8 25 idis 0 300 7 62 0 381 s TYP 0 195 4 95 0 115 2 93 A 0 130 p 3 30 X MIN e 0 015 0 381 Ex 0 008 0 204 REV A C1968a 0 5 99 PRINTED IN U S A
10. l register without disturbing the present DAC output voltage value Data can only be loaded when the CS pin is active low After the new value is fully loaded in the serial input register it can be asynchronously transferred to the DAC register by strobing the LD pin The DAC register uses a level sensitive LD strobe that should be returned high before any new data is loaded into the serial input register At any time the contents of the DAC resister can be reset to zero by strobing the CLR pin which causes the DAC output voltage to go to zero volts All of the timing requirements are detailed in Figure 3 along with Table I Control Logic Truth Table All digital inputs are protected with a Zener type ESD protection structure Figure 22 that allows logic input voltages to exceed the Vpp supply voltage This feature can be useful if the user is loading one or more of the digital inputs with a 5 V CMOS logic input voltage level while operating the AD8300 on a 3 3 V power supply If this mode of interface is used make sure that the Vor of the 5 V CMOS meets the Vg input requirement of the AD8300 operating at 3 V See Figure 5 for the effect on digital logic input threshold versus operating Vpp supply voltage Figure 22 Equivalent Digital Input ESD Protection Unipolar Output Operation This is the basic mode of operation for the AD8300 The AD8300 has been designed to drive loads as low as 400 Q in parallel with 500 pF The code table for t
11. ogic input voltage levels present on the SDI CLK CS LD and CLR pins Since these inputs are standard CMOS logic structures they contribute static power dissipation dependent on the actual driving logic AD8300 Vou and Vo voltage levels Consequently for optimum dissipa tion use of CMOS logic versus TTL provides minimal dissipa tion in the static state A Vi 0 V on the logic input pins provides the lowest standby dissipation of 1 2 mA with a 3 3 V power supply As with any analog system it is recommended that the AD8300 power supply be bypassed on the same PC card that contains the chip Figure 8 shows the power supply rejection versus fre quency performance This should be taken into account when using higher frequency switched mode power supplies with ripple frequencies of 100 kHz and higher One advantage of the rail to rail output amplifiers used in the AD8300 is the wide range of usable supply voltage The part is fully specified and tested over temperature for operation from 2 7 V to 5 5 V If reduced linearity and source current capa bility near full scale can be tolerated operation of the AD8300 is possible down to 2 1 volts The minimum operating supply voltage versus load current plot in Figure 2 provides information for operation below Vpp 42 7 V TIMING AND CONTROL The AD8300 has a separate serial input register from the 12 bit DAC register that allows preloading of a new data value MSB first into the seria
12. onditions above those indicated in the operational LD operation Sa cee sme anaa mme g lorax Clock input positive edge clocks data into shift register 4 SDI Serial Data Input input data loads directly into the shift register MSB first ORDERING GUIDE 5 LD Load DAC register strobes active low Package Package Transfers shift register data to DAC register Model INL Temp Description Options See Truth Table I for operation Asynchro nous active low input iD ie sara ai e sd CLR Resets DAC register to zero condition Asynchronous active low input NOTES 7 GND Analog and Digital Ground XIND 40 C to 85 C The AD8300 contains 630 transistors The die size measures 72 mil x 65 mil 8 Vour DAC voltage output 2 0475 V full scale with 0 5 mV per bit An internal tempera ture stabilized reference maintains a fixed full scale voltage independent of time tem perature and power supply variations SDI ot Kp A p X oe A pr X ne A ps X pa A vs X pz A pt A voy CLK Figure 3 Timing Diagram CAUTION 1LSB ERROR BAND ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8300 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid
13. performance degradation or loss of functionality Ls ESD SENSITIVE DEVICE 4 REV A Typical Performance Characteristics AD8300 2 5 POSITIVE TA 40 TO 85 C CURRENT o lt LIMIT pes rmm 1 o aM Vout 1V DIV Wi Qs M NN E s E 800H Q 2 D TO 1 024V E E m 1 0 5 3 BELZIINEN 5 een tn pee ii eir e ipei o 0 5 NEGATIVE a CURRENT LIMIT 7 HORIZONTAL 1ps DIV 80 1 2 0 1 2 3 4 5 6 OUTPUT VOLTAGE Volts Vpp SUPPLY VOLTAGE Volts Figure 4 lour vs Vout Figure 5 Logic Input Threshold Figure 6 Detail Settling Time Voltage vs Vpp TIME 100ps DIV BI LOAD 5V DIV REB HORIZONTAL 20ps DIV BROADBAND NOISE 200pV DIV 0 10 100 1k 10k 100k 1M FREQUENCY Hz Figure 7 Broadband Noise Figure 8 Power Supply Rejection Figure 9 Large Signal Settling Time vs Frequency X BELTIAMNN a B LLLI gt y Mour zomviow n 3 TASAS Sanan DATA FFF CODE 800 TO 7FFH 0 5ps DIV 1 2 3 4 5 LOGIC VOLTAGE Volts Figure 10 Supply Current vs Logic Figure 11 Midscale Transition Figure 12 Digital Feedthrough vs Input Voltage Performance Time REV A b AD8300 60 TUE XINL ZS FS ss 300 UNITS 50 Vpp 43V TA 25 C FR
14. tling time specification does not apply for negative going transitions within the last 6 LSBs of ground Some devices exhibit double the typical settling time in this 6 LSB region Specifications subject to change without notice REV A 3 AD8300 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATIONS Noi te GND 2312 res LEPIDE IER EDS 0 3 V 7 V SO 8 Plastic DIP Logic Inputs to GND 00 cee eee 0 3 V 7 V Vena te GND 4 S esderRRERY4e ICE ERES 03 V Vig 0 3 V i Vop 1 e 8 Vour Iour Short Circuit to GND sees 50 mA E cs 2 AD8300 7 GND Package Power Dissipation T Max T 0y4 cLk 3 TOP VIEW 6 GER Thermal Resistance 0j4 spi 4 5 CD 8 Lead Plastic DIP Package N 8 103 C W 8 Lead SOIC Package SO 8 158 C W PIN DESCRIPTIONS Maximum Junction Temperature T Max 150 C R Operating Temperature Range E TET 40 C to 85 C Tos a Ceu Storage Temperature Range 65 C to 150 C 1 Vpp Positive power supply input Specified range Lead Temperature Soldering 10 secs 300 C of operation 2 7 V to 5 5 V Stresses above those listed under Absolute Maximum Ratings may cause perma 2 CS Chip Select active low input Disables shift nent damage to the device This is a stress rating only functional operation of the register loading when high Does not affect device at these or any other c
15. utput Resistance to GND Rour Data 000g 30 Q Capacitive Load Cy No Oscillation 500 pF LOGIC INPUTS Logic Input Low Voltage Vir 0 8 V Logic Input High Voltage Vin 2 4 V Input Leakage Current In 10 uA Input Capacitance C 10 pF INTERFACE TIMING SPECIFICATIONS Clock Width High tcu 30 ns Clock Width Low tcr 30 ns Load Pulsewidth tipyw 30 ns Data Setup tps 15 ns Data Hold tpu 15 ns Clear Pulsewidth tcrwR 30 ns Load Setup tipi 15 ns Load Hold trpa2 30 ns Select tcss 30 ns Deselect tcsH 30 ns AC CHARACTERISTICS Voltage Output Settling Time ts To 0 2 of Full Scale 6 us To 1 LSB of Final Value 13 us Output Slew Rate SR Data 000g to FFFy to 0004 2 2 V us DAC Glitch 15 nV s Digital Feedthrough 15 nV s SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE DNL lt 1 LSB 2 7 5 5 V Positive Supply Current Ipp Vpp 5 V Vy 0 V Data 000g 1 2 1 7 mA Vpp 5 5 V Vin 2 3 V Data FFFy 2 8 4 0 mA Power Dissipation Ppiss Vpp 5 V Vg 0 V Data 000g 6 5 1 mW Power Supply Sensitivity PSS AVpp 10 0 001 0 006 NOTES 11 LSB 0 5 mV for 0 V to 2 0475 V output range The first two codes 0005 0015 are excluded from the linearity error measurement Includes internal voltage reference error These parameters are guaranteed by design and not subject to production testing gt All input control signals are specified with tg tp 2 ns 10 to 9096 of 5 V and timed from a voltage level of 1 6 V The set
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ANALOG DEVICES AD8300 English products handbook