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ANALOG DEVICES DAC8043A English products handbook

1. TSSOP RU 8 Dimensions shown in millimeters 4 50 4 40 6 40 BSC 4 30 pwa i oo gt e 0 65 BSC 0 15 ane 1 20 oo GREED 4 palea Fe e gt je 0 30 0 0 75 COPLANARITY SEATING 0 20 pele 0 10 0 19 PLANE Sog 0 60 0 09 TE COMPLIANT TO JEDEC STANDARDS MO 153 AA REV B C00272 0 4 06 B
2. Bits Relative Accuracy INL 0 5 1 0 LSB max Differential Nonlinearity DNL All Grades Monotonic to 12 Bits 0 5 1 0 LSB max Gain Error GFsE Ta 25 C Data FFFy 1 0 2 0 LSB max Ta 40 C 85 C Data FFFy 2 0 2 0 LSB max Gain Tempco TCGrs Iour Pin Measured 5 5 ppm C max Output Leakage Current like Data 000p Iour Pin Measured 5 5 nA max Ta 40 C 85 C Data 000y Iour Pin Measured 25 25 nA max Zero Scale Error Izsz Data 0004 0 03 0 03 LSB max Ta 40 C 85 C Data 0004 0 15 0 15 LSB max REFERENCE INPUT Input Resistance Rrer Absolute Tempco lt 50 ppm C 7 15 7 15 kQ min max Input Capacitance CREF 5 5 pF typ ANALOG OUTPUT Output Capacitance Cour Data 0004 25 25 pF typ Data FFFy 30 30 pF typ DIGITAL INPUTS Digital Input Low Vin 0 8 0 8 V max Digital Input High Vin 2 4 2 4 V min Input Leakage Current I Viocic 0 V to 5 V 0 001 1 0 001 1 UA typ max Input Capacitance Cy Viocic 0 V 10 10 pF max INTERFACE TIMING Data Setup tps 10 10 ns min Data Hold tou 5 5 ns min Clock Width High tcu 25 25 ns min Clock Width Low teL 25 29 ns min Load Pulsewidth trp 25 25 ns min LSB CLK to LD DAC tasp 0 0 ns min AC CHARACTERISTICS Output Current Settling Time ts To 0 01 of Full Scale Ext Op Amp OP42 i 1 us max DAC Glitch Q Data 000y to FFFy to 000p Vrer 0 V 20 20 nVs max Feedthrough Voyr Vrzr FT Veer 20 V p p Data 0004 f 10 kHz 1 1 mV p p Total Harmonic Distortion THD Veer 6 V
3. Effect Updated with Current Shift Register Contents L t No Effect Latched All 12 Bits NOTES t positive logic transition as The DAC Register LD input is level sensitive Any time LD is logic low data in the serial register will directly control the switches in the R 2R DAC ladder Typical Performance Characteristics 35 50 SS 200 UNITS 30 pel Ta 40 C TO 85 C A Vpp 5V Vpp 5V 2 Vper 10V 40 Vper 10V 25 gt gt 2 20 30 W W 2 gt g 15 E E 20 10 10 5 0 0 1 0 0 5 0 0 0 5 1 0 0 1 2 TOTAL UNADJUSTED ERROR LSB FULL SCALE TEMPCO ppm C Figure 3 Total Unadjusted Error Histogram Figure 4 Full Scale Output Tempco Histogram _A REV B 0 5 2 a SUPPLY CURRENT Ipp MA 0 1 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 LOGIC INPUT VOLTAGE Volts Figure 5 Supply Current vs Logic Input Voltage 10 Vpp 5V Vioaic lt q 2 0 1 i a 0 01 0 001 55 35 15 5 25 45 65 85 105 125 TEMPERATURE C Figure 6 Supply Current vs Temperature 3500 3000 2500 ODE F55H lt q 2000 1 a gt 1500 CODE 800H 1000 CODE FFFH 500 i 1k 10k 100k 1M 10M 100M FREQUE
4. NOMINAL CHANGE IN VOLTAGE mV 0 100 200 300 400 500 600 HOURS OF OPERATION AT 150 C Figure 15 Long Term Drift Accelerated by Burn in 0 032 0 018 0 010 THD dB THD 0 0056 0 0032 FREQUENCY Hz Figure 16 THD vs Frequency REV B DAC8043A PARAMETER DEFINITIONS INTEGRAL NONLINEARITY INL This is the single most important DAC specification ADI mea sures INL as the maximum deviation of the analog output from the ideal from a straight line drawn between the end points It is expressed as a percent of full scale range or in terms of LSBs Refer to Analog Devices Data Reference Manual for additional digital to analog converter definitions INTERFACE LOGIC INFORMATION The DAC8043A has been designed for ease of operation The timing diagram Figure 2 illustrates the input register loading sequence Note that the most significant bit MSB is loaded first Once the 12 bit input register is full the data is transferred to the DAC register by taking LD momentarily low DIGITAL SECTION The DAC8043A s digital inputs SRI LD and CLK are TTL compatible The input voltage levels affect the amount of cur rent drawn from the supply peak supply current occurs as the digital input VIN passes through the transition region See the Supply Current vs Logic Input Voltage graph located in the typical perfor
5. QUADRANT MULTIPLYING Figure 20 shows a suggested circuit to achieve 4 quadrant mul tiplying operation The summing amplifier multiplies Vour by 2 and offsets the output with the reference voltage so that a midscale digital input code of 2048 places Voy at zero volts The negative full scale voltage will be Vggr when the DAC is loaded with all zeros The positive full scale output will be Vprr 1 LSB when the DAC is loaded with all ones Thus the digital coding is offset binary The voltage output transfer equation for various input data and reference or signal values follows Vour2 D 2048 1 x VREF where D is the decimal data loaded into the DAC register and Vprrr is the externally applied reference voltage source Precision resistors will be necessary to avoid ratio errors Other wise trimming will be required to achieve full accuracy specifica tions available from the DAC8043A device See the various Analog Devices Digital Potentiometer products for automated trimming solutions e g the AD5204 for low voltage applica tions or the AD7376 for high voltage applications DIGITAL INPUTS OMITTED FoR CLARITY VY TO Vrer Figure 20 Bipolar 4 Quadrant Operation OUTLINE DIMENSIONS 8 Lead Plastic Dual In Line Package PDIP N 8 Dimensions shown in inches and millimeters 0 400 10 16 0 365 9 27 e 0 355 9 02 3 S 0 280 7 11 0 250 6 35 0
6. rms Data FFF f 1 kHz 85 85 dB typ Output Noise Density en 10 Hz to 100 kHz Between Rpg and Ioyr 17 17 nV VHz max Multiplying Bandwidth BW 3 dB Vourt Vrer Vrer 100 mV rms Data FFFy 2 4 2 4 MHz typ SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE 4 5 5 5 4 5 5 5 V min max Positive Supply Current Ipp Viocic 0 V or Vpp 10 10 uA max Power Dissipation Pprss Viocic 0 V or Vpp 50 50 uW max Power Supply Sensitivity PSS AVpp 5 0 002 0 002 max NOTES Using internal feedback resistor Rpp see Figure 19 test circuit with Vpgr 10 V These parameters are guaranteed by design and not subject to production testing 3Calculated from worst case Rrrr Izse LSB Rrrr X Irra X 4096 Vpgr All input control signals are specified with tg tp 2 ns 10 to 90 of 5 V and timed from a voltage level of 1 6 V 5Calculation from e V4KTRB where K Boltzmann Constant K R Resistance Q T Resistor Temperature K B 1 Hz Bandwidth Specifications subject to change without notice REV B DAC8043A ABSOLUTE MAXIMUM RATINGS Vpp toGND 6265344 ud aatesidas taeda seeds 0 3 V 8 V VREF TOGN D semanan e maiae a de Bee ace 18 V R to GND ay esaigaadcasdee enaa ea AE a ES 18 V Logic Inputs to GND Vioutr to GND 0 3 V Vpp 0 3 V 0 3 V Vpp 0 3 V Iour Short Circuit to GND 0 0 eee eee 50 mA Package Power Dissipation T max T y4 Ther
7. 250 6 35 a 0 240 6 10 0 325 8 26 pin 177 SF L 0 310 7 87 0 100 2 54 9 300 7 62 29E 0 060 1 52 0 195 4 95 nat od 0 130 3 30 eee cots 0 115 2 92 f g 938 0 015 0 38 F 0 130 3 30 TE oe PLANE i 0 014 0 36 0 115 2 92 seating PLANE seat ee 0 022 0 56 M 0 005 0 13 0 430 10 93 0 018 0 46 MIN MAX 0 014 0 36 gt je 0 070 1 78 0 060 1 52 0 045 1 14 COMPLIANT TO JEDEC STANDARDS MS 001 BA CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS 8 Lead Standard Small Outline Package SOIC_N R 8 S Suffix Dimensions shown in millimeters and inches 5 00 0 1968 8 5 4 00 0 1574 6 20 0 2440 3 80 0 1497 J4 5 80 0 2284 y gt e 1 27 0 0500 0 50 0 0196 BSC 1 75 0 0688 0 25 0 0099 0 25 0 0098 1 35 0 0532 0 10 0 0040 _ _ IN a og 2 51 0 0201 1 27 0 0500 COPLANARITY 0 31 0 0122 0 25 0 0098 2T 0 0500 0 10 SEATING 0 25 0 0098 0 40 0 0157 PLANE 0 17 0 0067 COMPLIANT TO JEDEC STANDARDS MS 012 AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8 Lead Thin Shrink Small Outline Package
8. AC8043AFRU 1 0 40 C to 85 C 8 Lead TSSOP RU 8 DAC8043AFRU REEL 1 0 40 C to 85 C 8 Lead TSSOP RU 8 DAC8043AFRU REEL7 1 0 40 C to 85 C 8 Lead TSSOP RU 8 DAC8043AFRUZ 1 0 40 C to 85 C 8 Lead TSSOP RU 8 DAC8043AFRUZ REEL7 1 0 40 C to 85 C_ 8 Lead TSSOP RU 8 DAC8043AFS 1 0 40 C to 85 C 8 Lead SOIC_N R 8 DAC8043AFS REEL7 1 0 40 C to 85 C 8 Lead SOIC_N R 8 DAC8043AFSZ 1 0 40 C to 85 C 8 Lead SOIC_N R 8 DAC8043AFSZ REEL 1 0 40 C to 85 C 8 Lead SOIC_N R 8 The DAC8043A contains 346 transistors The die size measures 70 3 mm x 57 1 mm 4014 square mm The DAC8043A1ES DAC8043A1ESZ DAC8043A1FS and DAC8043A1FSZ have a rotated pinout Z Pb free part CAUTION PIN FUNCTION DESCRIPTIONS Name Function 1 7 Vrer DAC Reference Input Pin Establishes DAC full scale voltage Constant input resistance versus code 2 8 Rep Internal Matching Feedback Resistor Connect to external op amp output 3 1 Iour DAC Current Output full scale output 1 LSB less than reference input voltage Vpgp 4 2 GND Analog and Digital Ground 5 3 LD Load Strobe Level Sensitive Digital Input Transfers shift register data to DAC register while active low See truth table for operation 6 4 SRI 12 Bit Serial Register Input data loads directly into the shift register MSB first Extra leading bits are ignored 7 5 CL
9. ANALOG DEVICES 12 Bit Serial Input Multiplying D A Converter DAC8043A FEATURES Compact SOIC and TSSOP Packages True 12 Bit Accuracy 5 V Operation lt 10 pA Fast 3 Wire Serial Input Fast 1 ws Settling Time 2 4 MHz 4 Quadrant Multiply BW Pin for Pin Upgrade for DAC8043 Standard and Rotated Pinout APPLICATIONS Ideal for PLC Applications in Industrial Control Programmable Amplifiers and Attenuators Digitally Controlled Calibration and Filters Motion Control Systems GENERAL DESCRIPTION The DAC8043A is an improved high accuracy 12 bit multiply ing digital to analog converter in space saving 8 lead packages Featuring serial input double buffering and excellent analog performance the DAC8043A is ideal for applications where PC board space is at a premium Improved linearity and gain error performance permit reduced parts count through the elimina tion of trimming components Separate input clock and load DAC control lines allow full user control of data loading and analog output The circuit consists of a 12 bit serial in parallel out shift regis ter a 12 bit DAC register a 12 bit CMOS DAC and control logic Serial data is clocked into the input register on the rising edge of the CLOCK pulse When the new data word has been clocked in it is loaded into the DAC register with the LD input pin Data in the DAC register is converted to an output current by the D A converter Consuming only 10 uA from a single 5 V pow
10. K Clock Input positive edge clocks data into shift register 8 6 Vpp Positive Power Supply Input Specified range of operation 5 V 10 Note Pin numbers in parenthesis represent the rotated pinout of the DAC8043A1ES and DAC8043A1FS models DAC8043AE F PIN CONFIGURATIONS TOP VIEW lour L3 Not to Scale amp SRI enD 4 5 tb TSSOP 8 SOIC 8 PDIP 8 DAC8043A DAC8043A DAC8043A FRU ES FS EP FP DAC8043A1E AND DAC8043A1F PIN CONFIGURATION Rotated Pinout lour 1 Gnp 2 VREF TOP VIEW LD 3 Not to Scale Voo sRi 4 SOIC 8 DAC8043A1ES DAC8043A1FS ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the DAC8043A features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING eer ESD SENSITIVE DEVICE REV B 3 DAC8043A CLK LD DATA LOADED MSB D11 FIRST DAC REGISTER LOAD s CLK ter ton tio LD ts y OUT ERROR BAND zs T Figure 2 Timing Diagram Table I Control Logic Truth Table CLK LD Serial Shift Register Function DAC Register Function t H Shift Register Data Advanced One Bit Latched HorL L No
11. NCY Hz Figure 7 Supply Current vs Clock Frequency REV B DAC8043A 100 AVpp 5V 10 80 ao nol 1 ac 60 N a 40 20 1k 10k 100k 1M 10M FREQUENCY Hz Figure 8 Power Supply Rejection vs Frequency Vpp 5V Vrer 10V SUPERIMPOSED Ta 25 C 85 C DNL LSB SAL Nl ATL dd atad al o 512 1024 1536 2048 2560 3072 3584 4096 CODE Decimal Figure 9 Linearity Error vs Digital Code INL LSB 2000 1000 0 1000 2000 OPAMP OFFSET Vos pV Figure 10 Linearity Error vs External Op Amp Vos DAC8043A TIME 200ns DIV Figure 11 Midscale Transition Performance 5V DIV TIME 1s DIV Figure 12 Large Signal Settling Time ALL BITS ON 0 MSB B41 B10 12 a Bg i Bg 24 9 B7 S 36 gt p Be On Bs ji B 48 pE as B3 a lt r B2 60 qH By x A 5 LSB Bo 72 wall d 84 ALL BITS OFF 96 108 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 13 Reference Multiplying Bandwidth vs Fre quency and Code ATTENUATION dB 0 5 0 25 INL LSB 0 25 0 5 10 IVperf Volts Figure 14 Linearity Error vs Reference Voltage SAMPLE SIZE 50 CODE FFF CODE 000
12. er Iour or GND this yields a constant current in each ladder leg regardless of digital input code This constant current results in a constant input resis tance at Vger equal to R The Vpgr input may be driven by any REV B reference voltage or current ac or dc that is within the limits stated in the Absolute Maximum Ratings 10kQ 10kQ 10kQ Vrer O l l l BIT 1 MSB BIT2 BIT 3 DIGITAL INPUTS SWITCHES SHOWN FOR DIGITAL INPUTS HIGH THESE SWITCHES PERMANENTLY ON Figure 18 Simplified DAC Circuit The twelve output current steering NMOS FET switches are in series with each R 2R resistor BIT 12 LSB To further ensure accuracy across the full temperature range permanently ON MOS switches were included in series with the feedback resistor and the R 2R ladder s terminating resistor Figure 18 shows the location of the series switches During any testing of the resistor ladder or Reggppacxk such as incoming inspection Vpp must be present to turn ON these series switches DYNAMIC PERFORMANCE OUTPUT IMPEDANCE The DAC8043A s output resistance as in the case of the output capacitance varies with the digital input code This resistance looking back into the Ioyy terminal may be between 10 kQ the feedback resistor alone when all digital inputs are LOW and 7 5 KQ the feedback resistor in parallel with approximate 30 kQ of the R 2R ladder network resistance when any single bit logic is HIGH S
13. er supply the DAC8043A is the ideal low power small size high performance solution to many application problems The DAC8043A is specified over the extended industrial 40 C to 85 C temperature range DAC8043A is available in a PDIP package and the low profile 1 75 mm height SOIC 8 surface mount packages The DAC8043AFRU is available for ultra compact applications in a thin 1 1 mm TSSOP 8 package REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM DAC8043A Voo Reg ward O lout Ta 25 C 85 C 40 C Vpp 5V Vaer 10V 0 512 1024 1536 2048 2560 3072 3584 4096 CODE Figure 1 Integral Nonlinearity Error vs Code One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 461 3113 Analog Devices Inc 2006 DAC8043A SPECIFICATIONS ELECTRICAL CHARACTERISTICS Vo 5 V Vrer 10 V 40 C lt Ta lt 85 C unless otherwise noted Parameter Symbol Condition E Grade F Grade Unit STATIC PERFORMANCE Resolution N 12 12
14. mal Resistance za 8 Lead PDIP Package N 8 0 4 103 C W 8 Lead SOIC Package R 8 204 158 C W 8 Lead TSSOP Package RU 8 240 C W Maximum Junction Temperature Tj max 150 C Operating Temperature Range 40 C to 85 C Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 10 sec 300 C Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ORDERING GUIDE INL Temperature Package Package Model LSB Range Description Option DAC8043A1ES 0 5 40 C to 85 C_ 8 Lead SOIC_N R 8 DAC8043A1ESZ 0 5 40 C to 85 C 8 Lead SOIC_N R 8 DAC8043A 1FS 1 0 40 C to 85 C_ 8 Lead SOIC_N R 8 DAC8043A 1FSZ 1 0 40 C to 85 C 8 Lead SOIC_N R 8 DAC8043AEP 0 5 40 C to 85 C 8 Lead PDIP N 8 DAC8043AEPZ 0 5 40 C to 85 C 8 Lead PDIP N 8 DAC8043AES 05 40 C to 85 C 8 Lead SOIC_N R 8 DAC8043AESZ 0 5 40 C to 85 C_ 8 Lead SOIC_N R 8 DAC8043AFP 1 0 40 C to 85 C 8 Lead PDIP N 8 DAC8043AFPZ 1 0 40 C to 85 C 8 Lead PDIP N 8 D
15. mance characteristics curves Maintaining the digital input voltage levels as close as possible to the supplies VDD and GND minimizes supply current consumption The DAC8043A s digital inputs have been designed with ESD resis tance incorporated through careful layout and the inclusion of input protection circuitry Figure 17 shows the input protection diodes and series resistor this input structure is duplicated on each digital input High voltage static charges applied to the inputs are shunted to the supply and ground rails through for ward biased diodes These protection diodes were designed to clamp the inputs to well below dangerous levels during static discharge conditions VoD _ 5kO LD CLK SRI GND Figure 17 Digital Input Protection GENERAL CIRCUIT INFORMATION The DAC8043A is a 12 bit multiplying D A converter with a very low temperature coefficient It contains an R 2R resistor ladder network data input and control logic and two data registers The digital circuitry forms an interface in which serial data can be loaded under microprocessor control into a 12 bit shift regis ter and then transferred in parallel to the 12 bit DAC register The analog portion of the DAC8043A contains an inverted R 2R ladder network consisting of silicon chrome highly stable 50 ppm C thin film resistors and twelve pairs of NMOS current steering switches see Figure 18 These switches steer binarily weighted currents into eith
16. tatic accuracy and dynamic performance will be affected by these variations APPLICATIONS INFORMATION In most applications linearity depends upon the potential of the Iour and GND pins being at the same voltage potential The DAC is connected to an external precision op amp inverting input The external amplifiers noninverting input should be tied directly to ground without the usual bias current compensating resistor See Figures 19 and 20 The selected amplifier should have a low input bias current and low drift over temperature The amplifiers input offset voltage should be nulled to less than 200 microvolts less than 10 of 1 LSB All grounded pins should tie to a single common ground point to avoid ground loops The Vpp power supply should have a low noise level with adequate bypassing It is best to operate the DAC8043A from the analog power supply and grounds UNIPOLAR 2 QUADRANT MULTIPLYING The most straightforward application of the DAC8043A is in the 2 quadrant multiplying configuration shown in Figure 19 If the reference input signal is replaced with a fixed dc voltage DAC8043A reference the DAC output will provide a proportional dc voltage output according to the transfer equation Vour D 4096 x VREF where D is the decimal data loaded into the DAC register and Vper is the externally applied reference voltage source DIGITAL INPUTS OMITTED FOR CLARITY Figure 19 Unipolar 2 Quadrant Operation BIPOLAR 4

ANALOG DEVICES DAC8043A English products handbook

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