ANALOG DEVICES AD9744 English products handbook Rev B
Contents
1. 210MSPS LFCSP 90 2 4 1144 125 6 6dBFS LFCSP 85 165 5 5 LFCSP 80 12dBFS LFCSP 65MSPS M T 8 20Msps Bu XN 5 5 T X 7 lt a 165MSPS SN 65 l x 125MSPS LFCSP Y 60 0dBFS LFCSP 55 50 45 1 10 100 8 0 10 20 30 40 50 60 8 four MHz four MHz Figure 6 SFDR vs four 0 dBFS Figure 9 SFDR vs four 165 MSPS OdBFS LFCSP BFS LFCSP FS LFCSP a m a 5 a a o o 0 5 10 15 20 25 0 10 20 30 4 50 6 70 80 8 four MHz tour MHz Figure 7 SFDR vs four 65 MSPS Figure 10 SFDR vs four 210 MSPS 95 90 85 80 75 6dBFS 5 gt 70 124 5 a 65 o 60 OdBFS 55 50 45 E 0 5 10 15 20 25 30 35 40 45 5 0 5 10 15 20 25 3 8 four MHz four MHz Figure 8 SFDR vs four 125 MSPS Figure 11 SFDR vs four and lourrs 65 MSPS and 0 dBFS Rev B Page 9 of 32 09744 SFDR dBc SFDR dBc SNR dB 210MSPS LFCSP 210MSPS 25 20 15 10 5 0 Aour dBFS Figure 12 Single Tone SFDR vs Aour four 11 165MSPS LFCSP 65 5 5 125MSPS LFCSP 10MSP2. 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000000000 00000000000000 00000000000000 REV FAMILY Figure 47 SOIC Evaluation Board Assembly Primary Side nooooooooooooooofboo 00000000000000000000 15 EVALUATION BOARD TxDACO Figure 48 SOIC Evaluation Board Assembly Secondary Side Rev B Page 24 of 32 09744 CVDD DB13X DB12X DB11X DB10X 2 o tc o 9 DVDD m lt a gt la lt tc o tc AVDD u JP3 5 R3 R4 R15 R16 R17 R18 R19 R20 1000 1000 1000 21000 21000 21000 21000 21000 DB13X 1 RP3 a DB13 DB12X 2BP3 296 14 DB12 DB11X 3 RP3 DB10X m m z DB10 DB9X DB9 DB8X 20 u DB8 DB7X TRR DB7 DB6X 8 RP 220 9 DB6 DB5X 1 RP4 22 16 5 DB4X 2 RP4 22 15 DB4 DB1X 5 RP4 22 12 DB1 6 4 22011 aw CKEXTX 8 RP4 220 9 CKEXT R21 R24 R25 R26 R27 R28 1000 1000 1000 1000 1000 1000 Figure 49 LFCSP Evaluation Board Schematic Power Supply and Digital Inputs 02913 046 Rev 25 of 32 09744 AVDD Em DVDD m CVDD ves 0 1uF 0 1uF 0 1uF SLEEP o TP11 WHT R29 10kQ Der R11 DB6 500 DVDD L DB5 C13
3. DB13 DB12 DB11 DB10 DB9 DB8X DB8 DB7X DB7 DB6X DB6 DB5X DB5 DB4 DB3 DB2 DB1 DB0 CKEXT 02913 038 09744 AVDD CUT 14 16 17 UNDER DUT 10uF 0 1uF 6 16V DVDD did jc DVDR 29810 3 16V 0 1uF 0 1uF 1 R5 2 2 IOUTA R11 V 500 C13 V OPT 2 IOUT O 1 MODE 3 4 RESERVED 5 53 U1 IOUTA R6 AD9742 OUTB OPT y V 2 O 1uF O 1uF 1 12 C11 OPT V AVDD m AD B SLEEP 500 Y 1 3 S1 500 EXT 5 INT IOUTB REF V R3 2 2 10kQ NA B 5 3 5 JP11 8 Figure 42 SOIC Evaluation Board Output Signal Conditioning Rev B Page 21 of 32 09744 00 51620 Figure 43 SOIC Evaluation Board Primary Side 170 5160 Secondary Side Figure 44 SOIC Evaluation Board Rev Page 22 of 32 AD9744 50 61650 Ground Plane Figure 45 SOIC Evaluation Board v0 1620 Power Plane Figure 46 SOIC Evaluation Board Rev B Page 23 of 32 09744 90 51650 30 51650 zoooooooooooooooooooow 50000000000 00000000 00000000000000 00000000000000 00000000000000 00000000000000 00000000000000
4. 4 DB3 V DB2 TPi JP8 DB1 7 T WHT IOUT DB0 L 3 T1 4 po i AGND 3 4 5 CLKB Lez 6 V AVDD 11 1 1 CMODE 0 1uF JPS V DNP C12 7 R30 10 WHT CVDD R1 2ko V JP1 0 196 MODE Figure 50 LFCSP Evaluation Board Schematic Output Signal Conditioning CVDD C20 35 10uF 0 1uF 16V 02913 048 Figure 51 LFCSP Evaluation Board Schematic Clock Input Rev Page 26 of 32 02913 047 09744 02913 049 25 75 90 x re x zo ro 02913 050 Figure 53 LFCSP Evaluation Board Layout Secondary Side Rev B Page 27 of 32 09744 Figure 55 LFCSP Evaluation Board Layout Power Plane Rev B Page 28 of 32 02913 051 02913 052 AD9744 ANALOG DEVICES AD9744 LFCSP EVAL BOARD REV B no 85 02913 053 02913 054 Figure 57 LFCSP Evaluation Board Layout Assembly Secondary Side Rev B Page 29 of 32 09744 OUTLINE DIMENSIONS k 0 30 8 0 75 a gt lt 20 0 60 COPLANARITY 0 19 SEATING 0 09 0 45 0 10 TO JEDEC STANDARDS MO 153AE Figure 58 28 Lead Thin Shrink Small Out
5. Figure 18 SFDR vs Temperature 165 MSPS 0 dBFS Figure 21 Four Tone SFDR 39 01dBm 29 38000000MHz CHPWR 19 26dBm ACP UP 64 98dB ACP LOW 0 55dB ALT1 UP 66 26dB ALT1 LOW 64 23dB fcLock 78MSPS four 15 0MHz SFDR 79dBc AMPLITUDE OdBFS MAGNITUDE dBm CENTER 33 22 MHz 3 MHz SPAN 30 MHz FREQUENCY MHz FREQUENCY MHz Figure 19 Single Tone SFDR Figure 22 Two Carrier UMTS Spectrum 122 88 MSPS ACLR 64 dB LFCSP Package 20 fcLock 78MSPS RES BW 30kHz fout 15 0MHz 30 T foura 15 4MHz E SFDR 77dBc AMPLITUDE 0dBFS 50 60 5 80 lt 90 100 110 5 120 CENTER 10MHz SPAN 18MHz 8 LOWER UPPER 8 FREQUENCY MHz FREQ OFFSET REFBW dBm dBc 5 000MHz 3 840MHz 74 62 84 12 75 04 8454 8 Figure 20 Dual Tone SFDR Figure 23 Single Carrier UMTS Spectrum 61 44 MSPS ACLR 74 dB LFCSP Package Rev B Page 11 of 32 09744 O ACOM AD9744 AVDD URRENT SOURCE ARRAY VpirF VourA IOUTA ae SEGMENTED SWITCHES OUTA IOUTB f IOUTB FOR DB13 DB5 O Voute RLoAD 02913 022 DIGITAL DATA INPUTS DB13 DBO Figure 24 Simplified Block Dia
6. 40 to 85 28 Lead 300 Mil SOIC RW 28 AD9744ARRL 40 to 85 28 Lead 300 SOIC RW 28 AD9744ARZ 40 C to 85 C 28 Lead 300 Mil SOIC RW 28 AD9744ARZRL 40 to 85 28 Lead 300 SOIC RW 28 AD9744ARU 40 to 85 28 Lead TSSOP RU 28 AD9744ARURL7 40 C to 85 C 28 Lead TSSOP RU 28 AD9744ARUZ 40 to 85 28 Lead TSSOP RU 28 AD9744ARUZRL7 40 C to 85 C 28 Lead TSSOP RU 28 AD9744ACP 40 C to 85 C 32 Lead LFCSP CP 32 3 AD9744ACPRL7 40 C to 85 C 32 Lead LFCSP CP 32 3 AD9744ACPZ 40 to 85 32 Lead LFCSP CP 32 3 AD9744ACPZRL 7 40 to 85 32 Lead LFCSP 32 3 AD9744 EB Evaluation Board SOIC AD9744ACP PCB Evaluation Board LFCSP 17 Pb free part Rev B Page 31 of 32 09744 NOTES 2005 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners WWW ana 0 0 com 35 5 DEVICES Rev B Page 32 of 32
7. sss 13 Renumbered Figures 8 to Figure 26 sss 13 Added Figure 13 Added Figure 27 to Figure 35 seen 21 Updated Outline Dimensions eere 26 Rev B Page 2 of 32 SPECIFICATIONS 09744 DC SPECIFICATIONS Tmn to Tmax AVDD 3 3 V DVDD 3 3 V CLKVDD 3 3 V 20 mA unless otherwise noted Table 1 Parameter Min Typ Max Unit RESOLUTION 14 Bits DC ACCURACY Integral Linearity Error INL 5 0 8 5 LSB Differential Nonlinearity DNL 3 0 5 3 LSB ANALOG OUTPUT Offset Error 0 02 0 02 of FSR Gain Error Without Internal Reference 0 5 0 1 0 5 of FSR Gain Error With Internal Reference 0 5 0 1 0 5 of FSR Full Scale Output Current2 2 20 mA Output Compliance Range 1 1 25 V Output Resistance 100 kQ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1 14 1 20 1 26 V Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0 1 1 25 V Reference Input Resistance External Reference 7 kQ Small Signal Bandwidth 0 5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR C Gain Drift Without Internal Reference 50 ppm of FSR C Gain Drift With Internal Reference 100 ppm of FSR C Reference Voltage Drift 50 ppm C POWER SUPPLY Supply Voltages AVDD 2 7 3 3 3 6 V DVDD 2 7 3 3 3 6 V CLKVDD 2 7 3 3 3 6 V Analog Supply Current lavpp 33 36 mA Digital Supply Current 1 8 9 mA Clock Sup
8. 400 kHz Spacing fctock 78 MSPS four 15 0 MHz 18 2 MHz 0 dBFS Output 66 dBc 6 dBFS Output 68 dBc 12 dBFS Output 62 dBc 18 dBFS Output 61 dBc 1 Measured single ended into 50 load Output noise is measured with a full scale output set to 20 mA with no conversion activity It is a measure of the thermal noise only Noise spectral density is the average noise power normalized to a 1 Hz bandwidth with the DAC converting and producing an output tone DIGITAL SPECIFICATIONS Tmn to Tmax AVDD 3 3 V DVDD 3 3 V CLKVDD 3 3 V Iourrs 20 mA unless otherwise noted Table 3 Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage 2 1 3 V Logic 0 Voltage 0 0 9 V Logic 1 Current 10 10 Logic 0 Current 10 10 Input Capacitance 5 pF Input Setup Time ts 2 0 ns Input Hold Time tx 1 5 ns Latch Pulse Width 1 5 ns CLK INPUTS Input Voltage Range 0 3 V Common Mode Voltage 0 75 1 5 2 25 V Differential Voltage 0 5 1 5 V 1 Includes CLOCK pin on SOIC TSSOP packages and 1 pin on LFCSP package in single ended clock input mode 2 Applicable to and CLK inputs when configured for differential PECL clock input mode DB0 DB13 Figure 2 Timing Diagram Rev B Page 5 of 32 02913 002 09744 ABSOLUTE MAXIMUM RATINGS Table 4 Parameter With Respect to Min Max Unit AVDD ACOM 0 3 43 9 V DVDD DCOM 0 3 43 9 V CLKVDD CLKCOM 0 3 43 9 V ACOM DC
9. and or differential output Vpr of the AD9744 can be enhanced by selecting temperature tracking resistors for and due to their ratiometric relationship as shown in Equation 8 ANALOG OUTPUTS The complementary current outputs in each DAC IOUTA and IOUTB may be configured for single ended or differential operation and IOUTB can be converted into comple mentary single ended voltage outputs Voura and Vours via a load resistor Rroap as described in the DAC Transfer Function section by Equation 5 through Equation 8 The differential voltage Voir existing between Voura and Vours can also be converted to a single ended voltage via a transformer or differential amplifier configuration The ac performance of the AD9744 is optimum and specified using a differential trans former coupled output in which the voltage swing at IOUTA and IOUTB is limited to 0 5 V The distortion and noise performance of the AD9744 can be enhanced when it is configured for differential operation The common mode error sources of both and IOUTB can be significantly reduced by the common mode rejection of a transformer or differential amplifier These common mode error sources include even order distortion products and noise The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed wave form increases and or its amplitude decreases This is due to the first
10. are varied from nominal to minimum and maximum specified voltages Settling Time The time required for the output to reach and remain within a specified error band about its final value measured from the start of the output transition Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse It is specified as the net area of the glitch in pV s Spurious Free Dynamic Range The difference in dB between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth Total Harmonic Distortion THD THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal It is expressed as a percentage or in decibels dB Multitone Power Ratio The spurious free dynamic range containing multiple carrier tones of equal amplitude It is measured as the difference between the rms amplitude of a carrier tone to the peak spuri ous signal in the region of a removed tone O ACOM MINI CIRCUITS T1 1T RHODE amp SCHWARZ IOUTA A FSEA30 IOUTB SPECTRUM O 7 ANALYZER AWG2021 CLOCK RETIMED SO THAT THE DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50 DUTY CYCLE CLOCK 02913 005 Figure 5 Basic AC Characterization Test Set Up SOIC TSSOP Packages Rev Page 8 of 32 09744 TYPICAL PERFORMANCE CHARACTERISTICS
11. clock edge This becomes more important as the sample rate increases Figure 30 shows the relationship of SFDR to clock placement with different sample rates Note that at the lower sample rates more tolerance is allowed in clock place ment while at higher rates more care must be taken 02913 027 Figure 30 SFDR vs Clock Placement 20 MHz and 50 MHz Sleep Mode Operation The AD9744 has a power down function that turns off the out put current and reduces the supply current to less than 6 mA over the specified supply range of 2 7 V to 3 6 V and tempera ture range This mode can be activated by applying a logic level 1 to the SLEEP pin The SLEEP pin logic threshold is equal to 0 5 AVDD This digital input also contains an active pull down circuit that ensures that the AD9744 remains enabled if this input is left disconnected The AD9744 takes less than 50 ns to power down and approximately 5 us to power back up POWER DISSIPATION The power dissipation of the AD9744 is dependent on sev eral factors that include Thepower supply voltages AVDD CLKVDD and DVDD e The full scale current output Iourrs e The update rate e reconstructed digital input waveform The power dissipation is directly proportional to the analog supply current and the digital supply current Ipvpp is directly proportional to lourrs as shown in Figure 31 and is in
12. sake ignoring harmonics all of this noise is con centrated at 250 kHz To calculate how much of this undesired noise will appear as current noise superimposed on the full scale current Iourrs one must determine the in dB using Figure 39 at 250 kHz To calculate the PSRR for a given Rioap such that the units of PSRR are converted from A V to V V adjust the curve in Figure 39 by the scaling factor 20 log Rioap For instance if Rroap is 50 the PSRR is reduced by 34 dB that is PSRR of the DAC at 250 kHz which is 85 dB in Figure 39 becomes 51 dB Vovr V n AD9744 Proper grounding and decoupling should be a primary objec tive in any high speed high resolution system The AD9744 features separate analog and digital supplies and ground pins to optimize the management of analog and digital ground currents in a system In general AVDD the analog supply should be decoupled to ACOM the analog common as close to the chip as physically possible Similarly DVDD the digital supply should be decoupled to DCOM as close to the chip as physically possible For those applications that require a single 3 3 V supply for both the analog and digital supplies a clean analog supply may be generated using the circuit shown in Figure 40 The circuit con sists of a differential LC filter with separate power supply and return lines Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors F
13. ANALOQ DEVICES 14 Bit 210 MSPS TxDAC D A Converter 09744 FEATURES High performance member of pin compatible TxDAC product family Excellent spurious free dynamic range performance SFDR to Nyquist 83 dBc 5 MHz output 80 dBc 10 MHz output 73 dBc 20 MHz output SNR 5 MHz output 125 MSPS 77 dB Twos complement or straight binary data format Differential current outputs 2 to 20 Power dissipation 135 mW 3 3 V Power down mode 15 mW 3 3 V On chip 1 2 V reference CMOS compatible digital interface 28 lead SOIC 28 lead TSSOP and 32 lead LFCSP packages Edge triggered latches GENERAL DESCRIPTION The AD9744 is 14 bit resolution wideband third generation member of the TxDAC series of high performance low power CMOS digital to analog converters DACs The TxDAC fam consisting of pin compatible 8 10 12 and 14 bit DACs is specifically optimized for the transmit signal path of commu nication systems All ofthe devices share the same interface options small outline package and pinout providing an up ward or downward component selection path based on per formance resolution and cost The AD9744 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS The AD97445 low power dissipation makes it well suited for portable and low power applications Its power dissipation can be further reduced to a mere 60 mW with a slight degradation in performance by lowerin
14. C high slewing output from overloading the op amps input AD9744 IOUTA 02913 032 Figure 35 DC Differential Coupling Using an Op Amp The common mode rejection of this configuration is typically determined by the resistor matching In this circuit the differ ential op amp circuit using the AD8047 is configured to provide some additional signal gain The op amp must operate off a dual supply since its output is approximately 1 V A high speed am plifier capable of preserving the differential performance of the AD9744 while meeting other system level objectives such as cost or power should be selected The op amps differential gain gain setting resistor values and full scale output swing Rev B Page 17 of 32 09744 capabilities should all be considered when optimizing this circuit The differential circuit shown in Figure 36 provides the neces sary level shifting required in a single supply system In this case AVDD which is the positive analog supply for both the AD9744 and the op amp is also used to level shift the differen tial output of the AD9744 to midsupply that is AVDD 2 The AD8041 is a suitable amp for this application 5000 AD9744 2250 IOUTA OAVDD 02913 033 Figure 36 Single Supply DC Differential Coupled Circuit SINGLE ENDED UNBUFFERED VOLTAGE OUTPUT Figure 37 shows the AD9744 configured to provide a unipolar output range of approximately 0 V to 0 5 V f
15. EFIO is to be used any where else in the circuit an external buffer amplifier with an 09744 input bias current less than 100 nA should be used An ex ample of the use of the internal reference is shown in Figure 26 AVDD 84uA i REFIO 02913 057 REFLO Figure 25 Equivalent Circuit of Internal Reference 3 3V OPTIONAL EXTERNAL REF BUFFER CURRENT SOURCE ARRAY 02913 023 Figure 26 Internal Reference Configuration An external reference can be applied to REFIO as shown in Figure 27 The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control Note that the 0 1 uF compensation capacitor is not required since the internal refer ence is overridden and the relatively high input impedance of REFIO minimizes any loading of the external reference Vrerio Rset REFERENCE AD9744 CONTROL AMPLIFIER 02913 024 Figure 27 External Reference Configuration REFERENCE CONTROL AMPLIFIER The AD9744 contains a control amplifier that is used to regulate the full scale output current Iourrs The control amplifier is configured as a V I converter as shown in Figure 26 so that its current output Irer is determined by the ratio of the and an external resistor Rser as stated in Equation 4 Irer is copied to the segmented current sources with the proper scale factor to set Iourrs as s
16. ERRITE BEADS TTL CMOS O AVDD LOGIC CIRCUITS 02913 037 3 3V POWER SUPPLY Figure 40 Differential LC Filter for Single 3 3 V Applications Rev Page 19 of 32 09744 EVALUATION BOARD GENERAL DESCRIPTION The TxDAC family evaluation boards allow for easy setup and testing of any product in the SOIC and LFCSP pack ages Careful attention to layout and circuit design combined with a prototyping area allows the user to evaluate the AD9744 easily and effectively in any application where high resolution high speed conversion is required This board allows the user the flexibility to operate the AD9744 in various configurations Possible output configurations in clude transformer coupled resistor terminated and single and differential outputs The digital inputs are designed to be driven from various word generators with the on board option to add a resistor network for proper load termination Provisions are also made to operate the AD9744 with either the internal or external reference or to exercise the power down feature DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB13X DB12X DB11X DB10X DB9X JP3 DB4X LL CKEXTX DEAE DB2X DB1X DB0X T E RIBBON CKEXTX RED 3 RP4 22014 4 RP4 220 13 6 RP4 22011 7 RP4 22010 a 8 RP4 2209 Figure 41 SOIC Evaluation Board Power Supply and Digital Inputs Rev B Page 20 of 32
17. OM 0 3 40 3 V ACOM CLKCOM 0 3 40 3 V DCOM CLKCOM 0 3 40 3 V AVDD DVDD 3 9 43 9 AVDD CLKVDD 3 9 3 9 V DVDD CLKVDD 3 9 3 9 V CLOCK SLEEP DCOM 0 3 DVDD 0 3 V Digital Inputs MODE DCOM 0 3 DVDD 0 3 V IOUTA IOUTB ACOM 1 0 AVDD 0 3 V REFIO REFLO FS ADJ ACOM 0 3 AVDD 0 3 V CLK CLK CMODE CLKCOM 0 3 CLKVDD 0 3 V Junction Temperature 150 C Storage Temperature 65 150 C Lead Temperature 10 sec 300 Be Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum ratings for extended periods may effect device reliability THERMAL CHARACTERISTICS Thermal Resistance 28 Lead 300 Mil SOIC 55 9 C W 28 Lead TSSOP 67 7 C W 32 Lead LFCSP 32 5 C W Thermal impedance measurements were taken on 4 layer board in still air in accordance with EIA JESD51 7 ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprie lt tary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic Spr Aat dischar
18. Renumbered Sequentially 11 Changes to Functional Description 13 Changes to Reference Operation 13 Added Figure 25 Renumbered Sequentially 13 Changes to Digital Inputs Section ses 15 Changes to Figure 31 and Figure 32 sss 16 Updated Outline Dimensions seen 30 Changes to Ordering Guide 5 03 Rev 0 to Rev A Added 32 Lead LFCSP Package Universal Edit to Features a eti RR REN RE 1 Edits to Product Highlights sse 1 Edits to DC Specifications sse 2 Edits to Dynamic Specifications sss 3 Edits to Digital Specifications sse 4 Edits to Absolute Maximum Ratings eee 5 Edits to Thermal Characteristics sees 5 Editsto Ordering asua t 5 Edits to Pin Configuration seen 6 Edits to Pin Function 2222 6 Figure u peter ies 7 Replaced 8 Editsto Figure eite 10 Edits to Functional Description sse 10 Added Clock Input Section sia Added Figute 7 etae RR Sette Edits to DAC Timing Section Edits to Sleep Mode Operation Section sss 13 Edits to Power Dissipation Section
19. S LFCSP 25 20 15 10 5 0 Aour dBFS Figure 13 Single Tone SFDR vs Aour four 5 ourFS 20mA LFCSP lourFS 20 lourFS 10 5mA LFCSP 0 30 60 90 120 150 180 210 fcLock MSPS Figure 14 SNR vs faock and lourrs four 5 MHz and 0 dBFS 95 90 a 65MSPS 8 3 10 3 165MSPS 22 6 24 6 N m 210MSPS 29 31 SFDR dBc o a 210MSPS 29 31 1 LFCSP 25MSPS 16 9 18 9 e a 02913 013 1 5 20 15 10 5 Aour dBFS Figure 15 Dual Tone IMD vs Aour four 7 1 0 ERROR LSB o 1 a 02913 008 i M n 4096 8192 12288 Figure 16 Typical INL 16384 0 2 ERROR LSB b gt N 5 5 1 EN eo 02913 011 Rev 10 of 32 4096 8192 12288 CODE Figure 17 Typical DNL 16384 02913 015 02913 018 02913 014 SFDR dBc MAGNITUDE dBm MAGNITUDE dBm 09744 95 fcLock 78MSPS 4 2 four 15 0 2 four 15 4MHz fours 15 8MHz 80 foura 16 2MHz SFDR 75dBc 75 m AMPLITUDE OdBFS 19MHz a a 70 5 65 34MHz 60 T 49MHz 55 50 45 8 z 40 20 0 20 40 60 80 8 8 TEMPERATURE FREQUENCY MHz
20. amily which offers excellent INL and DNL performance 2 Data input supports twos complement or straight binary data coding 3 High speed single ended CMOS clock input supports 210 MSPS conversion rate 4 Low power Complete CMOS DAC function operates on 135 mW from a 2 7 V to 3 6 V single supply The DAC full scale current can be reduced for lower power operation and a sleep mode is provided for low power idle periods 5 On chip voltage reference The AD9744 includes a 1 2 V temperature compensated band gap voltage reference 6 Industry standard 28 lead SOIC 28 lead TSSOP and 32 lead LFCSP packages Protected by U S Patent Numbers 5568145 5689257 and 5703519 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved 09744 TABLE OF CONTENTS Specifications reei se a r 3 5 u u a ette e is 3 Dynamic Specifications seen 4 Digital Specifications seen 5 Absolute Maximum Ratings eerte 6 Thermal Characteristics eene 6 ESD Caution iiie ERES 6 Pin Configurations and Function Descriptions 7 Terminology nt tie haqa is 8 Typical Performance Characteristics sse 9 F nctionab Description a eter eet tenes 13 Reference Operation au a unan tet teer iden 13 Re
21. ce is typically achieved when the input data transitions on the falling edge of a 50 duty cycle clock AD9744 CLOCK INPUT SOIC TSSOP Packages The 28 lead package options have a single ended clock input CLOCK that must be driven to rail to rail CMOS levels The quality of the DAC output is directly related to the clock quality and jitter 15 key concern Any noise or jitter in the clock will translate directly into the DAC output Optimal performance will be achieved if the CLOCK input has a sharp rising edge since the DAC latches are positive edge triggered LFCSP Package A configurable clock input is available in the LFCSP package which allows for one single ended and two differential modes The mode selection is controlled by the CMODE input as summarized in Table 6 Connecting CMODE to CLKCOM selects the single ended clock input In this mode the CLK input is driven with rail to rail swings and the CLK input is left floating If CMODE is connected to CLKVDD the differen tial receiver mode is selected In this mode both inputs are high impedance The final mode is selected by floating CMODE This mode is also differential but internal terminations for positive emitter coupled logic PECL are activated There is no significant performance difference among any of the three clock input modes Table 6 Clock Mode Selection CMODE Pin Clock Input Mode CLKCOM Single Ended CLKVDD Differential Float PECL The s
22. ference Control Amplifier 13 DAC Transfer Function 14 Analog 14 Digital eene tete 15 Clock IPUN ERUDITI 15 DAC 16 Power DissIpatI n 16 Applying the 9744 2 1112 17 Differential Coupling Using a Transformer 17 Differential Coupling Using an Op 17 Single Ended Unbuffered Voltage Output 18 Single Ended Buffered Voltage Output Configuration 18 Power and Grounding Considerations Power Supply oret e UR ERRARE I ARRIUS 18 Evaluation Board seen 20 General Description cce i 20 Outline DIMENSIONS 30 Ordering 31 REVISION HISTORY 4 05 Rev to Rev Updated Form t Universal Changes to General Description sse 1 Changes to Product Highlights s Changes to DC Specifications 3 Changes to Dynamic Specifications z4 Changes to Pin Function Description aaa 7 Changes to Figure 6 and Figure 9 sse 9 Inserted New Figure 10 Renumbered Sequentially 9 Changes to Figure 12 Figure 13 Figure 14 and Figure 15 10 Changes to Figure 22 Caption 11 Inserted New Figure 23
23. g only MINI CIRCUITS IOUTA AD9744 OPTIONAL 02913 031 Figure 34 Differential Output Using Transformer The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB The complementary voltages ap pearing at IOUTA and IOUTB that is Voura and Vours swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9744 A differ ential resistor may be inserted in applications where the output of the transformer is connected to the load Rioap via passive reconstruction filter or cable Rowe is determined by the transformer s impedance ratio and provides the proper source termination that results in alow VSWR Note that approxi mately half the signal power will be dissipated across DIFFERENTIAL COUPLING USING AN OP AMP An op amp can also be used to perform a differential to single ended conversion as shown in Figure 35 The AD9744 is configured with two equal load resistors of 25 The differential voltage developed across and IOUTB is converted to a single ended signal via the differential op amp configuration An optional capacitor can be installed across IOUTA and IOUTB forming a real pole in a low pass filter The addition of this capacitor also enhances the op amps distortion performance by preventing the DA
24. g the full scale current output Also a power down mode reduces the standby power dissipation to approximately 15 mW A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance Rev B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners APPLICATIONS Wideband communication transmit channel Direct IFs Base stations Wireless local loops Digital radio links Direct digital synthesis DDS Instrumentation FUNCTIONAL BLOCK DIAGRAM REFLO 150 AVDD ACOM CURRENT AD9744 SES ADJ SOURCE e Lama LSB O mcus swmcwes ioute z o LATCHES 02913 001 Figure 1 Edge triggered input latches and a 1 2 V temperature compen sated band gap reference have been integrated to provide a complete monolithic DAC solution The digital inputs support 3 V CMOS logic families PRODUCT HIGHLIGHTS 1 The AD9744 is the 14 bit member of the pin compatible TxDAC f
25. ges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Rev B Page 6 of 32 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS MSB DB13 DB12 DB11 DB10 DB9 DB8 AD9744 TOP VIEW DB7 7 to Scale 22 DB6 DB5 DB4 DB3 DB2 DB1 LSB DB0 NC NO CONNECT 02913 003 Figure 3 28 Lead SOIC and TSSOP Table 5 Pin Function Descriptions 30 DB10 29 DB11 28 DB12 27 DB13 MSB 26 DCOM 25 SLEEP tn Ar c pBz 1 Ox pn 24 FS ADJ DB6 2 INDICATOR 23 REFIO DVDD 3 22 ACOM AD9744 21 20 IOUTB 19 ACOM 18 AVDD 17 AVDD DB54 DB45 DB36 DB27 DB18 TOP VIEW Not to Scale LSB DB0 9 DCOM 10 CLKVDD 11 CLK 12 CLK 13 NC NO CONNECT Figure 4 32 Lead LFCSP 02913 004 09744 SOIC TSSOP LFCSP Pin No Pin No Mnemonic Description 1 27 DB13 Most Significant Data Bit MSB 2to 13 28 to 32 DB12 to Data Bits 12 to 1 1 2 4to8 DB1 14 9 DB0 Least Significant Data Bit LSB 15 25 SLEEP Power Down Control Input Active high Contains active pull down circuit it may be left unterminated if not used 16 N A REFLO Reference Ground when Internal 1 2 V Reference Used Connect to ACOM for both internal and external reference operation modes 17 23 REFIO Reference Input Output Serves as reference input when using external reference Serves as 1 2 V reference output whe
26. gram SOIC TSSOP Packages Rev B Page 12 of 32 FUNCTIONAL DESCRIPTION Figure 24 shows a simplified block diagram of the AD9744 The AD9744 consists of a DAC digital control logic and full scale output current control The DAC contains a PMOS current source array capable of providing up to 20 mA of full scale cur rent Iourrs The array is divided into 31 equal currents that make up the five most significant bits MSBs The next four bits or middle bits consist of 15 equal current sources whose value is 1 16th of an MSB current source The remaining LSBs are binary weighted fractions of the middle bits current sources Implementing the middle and lower bits with current sources instead of an R 2R ladder enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DACS high output impedance that is gt 100 All of these current sources are switched to one or the other of the two output nodes that is IOUTA or IOUTB via PMOS differential current switches The switches are based on the architecture that was pioneered in the AD9764 family with further refinements to reduce distortion contributed by the switching transient This switch architecture also reduces vari ous timing errors and provides matching complementary drive signals to the inputs of the differential current switches The analog and digital sections of the AD9744 have separate power supply inputs that is AVDD and DVDD tha
27. he reliability of the AD9744 The positive output compliance range is slightly dependent on the full scale output current Iourrs It degrades slightly from its nominal 1 2 V for an 20 mA to 1 V for an Iourrs 2 mA The optimum distortion performance for a single ended or differential output is achieved when the maximum full scale signal at IOUTA and IOUTB does not exceed 0 5 V DIGITAL INPUTS The AD9744 digital section consists of 14 input bit channels and a clock input The 14 bit parallel data inputs follow stan dard positive binary coding where DB13 is the most significant bit MSB and is the least significant bit LSB produces a full scale output current when all data bits are at Logic 1 IOUTB produces a complementary output with the full scale current split between the two outputs as a function of the input code DVDD DIGITAL INPUT 02913 025 Figure 28 Equivalent Digital Input The digital interface is implemented using an edge triggered master slave latch The DAC output updates on the rising edge of the clock and is designed to support a clock rate as high as 210 MSPS The clock can be operated at any duty cycle that meets the specified latch pulse width The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met although the location of these transition edges may affect digital feedthrough and distortion performance Best performan
28. ingle ended input mode operates in the same way as the CLOCK input in the 28 lead packages as previously described In the differential input mode the clock input functions as a high impedance differential pair The common mode level of the CLK and CLK inputs can vary from 0 75 V to 2 25 V and the differential voltage can be as low as 0 5 V p p This mode can be used to drive the clock with a differential sine wave since the high gain bandwidth of the differential inputs will convert the sine wave into a single ended square wave internally The final clock mode allows for a reduced external component count when the DAC clock is distributed on the board using PECL logic The internal termination configuration is shown in Figure 29 These termination resistors are untrimmed and can vary up to 20 However matching between the resistors should generally be better than 1 Rev B Page 15 of 32 09744 AD9744 TO DAC CORE 1 3 NOM 02913 026 Figure 29 Clock Termination in PECL Mode DAC TIMING Input Clock and Data Timing Relationship Dynamic performance in a DAC is dependent on the relation ship between the position of the clock edges and the time at which the input data changes The AD9744 is rising edge trig gered and so exhibits dynamic performance sensitivity when the data transition is close to this edge In general the goal when applying the AD9744 is to make the data transition close to the falling
29. line Package TSSOP RU 28 Dimensions shown in millimeters 18 10 0 7126 17 70 0 6969 28 15 7 60 0 2992 7 40 0 2913 10 65 0 4193 1 14 10 00 0 3937 2 65 0 1043 0 75 0 0295 5 2 35 0 0925 0 25 0 0098 0 30 0 0118 0 10 0 0039 gt e 8 1 27 0 0500 0 51 0 0201 SEATING 0 1 27 0 0500 COPLANARITY 0 51 0 0201 0 32 0 0126 27 0 0 10 BSC 033 0 0130 PLANE 53 0 0091 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 59 28 Lead Standard Small Outline Package SOIC Wide Body RW 28 Dimensions shown in millimeters and inches Rev B Page 30 of 32 ORDERING PIN 1 INDICATOR 1 00 0 85 0 80 PIN 1 INDICATOR PAD BOTTOM VIEW 0 25 MIN 0 80 MAX 15 MAX 0 65 TYP Ta 0 02 0 30 COPLANARITY 0 23 0 20 REF 0 08 SEATING 225 PLANE 0 18 COMPLIANT TO JEDEC STANDARDS MO 220 VHHD 2 Figure 60 32 Lead Lead Frame Chip Scale Package LFCSP 5mm x 5 mm Body CP 32 3 Dimensions shown in millimeters 09744 Model Temperature Range Package Description Package Options AD9744AR
30. lized to full scale associated with a 1 LSB change in digital input code Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases Offset Error The deviation of the output current from the ideal of zero is called the offset error For IOUTA 0 mA output is expected when the inputs all 0s For IOUTB 0 mA output is expected when all inputs are set to 1s Gain Error The difference between the actual and ideal output span The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 05 Output Compliance Range The range of allowable voltage at the output of a current output DAC Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance Temperature Drift It is specified as the maximum change from the ambient 25 value to the value at either or For offset and gain drift the drift is reported in ppm of full scale range FSR per For reference drift the drift is reported in ppm per CLOCK LATCHES xou lei DCOM RETIMED CLOCK DIGITAL OUTPUT CLOCK DATA OUTPUT LECROY 9210 TEKTRONIX AWG 2021 PULSE GENERATOR WITH OPTION 4 AD9744 6466064 666664 66666 5 Power Supply Rejection The maximum change in the full scale output as the supplies
31. ll scale output should be set within 015 voltage output swing capabilities by scaling Iourss and or Res An improvement in ac distortion performance may result with a reduced Iourss since the signal current U1 will be required to sink less signal current Vout lourrs x RFB 02913 035 Figure 38 Unipolar Buffered Voltage Output POWER AND GROUNDING CONSIDERATIONS POWER SUPPLY REJECTION Many applications seek high speed and high performance under less than ideal operating conditions In these application circuits the implementation and construction of the printed circuit board is as important as the circuit design Proper RF techniques must be used for device selection placement and routing as well as power supply bypassing and grounding to ensure optimum performance Figure 43 to Figure 46 illustrate the recommended printed circuit board ground power and signal plane layouts implemented on the AD9744 evaluation board One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution This is referred to as the power supply rejection ratio PSRR For dc variations of the power supply the resulting performance of the DAC directly corresponds to a gain error associated with the DAC s full scale current Iourrs AC noise on the dc supplies is common in applications where the power distribution is ge
32. n erated by a switching power supply Typically switching power supply noise will occur over the spectrum from tens of KHz to several MHz The PSRR vs frequency of the AD9744 AVDD supply over this frequency range is shown in Figure 39 85 80 PSRR dB o e a a 40 0 2 6 8 10 12 FREQUENCY MHz 02913 036 Figure 39 Power Supply Rejection Ratio PSRR vs Frequency Rev B Page 18 of 32 Note that the ratio in Figure 39 is calculated amps out volts in Noise on the analog power supply has the effect of modulat ing the internal switches and therefore the output current The voltage noise on AVDD therefore will be added in a nonlinear manner to the desired IOUT Due to the relative different size of these switches the PSRR is very code dependent This can produce a mixing effect that can modulate low frequency power supply noise to higher frequencies Worst case PSRR for either one of the differential DAC outputs will occur when the full scale current is directed toward that output As a result the PSRR measurement in Figure 39 represents a worst case condi tion in which the digital inputs remain static and the full scale output current of 20 mA is directed to the DAC output being measured An example serves to illustrate the effect of supply noise on the analog supply Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV of noise and for simplicity s
33. n using internal reference Requires 0 1 uF capacitor to when using internal reference 18 24 FS ADJ Full Scale Current Output Adjust 19 N A NC No Internal Connection 20 19 22 Analog Common 21 20 IOUTB Complementary DAC Current Output Full scale current when all data bits are 0s 22 21 IOUTA DAC Current Output Full scale current when all data bits are 1s 23 N A RESERVED Reserved Do not connect to common or supply 24 17 18 AVDD Analog Supply Voltage 3 3 V 25 16 MODE Selects Input Data Format Connect to DCOM for straight binary DVDD for twos complement N A 15 CMODE Clock Mode Selection Connect to CLKCOM for single ended clock receiver drive CLK and float CLK Connect to CLKVDD for differential receiver Float for PECL receiver terminations on chip 26 10 26 DCOM Digital Common 27 3 DVDD Digital Supply Voltage 3 3 V 28 N A CLOCK Clock Input Data latched on positive edge of clock N A 12 CLK Differential Clock Input N A 13 CLK Differential Clock Input N A 11 CLKVDD Clock Supply Voltage 3 3 V N A 14 Clock Common Rev B Page 7 of 32 09744 TERMINOLOGY Linearity Error Also Called Integral Nonlinearity or INL It is defined as the maximum deviation of the actual analog output from the ideal output determined by a straight line drawn from zero to full scale Differential Nonlinearity or DNL DNL is the measure of the variation in analog value norma
34. o current outputs will typically drive resistive load di rectly or via a transformer If dc coupling is required IOUTA and IOUTB should be directly connected to matching resistive loads that are tied to analog common Note that Rioap may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 or 75 cable The single ended voltage output appearing at the IOUTA and IOUTB nodes is simply Voura IOUTA x Rjoap 5 Vours x Rjoap 6 Note that the full scale value of and Vours should not exceed the specified output compliance range to maintain speci fied distortion and linearity performance IOUTB x RjoAp 7 Substituting the values of IOUTA IOUTB and can be expressed as V prr 2 DAC CODE 16383 16384 8 32 X 1227726 Equation 7 Equation 8 highlight some of advantages of operating the AD9744 differentially First the differential operation helps cancel common mode error sources associated with and IOUTB such as noise distortion and dc offsets Second the differential code dependent current and subsequent voltage is twice the value of the single ended voltage output that is or Vours thus providing twice the signal power to the load Note that the gain drift temperature performance for a single ended Vovra
35. or a doubly termi nated 50 cable since the nominal full scale current Iourrs of 20 mA flows through the equivalent Rioap of 25 In this case Rioap represents the equivalent load resistance seen by IOUTA or IOUTB The unused output IOUTA or IOUTB can be con nected to directly or via a matching Rioap Different values of Iourzs and Rroap can be selected as long as the positive compliance range is adhered to One additional consideration in this mode is the integral nonlinearity INL discussed in the Analog Outputs section For optimum INL performance the single ended buffered voltage output configuration is suggested loutrs 20mA AD9744 Vouta OV 0 5V 02913 034 Figure 37 0 V to 0 5 V Unbuffered Voltage Output SINGLE ENDED BUFFERED VOLTAGE OUTPUT CONFIGURATION Figure 38 shows a buffered single ended output configuration in which the op amp U1 performs I V conversion on the AD9744 output current U1 maintains IOUTA or IOUTB ata virtual ground minimizing the nonlinear output impedance effect on the DAC s INL performance as described in the Analog Outputs section Although this single ended configura tion typically provides the best dc linearity performance its ac distortion performance at higher DAC update rates may be limited 015 slew rate capabilities U1 provides a negative unipolar output voltage and its full scale output voltage is sim ply the product of Res and Ioures The fu
36. order cancellation of various dynamic common mode distortion mechanisms digital feedthrough and noise Performing a differential to single ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load assuming no source termination Since the output currents of IOUTA and IOUTB are complementary they become additive when processed differentially A properly selected transformer will allow the AD9744 to provide the required power and voltage levels to different loads Rev B Page 14 of 32 The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kO in parallel with 5 pF It is also slightly dependent on the output voltage that is Voura and Vours due to the nature of a PMOS device As a result maintaining IOUTA and or IOUTB at a virtual ground via an I V op amp configuration will result in the optimum dc linearity Note that the INL DNL specifications for the AD9744 are measured with IOUTA maintained at a virtual ground via an op amp IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance The negative output compliance range of 1 is set by the breakdown limits of the CMOS process Operation beyond this maximum limit may result in a break down of the output stage and affect t
37. pling a bipolar output signal gain and or level shifting within the bandwidth of the chosen op amp A single ended output is suitable for applications requiring a unipolar voltage output A positive unipolar output voltage results ifIOUTA and or IOUTB are connected to an appro priately sized load resistor Rioap referred to This configuration may be more suitable for a single supply system requiring a dc coupled ground referred output voltage Alter natively an amplifier could be configured as an I V converter thus converting IOUTA or IOUTB into a negative unipolar voltage This configuration provides the best dc linearity since or IOUTB is maintained at a virtual ground DIFFERENTIAL COUPLING USING A TRANS FORMER An RF transformer can be used to perform a differential to single ended signal conversion as shown in Figure 34 A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral con tent lies within the transformer s pass band An RF transformer such as the Mini Circuits T1 1T provides excellent rejection of common mode distortion that is even order harmonics and noise over a wide frequency range It also provides electrical isolation and the ability to deliver twice the power to the load Transformers with different impedance ratios may also be used 09744 for impedance matching purposes Note that the transformer provides ac couplin
38. ply Current 5 6 mA Supply Current Sleep Mode lavo 5 6 mA Power Dissipation 135 145 mW Power Dissipation 145 mW Power Supply Rejection Ratio AVDD 1 1 of FSR V Power Supply Rejection Ratio DVDD 0 04 0 04 of FSR V OPERATING RANGE 40 85 1 Measured at IOUTA driving a virtual ground 2 Nominal full scale current is 32 times the Inr current 3 An external buffer amplifier with input bias current 100 nA should be used to drive any external load Measured at faoc 25 MSPS and four 1 MHz 5 Measured as unbuffered voltage output with lourrs 20 mA and 50 Rioao at IOUTA and IOUTB faoc 100 MSPS and four 40 MHz 6 5 power supply variation Rev B Page 3 of 32 AD9744 DYNAMIC SPECIFICATIONS Tum to AVDD 3 3 V DVDD 3 3 V CLKVDD 3 3 V Iourrs 20 mA differential transformer coupled output 50 doubly terminated unless otherwise noted Table 2 Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate 210 MSPS Output Settling Time to 0 196 11 ns Output Propagation Delay trp 1 ns Glitch Impulse 5 5 Output Rise Time 10 to 90 2 5 ns Output Fall Time 10 to 90 2 5 ns Output Noise lourrs 20 mA 50 pA VHz Output Noise loutrs 2 mA 30 pA VHz Noise Spectral Density 155 dBm Hz AC LINEARITY Spurious Free Dynamic Range to Nyquist 25 MSPS four 1 00 MH
39. sensitive to Conversely is dependent on both the digital input waveform and digital supply DVDD Figure 32 shows Ipvpp as a function of full scale sine wave output ratios four fciock for various update rates with DVDD 3 3 V lavpp mA 02913 028 lourrs mA Figure 31 VS lourrs 20 18 210MSPS 16 4 165MSPS lt 12 10 125MSPS 8 65MSPS 4 2 0 0 01 0 1 1 02913 029 RATIO four fcLoci Figure 32 vs Ratio DVDD 3 3 Rev B Page 16 of 32 E o mA gt a o 02913 030 fcLock MSPS Figure 33 lakvop vs and Clock Mode APPLYING THE AD9744 Output Configurations The following sections illustrate some typical output configura tions for the AD9744 Unless otherwise noted it is assumed that is set to a nominal 20 mA For applications requiring the optimum dynamic performance a differential output configu ration is suggested A differential output configuration may consist of either an RF transformer or a differential op amp configuration The transformer configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling The differential op amp configuration is suitable for applications requiring dc cou
40. t can operate independently over a 2 7 V to 3 6 V range The digital section which is capable of operating at a rate of up to 210 MSPS consists of edge triggered latches and segment decoding logic circuitry The analog section includes the PMOS current sources the associated differential switches a 1 2 V band gap voltage reference and a reference control amplifier The DAC full scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor Rser connected to the full scale adjust FS ADJ pin The external resistor in combination with both the reference control amplifier and voltage reference Vrerio sets the reference current Irer which is replicated to the segmented current sources with the proper scaling factor The full scale current Iourrs is 32 times REFERENCE OPERATION The AD9744 contains an internal 1 2 V band gap reference The internal reference cannot be disabled but can be easily overrid den by an external reference with no effect on performance Figure 25 shows an equivalent circuit of the band gap reference REFIO serves as either an output or an input depending on whether the internal or an external reference is used To use the internal reference simply decouple the REFIO pin to ACOM with a 0 1 capacitor and connect REFLO to ACOM via a resistance less than 5 The internal reference voltage will be present at REFIO If the voltage at R
41. tated in Equation 3 Rev B Page 13 of 32 09744 The control amplifier allows wide 10 1 adjustment span of Iovres over a 2 mA to 20 mA range by setting Ins between 62 5 uA and 625 uA The wide adjustment span of Iourrs pro vides several benefits The first relates directly to the power dissipation of the AD9744 which is proportional to lourrs refer to the Power Dissipation section The second relates to the 20 dB adjustment which is useful for system gain control purposes The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency small signal multiplying applications DAC TRANSFER FUNCTION Both DACs in the AD9744 provide complementary current outputs IOUTA and IOUTB IOUTA provides a near full scale current output Iourrs when all bits are high that is DAC CODE 16383 while IOUTB the complementary output provides no current The current output appearing at IOUTA and IOUTB is a function of both the input code and Iourrs and can be expressed as IOUTA DAC CODE 16384 x Ioures 1 IOUTB 16383 DAC CODE 16384 x Q where DAC CODE 0 to 16383 that is decimal representation As mentioned previously Iourrs is a function of the reference current Irer which is nominally set by a reference voltage and external resistor It can be expressed as Iourrs 32 3 where Trep Vagrto 4 The tw
42. z 0 dBFS Output 77 90 dBc 6 dBFS Output 87 dBc 12 dBFS Output 82 dBc 18 dBFS Output 82 dBc faoc 65 MSPS four 1 00 MHz 85 dBc 65 MSPS four 2 51 MHz 84 dBc faoc 65 MSPS four 10 MHz 80 dBc faoc 65 MSPS four 15 MHz 75 dBc faoc 65 MSPS four 25 MHz 74 dBc faoc 165 MSPS four 21 MHz 73 dBc 165 MSPS four 41 MHz 60 dBc faoc 210 MSPS four 41 MHz 68 dBc faoc 210 MSPS four 69 MHz 64 dBc Spurious Free Dynamic Range Within a Window faoc 25 MSPS four 1 00 MHz 2 MHz Span 84 90 dBc faoc 50 MSPS four 5 02 MHz 2 MHz Span 90 dBc faoc 65 MSPS four 5 03 MHz 2 5 MHz Span 87 dBc faoc 125 MSPS four 5 04 MHz 4 MHz Span 87 dBc Total Harmonic Distortion faoc 25 MSPS four 1 00 MHz 86 77 dBc faoc 50 MSPS four 2 00 MHz 77 dBc 65 MSPS four 2 00 MHz 77 dBc 125 MSPS four 2 00 MHz 77 dBc Signal to Noise Ratio faoc 65 MSPS four 5 MHz loutrs 20 mA 82 dB faoc 65 MSPS four 5 MHz loutrs 5 mA 88 dB fa ock 125 MSPS four 5 MHz lourrs 20 77 dB faoc 125 MSPS four 5 MHz lourrs 5 mA 78 dB faoc 165 MSPS four 5 MHz lourrs 20 mA 70 dB faoc 165 MSPS four 5 MHz lourrs 5 mA 70 dB faoc 210 MSPS four 5 MHz loures 20 mA 74 dB faoc 210 MSPS four 5 MHz lourrs 5 mA 67 dB Rev B Page 4 of 32 09744 Parameter Min Typ Max Unit Multitone Power Ratio 8 Tones at
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