ANALOG DEVICES ADV7125 English products handbook Rev C
Contents
1. RED AND BLUE GREEN NOTES 1 OUTPUTS CONNECTED TO A DOUBLY TERMINATED 750 LOAD 2 Veer 1 235V Rser 5300 3 RS 343 LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS ADV7125 Table 7 details the resultant effect on the analog outputs of BLANK and SYNC All these digital inputs are specified to accept TTL logic levels CLOCK INPUT The CLOCK input of the ADV7125 is typically the pixel clock rate of the system It is also known as the dot rate The dot rate and thus the required CLOCK frequency is determined by the on screen resolution according to the following equation Dot Rate Horiz Res x Vert Res x Refresh Rate Retrace Factor where Horiz Res is the number of pixels per line Vert Res is the number of lines per frame Refresh Rate is the horizontal scan rate This is the rate at which the screen must be refreshed typically 60 Hz for a noninterlaced system or 30 Hz for an interlaced system Retrace Factor is the total blank time factor This takes into account that the display is blanked for a certain fraction of the total duration of each frame for example 0 8 Therefore for a graphics system with a 1024 x 1024 resolution a noninterlaced 60 Hz refresh rate and a retrace factor of 0 8 Dot Rate 1024 x 1024 x 60 0 8 78 6 MHz The required CLOCK frequency is thus 78 6 MHz All video data and control inputs are latched into the ADV7125 on the rising edge of CLOCK as previousl2. sssssessssssssssssessssssssssssrreessss 11 Digital Tip uty ienr ienien e a E A Ra 11 Clock Tip Ut asesan ns a RERS ESERSE 11 Video Synchronization and Control sssssssssssssssssssssssesssssss 12 Reference Input ir E E E A 12 DA GS EE E 12 Analog QUUPUts ss cassis ssdssseectisaseondscdiensddsssnecsdatienndsedsenesdosbeosdiobse 12 Gray Scale Operation eecssesesseeseesesesesseseeseenseneenseneese 13 Video Output Buffers 13 PCB Layout Considerations cscsssessseesesesseesesseeseessesseese 13 Digital Signal Interconnect ccessessesssessesseesessessessesseesseeseenes 13 Analog Signal Interconnect ccessessssesesseessessesssesesseesesseenee 14 Outline Dimensions iesise enas en aE E 15 Ordering Guide w 16 Automotive Products cccccccssscscsssscscsssssscscssssssssssscssssssssssscseees 16 Changes to Figure 3 and Table 6 csssesssssesssesesseessessesseesseeseens 8 Deleted Ground Planes Section Power Planes Section and Supply Decoupling Section i seseseseseseeseeseeseeseeneenesneess 11 Changes fo Figure 5 ois assceccecsizeceendes n e R E EA 11 Changes to Table 7 Analog Outputs Section Figure 6 and PA SUT Oe rr E E AR genta KEA 12 Changes to Video Output Buffers Section PCB Layout Considerations Section and Figure 9 ssssesssessserrssssrresssseereeees 13 Changes to Analog Signal Interconnect Section and Figur 10 2 sccstescscsnsbsassiedeeddacoeesgesestescddostesasashesssdessecs
3. 40 C to 85 C 48 Lead LQFP 170 MHz ST 48 ADV7125BCPZ170 40 C to 85 C 48 Lead LFCSP_VQ 170 MHz CP 48 1 ADV7125BCPZ170 RL 40 C to 85 C 48 Lead LFCSP_VQ 170 MHz CP 48 1 ADV7125WBCPZ170 40 C to 85 C 48 Lead LFCSP_VQ 170 MHz CP 48 1 ADV7125WBCPZ170 RL 40 C to 85 C 48 Lead LFCSP_VQ 170 MHz CP 48 1 1 Z RoHS Compliant Part 2 W Qualified for Automotive Applications 3 ADV7125JSTZ330 is available in a 3 3 V option only AUTOMOTIVE PRODUCTS The ADV7125W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications Note that these automotive models may have specifications that differ from the commercial models therefore designers should review the Specifications section of this data sheet carefully Only the automotive grade products shown are available for use in automotive applications Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models 2002 2011 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D03097 0 2 11 C mics Rev C Page 16 of 16
4. MONITOR Equation 1 applies to the ADV7125 only when SYNC is being used If SYNC is not being encoded onto the green channel Equation 1 is similar to Equation 2 Using a variable value of Rser allows for accurate adjustment of the analog output video levels Use of a fixed 560 Q Rser resistor yields the analog output levels quoted in the Specifications section These values typically correspond to the RS 343A video wave form values as shown in Figure 5 DACS The ADV7125 contains three matched 8 bit DACs The DACs are designed using an advanced high speed segmented architec ture The bit currents corresponding to each digital input are routed to either the analog output bit 1 or GND bit 0 by a sophisticated decoding scheme Because all this circuitry is on one monolithic device matching between the three DACs is optimized As well as matching the use of identical current sources in a monolithic design guarantees monotonicity and TERMINATION REPEATED THREE TIMES FOR RED GREEN AND BLUE DACs 03097 006 Figure 6 Analog Output Termination for RS 343A IOR IOG IOB Zs 1500 SOURCE TERMINATION ZL 750 MONITOR TERMINATION REPEATED THREE TIMES FOR RED GREEN AND BLUE DACs 03097 007 Figure 7 Analog Output Termination for RS 170 More detailed information regarding load terminations for various output configurations including RS 343A and RS 170 is available in the AN 205 Application No
5. OUTLINE DIMENSIONS 0 75 wt 1 60 0 60 7 MAX 0 45 TOP VIEW 0 20 PINS DOWN 0 09 a 4 35 Le 0 08 COPLANARITY VIEWA 0 50 0 27 BSC LEAD PITCH VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS 026 BBC 0 22 0 17 051706 A Figure 11 48 Lead Low Profile Quad Flat Package LQFP ST 48 Dimensions shown in millimeters PIN 1 INDICATOR TOP EXPOSED 5 25 VIEW PAD 510 SQ BOTTOM VIEW 2 0 80 MAX 12 MAX 0 65 MA 0 65 TYP 0 05 MAX 0 02 NOM Je 0 50 BSc E 1 COPLANARITY SEATING 9 20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO 220 VKKD 2 Eas MIN FOR PROPER CONNECTION OF THE EXPOSED PAD REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET Figure 12 48 Lead Lead Frame Chip Scale Package LFCSP_VQ 7mm x 7mm Body Very Thin Quad CP 48 1 Dimensions shown in millimeters Rev C Page 15 of 16 080108 A ADV7125 ADV7125 ORDERING GUIDE Model 2 3 Temperature Range Package Description Speed Option Package Option ADV7125KSTZ50 40 C to 85 C 48 Lead LQFP 50 MHz ST 48 ADV7125KSTZ50 REEL 40 C to 85 C 48 Lead LQFP 50 MHz ST 48 ADV7125KSTZ140 40 C to 85 C 48 Lead LQFP 140 MHz ST 48 ADV7125JSTZ240 0 C to 70 C 48 Lead LQFP 240 MHz ST 48 ADV7125JSTZ330 0 C to 70 C 48 Lead LQFP 330 MHz ST 48 ADV7125WBSTZ170 40 C to 85 C 48 Lead LOFP 170 MHz ST 48 ADV7125WBSTZ170 RL
6. single 5 V 3 3 V power supply and clock are all that are 2 Guaranteed monotonic to eight bits required to make the part functional The ADV7125 has additional video control signals composite SYNC and BLANK as well as a power save mode 3 Compatible with a wide variety of high resolution color graphics systems including RS 343A and RS 170 ADV is a registered trademark of Analog Devices Inc Rev C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2002 2011 Analog Devices Inc All rights reserved ADV7125 TABLE OF CONTENTS Features erine eae or or E S EEEE EE 1 Applications Aee a eaaa aa EAE 1 Functional Block Diagram sssssssssssssssssssssssssssssssssssssstreesssssssnreseee 1 General Description sasisivs ccssavssseisawsstessaasveisassaswsstvectessapaeesanveneisaves 1 Product Highlights z s 1 Revision Histoty sssusa a late 2 SPECHICALIONS s ucssssssscassissssicsuebeeeddasanond sianv
7. fax maximum specification production tested at 125 MHz and 5 V Limits specified here are guaranteed by characterization tz gt t lt u lt lt t CLOCK DIGITAL INPUTS R7 TO RO G7 TO GO B7 TO BO SYNC BLANK t ___ ANALOG OUTPUTS IOR IOR IOG TOG IOB TOB NOTES 1 OUTPUT DELAY t6 MEASURED FROM THE 50 POINT OF THE RISING EDGE OF CLOCK TO THE 50 POINT OF FULL SCALE TRANSITION 2 OUTPUT RISE FALL TIME t7 MEASURED BETWEEN THE 10 AND 90 POINTS OF FULL SCALE TRANSITION 3 TRANSITION TIME tg MEASURED FROM THE 50 POINT OF FULL SCALE TRANSITION TO WITHIN 2 OF THE FINAL OUTPUT VALUE 03097 002 Figure 2 Timing Diagram Rev C Page 6 of 16 ABSOLUTE MAXIMUM RATINGS Table 5 Parameter Rating Vaa to GND 7V Voltage on Any Digital Pin GND 0 5 V to Vaa 0 5 V Ambient Operating Temperature Ta 40 C to 85 C Storage Temperature Ts 65 C to 150 C Junction Temperature T 150 C Lead Temperature Soldering 10 sec 300 C Vapor Phase Soldering 1 Minute 220 C lour to GND OV to Vaa ADV7125 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended
8. information onto the ADV7125 the SYNC input should be tied to logic low REFERENCE INPUT The ADV7125 contains an on board voltage reference The Vrer pin should be connected as shown in Figure 10 A resistance Rser connected between the Rser pin and GND determines the amplitude of the output video level according to Equation 1 and Equation 2 for the ADV7125 low glitch The on board operational amplifier stabilizes the full scale output current against temperature and power supply variations ANALOG OUTPUTS The ADV7125 has three analog outputs corresponding to the red green and blue video signals The red green and blue analog outputs of the ADV7125 are high impedance current sources Each one of these three RGB current outputs is capable of directly driving a 37 5 Q load such as a doubly terminated 75 Q coaxial cable Figure 6 shows the required configuration for each of the three RGB outputs connected into a doubly terminated 75 Q load This arrangement develops RS 343A video output voltage levels across a 75 Q monitor A suggested method of driving RS 170 video levels into a 75 Q monitor is shown in Figure 7 The output current levels of the DACs remain unchanged but the source termination resistance Zs on each of the three DACs is increased from 75 Q to 150 Q IOR IOG IOB IOG mA 11 444 8 x Vrer V Rser Q IOR IOB mA 7989 6 x Vrer V Rser Q 1 2 SOURCE TERMINATION Z 750
9. the ADV7125 when this pin is active 49 EPAD EP EPAD The LFCSP_VQ has an exposed paddle that must be connected to GND Rev C Page 9 of 16 ADV7125 TERMINOLOGY Blanking Level The level separating the SYNC portion from the video portion of the waveform Usually referred to as the front porch or back porch At 0 IRE units it is the level that shuts off the picture tube resulting in the blackest possible picture Color Video RGB This refers to the technique of combining the three primary colors of red green and blue to produce color pictures within the usual spectrum In RGB monitors three DACs are required one for each color Sync Signal SYNC The position of the composite video signal that synchronizes the scanning process Gray Scale The discrete levels of video signal between reference black and reference white levels An 8 bit DAC contains 256 different levels Raster Scan The most basic method of sweeping a CRT one line at a time to generate and display images Reference Black Level The maximum negative polarity amplitude of the video signal Reference White Level The maximum positive polarity amplitude of the video signal Sync Level The peak level of the SYNC signal Video Signal The portion of the composite video signal that varies in gray scale levels between reference white and reference black Also referred to as the picture signal this is the portion that can be visually observed
10. 50 MHz grade 0 5 140 MHz 140 MHz grade 0 5 240 MHz 240 MHz grade Data and Control Setup ti 0 5 ns Data and Control Hold te 1 5 ns CLOCK Period ts 4 17 ns CLOCK Pulse Width High t4 1 875 ns fck max 240 MHz CLOCK Pulse Width Low ts 1 875 ns foix_max 240 MHz CLOCK Pulse Width High t4 2 85 ns fck max 140 MHz CLOCK Pulse Width Low ts 2 85 ns fck max 140 MHz CLOCK Pulse Width High ta 8 0 ns fck max 50 MHz CLOCK Pulse Width Low ts 8 0 ns fck max 50 MHz Pipeline Delay ted 1 0 1 0 1 0 Clock cycles PSAVE Up Time tio 2 10 ns 1 The maximum and minimum specifications are guaranteed over this range Temperature range Tmn to Tmax 40 C to 85 C at 50 MHz and 140 MHz 0 C to 70 C at 240 MHz 3 Timing specifications are measured with input levels of 3 0 V Vin and O V Vi for both 5 V and 3 3 V supplies 4 Rise time was measured from the 10 to 90 point of zero to full scale transition fall time from the 90 to 10 point of a full scale transition 5 Measured from 50 point of full scale transition to 2 of final value Guaranteed by characterization 7 fak maximum specification production tested at 125 MHz and 5 V Limits specified here are guaranteed by characterization Rev C Page 5 of 16 ADV7125 3 3 V TIMING SPECIFICATIONS Vaa 3 0 V to 3 6 V Vrer 1 235 V Reser 560 Q Ci 10 pF All specifications Tun to Tmax unless otherwise noted Tj max 110 C Table 4 Param
11. ANALOG CMOS 330 MHz DEVICES Triple 8 Bit High Speed Video DAC ADV7125 FEATURES FUNCTIONAL BLOCK DIAGRAM 330 MSPS throughput rate Vaa Triple 8 bit DACs RS 343A RS 170 compatible output Se BEANICAND SYNC LOGIC Complementary outputs DAC output current range 2 0 mA to 26 5 mA TTL compatible inputs Internal Reference 1 235 V Single supply 5 V 3 3 V operation 48 lead LQFP and LFCSP packages Low power dissipation 30 mW minimum 3 V Low power standby mode 6 mW typical 3 V Industrial temperature range 40 C to 85 C _ VOLTAGE Pb free lead free packages RESIRCUIT j Qualified for automotive applications APPLICATIONS GND Rey COMP Digital video systems Figure 1 High resolution color graphics Digital radio modulation Image processing Instrumentation Video signal reconstruction Automotive infotainment units GENERAL DESCRIPTION The ADV7125 ADV is a triple high speed digital to analog The ADV7125 is fabricated in a 5 V CMOS process Its converter on a single monolithic chip It consists of three high monolithic CMOS construction ensures greater functionality speed 8 bit video DACs with complementary outputs a with lower power dissipation The ADV7125 is available in standard TTL input interface and a high impedance analog 48 lead LQFP and 48 lead LFCSP packages output current source PRODUCT HIGHLIGHTS The ADV7125 has three separate 8 bit wide input ports A 1 330 MSPS 3 3 V only throughput
12. Rev C Page 10 of 16 CIRCUIT DESCRIPTION AND OPERATION The ADV7125 contains three 8 bit DACs with three input channels each containing an 8 bit register Also integrated on board the part is a reference amplifier The CRT control functions BLANK and SYNC are integrated on board the ADV7125 DIGITAL INPUTS There are 24 bits of pixel data color information RO to R7 G0 to G7 and B0 to B7 latched into the device on the rising edge of each clock cycle This data is presented to the three 8 bit DACs and then converted to three analog RGB output wave forms see Figure 4 noone oa ae oe oe ee DIGITAL INPUTS R7 TO RO G7 TO G0 paral B7 TO B0 DATA SYNC BLANK ANALOG OUTPUTS IOR TOR IOG 10G IOB IOB 03097 004 Figure 4 Video Data Input Output The ADV7125 has two additional control signals that are latched to the analog video outputs in a similar fashion BLANK and SYNC are each latched on the rising edge of CLOCK to maintain synchronization with the pixel data stream The BLANK and SYNC functions allow for the encoding of these video synchronization signals onto the RGB video output This is done by adding appropriately weighted current sources to the analog outputs as determined by the logic levels on the BLANK and SYNC digital inputs Figure 5 shows the analog output RGB video waveform of the ADV7125 The influence of SYNC and BLANK on the analog video waveform is illustrated
13. and other analog circuitry Digital signal lines should not overlay the analog power plane Due to the high clock rates used long clock lines to the ADV7125 should be avoided to minimize noise pickup Connect any active pull up termination resistors for the digital inputs to the regular PCB power plane Vcc and not to the analog power plane Rev C Page 13 of 16 ADV7125 ANALOG SIGNAL INTERCONNECT For optimum performance the analog outputs should each Place the ADV7125 as close as possible to the output connectors have a SOuney tet aon i esistance to gr ound of75 o doubly thus minimizing noise pickup and reflections due to impedance terminated 75 Q configuration This termination resisrance mismatch should be as close as possible to the ADV7125 to minimize reflections The video output signals should overlay the ground plane and e l Additional information on PCB design is available in the not the analog power plane thereby maximizing the high nae l i frequency power supply rejection AN 333 Application Note Design and Layout of a Video Graphics System for Reduced EMI which is available from Analog Devices at www analog com POWER SUPPLY DECOUPLING 0 1uF AND 0 01F CAPACITOR FOR EACH Va GROUP 0 1uF Vaa H 41 TO 48 MONITOR CRT 10G ADV7125 IOB CONNECTORS COMPLEMENTARY OUTPUTS 1 2 14 15 25 26 39 40 03097 010 Figure 10 Typical Connection Diagram Rev C Page 14 of 16
14. ds is described in the Analog Outputs section and illustrated in Figure 9 However in some applications it may be required to drive long transmis sion line cable lengths Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses The inclusion of output buffers compensates for some cable distortion Buffers with large full power bandwidths and gains between two and four are required These buffers also need to be able to supply sufficient current over the complete output voltage swing Analog Devices produces a range of suitable op amps for such applications These include the AD843 AD844 AD847 and AD848 series of monolithic op amps In very high frequency applications 80 MHz the AD8061 is recommended More information on line driver buffering circuits is given in the relevant op amp data sheets Use of buffer amplifiers also allows implementation of other video standards besides RS 343A and RS 170 Altering the gain components of the buffer circuit results in any desired video level ADV7125 Z2 Zi IOR IOG IOB Z 750 MONITOR Zs 750 SOURCE TERMINATION 03097 009 Z1 GAIN G 1 Z2 Figure 9 AD848 As an Output Buffer PCB LAYOUT CONSIDERATIONS The ADV7125 is optimally designed for lowest noise perfor mance both radiated and conducted noise To complement the excellent noise performance of the ADV7125 it is imperative that great care be given
15. eddastneccdstieandgeasensdaneiessisstie 3 5 V Electrical Characteristics csssessessesssessesssessessesseessesseenes 3 3 3 V Electrical Characteristics cscessesssssessesseessesesseesessesaes 4 5 V Timing Specifications sssssssssssssssesstsssssssssssressreeessssssssseeee 5 3 3 V Timing Specifications ssssssssssssesessssssssssssssreresssssssssrseee 6 Absolute Maximum Ratings ss ssssssssssssssssstssssssssssrstrreessssssssssene 7 ESD Caution sisses irisse Seia Pin Configuration and Function Descriptions Terminologiari a a E VE RENE REVISION HISTORY 2 11 Rev B to Rev C Chang to Table Griene eaae eenaa E E EAE EEEE SEERE EAS 8 7 10 Rev A to Rev B Change to Features Section ssssssssssssssssssssssssstesssssssssrresessseteeessssssss 1 Changes to Clock Frequency Parameter Table 4 0 0 0 cscs 6 Changes to Figure 2 otc csiisvsssssset ssancsnasssienesdestnsessssiernacoasensdansbaseseeniees 6 Changes to Figure 4 and Figure 5 0 cscsessessssesseessessesseessesseenes 11 Changes to lable 7 scsi E ECEE 12 Changes to Endnotes to Ordering Guide 15 Added Automotive Products Section cccecesesssesesesseesesseenes 15 3 09 Rev 0 to Rev A Updated Formats iiiiiccsacsveinivanientiane niente Universal Changes to Features Section Applications Section and General Description Sect ON wes cicsccssssestesssgsecdesissovecseseneconiseoveszveesseteerareevieets 1 Circuit Description and Operation
16. eter Symbol Min Typ Max Unit Conditions ANALOG OUTPUTS Analog Output Delay te 7 5 ns Analog Output Rise Fall Time t7 1 0 ns Analog Output Transition Time ts 15 ns Analog Output Skew to 1 2 ns CLOCK CONTROL CLOCK Frequency fck 50 MHz 50 MHz grade 140 MHz 140 MHz grade 240 MHz 240 MHz grade 330 MHz 330 MHz grade Data and Control Setup ti 0 2 ns Data and Control Hold ta 1 5 ns CLOCK Period ts 3 ns CLOCK Pulse Width High t4 1 4 ns foik_max 330 MHz CLOCK Pulse Width Low ts 1 4 ns foix_max 330 MHz CLOCK Pulse Width High t4 1 875 ns fc k_max 240 MHz CLOCK Pulse Width Low ts 1 875 ns foik_max 240 MHz CLOCK Pulse Width High t4 2 85 ns fck max 140 MHz CLOCK Pulse Width Low ts 2 85 ns fck max 140 MHz CLOCK Pulse Width High t4 8 0 ns fcuk max 50 MHz CLOCK Pulse Width Low ts 8 0 ns fck max 50 MHz Pipeline Delay ted 1 0 1 0 1 0 Clock cycles PSAVE Up Time tio 4 10 ns 1 These maximum and minimum specifications are guaranteed over this range Temperature range Tmn to Tmax 40 C to 85 C at 50 MHz and 140 MHz 0 C to 70 C at 240 MHz and 330 MHz 3 Timing specifications are measured with input levels of 3 0 V Vin and O V Vi for 3 3 V supplies 4 Rise time was measured from the 10 to 90 point of zero to full scale transition fall time from the 90 to 10 point of a full scale transition 5 Measured from 50 point of full scale transition to 2 of final value 6 Guaranteed by characterization 7
17. ieneseesiecobescccestes 14 Updated Outline Dimensions cseeesssesesseesseseesnesesseese 15 Changes to Ordering Guide 10 02 Revision 0 Initial Version Rev C Page 2 of 16 ADV7125 SPECIFICATIONS 5 V ELECTRICAL CHARACTERISTICS Vaa 5 V 5 Vre 1 235 V Rser 560 Q Cr 10 pF All specifications Tmn to Tmax unless otherwise noted Ty max 110 C Table 1 Parameter Min Typ Max Unit Test Conditions STATIC PERFORMANCE Resolution Each DAC 8 Bits Integral Nonlinearity BSL 1 0 4 1 LSB Differential Nonlinearity 1 0 25 1 LSB Guaranteed Monotonic DIGITAL AND CONTROL INPUTS Input High Voltage Vin 2 V Input Low Voltage Vit 0 8 V Input Current l n 1 1 yA Vin 0 0 V or Voo PSAVE Pull Up Current 20 yA Input Capacitance Cin 10 pF ANALOG OUTPUTS Output Current 2 0 26 5 mA Green DAC SYNC high 2 0 18 5 mA RGB DAC SYNC low DAC to DAC Matching 1 0 5 Output Compliance Range Voc 0 1 4 V Output Impedance Rout 100 kQ Output Capacitance Cout 10 pF lout 0 MA Offset Error 0 025 0 025 FSR Tested with DAC output 0 V Gain Error 5 0 5 0 FSR FSR 18 62 mA VOLTAGE REFERENCE EXTERNAL AND INTERNAL Reference Range Vrer 1 12 1 235 1 35 V POWER DISSIPATION Digital Supply Current 3 4 9 mA fak 50 MHz 10 5 15 mA fak 140 MHz 18 25 mA fax 240 MHz Analog Supply Current 67 72 mA Rser 530 Q 8 mA Rset 4933 Q Standby Supply Current 2 1 5 0 mA PSAVE low dig
18. ital and control inputs at Voo Power Supply Rejection Ratio 0 1 0 5 1 Temperature range Tmn to Tmax 40 C to 85 C at 50 MHz and 140 MHz 0 C to 70 C at 240 MHz and 330 MHz 2 Gain error Measured FSC Ideal FSC 1 x 100 where Ideal Vrer Rset X K x OXFFH x 4 and K 7 9896 3 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and Vov 4 These maximum minimum specifications are guaranteed by characterization in the 4 75 V to 5 25 V range Rev C Page 3 of 16 ADV7125 3 3 V ELECTRICAL CHARACTERISTICS Vaa 3 0 V to 3 6 V Vre 1 235 V Rser 560 Q Cr 10 pF All specifications Tum to Tmax unless otherwise noted Tj max 110 C Table 2 Parameter Min Typ Max Unit Test Conditions STATIC PERFORMANCE Resolution Each DAC 8 Bits Rset 680 Q Integral Nonlinearity BSL 1 0 5 1 LSB Rset 680 Q Differential Nonlinearity 1 0 25 1 LSB Rser 680 Q DIGITAL AND CONTROL INPUTS Input High Voltage Vin 2 0 V Input Low Voltage Vit 0 8 V Input Current l n 1 1 uA Vin 0 0 V or Voo PSAVE Pull Up Current 20 uA Input Capacitance Cin 10 pF ANALOG OUTPUTS Output Current 2 0 26 5 mA Green DAC SYNC high 2 0 18 5 mA RGB DAC SYNC low DAC to DAC Matching 1 0 Output Compliance Range Voc 0 14 V Output Impedance Rout 70 kQ Output Capacitance Cout 10 pF Offset Error 0 0 FSR Te
19. periods may affect device reliability 1 Analog output short circuit to any power supply or common GND can be of an indefinite duration ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge y without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev C Page 7 of 16 ADV7125 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6 Pin Function Descriptions 38 PSAVE 37 Rget o x on t 46 R5 45 R4 44 R3 43 R2 42 R1 41 RO 40 GND 39 GND GND 1 l Oe NG 36 VREF GND 24 INDICATOR 35 COMP Go 3 34 IOR Gi 41 33 IOR G2 sh 32 IOG c3 ep ADV7125 31 10G G4 70 TOP VIEW 30 Vaa G5 8 l Not to Scale 29 VAa G6 oH 28 IOB G7 101 27 IOB BLANK 11 26 GND SYNC 12 25GND 2TH Sr esgngRgyR eo 98a aka oaaSs gt 00 o 3 NOTES 1 THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND Figure 3 Pin Configuration Pin Number Mnemonic Description 1 2 14 15 25 GND Ground All GND pins must be connected 26 39 40 3 to 10 16 to GO to G7 Red Green and Blue Pixel Data Inputs TTL Compatible Pixel data is latched on the rising edge of 23 41 to 48 BO to B7 CLOCK RO GO and BO a
20. re the least significant data bits Unused pixel data inputs should be RO to R7 connected to either the regular printed circuit board PCB power or ground plane 11 BLANK Composite Blank Control Input TTL Compatible A Logic 0 on this control input drives the analog outputs IOR IOB and IOG to the blanking level The BLANK signal is latched on the rising edge of CLOCK While BLANK is a Logic 0 the RO to R7 GO to G7 and BO to B7 pixel inputs are ignored 12 SYNC Composite Sync Control Input TTL Compatible A Logic 0 on the SYNC input switches off a 40 IRE current source This is internally connected to the IOG analog output SYNC does not override any other control or data input therefore it should only be asserted during the blanking interval SYNC is latched on the rising edge of CLOCK If sync information is not required on the green channel the SYNC input should be tied to Logic 0 13 29 30 Vaa Analog Power Supply 5 V 5 AIl Vaa pins on the ADV7125 must be connected 24 CLOCK Clock Input TTL Compatible The rising edge of CLOCK latches the RO to R7 G0 to G7 BO to B7 SYNC and BLANK pixel and control inputs It is typically the pixel clock rate of the video system CLOCK should be driven by a dedicated TTL buffer 33 31 27 TOR IOG IOB Differential Red Green and Blue Current Outputs High Impedance Current Sources These RGB video outputs are specified to directly drive RS 343A and RS 170 video levels into a doubly termina
21. sted with DAC output 0V Gain Error 0 FSR FSR 18 62 mA VOLTAGE REFERENCE EXTERNAL Reference Range Vrer 1 12 1 235 1 35 V VOLTAGE REFERENCE INTERNAL Voltage Reference VreF 1 235 V POWER DISSIPATION Digital Supply Current 2 2 5 0 mA fak 50 MHz 6 5 12 0 mA fak 140 MHz 11 15 mA fak 240 MHz 16 mA fak 330 MHz Analog Supply Current 67 72 mA Rser 560 Q 8 mA Rset 4933 Q Standby Supply Current 2 1 5 0 mA PSAVE low digital and control inputs at Voo Power Supply Rejection Ratio 0 1 0 5 1 Temperature range Tmn to Tmax 40 C to 85 C at 50 MHz and 140 MHz 0 C to 70 C at 240 MHz and 330 MHz 2 These max min specifications are guaranteed by characterization in the 3 0 V to 3 6 V range 3 Gain error Measured FSC Ideal FSC 1 x 100 where Ideal Vrer Rset x K x OxFFH x 4 and K 7 9896 Digital supply is measured with continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and Vpp Rev C Page 4 of 16 5 V TIMING SPECIFICATIONS ADV7125 Vaa 5 V 5 Vre 1 235 V Rser 560 Q Ci 10 pF All specifications Tmn to Tmax unless otherwise noted Tj max 110 C Table 3 Parameter Symbol Min Typ Max Unit Conditions ANALOG OUTPUTS Analog Output Delay te 5 5 ns Analog Output Rise Fall Time t7 1 0 ns Analog Output Transition Time ts 15 ns Analog Output Skew to 1 2 ns CLOCK CONTROL CLOCK Frequency fck 0 5 50 MHz
22. te Video Formats and Required Load Terminations available from Analog Devices at www analog com Rev C Page 12 of 16 Figure 5 shows the video waveforms associated with the three RGB outputs driving the doubly terminated 75 Q load of Figure 6 As well as the gray scale levels black level to white level Figure 5 also shows the contributions of SYNC and BLANK for the ADV7125 These control inputs add appro priately weighted currents to the analog outputs producing the specific output level requirements for video applications Table 7 details how the SYNC and BLANK inputs modify the output levels GRAY SCALE OPERATION The ADV7125 can be used for standalone gray scale mono chrome or composite video applications that is only one channel used for video information Any one of the three channels red green or blue can be used to input the digital video data The two unused video data channels should be tied to Logic 0 The unused analog outputs should be terminated with the same load as that for the used channel that is if the red channel is used and IOR is terminated with a doubly terminated 75 Q load 37 5 Q IOB and IOG should be terminated with 37 5 Q resistors see Figure 8 03097 008 Figure 8 Input and Output Connections for Standalone Gray Scale or Composite Video VIDEO OUTPUT BUFFERS The ADV7125 is specified to drive transmission line loads The analog output configuration to drive such loa
23. ted 75 Q load If the complementary outputs are not required these outputs should be tied to ground 34 32 28 IOR IOG IOB Red Green and Blue Current Outputs These high impedance current sources are capable of directly driving a doubly terminated 75 Q coaxial cable All three current outputs should have similar output loads whether or not they are all being used 35 COMP Compensation Pin This is a compensation pin for the internal reference amplifier A 0 1 uF ceramic capacitor must be connected between COMP and Vaa 36 VREF Voltage Reference Input for DACs or Voltage Reference Output 1 235 V Rev C Page 8 of 16 ADV7125 Pin Number Mnemonic Description 37 Rset A resistor Rset connected between this pin and GND controls the magnitude of the full scale video signal Note that the IRE relationships are maintained regardless of the full scale output current The relationship between Rser and the full scale output current on IOG assuming Isync is connected to IOG is given by Rser Q 11 445 x Vre V IOG mA The relationship between Rser and the full scale output current on IOR IOG and IOB is given by IOG mA 11 444 8 x Veer V Rser Q SYNC being asserted IOR IOB mA 7989 6 x Vrer V Rser Q The equation for IOG is the same as that for IOR and IOB when SYNC is not being used that is SYNC tied permanently low 38 PSAVE Power Save Control Pin Reduced power consumption is available on
24. to the PCB layout Figure 10 shows a recommended connection diagram for the ADV7125 The layout should be optimized for lowest noise on the ADV7125 power and ground lines This can be achieved by shielding the digital inputs and providing good decoupling Shorten the lead length between groups of Vaa and GND pins to minimize inductive ringing It is recommended to use a 4 layer printed circuit board with a single ground plane The ground and power planes should separate the signal trace layer and the solder side layer Noise on the analog power plane can be further reduced by using multiple decoupling capacitors see Figure 10 Optimum performance is achieved by using 0 1 uF and 0 01 uF ceramic capacitors Individually decouple each Vaa pin to ground by placing the capacitors as close as possible to the device with the capacitor leads as short as possible thus minimizing lead inductance It is important to note that while the ADV7125 contains circuitry to reject power supply noise this rejection decreases with frequency If a high frequency switching power supply is used pay close attention to reducing power supply noise A dc power supply filter Murata BNX002 provides EMI suppression between the switching power supply and the main PCB Alternatively consideration can be given to using a 3 terminal voltage regulator DIGITAL SIGNAL INTERCONNECT Isolate the digital signal lines to the ADV7125 as much as possible from the analog outputs
25. y described in the Digital Inputs section It is recommended that the CLOCK input to the ADV7125 be driven by a TTL buffer for example the 74F244 WHITE LEVEL BLANK LEVEL SYNC LEVEL 03097 005 Figure 5 Typical RGB Video Output Waveform Rev C Page 11 of 16 ADV7125 Table 7 Typical Video Output Truth Table Rser 530 Q Rioap 37 5 Q Video Output Level 10G mA 10G mA IOR IOB mA IOR IOB mA SYNC BLANK DAC Input Data White Level 26 0 0 18 67 0 1 1 OxFFH Video Video 7 2 18 67 Video Video 18 67 Video 1 1 Data Video to BLANK Video 18 67 Video Video 18 67 Video 0 1 Data Black Level 7 2 18 67 0 18 67 1 1 0x00H Black to BLANK 0 18 67 0 18 67 0 1 Ox00H BLANK Level 7 2 18 67 0 18 67 1 0 OxXXH don t care SYNC Level 0 18 67 0 18 67 0 0 OxXXH don t care VIDEO SYNCHRONIZATION AND CONTROL The ADV7125 has a single composite sync SYNC input control Many graphics processors and CRT controllers have the ability to generate horizontal sync HSYNC vertical sync VSYNC and composite SYNC In a graphics system that does not automatically generate a composite SYNC signal the inclusion of some additional logic circuitry enables the generation of a composite SYNC signal The sync current is internally connected directly to the IOG output thus encoding video synchronization information onto the green video channel If it is not required to encode sync
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ANALOG DEVICES ADV7125 English products handbook Rev C