ANALOG DEVICES AD5582/AD5583 English products handbook Rev A
Contents
1. Parameter Symbol Condition Min Typ Max Unit STATIC PERFORMANCE Resolution N AD5582 12 Bits AD5583 10 Bits Relative Accuracy INL 1 1 LSB Differential Nonlinearity DNL Monotonic 1 LSB Zero Scale Error VzsE Data 000y for AD5582 2 2 LSB and AD5583 Gain Error Nor Data 0xFFFy for AD5582 2 2 LSB VGE Data 0x3FFy for AD5583 A 4 LSB Full Scale Tempco TCVrs 1 5 ppm C REFERENCE INPUT VperH Input Range VREFH Nern 0 5 Vpp V Var Input Range VREFL Vss VkerH 0 51 V Input Resistance Born Data 555p Minimum Rprr 12 20 kQ for AD5582 and 155p for AD5583 Input Capacitance CREF 80 pF REF Input Current pEF Data 555y for AD5582 1000 HA REF Multiplying Bandwidth BWper Code Full Scale 1 3 MHz R1 R2 Matching R1 R2 AD5582 0 025 AD5583 0 100 ANALOG OUTPUT Output Current Loun Data 800y for AD5582 and 2 mA 200H for AD5583 AVour lt 2 mV Output Current Iour Data 8004 for AD5582 and 200y for AD5583 AVour lt l 8 mV 20 mA Capacitive Load 7 CL No Oscillation Note 7 pF REV A 3 AD5582 AD5583 ELECTRICAL CHARACTERISTICS continued Parameter Symbol Condition Min Typ Max Unit LOGIC INPUTS OUTPUTS Logic Input Low Voltage Vir 0 8 V DVpp 3 V 10 0 4 V Logic Input High Voltage Vim 2 4 V DVpp 3 Vt 10 2 1 V Input Leakage Current In HA Input Capacitance Cr pF Output Voltage High Non Lon 0 8 mA 2 4 V Output Voltage Low VoL Lo 1 2 mA TA 85 C 02. FFFy 0 8004 4004 2004 1004 24 0804 0404 0204 0104 0084 0044 0024 0014 b o ATTENUATION dB I N N 0004 96 100 1k 10k 100k 1M 10M FREQUENCY Hz TPC 25 AD5582 Multiplying Bandwidth AD5582 AD5583 0 8 Vpp 5V 0 6 L Vss 5V VaEFH 4V 0 4 L REFL 4V d ZSE DRIFT a 0 m 30 m 0 o 30 mz m w 0 2 30 0 4 30 GE DRIFT 0 6 0 8 0 100 200 300 400 500 600 HOURS OF OPERATION AT 150 C TPC 26 AD5582 Long Term Drift Test Circuit Test Circuit 1 THEORY OF OPERATION The AD5582 AD5583 are quad voltage output 12 10 bit parallel input DACs in compact TSSOP 48 packages Each DAC is a voltage switching high impedance R 20 kQ R 2R ladder configuration with segmentation to optimize die area and precision Figure 3 shows a simplified R 2R structure without the segmentation The 2R resistances are switched between Vkerr and Veerr and the output is obtained from the rightmost ladder node As the code is sequenced through all possible states the voltage of this node changes in steps of 2 3 Vpern Map 12 1 starting from the lowest Vperr and going to the highest Vgern DUTLSB Buffering it with an amplifier with a gain of 1 5 brings the output to Vour Verra V
3. SEATING 0 20 0 45 BSC 0 17 PLANE lt E COMPLIANT TO JEDEC STANDARDS MO 153ED REV A 19 AD5582 AD5583 Revision History Location 8 03 Data Sheet changed from REV 0 to REV A Change to Figure 1 Changes to SPECIFICATIONS Changes to TIMING CHARACTERISTICS Changes to PIN FUNCTION DESCRIPTIONS Changes to Figures 2a 2b 20 REV A A C03040 0 8 03
4. 10 to 90 of 3 V and timed from a voltage level of 1 5 V Specifications subject to change without notice TIMING CHARACTERISTICS Von 15Vor5V Vss 0V Dun 3V 10 Var 10V VREFL 0 V 40 C AT lt 125 C unless otherwise noted Parameter Symbol Condition Min Typ Max Unit INTERFACE TIMING Chip Select Write Pulse Width twes 35 ns Chip Select Read Pulse Width tres 130 ns Write Setup tws 50 ns Write Hold twH 0 ns Address Setup tas 50 ns Address Hold taH 0 ns Load Setup tis 0 ns Load Hold Du 0 ns Write Data Setup twos 50 ns Write Data Hold twpH 0 ns Load Data Pulse Width tipw 35 ns Reset Pulse Width tRESET 35 ns Read Data Hold tRDH 0 ns Read Data Setup RDS 0 ns Data to Hi Z tpz Cy 10 pF 80 100 ns Chip Select to Data tesp Cy 10 pF 80 100 ns Chip Select Repetitive Pulse Width csp 20 ns Load Setup in Double Buffer Mode LDS 35 ns Load Data Hold LDH 0 ns All input control signals are specified with te tp 2 ns 10 to 90 of 3 V and timed from a voltage level of 1 5 V Specifications subject to change without notice REV A AD5582 AD5583 ABSOLUTE MAXIMUM RATINGS Thermal Resistance Junction to Case fr 42 C W Vpop t esibita s Al ya sul k 0 3 V to 18 V Maximum Junction Temperature Ty Max 150 C Vpop to GND qu ma tiene graces Goa 0 3 V to 18 V Package Power Dissipation T Max T y4 Mss tO GND revera sirgst Ma aa ite s 0 3 V to 9 V Op
5. 120 140 0 512 1024 1536 2048 2560 3072 3584 4096 TEMPERATURE C CODE Decimal TPC 14 AD5582 Supply Current vs Temperature TPC 17 AD5582 Referenced Input Resistance 20 Von 5V OR 15V Vpp 5V 0 5V 18 H DVpp 3V Vss 0V ja SN Vper 4V Vpp 5V OR 15V m DATA 8004 7 ss 12 Z a m 40 T S o 8 2 a 5 6 o 4 2 0 0 1 2 3 4 5 10k 100k 1M 10M 100M Vin V CLOCK FREQUENCY Hz TPC 15 AD5582 Supply Current vs Logic Input Voltage TPC 18 AD5582 Supply Current vs Clock Frequency REV A 13 AD5582 AD5583 Vpp 5V 0 5V R vero TLL pene IN 100 Vogt 4V 80 DATA 8004 70 aee e eE V h e 60 SS H AN MAN m 50 m o gt A HH PA Wert m Vour 0 5V DIV 1 10 100 k 10k 100k 1M GRAPH lt 1 gt FREQUENCY Hz GRAPH lt 2 gt w RINGING a 2 F TPC 19 AD5582 PSRR vs Frequency TPC 22 Large Signal Settling VVhen Loaded See Test Circuit 1 qin le DON Vour 0 1V DIV DJ TPC 20 Small Signal Response Operating TPC 23 Midscale Transition Glitch at Near Rail C 2 nF See Test Circuit 1 23004 Z 7285 2300 730 AMPLITUDE pV NOISE DENSITY nV VHz 230 73 23 an 5pS DIV DATA 5V DIV ol _ TPC 21 Large Signal Settling TPC 24 AD5582 Output Noise Density 14 REV A
6. 4 Using On Board Matching Resistors to Generate a Negative Voltage REF Digital UO Digital I O consists of a 12 10 bit bidirectional data bus two register select inputs AO and Al an RW input a Reset RS a Chip Select CS and a Load DAC LDAC input Control of the DACs and the bus direction is determined by these inputs as shown in Table I All digital pins are TTL CMOS compat ible and all internal registers are level triggered The register selects inputs AO and Al Decoding of the registers is enabled by the CS input When CS is high no decoding is taking place and neither the writing nor the reading of the input registers is enabled The loading of the second bank of registers is controlled by the asynchronous LDAC input By taking LDAC low while CS is enabled the individual channel is updated as single buffer mode Figure 2a If CS is enabled sequentially to load data into all input registers then a subsequent LDAC pulse will allow all channels to be updated simultaneously as double buffer mode Figure 2b R W controls the writing to and reading from the input register 16 Reset The RS function can be used either at povver up or at any time during operation The RS function has priority over any other digital inputs This pin is active low and sets the DAC output registers to either zero scale or midscale determined by the state of the MSB The reset to midscale is useful when the DAC is configured for bi
7. 4 V Lo 0 6 mA DVpp 3V VoL IoL 1 0 mA Ta 125 C 0 4 V Tor 0 5 mA DVpp 3V AC CHARACTERISTICS Output Slew Rate SR Data Zero Scale to Full Scale 2 V us to Zero Scale Settling Time ts To 0 1 of Full Scale 14 Hs DAC Glitch Q Code 7FFy to 800p to 7FFy for 100 nV s AD5582 and 1FFy to 200p to 1FFy for AD5583 Digital Feedthrough Vour tes Data Midscale CS Toggles at 5 nV s f 16 MHz Analog Crosstalk VouT VREF VkeF 1 5 V dc 1 Vp p 80 dB Data 000y f 100 kHz Output Noise en f 1 kHz 33 nV VHz SUPPLY CHARACTERISTICS Single Supply Voltage Range Vpp Vss 0 V 3 16 5 V Dual Supply Voltage Range Vpp Vss Vpp 2 7 V to 6 5 V 0 5 46 5 V Vss 6 5 V to 2 7 V Digital Logic Supply DVpp 2 7 6 5 V Positive Supply Current Ipp Nu 0 V No Load 2 3 3 5 mA Power Dissipation Ppiss Nu 0 V No Load 34 5 52 5 mW Power Supply Sensitivity PSS AVpp 5 30 ppm V NOTES VTypical specifications represent average readings measured at 25 C 2DAC Output Equation Vour Vasey Vpern Non X D 2N where D data in decimal loaded in corresponding DAC Register A B C D and N equals the number of bits AD5582 12 bits AD5583 10 bits One LSB step voltage Vern VpErL 4096 V and VperH VReru 1024 V for AD5582 and AD5583 respectively 3The first two codes 0009 00143 of the AD5583 and the first four codes 0004 00144 00241 0034 of the AD5582 are excluded from the linearity error measurement in singl
8. Chip Select Active Low 11 RI RI Terminal for Negative Reference 35 RW Read Write Mode Select 12 RCT Center Tap Terminal for Negative Reference 36 1 DGND3 Digital Ground 3 13 R2 R2 Terminal for Negative Reference 37 Vss3 Negative Power Supply for Analog Switches 14 DVpp Power Supply for Digital Circuits 38 Vpp3 Positive Power Supply for Analog Switches 15 ILDAC DAC Register Load Active Low Level Sensitive 30 VhEFLD DAC D Voltage Reference Low Terminal 16 RS Reset Strobe 40 VherHD DAC D Voltage Reference High Terminal 17 MSB MSB 0 Reset to 000p 41 VperHc DAC C Voltage Reference High Terminal MSB 1 Reset to 8004 42 VperLc DAC C Voltage Reference Low Terminal 18 DBO Data Bit 0 43 INC No Connect 19 D I Data Bit 1 44 VOD DAC D Output 20 DB2 Data Bit 2 45 Vss Negative Power Supply for DAC C and D 21 DB3 Data Bit 3 46 Vpp2 Positive Power Supply for DAC C and D 22 IDGNDI Digital Ground 1 47 VOC DAC C Output 23 DB4 Data Bit 4 48 AGND2 Analog Ground for DAC C and D 24 DB5 Data Bit 5 AD5582 optimizes internal layout design to reduce die area so that all supply voltage pins are required to be connected externally See Figure 5 REV A AD5582 AD5583 AD5583 PIN CONFIGURATION NC NO CONNECT AD5583 PIN FUNCTION DESCRIPTIONS Pin Pin No Mnemonic Description No Mnemonic Description 1 1AGNDI Analog Ground for DAC A and B 25 DB4 Data Bit 4 2
9. Negative Power Supply for DAC C and D other than Dummy Pad 46 Vpp2 Positive Power Supply for DAC C and D 20 DBO Data Bit 0 47 VOC DAC C Output 21 DBI Data Bit 1 48 AGND2_ Analog Ground for DAC C and D 22 DGND1 _ Digital Ground 1 23 DB2 Data Bit 2 24 DB3 Data Bit 3 AD5583 optimizes internal layout design to reduce die area so that all supply voltage pins are required to be connected externally See Figure 5 REV A AD5582 AD5583 TIMING DIAGRAMS tesp 10ns 1 1 ta tas 35ns l L I ADDRESS 1 ONE ADDRESS ADDRESS FOUR LDAC l twpH Ons gt l 1 DATA IN Figure 2a Single Buffer Mode Output Updated Individually DVpp 5 V tesp 10ns twcs 20ns a typ Ons La tws 35ns l ADDRESS l FOUR ADDRESS ADDRESS ONE ADDRESS THREE i LpH Ons 1 Lpsz Ons gt l I l l l l 1 1 1 l l l twps 35ns 1 DATA IN Figure 2b Double Buffer Mode Output Updated Simultaneously DVpp 5 V REV A 9 AD5582 AD5583 l l twes 20ns U CS l l 1 1 gt L4 tws 35ns twp Ons RAW l l pl tg 35ns gt a tay Ons A0 A1 l l tipw 20ns l l bus Ons l eeneg 1 LDAC 1 l I ji twps 35ns twoH Ons DATA IN treseT 20ns RS Figure 2c Data Write Input and Output Registers Timing La trcg 130ns
10. __p l 1 1 l l l taps 35ns gt npH Ons l l RAW 1 1 l l l 1 tas 35ns weg tan Ons e AO A1 l l l 1 tesp 100ns MAX w a I4 tpz 100ns MAX DATA OUT HI Z HI Z j Figure 2d Data Output Read Timing 10 REV A Typical Performance Characteristics AD5582 AD5583 1 0 1 0 0 8 0 8 0 6 0 6 0 4 0 4 s 72 e 02 o N d o o z l z z 0 2 D 0 2 0 4 0 4 0 6 0 6 0 8 0 8 1 0 1 0 O 512 1024 1536 2048 2560 3072 3584 4096 0 128 256 384 512 640 768 896 1024 CODE Decimal CODE Decimal TPC 1 AD5582 Integral Nonlinearity Error TPC 4 AD5583 Differential Nonlinearity Error 1 0 Vpp 5V 0 8 Vss 0V VprerL OV 0 6 NO LOAD 0 4 0 2 DNL LSB o ERROR LSB 0 2 0 4 0 6 0 8 h 512 1024 1536 2048 2560 3072 3584 4096 0 5 10 15 20 25 30 CODE Decimal Von VherH mV TPC 2 AD5582 Differential Nonlinearity Error TPC 5 AD5582 INL DNL ZSE and GE at Positive Rail to Rail Operation Vpp AEN Vss 5V VaerH 4V NO LOAD INL LSB ERROR LSB 0 128 256 384 512 640 768 896 1024 e 5 10 15 20 25 30 35 CODE Decimal VRErL Vss mv TPC 3 AD5583 Integral Nonlin
11. zero scale All X X X 1 X l All registers latched to midscale or zero scale All MSB 0 resets to zero scale MSB 1 resets to midscale X Don t Care Input and output registers are transparent when asserted compliance is mainly limited by the op amp supply voltages This circuit is versatile but users must pay attention to the This circuit can be used in 4 to 20 mA current transmitters with compensation Without Cl it can be shown that the output up to 500 Q of load impedance becomes FU R3 R1 R2 Rt R zo 5 150k0 15k0 R1 R2 R3 RV R24 R3 If the resistors are perfectly matched Zo is infinite which is highly desirable On the other hand if they are not matched Zo pa can either be positive or negative The latter because of the pole in the right S plane can cause oscillation As a result C1 in the range of a few pF is needed to prevent the oscillation For critical applications C1 should be found empirically without overcompensating VaeFH pp Boosted Programmable Voltage Source u2 RCT AD5582 For users who need higher than 20 mA current driving capabil R2 VperL Vss 4 itv thev can add an external op amp and power transistors The m ic capacitive loading capability will change but it can still drive d 100 nF capacitive load without oscillation in this circuit Figure 7 shows a programmable power supply with 200 mA capability Vo FDV30IN Vo E DEC
12. 5582 0 025 AD5583 0 100 ANALOG OUTPUT Output Current lout Data 800y for AD5582 and 2 mA 2004 for AD5583 AVour lt 2 mV Output Current Iour Data 8004 for AD5582 and 200y for AD5583 AVour lt l 8 mV 20 mA AVour lt 15mV 20 mA Capacitive Load 7 CL No Oscillation Note 7 pF LOGIC INPUTS Logic Input Low Voltage Vi DVpp 5 V 10 0 8 V DVpp 3V 10 0 4 V Logic Input High Voltage Vin DVpp 5 V 10 2 4 V DVpp 3 Vt 10 2 1 V Input Leakage Current In 0 01 1 HA Input Capacitance CL 5 pF Output Voltage High Vou Iou 0 8 mA 2 4 V Output Voltage Low VoL Lou 1 2 mA TA 85 C 0 4 V IoL 0 6 mA DVpp 3V ToL 1 0 mA TA 125 C 0 4 V Ion 70 5 mA DVpp 3V AC CHARACTERISTICS Output Slew Rate SR Data Zero Scale to Full Scale 2 Mis to Zero Scale Settling Time ts To 0 1 of Full Scale 5 Hs DAC Glitch Q Code 7FFy to 800z to 7FFu 100 nV s for AD5582 and 1FFy to 2004 to 1FFy for AD5583 Digital Feedthrough Vour tes Data Midscale CS Toggles at 5 nV s f 16 MHz Analog Crosstalk Vour Vrer Vrer 1 5 V dc 1 Vp p 80 dB Data 000p f 100 kHz Output Noise en f 1 kHz 33 nV VHz REV A AD5582 AD5583 Parameter Symbol Condition Min Typ Max Unit SUPPLY CHARACTERISTICS Single Supply Voltage Range Vpp Vss 0 V 2 18 V Dual Supply Voltage Range Vpp Vss Vpp 2 7 V to 6 5 V 9 9 V Vss 6 5 V to 2 7 V Digital Logic Supply DVpp 2 7 8 V Positive Supply Current I
13. ANALOG DEVICES Quad Parallel Input Voltage Output 12 10 Bit Digital to Analog Converters AD5582 AD5583 FEATURES 12 Bit Linearity and Monotonic AD5582 10 Bit Linearity and Monotonic AD5583 Wide Operating Range Single 5 V to 15 V or Dual 5 V Supply Unipolar or Bipolar Operation Double Buffered Registers Enable Independent or Simultaneous Multichannel Update 4 Independent Rail to Rail Reference Inputs 20 mA High Current Output Drive Parallel Interface Data Readback Capability 5 us Settling Time Built In Matching Resistor Simplifies Negative Reference Unconditionallv Stable Under Anv Capacitive Loading Compact Footprint TSSOP 48 Extended Temperature Range 40 C to 125 C APPLICATIONS Process Control Equipment Closed Loop Servo Control Data Acquisition Systems Digitally Controlled Calibration Optical Network Control Loops 4 m to 20 mA Current Transmitter GENERAL DESCRIPTION The AD5582 AD5583 family of quad 12 10 bit voltage output digital to analog converters is designed to operate from a single 5 V to 15 V or dual 5 V supply It offers the user ease of use in single or dual supply systems Built using an advance BICMOS process this high performance DAC is dynamically stable capable of high current drive and in small form factor The applied external reference Nor determines the full scale out put voltage ranges from Vss to Vpp resulting in a wide selection of full scale outputs For m
14. OUPLING CAPS ARE OMITTED FOR CLARITY o 5V 5V u1 4 096V z 2 maps REF198 Figure 6 Programmable Current Source with Bidirectional V Vi Current Control and High Voltage Compliance Capabilities a SC us 7 Figure 6 shows that if the resistor network is matched the load n current is z n R2 R3 RI L7 RB DAC 4 DECOUPLING CAPS ARE OMITTED FOR CLARITY R3 in theory can be made small to achieve the current needed Figure e Boosien Programmable valage sOureg within the U4 output current driving capability In this circuit the AD8510 can deliver 20 mA in both directions and the voltage compliance approaches 15 V REV A 17 AD5582 AD5583 AD5582 Vss1 TO 3 VOA VOB Vppl TO 3 VOC VOD DECOUPLING CAPS ARE OMITTED FOR CLARITY Figure 8 Programmable PGA In this circuit the inverting input of the op amp forces the Vo to be equal to the DAC output The load current is then delivered by the supply via the N Ch FET NI U3 needs to be a rail to rail input type With a Vpp of 5 V this circuit can source a maximum of 200 mA at 4 096 V full scale 100 mA at midscale and 50 mA near zero scale outputs Higher current can be achieved with N1 in a larger package mounted on a heat sink Programmable PGA The AD603 is a low noise voltage controlled amplifier for use in RF and IF AGC automatic gain control systems It provides accurate pin selectable gains of 11 dB to 31 dB with a band wid
15. VOB DAC B Output 26 DB5 Data Bit 5 3 Mon Positive Power Supply for DAC A and B 27 IDGND2 Digital Ground 2 4 Maer Negative Power Supply for DAC A and B 28 DB6 Data Bit 6 5 VOA DAC A Output 29 DB7 Data Bit 7 6 NC No Connect Do Not Connect Anything 30 DB8 Data Bit 8 other than Dummy Pad 31 DB9 Data Bit 9 7 1 VhEFLB DAC B Voltage Reference Low Terminal 32 AO Address Input 0 8 1 VherHB DAC B Voltage Reference High Terminal 33 Al Address Input 1 9 VREFHA DAC A Voltage Reference High Terminal 34 CS Chip Select Active Low 10 VkEFLA DAC A Voltage Reference Low Terminal 35 RW Read Write Mode Select 11 1R1 RI Terminal for Negative Reference 36 DGND3 _ Digital Ground 3 12 RCT Center Tap Terminal for Negative Reference 37 Vss3 Negative Power Supply for Analog Switches 13 R2 R2 Terminal for Negative Reference 38 Vpps Positive Power Supply for Analog Switches 14 DVpp Power Supply for Digital Circuits 39 Neen DAC D Voltage Reference Low Terminal 15 LDAC DAC Register Load Active Low Level Sensitive 40 VREFuD DAC D Voltage Reference High Terminal 16 IRS Reset Strobe 41 VkEruHc DAC C Volrage Reference High Terminal 17 MSB MSB 0 Reset to 000p 42 VREFLC DAC C Voltage Reference Low Terminal MSB 1 Reset to 200q 43 NC No Connect Do Not Connect Anything 18 INC No Connect Do Not Connect Anything other than Dummy Pad other than Dummy Pad 44 VOD DAC D Output 19 INC No Connect Do Not Connect Anything 45 Noe
16. con nected externally See Figure 5 AD5582 AD5583 Figure 5 Power Supply Configurations APPLICATIONS Programmable Current Source AD5582 AD5583 high current capability allow them to be used directly in programmable current source applications such as 4 m to 20 mA current transmitter and other general purpose applications For higher compliance voltage that is higher than 15 V Figure 6 shows a versatile V I conversion circuit using an improved Howland Current Pump In addition to the precision current conversion it provides this circuit enables a bidirec tional current flow and high voltage compliance The voltage REV A AD5582 AD5583 Table I AD5582 AD5583 Logic Table INPUT DAC OPERATION SELECTED Al A0 RW CS LDAC RS REGISTER REGISTER MODE DAC 0 0 0 0 0 1 Write Transparent Transparent A 0 1 0 0 0 1 Write Transparent Transparent B 1 0 0 0 0 1 Write Transparent Transparent C 1 1 0 0 0 1 Write Transparent Transparent D 0 0 0 0 1 1 Write Hold Write Input A 0 1 0 0 1 1 Write Hold Write Input B 1 0 0 0 1 1 Write Hold Write Input C 1 1 0 0 1 1 Write Hold Write Input D 0 0 1 0 1 1 Read Hold Readback to DO to DN A 0 1 1 0 1 1 Read Hold Readback to DO to DN B 1 0 1 0 1 1 Read Hold Readback to DO to DN C 1 1 1 0 1 1 Read Hold Readback to DO to DN D X X X 1 0 1 Hold Update All Registers Update All Registers All X X X 1 1 1 Hold Hold Hold All X X X X X 0 All registers reset to midscale or
17. e Loads TPC 11 AD5582 Linearity Errors vs Differential Reference Ranges 0 2 00 2 H T 195 Vpp 5V OR 15V S 4 Vss 5V OR OV Veg OV VREFH 4V 1 85 VaEFH 4V T VrerL OV 2 a _ 1 80 e a Vpp 5V g 8 E 1 75 Vss 5V T Vpp 15V 8 een Z 40 Vss OV 1 70 3 VaerH 10V Vert ON 1 65 12 1 60 14 RESISTIVE LOAD R IS BETWEEN Vout AND GND 1 55 16 l l LI 1 50 100 1k 10k 100k 0 2 4 6 8 1012 14 16 Von V TPC 9 AD5582 Gain Error vs Resistive Load TPC 12 AD5582 Supply Current vs Supply Voltage 12 REV A AD35582 AD5583 3 5 300 3 0 EY 2 5 b 200 LU E SS E O 150 Q VREFL 75V L B 1 5 LU Vpp AEN 100 1 0 Vss 0V m VreFL OV m 50 0 5 0 0 10 5 0 5 10 15 20 0 512 1024 1536 2048 2560 3072 3584 4096 VaerH V CODE Decimal TPC 13 AD5582 Supply Current vs Reference Voltage TPC 16 AD5582 Reference Current 4 0 Vpp 15V ae Vss ON Vasen 10V VperL OV 3 0 REFL d 2 5 A S 20 ii 8 ar 1 5 Vpp z AEN Vss 5V 1 0 VaerH 4V VaerL ON 0 5 0 60 40 20 0 20 40 60 80 100
18. e supply operation These parameters are guaranteed by design and not subject to production testing gt Dual supply operation Vper Vss exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors Short circuit output and supply currents are 24 mA and 25 mA respectively Part is stable under any capacitive loading conditions 5The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation Specifications subject to change without notice REV A TIMING CHARACTERISTICS unless otherwise noted AD5582 AD5583 Von 15Vor5V Vss V Dun 5V 10 Noen 10V Noen 0V 40 C lt Th lt 125 C Parameter Symbol Condition Min Typ Max Unit INTERFACE TIMING Chip Select Write Pulse Width twes 20 ns Chip Select Read Pulse Width RCS 130 ns Write Setup tws 35 ns Write Hold twH 0 ns Address Setup tas 39 ns Address Hold tay 0 ns Load Setup tis 0 ns Load Hold LH 0 ns Write Data Setup twps 35 ns Write Data Hold twpH 0 ns Load Data Pulse Width LDV 20 ns Reset Pulse VVidth RESET 20 ns Read Data Hold RDH 0 ns Read Data Setup RDS 0 ns Data to Hi Z pz C 10 pF 100 ns Chip Select to Data csD C 10 pF 100 ns Chip Select Repetitive Pulse Width tcsp 10 ns Load Setup in Double Buffer Mode tips 20 ns Load Data Hold LDH 0 ns AU input control signals are specified with tp tp 2 ns
19. earity Error TPC 6 AD5582 INL DNL GE and ZSE at Negative Rail to Rail Operation REV A 11 AD5582 AD5583 1 0 40 Vpp 5V 0 8 Vss 5V a VaerH 4V D I v 0V k R NO LOAD 20 0 4 a 10 0 2 5 4 0 c 0 i o m z m 0 2 H 0 0 4 e GAIN 0 6 ERROR 0 8 RESISTIVE LOAD R IS BETWEEN PULL UP RESISTIVE LOAD R Vout AND GND IS BETWEEN V pp AND V our 1 0 l 40 L L T T L L i LLL O 512 1024 1536 2048 2560 3072 3584 4096 100 1k 10k 100k 1M CODE Decimal PPU 0 TPC 7 AD5582 INL at Various Resistive Loads TPC 10 AD5582 Gain and Zero Scale Error vs Pull Up Resistive Loads 0 5 Vpp 5V 5 0 0 4 Vss 5V Vrern 4V k 0 3 VheFL OV 4 0 0 2 m R NO LOAD 3 5 04 m 3 0 al m a H 25 z D 31 A s e 20 0 2 k Z 15 0 3 INL 1 0 _o 4 RESISTIVE LOAD R IS BETWEEN DNL Vour AND GND 0 5 0 5 0 512 1024 1536 2048 2560 3072 3584 4096 0 CODE Decimal 0 2 4 6 8 10 12 VREFH VREFL V TPC 8 AD5582 DNL at Various Resistiv
20. ement in medium voltage applications in new designs as well as anv other general purpose multichannel 10 to 12 bit applications The AD5582 AD5583 are specified over the extended industrial 40C to 125 C temperature range and offered in a thin and compact 1 1 mm TSSOP 48 package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD3982 AD5983 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Dim m Vss 5V Dun 5V 10 Von 42 5 V Vor 2 5 V 40 C lt Ta lt 125 C unless otherwise noted Parameter Symbol Condition Min Typ Max Unit STATIC PERFORMANCE Resolution N AD5582 12 Bits AD5583 10 Bits Relative Accuracy INL 1 1 LSB Differential Nonlinearity DNL Monotonic LSB Zero Scale Error VzsE Data 0004 for AD5582 2 2 LSB and AD5583 Gain Error VsE Data 0xFFFy for AD5582 2 2 LSB VGE Data 0x3FFy for AD5583 4 4 LSB Gain Error VGE Vpp 2 7 V to 4 5 V i 4 LSB Full Scale Tempco TCVks 1 5 ppm C REFERENCE INPUT VperH Input Range VREFH VerL 0 5 Vpp V VREFL Input Range VREFL Vss VkerH 0 5 V Input Resistance Rrer Data 555y Minimum Rper 12 20 kQ for AD5582 and 155y for AD5583 Input Capacitance CREF 80 pF REF Input Current pEF Data 555y for AD5582 500 HA REF Multiplying Bandwidth BWper Code Full Scale 13 MHz R1 R2 Matching R1 R2 AD
21. erating Temperature Range 40 C to 125 C Npp tO VRERE entes taulei nei e S S 0 3 V to 18 V Storage Temperature Range 65 C to 150 C A 7 tO Vss dee anda iae deeb dh a aa a oa 0 3 V to 18 V Lead Temperature A a tO Mamer oeii m i a a E 0 3 V to 18 V RV 48 Soldering 60 secs 300 C DV pp t9 GND suyu ya hale qatel a 8V Stresses above those listed under Absolute Maximum Ratings may cause perma Logic Inputs to GND Vss 0 3 V Vpp 0 3 V nent damage to the device This is a stress rating only functional operation of the Vourto GND Vss 0 3 V Vpp 0 3 V device at these or any other conditions above those indicated in the operational Tour Short Circuit to GND 24 mA sections of this specification is not implied Exposure to absolute maximum rating Thermal Resistance Junction to Ambient Oja 0021 115 C W conditions for extended periods may affect device reliability ORDERING GUIDE Resolution Temperature Package Package Container Top Model Bits Range Description Option Quantity Marking AD5582YRV REEL 12 40 C to 125 C TSSOP 48 RV 48 2500 AD5582Y AD5583YRV REEL 10 40 C to 125 C TSSOP 48 RV 48 2500 AD5583Y AD5582YRV 12 40 C to 125 C TSSOP 48 RV 48 39 AD5582Y AD5583YRV 10 40 C to 125 C TSSOP 48 RV 48 39 AD5583Y NOTES The AD5582 contains 4116 transistors The die size measur
22. es 108 mil X 144 mil First row marking is shown in the table above Second row marking contains date code in YYWW format Third row marking contains the lot number CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily WARNING i accumulate on the human body and test equipment and can discharge without detection Although the AD5582 AD5583 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are E recommended to avoid performance degradation or loss of functionality SENSITIVE DEVICE 6 REV A AD5582 AD5583 AD5582 PIN CONFIGURATION NC NO CONNECT AD5582 PIN FUNCTION DESCRIPTIONS Pin Pin No Mnemonic Description No Mnemonic Description 1 JAGNDI Analog Ground for DAC A and B 25 DB6 Data Bit 6 2 VOB DAC B Ourput 26 DB7 Data Bit 7 3 Vpp1 Positive Power Supply for DAC A and B 27 DGND2 Digital Ground 2 4 Vssi Negative Power Supply for DAC A and B 28 DB8 Data Bit 8 5 VOA DAC A Output 29 DBO Data Bit 9 6 NC No Connect 30 DB10 Data Bit 10 7 VREFLB DAC B Voltage Reference Low Terminal 31 DB11 Data Bit 11 8 VheFHB DAC B Voltage Reference High Terminal 32 AO Address Input 0 9 VREFHA DAC A Voltage Reference High Terminal 33 Al Address Input 1 10 1 VkEFLA DAC A Voltage Reference Low Terminal 34 CS
23. kErL aen 1 where D is the decimal equivalent of the data bits and N is the numbers of bits If Vperr is equal to Vkerz aS Vper Vour is simplified to 2D Voor lb OUT EE REF 2D Vor 1 OUT 2 REF For AD5582 2 For AD5583 3 The advantage of this scheme is that it allows the DAC to inter polate between two voltages for differential references or single ended reference REV A These DACs feature double buffers which allow both synchro nous and asynchronous channels update with additional data readback capability These parts can be reset to zero scale or mid scale controlled by the RS and MSB pins When RS is activated the MSB of 0 resets the DACs to zero scale and the MSB of 1 resets the DACs to midscale The ability to operate from wide supply voltages 5 V to 15 V or 5 V with multiplying bipolar references is another key feature of these DACs Figure 3 Simplified R 2R Architecture Segmentation Not Shown Power Supplies There are three separate power supplies needed for the opera tion of the DACs For dual supply Vss can be set from 6 5 V to 2 7 V and Vpp can be set from 42 7 V to 6 5 V For single supply Vss should be set at 0 V while Vpp is set from 3 V to 16 5 V However setting the single supply of Vpp below 4 5 V can impact the overall accuracy of the device 15 AD5582 AD5583 Since these DACs can be operated at high voltages the digital signal leve
24. ls are therefore controlled separately by the provision of DVpp DVpp can be set as low as 2 7 V but no greater than 6 5 V This allows the DAC to be operable from low level digital signals generated from a wide range of microcontrollers FPGA and signal processors Reference Input All four channels of DACs allow independent and differential reference voltages The flexibility of independent references allows users to apply a unique reference voltage to each channel Similarly bipolar references can be applied across the differential references To maintain optimum accuracy the difference between VherH and Vperr should be greater than 1 V See TPC 11 The voltages applied to these reference inputs set the output voltage limits of all four channels of the DACs and Vperp must always be higher than Neen VperH can be set at any voltage from Neen 0 5 V to Vpp while Vperr can be set at any voltage from Vss to VherH 0 5 V In addition a symmetrical negative reference can be generated easily by an external op amp in an inverting mode with a pair of built in precision resistors RI and R2 These resistors are matched within 0 025 for the AD5582 and 0 1 for the AD5583 which is equivalent to less than 1 LSB mis match Figure 4 shows a simple configuration Common reference or references can be applied to all four chan nels but each reference pin should be decoupled with a 0 1 UF ceramic capacitor mounted close to the pin Figure
25. polar references and the output will be reset to 0 V Output Amplifiers Unlike many voltage output DACs the AD5582 AD5583 feature buffered voltage outputs with high output current driving capa bility Each output is capable of both sourcing and sinking 20 mA eliminating the need for external buffers when driving any capaci tive loads without oscillation These amplifiers also have short circuit protection Glitch The worst case glitch of the AD5582 occurs at the transitions between midscale 1000 0000 0000p to midscale minus 1 0111 1111 11118 or vice versa The glitch energy is mea sured as 100 mV X 1 us or equivalent to 100 nV s Such glitch occurs in a shorter duration than the settling time and therefore most applications will be immune to such an effect without a deglitcher Layout and Power Supply Bypassing It is a good practice to employ compact minimum lead length PCB layout design The leads to the input should be as short as possible to minimize IR drop and stray inductance It is also essential to bypass the power supplies with quality capaci tors for optimum stability Supply leads to the device should be bypassed with 0 01 UF to 0 1 uF disc or chip ceramics capacitors Low ESR 1 uF to 10 uF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance The AD5582 AD5583 optimize internal layout design to reduce die area so that all analog supply pins are required to be
26. pp Vu 0 V No Load 151 3 mA Negative Supplv Current Iss Vu 0 V No Load 1 5 3 mA Power Dissipation Ppiss Vu 0 V No Load 16 30 mW Power Supply Sensitivity Pss AVpp 5 30 ppm V NOTES Typical specifications represent average readings measured at 25 C DAC Output Equation Vour VrerL Vkeru Vperr X D 2N where D data loaded in corresponding DAC Register A B C D and N equals the number of bits AD5582 12 bits AD5583 10 bits One LSB step voltage V geru VpEr 4096 V and Vkeru VneFL9 1024 V for AD5582 and AD5583 respectively gt The first two codes De 0014 of the AD5583 and the first four codes 0004 0014 002 0034 of the AD5582 are excluded from the linearity error measurement in single supply operation These parameters are guaranteed by design and not subject to production testing gt Dual supply operation Noen Vss exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors SShort circuit output and supply currents are 24 mA and 25 mA respectively Part is stable under any capacitive loading conditions 5The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation Specifications subject to change without notice Voo 15 V Vss 0 V Don 5 V 10 Vir 10 V Vir 0 V ELECTRICAL CHARACTERISTICS 40C lt T lt 512571 mees otherwise noted
27. th of 90 MHz or 9 dB to 51 dB with a bandwidth of 9 MHz Any intermediate gain range may be arranged using one external resistor between Pin 5 and Pin 7 The input referred noise spectral density is only 1 3 nV VHz and power consumption is 125 mW at the recommended 5 V supplies BER The decibel gain is linear in dB accurately calibrated and stable over temperature and supply The gain is controlled at a high impedance 50 MQ low bias 200 nA differential input the scaling is 25 mV dB requiring a gain control voltage of only 1 V to span the central 40 dB of the gain range An overrange and underrange of 1 dB is provided whatever the selected range The gain control response time is less than 1 ms for a 40 dB change The differential gain control interface allows the use of either differential or single ended positive or negative control voltages where the common mode range is 1 2 V to 2 0 V The AD5582 AD5583 is ideally suited to provide the differential input range of 1 V within the common mode range of 0 V to 2 V To accomplish this place Vperp at 2 0 V and Vpgry at 1 0 V then all 4096 V levels of the AD5582 will fall within the gain control range of the AD603 Please refer to the AD603 data sheet for further information regarding gain control layout and general operation REV A AD5582 AD5583 OUTLINE DIMENSIONS 48 Lead Thin Shrink Small Outline Package TSSOP RV 48 Dimensions shown in millimeters
28. ultiplying and wide dynamic appli cations ac reference inputs can be as high as Vpp Vssl Two built in precision trimmed resistors are available and can be configured easily to provide four quadrant multiplications A doubled buffered parallel interface offers a fast settling time A common level sensitive load DAC strobe LDAC input allows additional simultaneous update of all DAC outputs An external asynchronous reset RS forces all registers to the zero code state when the MSB 0 or to midscale when the MSB 1 Both parts are offered in the same pinout and package to allow users to select the appropriate resolution for a given application without PCB layout changes REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies AD5582 FUNCTIONAL BLOCK DIAGRAM Vpp3 Vss3 VREFLA VREFHA VREFLB VREFHB ADDR B DECODE CONTROL DGND1 DGND2 DGND3 Vperup VhEFLD VrerHc VREFLC DIGITAL CIRCUITRV OMITTED FOR CLARITV Figure 1 Using Built In Matching Resistors to Generate a Negative Voltage Reference The AD5582 is well suited for DAC8412 replac
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ANALOG DEVICES AD5582/AD5583 English products handbook Rev A