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ANALOG DEVICES AD9734 English products handbook

1. DB9 MSB DB8 Z m m m m m 4 al M lt Figure 4 AD9734 Digital LVDS Input Clock I O View Table 8 AD9734 Pin Function Descriptions Pin No Mnemonic Description A1 A2 A3 B1 B2 B3 C1 C2 C3 D2 D3 CVDD18 1 8V Clock Supply A4 A5 A6 A9 A10 A11 B4 B5 B6 B9 AVSS Analog Supply Ground B10 B11 CA C5 C6 C9 C10 C11 DA D5 D6 D9 D10 D11 A7 B7 C7 D7 IOUTB DAC Negative Output 10 mA to 30 mA full scale output current A8 B8 C8 D8 IOUTA DAC Positive Output 10 mA to 30 mA full scale output current A12 A13 B12 B13 C12 C13 D12 D13 AVDD33 3 3 V Analog Supply A14 DNC Do Not Connect 14 1120 Nominal 1 2 V Reference Tie to analog ground via 10 resistor to generate a 120 pA reference current 614 VREF Band Gap Voltage Reference I O Tie to analog ground via 1 capacitor output impedance approximately 5 kO 01 E2 E3 E4 F2 F3 F4 G1 G2 G3 G4 CVSS Clock Supply Ground D14 IPTAT Factory Test Pin Output current proportional to absolute ET F1 E11 E12 F11 F12 G11 G12 E13 E14 F13 F14 G13 G14 H1 H2 H3 H4 H11 H12 H13 H14 J1 J2 J3 J4 J11 J12 J13 J14 K1 K2 K3 K4 K11 K12 L2 L3 L4 L5 L6 L9 L10 L11 L12 M3 M4 M5 M6 M9 M10 M11 M12 DACCLK DACCLK AVSS IRQ UNSIGNED RESET PD CSB 2x SDIO
2. O O OOOO O O OAVDD33 3 3V ANALOG SUPPLY AVSS ANALOG SUPPLY GROUND 55 ANALOG SUPPLY GROUND SHIELD Figure 5 Analog Supply Pins Top View 123 45 6 7 8 9 10 11 12 13 14 OCVDD18 1 8 CLOCK SUPPLY CVSS CLOCK SUPPLY GROUND Figure 6 Clock Supply Pins Top View 04862 002 04862 003 PIN MODE Rev A Page 16 of 72 uzzr z crommoou vr 123 45 6 7 8 9 10 11 12 13 14 9999 eeoo gt ODVDD18 1 8 DIGITAL SUPPLY DVDD33 3 3V DIGITAL SUPPLY DVSS DIGITAL SUPPLY GROUND 04862 004 Figure 7 Digital Supply Pins View N I
3. CODE CODE Figure 16 AD9736 INL 25 C 20 mA FS Figure 19 AD9736 DNL 25 C 20 mA FS 0 6 0 5 0 4 0 3 0 2 m 01 sj 0 9 Q 01 r4 r4 m 02 0 3 0 4 0 5 o ad 2 0 2048 4096 6144 8192 10240 12288 14336 16384 5 2048 4096 6144 8192 10240 12288 14336 16384 5 CODE 3 CODE Figure 17 AD9736 INL 85 C 20 mA FS Figure 20 AD9736 DNL 85 C 20 mA FS Rev A Page 19 of 72 AD9734 AD9735 AD9736 AD9736 STATIC LINEARITY 30 mA FULL SCALE 2 0 0 6 0 5 1 5 0 4 1 0 0 3 0 2 0 1 eO a 0 1 ERROR LSB ERROR LSB 0 2 1 0 0 3 0 4 0 5 0 6 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE Figure 21 AD9736 INL 40 C 30 mA FS Figure 24 AD9736 DNL 40 C 30 mA FS 04862 019 04862 022 2 0 1 5 1 0 0 5 ERROR LSB ERROR LSB 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE Figure 22 AD9736 INL 25 C 30 mA FS Figure 25 AD9736 DNL 25 C 30 mA FS 04862 0
4. 3 o o o o o o gt DETAIL DETAIL A 1 00 MAX 0 85 MIN 0 43 MAX 0 25 MIN A 0 55 0 50 PLANE 0 45 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO 205 AE Figure 116 160 Lead Chip Scale Package Ball Grid Array CSP_BGA BC 160 1 Dimensions shown in millimeters EU COPLANARITY ORDERING GUIDE Model Temperature Range Package Description Package Option AD9734BBC 40 C to 85 C 160 Lead Chip Scale Package Ball Grid Array CSP BGA BC 160 1 AD9734BBCRL 40 C to 85 C 160 Lead Chip Scale Package Ball Grid Array CSP BC 160 1 AD9734BBCZ 40 C to 85 C 160 Lead Chip Scale Package Ball Grid Array CSP_BGA BC 160 1 AD9734BBCZRL 40 to 85 C 160 Lead Chip Scale Package Ball Grid Array CSP_BGA BC 160 1 AD9735BBC 40 C to 85 C 160 Lead Chip Scale Package Ball Grid Array CSP_BGA BC 160 1 AD9735BBCZ 40 C to 85 C 160 Lead Chip Scale Package Ball Grid Array CSP BC 160 1 AD9735BBCRL 40 C to 85 C 160 Lead Chip Scale Package Ball Grid Array CSP BC 160 1 AD9735BBCZRL 40 to 85 C 160 Lead Chip Scale Package Ball Grid Array CSP_BGA BC 160 1 AD9736BBC 40 C to 85 C 160 Lead Chip Scale Package Ball Grid Array CSP_BGA BC 160 1 AD9736BBCRL 40 C to 85 C 160 Lead Chip Sc
5. Bit Name Read Write Description LVDS WRITE Don t care READ 0 no active LVDS receiver interrupt 1 interrupt in LVDS receiver occurred SYNC WRITE Don t care READ 0 no active SYNC logic interrupt 1 interrupt in SYNC logic occurred CROSS WRITE Don t care READ 0 no active CROSS logic interrupt 1 interrupt in CROSS logic occurred IE LVDS WRITE 0 reset LVDS receiver interrupt and disable future LVDS receiver interrupts 1 enable LVDS receiver interrupt to activate IRQ pin IE SYNC WRITE 0 reset SYNC logic interrupt and disable future SYNC logic interrupts 1 enable SYNC logic interrupt to activate pin IE CROSS WRITE 0 reset CROSS logic interrupt and disable future CROSS logic interrupts 1 enable CROSS logic interrupt to activate pin Rev A Page 30 of 72 AD9734 AD9735 AD9736 FULL SCALE CURRENT FSC REGISTERS REG 2 REG 3 ADDR Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x02 FSC 1 SLEEP 5 lt 9 gt 5 lt 8 gt 0x03 FSC 2 FSC 7 FSC 6 FSC 5 FSC 4 FSC 3 FSC 2 FSC 1 FSC 0 Table 12 Full Scale Current Output Register Bit Descriptions Bit Name Read Write Description SLEEP WRITE 0 enable DAC output 1 set DAC output current to 0 mA 5 lt 9 0 gt WRITE 0x000 10 mA full scale output current 0x200 20 mA full scale output current Ox3FF 30 mA full
6. e 249 ra a NO 5 Eldl a 2 gt ra lt 2 a 2 lt SILKSCREEN ERROR THE AD9736 IS SOLDERED DIRECTLY TO THE PCB THE SOCKET IS NOT INSTALLED NOTE 5f 04862 107 Figure 109 CB Layout Top Placement AD973x Evaluation Board Rev F Rev A Page 62 of 72 AD9734 AD9735 AD9736 AD9734 AD9735 AD9736 0000 DOC 04861 109 Figure 111 PCB Layout Layer 2 AD973x Evaluation Board Rev F Rev A Page 64 of 72 AD9734 AD9735 AD9736 04862 110 Figure 112 PCB Layout Layer 3 AD973x Evaluation Board Rev F Rev A Page 65 of 72 AD9734 AD9735 AD9736 014862 111 Figure 113 PCB Layout Layer 4 AD973x Evaluation Board Rev F Rev A Page 66 of 72 AD9734 AD9735 AD9736 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIZII s oar IIIIIUI II INWIII IIIIIIIIIIIG IUZIIIIIzIIIIIII e g 622 922 922 ura o 2 04862 112 Figure 114 Layout Bottom Placement AD973x Evaluation Board Rev Rev A Page 67 of 72 cv cv lt cv lt puondo f09 S09 L 3 00 00 2 82122 Sass eee ou 00 coo 8 5600 sak l
7. lt 0 gt lt 0 gt lt 1 gt lt 1 gt DATACLK OUT DATACLK_OUT DATACLK IN DATACLK DB lt 2 gt DB lt 2 gt DB 3 DB 3 4 DB 4 DB 4 4 DB 5 DB 5 4 DB lt 6 gt DB lt 6 gt Negative Positive Data Input Bit 8 Conforms to IEEE 1596 reduced range link No Connect Negative Positive Data Input Bit 7 Conforms to IEEE 1596 reduced range link No Connect No Connect No Connect Negative Positive Data Input Bit 0 LSB Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 1 Conforms to IEEE 1596 reduced range link Negative Positive Data Output Clock Conforms to IEEE 1596 reduced range link Negative Positive Data Input Clock Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 2 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 3 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 4 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 5 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 6 Conforms to IEEE 1596 reduced range link Rev A Page 15 of 72 AD9734 AD9735 AD9736 LOCATION OF SUPPLY AND CONTROL PINS gt gt 123456 7 8 9 10 11 12 13 14
8. data formats This functionality is controlled LSBFIRST at Reg 0 Bit 6 The default is MSB first LSBFIRST 0 spo no aa as az As no pruibes oss When LSBFIRST 0 MSB first the instruction and data bytes Figure 69 Serial Register Interface Timing MSB First Write must be written from the most significant bit to the least INSTRUCTION CYCLE DATA TRANSFER CYCLE significant bit Multibyte data transfers in MSB first format start 55 with instruction byte that includes the register address of the most significant data byte Subsequent data bytes should follow SCLK in order from high address to low address In MSB first mode the serial port internal byte address generator decrements for SDIO ZEE _ each data byte of the multibyte communication cycle 0 When LSBFIRST 1 LSB first the instruction and data bytes must be written from least significant bit to most significant bit Figure 70 Serial Register Interface Timing MSB First Read Multibyte data transfers in LSB first format start with an 04862 067 04862 068 instruction byte that includes the register address of the least INSTRUCTION CYCLE DATATRANSFERCYCLE significant data byte followed by multiple data bytes The serial se port internal byte address generator increments for each byte of the multib
9. 83 ZH 1004 4301 LV ATIVOIdAL 318V1d329V SI WO2 V W L S3AOSdWI HOIHM ZH dl 3aniridWv LNdLNO S3HOIH QVO 1V33 3HOW N3WHOJSNVML 1 1 V LON JYV atl V 35384 6138 ZLY LL ANY Q3AOW3S 38 NV 61 ZLY VSSA 21 971 l l lOLla 09094 09094 VSSA dnoozviNs S p VSS 8 09094 09094 501 9870 VSSA di di Li ZLav NI 7HINOO EL HPL HOV3 OL GASVAYONI 33V 7HIN009 8 8 ANY 023 51 962 ANY 569 INYA OL SLICYO8IO INIW LL qasn AVN TVN9IS SAMI VSSA ASVLIOA AGON VSSA AWSLY avo1 60S NMOHS 513 81 1VN9IS TWOIdAL NOILVSH3N39 TVNOIS 31304 39NVIWHOH H3d WAWILdO S3GlAO d 3 SIHL 8 8 d d 09099 9 A38 JHL NO Z Nid LL i Nid LL Gaqav poke dnoozvws G p VSSA O0 91 9 HE Ig 602 61 ZEN uid xxzi iilav 2 d GOS 84 93 dX19 Q3TIVLISNI 981 LL ose LON SI VEL 09094 ose 07H Figure 107 Clock Input and Analog Output AD973x Evaluation Board Rev F Rev A Page 60 of 72 AN L LL86d Nd A3MIOSIG 901 2980 LNSZZE19 9X4 DINOSVNVd 3 0 Qv38 0
10. eene 55 Power Supply Sequencing seen 56 AD973x Evaluation Board Schematics sss 57 AD973x Evaluation Board PCB Layout sss 62 Outline Dimensions essent 69 Ordering Guilde acidi UDIN 69 Rev A Page 3 of 72 AD9734 AD9735 AD9736 SPECIFICATIONS DC SPECIFICATIONS AVDD33 DVDD33 3 3 V CVDD18 DVDD18 1 8 V maximum sample rate Irs 20 mA 1x mode 25 O 1 balanced load unless otherwise noted Table 1 AD9736 AD9735 AD9734 Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 14 12 10 Bits ACCURACY Integral Nonlinearity INL 5 6 1 0 5 6 1 5 0 50 1 5 0 5 0 12 0 5 LSB Differential Nonlinearity DNL 2 1 0 6 2 1 0 5 0 25 0 5 0 1 0 06 0 1 LSB ANALOG OUTPUTS Offset Error 0 01 0 005 0 01 0 01 0 005 0 01 0 01 0 005 0 01 FSR Gain Error With Internal 1 0 1 0 1 0 FSR Reference Gain Error Without Internal 1 0 1 0 1 0 FSR Reference Full Scale Output Current 8 66 20 2 31 66 8 66 20 2 31 66 8 66 20 2 31 66 mA Output Compliance Range 1 0 1 0 1 0 1 0 1 0 1 0 V Output Resistance 10 10 10 MO Output Capacitance 1 1 1 pF TEMPERATURE DRIFT Offset 0 0 0 ppm C Gain 80 80 80 ppm C Reference Voltage 40 40 40 ppm C REFERENCE Internal Reference Voltage 1 14 1 2 1 26 1 14 12 1 26 1 14 12 1 26 V Output Resistance 5 5
11. 23 RESET Operation metet td 38 AD9736 Dynamic Performance 20 mA Full Scale 24 Programming Sequence 38 AD9735 AD9734 Dynamic Performance 20 mA INTE I NE 27 Interpolation eme 39 AD973x WCDMA ACIR 20 mA Full 28 Data Interface Controllers sse 39 c m I I DU 29 LVDS Sample 4 4 044 40 SPI Register Details 30 LVDS Sample Logic 40 Mode Register Reg 0 eerte 30 Operating the LVDS Controller in Manual Mode via the dg o 41 Interrupt Request Register IRQ Reg 1 30 Rev A Page 2 of 72 AD9734 AD9735 AD9736 Operating the LVDS Controller in Surveillance and Auto Mode cate daa 41 SYNC Logic and Controller eee 42 SYNC Logic and Controller 42 Operation in Manual Mode see 42 Operation in Surveillance and Auto Modes 42 EIEQ Byp ass cocco 42 Digital Built In Self Test BIST sss 44 OVOEVIEW etl eae 44 AD973x BIST Procedure sse 45 AD973x Expected BIST Signatures sss 45 Generating Expected Signature
12. DB 7 DB 7 4 DB 8 DB 8 4 Negative Positive Data Input Bit 10 Conforms to IEEE 1596 reduced range link No Connect Negative Positive Data Input Bit 9 Conforms to IEEE 1596 reduced range link No Connect Negative Positive Data Input Bit O LSB Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 1 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 2 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 3 Conforms to IEEE 1596 reduced range link Negative Positive Data Output Clock Conforms to IEEE 1596 reduced range link Negative Positive Data Input Clock Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 4 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 5 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 6 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 7 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 8 Conforms to IEEE 1596 reduced range link Rev A Page 13 of 72 AD9734 AD9735 AD9736 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B oo D DACCLK E OOO DACCLK F H J K L OOOO nc M N 8888 22283 DATACLK OUT
13. 90 78 16 85 74 72 80 70 68 66 64 62 60 58 60 56 54 LES 52 75 40 70 85 C 25 C SFDR dBc IMD dBc 65 55 50 0 100 200 300 400 500 600 four MHz 0 50 100 150 200 250 300 350 400 450 500 550 four MHz 04862 041 04862 044 Figure 43 AD9736 SFDR vs four over 50 Parts 25 C 1 2 GSPS Figure 46 AD9736 IMD vs four over Temperature 1 2 GSPS Rev A Page 24 of 72 AD9734 AD9735 AD9736 95 90 85 80 SFDR 75 IMD dBc 70 IMD AND SFDR dBc 65 60 55 0 100 200 300 400 500 600 four MHz 0 10 100 four MHz 04862 045 04862 048 Figure 47 AD9736 Low Frequency IMD SFDR vs four 25 1 2 GSPS Figure 50 AD9736 IMD vs four over Aovr 25 C 1 2 GSPS 90 85 ORDER 80 75 70 65 SFDR IMID dBc SFDR IMD dBc 60 55 50 0 50 100 150 200 250 300 350 four MHz 0 50 100 150 200 250 300 350 four MHz 04862 046 04862 049 Figure 51 AD9736 SFDR vs four 25 C 1 2 GSPS 1x and 2x Interpolation SPS I LI THIRD ORDER 0 2x Figure 48 AD9736 IMD SFDR vs four 25 C 1 2 GSPS 2x Interpolation 12dBFS
14. Jitter Bit to Bit Skew Bit to DATACLK_IN Skew Data Sampling Signal Resolution For the 400 mV p p LVDS signal case Minimum Data Valid 465 ps 100 ps 10 ps 50 ps 80 ps 465 ps 240 ps 225 ps For correct data capture the input data must be valid for 225 ps Slower edges more jitter or more skew require an increase in the clock period to maintain the minimum data valid period Table 27 shows the typical minimum data valid period for 400 mV differential and 250 mV differential LVDS swings The ability of the AD973x to capture incoming data is dependent on the speed of the silicon which varies from lot to lot The typical or average silicon speed operates with data that is valid for 225 ps at 85 C Statistically the worst extreme for slow silicon may require up to a 344 ps valid data period as specified in Table 2 Table 27 Typical Minimum Data Valid Times Differential Input BIST Min Clock Typ Min Data Voltage Max fax Period Valid at Receiver 400 mV 2 15 GHz 465 ps 225 ps 250 2 00 GHz 500 ps 260 ps At 1 2 GHz the typical 400 mV p p minimum data valid period of 225 ps leaves 608 ps for external factors Under the same conditions the worst expected minimum data valid period of 344 ps leaves 489 ps for external data uncertainty The 100 mV LVDS Vo threshold test is a dc test to verify that the input logic state changes It does not indicate the o
15. MOVE OL NYALLWd V SHONVYATIOL ONISSADONd a3 13A31 LOH 33Q710S 1 38 OL S3 1 GALV1d 0350 SV3sv 34405 MOIHL NIIN HONI L00 Q31V 1d03123 13 SAAILONGNOD JHL S3 NYHL GALV 1d Z TWNYSLNI YAddOD 20 Z L OL SH3AVT GV19 34405 7ZO vl 200 790 AXOd3 SSV79 bud YAAVT UNOS 7TIVISSLVIN L SALON 3015 ANVONOO3S N3339S flIS 3015 ANVONOO3S 3ISVW33g10S AAV 3015 ANVONOO3S 33AV1 3Nv1d 100 290 dny20 s 4840 ES le BR 3NY d H3AV1 3015 AsvWiald 3015 ANWNINd 0705 3015 3 5 VEO 335 C 1NVISNOO 2151937310 3309 lt 6 5 000 seve lt We TMVI3O 9I 310N 335 51 29870 ec ES 001 lt 1 AD973x Evaluation Board Rev F Figure 115 PCB Fabrication Detai Rev A Page 68 of 72 AD9734 AD9735 AD9736 OUTLINE DIMENSIONS A1 CORNER MU AREA s BALL A1 INDICATOR 1 40 MAX dE TOP VIEW BSC SQ 13 11 9 5 aA 14 12 10 8 76
16. Reg 1 Bit 2 to allow the phase offset PHOF lt 1 0 gt to be automatically updated if FIFOSTAT lt 2 0 gt violates the threshold value The FIFOSTAT signal is filtered to improve noise immunity and reduce unnecessary phase offset updates The filter operates with the following algorithm FIFOSTAT FIFOSTAT AFIFOSTAT 2 SFLT 3 0 where 0 lt SFLT lt 3 0 gt x 12 Values greater than 12 are set to 12 If SFLT 3 0 is too small clock jitter and noise can cause erratic behavior Normally SFLT can be set to the maximum value FIFO BYPASS When the MODE bit Reg 1 Bit 2 is set to 0 the FIFO is bypassed with a mux When the FIFO is enabled the pipeline delay through the AD973x increases by the delta between the FIFO read pointer and write pointer plus 4 more clock periods Rev A Page 42 of 72 AD9734 AD9735 AD9736 DACCLK INTERNAL DELAY EXTERNAL DELAY le DATACLK OUT DATACLK CPC Cb CP C 45 45 Xy X Co UPS CO CPG L SAMPLE_SETUP SAMPLE_DELAY DSS1 DSS2 QUE AST NES GNI QUU GEOP ERIE KEI SAFE ZONE ERROR ZONE L 2 M3 DATA A CAN BE FIFOSTAT IS SET SAFELY READ FROM EQUAL TO THE THE FIFO IN THE WRITE POINTER m SAFE ZONE IN THE EACH TIME THE ERROR ZONE THE READ POINTER POINTERS MAY CHANGES FROM
17. SFDR dBc SFDR IMD dBc 150 350 0 100 200 300 400 500 600 four ie four MHz 04862 047 04862 050 Figure 49 AD9736 SFDR vs four over Aour 25 C 1 2 GSPS Figure 52 AD9736 IMD vs four 25 C 1 2 GSPS 1x and 2x Interpolation Rev A Page 25 of 72 AD9734 AD9735 AD9736 NSD dBm Hz NSD dBm Hz NSD dBm Hz 150 152 154 156 158 160 162 164 166 168 170 0 150 152 154 156 158 160 162 164 166 168 170 0 1GSPS 1 2GSPS 100 200 300 400 500 600 four MHz Figure 53 AD9736 1 Tone NSD vs four over 25 C 85 C 40 25 C 100 200 300 400 500 600 four MHz 04862 051 04862 052 Figure 54 AD9736 1 Tone NSD vs four over Temperature 1 2 GSPS 150 152 154 156 158 160 162 164 166 170 0 100 200 300 400 500 600 four MHz Figure 55 AD9736 8 NSD vs four over 25 C 04862 053 150 152 154 156 NSD dBm Hz 164 166 168 170 NSD dBm Hz NSD dBm Hz Rev A Page 26 of 72 158 160 162 04862 054 four MHz Figure 56 AD9736 8 NSD vs four over Temperature 1 2 GSPS 157 158 159 160 161 16
18. 1 lt 0 gt 00 00 7 07 SYNC FIFOSTAT3 FIFOSTAT2 5 1 FIFOSTATO VALID SCHANGE PHOF 1 lt 0 gt 00 00 8 08 SYNC 2 SSURV SAUTO SFLT lt 3 gt SFLT lt 2 gt SFLT lt 1 gt SFLT 0 RESERVED 5 lt 0 gt 00 00 9 09 RESERVED 10 0A CROS CNT1 5 UPDEL lt 4 gt UPDEL lt 3 gt UPDEL lt 2 gt UPDEL 1 02 00 00 11 0B CROS_CNT2 DNDEL lt 5 gt DNDEL lt 4 gt DNDEL lt 3 gt DNDEL lt 2 gt DNDEL lt 1 gt DNDEL O 00 00 12 RESERVED 13 00 RESERVED 14 OE ANA MSEL lt 1 gt MSEL 0 TRMBG 2 TRMBG lt 1 gt TRMBG 0 CO CO 15 OF ANA CNT2 HDRM lt 7 gt HDRM 6 HDRM lt 5 gt HDRM 4 HDRM 3 HDRM 2 HDRM lt 1 gt HDRM 0 CA CA 16 10 RESERVED 17 11 BIST_CNT SEL lt 1 gt SEL lt 0 gt SIG_READ LVDS_EN SYNC_EN CLEAR 00 00 18 12 BIST lt 7 0 gt 19 13 BIST lt 15 8 gt 20 14 BIST lt 23 16 gt 21 15 BIST lt 31 24 gt 22 16 CCLK_DIV RESERVED RESERVED RESERVED RESERVED CCD lt 3 gt CCD lt 2 gt CCD lt 1 gt CCD lt 0 gt 00 00 Rev A Page 29 of 72 AD9734 AD9735 AD9736 SPI REGISTER DETAILS Reading these registers returns previously written values for all defined register bits unless otherwise noted Reset value for write registers in bold text MODE REGISTER REG 0 ADDR Name Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 MODE SDIO DIR LSB MSB RESET LONG INS 2x MODE FIFO MO
19. Alternatively it can be transformer coupled and clamped as shown in Figure 91 Rev A Page 50 of 72 AD9734 AD9735 AD9736 DAC OUTPUT DISTORTION SOURCES The second harmonic is mostly due to an imbalance in the output load The dc transfer characteristic of the DAC is capable of second harmonic distortion of at least 75 dBc Output load imbalance or digital data noise coupling onto DACCLK causes additional second harmonic distortion The DAC architecture inherently generates third harmonics the levels of which depend on the output frequency and amplitude generated If any output signal is rectified and coupled back onto the DAC clock it can generate additional third harmonic energy The distortion components should be identical in amplitude and phase at both AD973x outputs Even though each single ended output includes a large amount of second harmonic energy a careful differential to single ended conversion can remove most of it Optimum performance at high intermediate frequency IF output is obtained with the output circuit shown in Figure 93 This is the configuration implemented on the evaluation board Figure 107 The 20 series resistors allow the DAC to drive less reactive load which improves distortion Further improvement is realized by adding the Balun T3 to help provide an equal load to both DAC outputs R19 200 IOUTA J2 500 OUTPUT 04862 091 AVSS Figure 93 IF Signal Output Circuit B
20. M5 BRIEFLY OVERLAP 7 TO 0 DUE TO CLOCK JITTER OR NOISE READ PTRI PERCO 19000010 0000 07 FIFOSTAT SSS SS Se DAC_DATA 8 Figure 83 Sync Logic Timing Diagram Rev A Page 43 of 72 AD9734 AD9735 AD9736 DIGITAL BUILT IN SELF TEST BIST OVERVIEW The AD973x includes an internal signature generator that processes incoming data to create unique signatures These signatures are read back from the SPI port allowing verification of correct data transfer into the AD973x BIST vectors provided on the AD973x EB evaluation board CD check the full width data input or individual bits for PCB debug utilizing the procedure in the AD973X BIST Procedure section Alterna tively any vector can be used provided the expected signature is calculated in advance The MATLAP routine in the Generating Expected Signatures section calculates the expected signature BIST verifies correct data transfer because not all errors are always evident on a spectrum analyzer There are four BIST signature generators that can be read back using Reg 18 to Reg 21 based on the setting of the BIST selection bits Reg 17 Bits 7 6 as shown in Table 24 The BIST signature returned from the AD973x depends on the digital input during the test Because the filters in the DAC have memory it is important to put the correct idle value on the DATA input to flush the memory prior to reading the BIST signature DB lt 13 0 gt Placing the idle va
21. PIN F13 04862 066 Figure 68 AD973x SPI Port The AD973x can optionally be configured via external pins rather than the serial interface When the PIN MODE input Pin L1 is high the serial interface is disabled and its pins are reassigned for direct control of the DAC Specific functionality is described in the Pin Mode Operation section GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communication cycle with the AD973x Phase 1 is the instruction cycle which is the writing of an instruction byte into the AD973x coincident with the first eight SCLK rising edges The instruction byte provides the AD973x serial port controller with information regarding the data transfer cycle which is Phase 2 of the communication cycle The Phase 1 instruction byte defines whether the upcoming data transfer is read or write the number of bytes in the data transfer and the starting register address for the first byte of the data transfer The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD973x The remaining SCLK edges are for Phase 2 of the communica tion cycle Phase 2 is the actual data transfer between the AD973x and the system controller Phase 2 of the communica tion cycle is a transfer of 1 2 3 or 4 data bytes as determined by the instruction byte Using one multibyte transfer is the preferred method Single byte data transfers are useful to reduce CPU
22. Set desired operating mode 1x mode and signed data are default values and expected for the supplied BIST vectors 11 Set CLEAR Reg 17 Bit 0 SYNC EN Reg 17 Bit 1 and LVDS EN Reg 17 Bit 2 high 12 Wait 50 DATACLK IN cycles to allow 0s to propagate through and clear sync signatures 13 Set CLEAR low 14 Read all signature registers Reg 21 Reg 20 Reg 19 and Reg 18 for each of the four SEL Reg 17 Bits 7 6 values and verify they are all 0x00 LVDS Phase 1 a Reg 17 set to 0x26 SEL1 0 SELO 0 SIG READ 1 LVDS_EN 1 SYNC EN 1 b Read Reg 20 Reg 19 Reg 18 and Reg 17 LVDS Phase 2 a 17 set to 0x66 SELI 0 SELO 1 SIG READ 1 LVDS EN 1 SYNC EN 1 b Read Reg 20 Reg 19 Reg 18 and Reg 17 SYNC Phase 1 a Reg 17 set to 0 6 SEL1 1 SELO 0 SIG READ 1 LVDS EN 1 SYNC EN 1 b Read Reg 20 Reg 19 Reg 18 and Reg 17 SYNC Phase 2 a Reg 17 set to OXE6 SEL1 1 SELO 1 SIG READ 1 LVDS EN 1 SYNC EN 1 b Read Reg 20 Reg 19 Reg 18 and Reg 17 15 Clockthe BIST vector into the AD973x 16 After the BIST vector is clocked into the part hold DATA 0x0000 for signed 0x2000 for unsigned otherwise the additional nonzero data changes the signature 17 Read all signature registers Reg 21 Reg 20 Reg 19 and Reg 18 as described in Step 14 for each of the four SEL Reg 17 Bits 7 6 values and verify that they match
23. The following timing information allows system timing to be calculated so that multiple AD973xs can be synchronized DATACLK OUT changes relative to the rising edge of DACCLK and is delayed as shown in Figure 101 Because DACCLK is divided by 2 to create DATACLK the phase of DATACLK OUT can be 0 or 1805 There is no way to predict or control this relationship It can be different after each power cycle and is not affected by hardware or software resets e 04862 099 Figure 101 DACCLK to DATACLK OUT Delay The incoming data is de interleaved internally as shown in Figure 78 In Figure 78 DBU upper and DBL lower represent the de interleaved data paths Each edge of DATACLK IN latches an incoming sample in two alternating registers The DATACLK IN to data setup and hold definitions are illustrated in Figure 102 All the data input must be valid during the setup and hold period External skew effectively increases the setup and hold times that the data source must meet DATACLK IN N OR DATACLK OUT tosu gt 04862 100 Figure 102 Standard Definitions for DATACLK IN or DATACLK OUT to Data Setup and Hold SD 0 Table 28 AD973x Clock and Data Timing Parameters While correct DATA IN vs DATACLK IN timing is critical the transition of the incoming data to the DACCLK domain is equally critical By referencing the incoming DATA
24. sum 19 su 21 sum 20 su 22 sum 21 su 23 sum 22 su 24 sum 23 su 25 sum 24 su 26 sum 25 su 27 sum 26 su 28 sum 27 su 29 sum 28 su 30 sum 29 su 31 sum 30 su 32 sum 31 sum su end end for ret dec2hex 2 0 31 x sum 8 end bist m To generate the expected BIST signatures follow this procedure 1 Start MATLAB and type the following at the command prompt t round randn 1 100 x 22 8429 b1 b2 bist t The first statement creates a random vector of 14 bit words with a length of 100 2 Settequal to any desired vector or take this random vector and input it to the AD973x 3 Alter the command randn 1 100 to change the vector length as desired 4 Type 1 at the command line to see the calculated signature for the LVDS BIST Phase 1 5 b2 to see the value for LVDS BIST Phase 2 The values returned for b1 and b2 each are 32 bit hex values They correspond to Reg 18 Reg 19 Reg 20 and Reg 21 where b1 is the value read for SEL 1 0 0 0 see Table 17 and b2 is the value read for SEL 1 0 0 1 When the DAC is in 1x mode the signature at SYNC BIST Phase 1 should equal the signature at LVDS BIST Phase 1 The same is true for Phase 2 Rev A Page 46 of 72 AD9734 AD9735 AD9736 CROSS CONTROLLER REGISTERS The AD973x differential output stage is adjustable to equalize Figure 85 shows the effect of UPDEL an
25. 0 8 0 50 0 6 0 25 0 4 0 0 25 m 02 a a pus E 0 0 75 z x 02 1 00 0 4 1 25 0 6 1 50 1 75 0 8 2 00 2 1 0 E 0 2048 4096 6144 8192 10240 12288 14336 16384 5 0 2048 4096 6144 8192 10240 12288 14336 16384 5 CODE 3 CODE 3 Figure 11 AD9736 INL 85 C 10 mA FS Figure 14 AD9736 DNL 85 C 10 mA FS Rev A Page 18 of 72 AD9734 AD9735 AD9736 AD9736 STATIC LINEARITY 20 mA FULL SCALE ERROR LSB ERROR LSB 2048 4096 6144 8192 10240 12288 14336 16384 CODE 2048 4096 6144 8192 10240 12288 14336 16384 CODE Figure 15 AD9736 INL 40 C 20 mA FS Figure 18 AD9736 DNL 40 C 20 mA FS 1 0 0 6 0 8 0 5 0 6 0 4 0 4 0 3 0 2 0 2 0 0 1 0 2 0 0 4 0 1 0 6 0 2 0 8 0 3 1 0 0 4 1 2 0 5 En 1 4 0 2048 4096 6144 8192 10240 12288 14336 16384 2048 4096 6144 8192 10240 12288 14336 16384 04862 013 04862 016 ERROR LSB ERROR LSB 04862 014 04862 017
26. 1nF SCALING IFULL SCALE N 04862 086 Figure 88 Voltage Reference Circuit The reference current is obtained by forcing the band gap voltage across an external 10 resistor from 1120 Pin B14 to ground The 1 2 V nominal band gap voltage generates a 120 reference current in the 10 resistor This current is adjusted digitally by 5 lt 9 0 gt Reg 2 Reg 3 to set the output full scale current Irs V 0 lt FSC lt 90 gt R 1024 Rev A Page 48 of 72 AD9734 AD9735 AD9736 Always connect 10 resistor from the 1120 pin to ground and use the digital controls to vary the full scale current The AD973x is not a multiplying DAC Applying an analog signal to 1120 is not supported The full scale output current range is approximately 10 mA to 30 mA for register values from 0x000 to 0x3FE The default value of 0x200 generates 20 mA full scale The typical range is shown in Figure 89 35 VREF Pin C14 must be bypassed to ground with a 1 nF capacitor The band gap voltage is present on this pin and can 30 be buffered for use in external circuitry The typical output us impedance is near 5 If desired an external reference can be used to overdrive the internal reference by connecting it to the 2 VREF pin E 815 Pin D14 is used for factory testing Leave this pin floating 10 5 B 0 3 0 200 400 600 800 1000 DAC GAIN CO
27. 2191 oo 9 oo lt cv co cr aada 61 091 oul 81 S34 5 SSAB 08QV zar vieeaan SSA vowel A LISSA plover A L SSA 59 A 9 I gio 08059 ATU 7 aSvov 3 its 08052 42y aSvov 8 lt 6 9 lt 5 V 13934 059 seaqA 4 LISSA 224 LISSA z 9 m v SSA 9 9 OAOL ELA x D 8 8 ESSA 8 8 x ovy lt nov 4 ESSA 58256 SSA uJ og8QVn 508091 t Olar L m O46 n 18546 ovy lar z v 508024 D gt E gt adv SON O46 LLY 2 viecaaa 3 sar L 50809 LSSA LSSA gt td L z oar 2 sn sn SSA E vide 1304 5 95248 2 SSA E elder d 145 NI STVNOIS 1304 IdS LO3NNOO S IVNSIS 1 1 Nid 135 OL ASSHL ASN AD973x Evaluation Board Rev F Rev A Page 61 of 72 Figure 108 SPI Port Interfac AD9734 AD9735 AD9736 AD973x EVALUATION BOARD PCB LAYOUT LN e eR mm NO v HYDROGEN REV F 4 ANALOG DEVICES E Gr E
28. AD9736 DIGITAL SPECIFICATIONS AVDD33 DVDD33 3 3 V CVDD18 DVDD18 1 8 V maximum sample rate Irs 20 mA 1x mode 25 1 balanced load unless otherwise noted LVDS drivers and receivers are compliant to the IEEE 1596 reduced range link unless otherwise noted Table 2 Parameter Min Typ Max Unit LVDS DATA INPUT DB 13 0 DB 13 0 DB Via DB Via Input Voltage Range Via or Vis 825 1575 mV Input Differential Threshold 100 100 Input Differential Hysteresis 20 mV Receiver Differential Input Impedance Rin 80 120 Q LVDS Input Rate 1200 MSPS LVDS Minimum Data Valid Period tvoe 344 ps LVDS CLOCK INPUT DATACLK DATACLK DATACLK_IN Via DATACLK Input Voltage Range Via or Vis 825 1575 mV Input Differential Threshold 100 100 mV Input Differential Hysteresis 20 Receiver Differential Input Impedance Rin 80 120 Q Maximum Clock Rate 600 MHz LVDS CLOCK OUTPUT DATACLK_OUT DATACLK DATACLK_OUT Voa DATACLK OUT Vob 100 Termination Output Voltage High Voa or Vos 1375 mV Output Voltage Low Voa or Vos 1025 mV Output Differential Voltage Voo 150 200 250 mV Output Offset Voltage Vos 1150 1250 mV Output Impedance Single Ended Ro 80 100 120 Q Ro Mismatch Between and B 10 Change in Vop Between 0 and 1 AVoo 25 mV Change in Vos Between 0 and 1 AV
29. FIFO SCLK FSCO SDO FSC1 DVDD18 DVSS temperature is approximately 10 pA at 25 C with a slope of approximately 20 nA C Negative Positive DAC Clock Input DACCLK Analog Supply Ground Shield Tie to AVSS at the DAC If PIN_MODE 0 IRQ Active low open drain interrupt request output pull up to DVDD33 with 10 resistor If PIN MODE 1 UNSIGNED Digital input pin where 0 twos complement input data format 1 unsigned If PIN MODE 0 RESET 1 resets the AD9734 If PIN MODE 1 PD 1 puts the AD9734 in the power down state See the Serial Peripheral Interface section and the Pin Mode Operation section for pin description See the Pin Mode Operation section for pin description See the Pin Mode Operation section for pin description See the Pin Mode Operation section for pin description 1 8 V Digital Supply Digital Supply Ground Rev Page 14 of 72 AD9734 AD9735 AD9736 Pin No Mnemonic Description K13 14 DB lt 9 gt DB lt 9 gt Negative Positive Data Input Bit 9 MSB Conforms to IEEE 1596 reduced range link L1 PIN MODE 0 SPI Mode SPI is enabled 1 PIN Mode SPI is disabled direct pin control L7 L8 M7 M8 N7 N8 P7 P8 DVDD33 3 3V Digital Supply 113 114 M1 2 M13 M14 N1 P1 N2 P2 N3 P3 N4 P4 N5 P5 N6 P6 N9 P9 N10 P10 N11 P11 N12 P12 N13 P13 N14 P14 lt 8 gt lt 8 gt lt 7 gt lt 7 gt
30. Mly 8L EVSSA 9EEWSSA E 8451 issn D 615 ZHEEVSSA SEEWSSA 1 exoo T saaa V TL ayo 9EEVSSA vt VSSA ra 4 imi zaan ae vesiada 4722 50 suos 5126 86 SQA T 7 2 66 err 808090 ELEeVSSA 166 66 Ir 19 VSSA SS o 09 tH SSA 80 ibi N39O3GAH Eu 09099 gu 09099 dir 3svov 622 asiaan Figure 105 Circuitry Local to AD973x Evaluation Board Rev Rev A Page 58 of 72 oo 9 lt eG co cr deiaa 1nod xwioa NId X 15a dtaa Noga 8 Nega NINW19 0 1nONX15G N88G N68G Nerga SSA 0 9 720 892 24 2 01 298 0 96 H3QHO HOLO3NNOO JHL SI 9571 9510 9EZ60V 3LON E O 5 A c gt HOLO3NNOO 1101531 3 NInOlS3l Figure 106 High Speed Digital I O Connector AD973x Evaluation Board Rev F Rev A Page 59 of 72 cv LO cv lt cv oo co lt ZHIAO00L S t HPL
31. Typ Max Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Update Rate 1200 1200 1200 MSPS SPURIOUS FREE DYNAMIC RANGE SFDR 800 MSPS four 20 MHz 75 75 75 dBc 1200 MSPS four 50 MHz 80 76 76 dBc four 100 MHz 77 74 71 four 316 MHz 63 63 60 dBc four 550 MHz 55 54 53 dBc TWO TONE INTERMODULATION DISTORTION IMD 1200 MSPS 2 four 1 25 MHz four 40 MHz 88 84 83 dBc four 50 MHz 85 84 83 dBc fout 100 MHz 84 81 79 dBc four 316 MHz 70 5 67 66 dBc four 550 MHz 65 60 60 dBc NOISE SPECTRAL DENSITY NSD Single Tone 1200 MSPS four 50 MHz 165 162 154 dBm Hz four 100 MHz 164 161 154 dBm Hz four 241 2 158 5 160 5 159 5 155 dBm Hz four 316 MHz 158 157 152 dBm Hz four 550 MHz 155 155 149 dBm Hz Eight Tone foac 1200 MSPS 500 kHz Tone Spacing four 50 MHz 166 5 163 154 dBm Hz four 100 MHz 166 163 152 dBm Hz four 241MHz 163 3 165 161 5 150 5 dBm Hz four 316 MHz 164 162 151 dBm Hz four 550 MHz 162 160 150 dBm Hz Rev A Page 8 of 72 AD9734 AD9735 AD9736 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
32. and DATACLK IN timing to the DATACLK OUT signal some timing uncertainty can be removed The DATACLK OUT timing very closely tracks the timing of the DACCLK controlled registers Any variation in the path delay affects both paths in almost the same way If OUT is not used the full DACCLK to OUT path variation reduces the external timing margin Figure 101 shows a simplified view of the internal clocking scheme with the relevant delay paths The internal architecture is interleaved such that each phase has twice as long to make the transition across the clock domains This results in an extremely narrow window where the incoming data must be held stable Table 28 shows the timing parameters for Figure 101 and Figure 102 These parameters were measured for a sample of five devices from five silicon lots Worst case fast and slow skew lots were included in addition to the nominal or average lot The typical 40 C to typical 85 C spread illustrates the variability with temperature for a single lot Adding in lot to lot variation with the fast and slow lots indicates the worst case spread in timing The timing varies such that all of the parameters move in the same direction For example if the DATACLK IN to data setup time is fast the hold time is similarly fast The DACCLK to DATACLK OUT delay and the DATACLK OUT to data setup and hold is also at the fast end of the range Note that the polarities of s
33. be adjusted with the phase offset PHOF lt 1 0 gt Reg 7 Bits 1 0 Due to the architecture of the FIFO the phase offset can only adjust the read pointer in steps of 2 OPERATION IN MANUAL MODE To start operating the DAC in manual mode allow DACCLK and IN to stabilize then enable FIFO mode Reg 0 Bit 2 Read FIFOSTAT lt 2 0 gt Reg 7 Bits 6 4 to determine if adjustment is needed For example if FIFOSTAT lt 2 0 gt 6 the timing is not yet critical but it is not optimal To return to an optimal state FIFOSTAT 2 0 4 the lt 1 0 gt Reg 7 Bits 1 0 needs to be set to 1 Setting PHOF lt 1 0 gt 1 effectively increments the read pointer by 2 This causes the write pointer value to be captured two clocks later decreasing FIFOSTAT lt 2 0 gt from 6 to 4 OPERATION IN SURVEILLANCE AND AUTO MODES Once FIFOSTAT lt 2 0 gt is manually placed an optimal state the AD973x sync logic can run in surveillance or auto mode To start turn on surveillance mode by setting SSURV 1 Reg 8 Bit 7 then enable the sync interrupt Reg 1 Bit 2 If STRH lt 0 gt 0 Reg 8 Bit 0 an interrupt occurs if FIFOSTAT 2 0 0 or 7 If STRH lt 0 gt 1 Reg 8 Bit 0 an interrupt occurs if FIFOSTAT 2 0 0 1 6 or 7 The interrupt is read at Reg 1 Bit 6 at the AD973x IRQ pin To enter auto mode complete the preceding steps then set SAUTO 1 Reg 8 Bit 6 Next set the sync interrupt 0
34. driving signal must be set to a high impedance in time for the bus to turn around The serial output data from the AD973x is enabled by the falling edge of SCLK This causes the first output data bit to be shorter than the remaining data bits as shown in Figure 74 To assure proper reading of data read the SDIO or SDO pin prior to changing the SCLK from low to high Due to the more complex multibyte protocol multiple AD973x devices cannot be daisy chained on the SPI bus Multiple DACs should be controlled by independent CSB signals PIN MODE OPERATION When the PIN MODE input Pin L1 is set high the SPI port is disabled The SPI port pins are remapped as shown in Table 21 The function of these pins is described in Table 22 The remain ing PIN MODE register settings are shown in Table 9 Table 21 SPI MODE vs PIN MODE Inputs Table 22 PIN MODE Input Functions Mnemonic Function UNSIGNED 0 twos complement input data format 1 unsigned input data format 2x 0 interpolation disabled 1 interpolation 2 2x enabled 00 sleep mode 01 10 mA full scale output current 10 20 mA full scale output current 11 30 mA full scale output current PD 0 chip enabled 1 chip in power down state FIFO 0 input FIFO disabled 1 input FIFO enabled FSC1 FSCO Pin Number PIN PIN 1 E13 IRQ UNSIGNED F13 CSB 2x G13 SCLK FSCO E14 RESET PD F14 SDIO FIFO G14 SDO FSC1 Care must be t
35. overhead when register access requires one byte only Registers change immediately upon writing to the last bit of each transfer byte CSB Chip Select can be raised after each sequence of 8 bits except the last byte to stall the bus The serial transfer resumes when CSB is lowered Stalling on nonbyte boundaries resets the SPI SHORT INSTRUCTION MODE 8 BIT INSTRUCTION The short instruction byte is shown in the following table MSB LSB 17 l6 15 14 2 n 10 R W N1 0 4 2 1 0 R W Bit 7 of the instruction byte determines whether a read or a write data transfer occurs after the instruction byte write Logic high indicates read operation Logic 0 indicates a write operation N1 NO Bit 6 and Bit 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle The bit decodes are shown in Table 20 A4 A3 A2 AO Bit 4 Bit 3 Bit 2 Bit 1 and Bit 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle For multibyte transfers this address is the starting byte address The remaining register addresses are generated by the AD973x based on the LSBFIRST bit Reg 0 Bit 6 Table 20 Byte Transfer Count N1 N2 Description 0 0 Transfer 1 byte 0 1 Transfer 2 bytes 1 0 Transfer 3 bytes 1 1 Transfer 4 bytes LONG INSTRUCTION MODE 16 BIT INSTRUC
36. reception in the DAC with changes in temperature and voltage The sync controller manages the FIFO to assure proper transfer of the received data to the DAC core with changes in temperature and voltage The DAC is intended to operate with both controllers active unless data and clock alignment is managed externally Rev A Page 38 of 72 AD9734 AD9735 AD9736 INTERPOLATION FILTER In 2x mode the input data is interpolated by a factor of 2 so that it aligns with the DAC update rate The interpolation filter is a hard coded 55 tap symmetric FIR with a 0 001 dB pass band flatness and a stop band attenuation of about 90 dB The transition band runs from 20 of to 30 of fnac The FIR response is shown in Figure 75 where the frequency axis is normalized to Figure 76 shows the pass band flatness and Table 23 shows the 16 bit filter coefficients Table 23 FIR Interpolation Filter Coefficients Coefficient Number Coefficient Number Tap Weight 1 55 7 2 54 0 3 53 24 4 52 0 5 51 62 6 50 0 7 49 135 8 48 0 9 47 263 10 46 0 11 45 471 12 44 0 13 43 793 14 42 0 15 41 1273 16 40 0 17 39 1976 18 38 0 19 37 3012 20 36 0 21 35 4603 22 34 0 23 33 7321 24 32 0 25 31 13270 26 30 0 27 29 41505 28 65535 0 10 20 _ 30 5 40 5 60 70 80 90 0 0 05 0 10 0 15 0 20 0 25 0 30 0 35 0 40 0 45 0 50 FREQUENCY NOR
37. 10 txt 10 D5430B00 15BC0500 bit11 txt 11 D5470900 15B80400 bit12 txt 12 054 0000 15800600 bit13 txt 13 D55F0500 15A00200 Note the following for Table 26 e term rise refers to Phase 1 and fall refers to Phase 2 Byte order is Decimal Register Address 21 Address 20 Address 19 and Address 18 SYNC phase should always equal LVDS phase in 1x mode Rev A Page 45 of 72 AD9734 AD9735 AD9736 GENERATING EXPECTED SIGNATURES The following MATLAB code duplicates the internal logic of the AD973x To use it save this code in a file called bist m begin bist m function ret2 bist vec retl bistl vec 1 2 1length vec 1 ret2 bistl vec 2 2 1length vec function ret bistl v sum zeros 1 32 for i 1 length v if v i Su 1 xor sum 32 bitget v i 1 su 2 xor sum 1 bitget v i 2 su 3 xor sum 2 bitget v i 3 su 4 xor sum 3 bitget v i 4 su 5 xor sum 4 bitget v i 5 su 6 xor sum 5 bitget v i 6 su 7 xor sum 6 bitget v i 7 su 8 xor sum 7 bitget v i 8 su 9 xor sum 8 bitget v i 9 su 10 xor sum 9 bitget v i 10 Su 11 xor sum 10 bitget v i 11 su 12 xor sum 11 bitget v i 12 su 13 xor sum 12 bitget v i 13 su 14 xor sum 13 bitget v i 14 su 15 sum 14 su 16 sum 15 su 17 sum 16 su 18 sum 17 su 19 sum 18 su 20
38. 12 0 CODE Figure 28 AD9735 INL 25 C 20 mA FS 00 29870 861 40323 0 350 0 400 3584 4096 3072 1024 1536 2048 2560 512 0 CODE Figure 32 AD9735 DNL 25 C 30 mA FS 420 298 0 que N e o 861 40323 0 2 x 1 10 1 0 6 3584 4096 1536 2048 2560 3072 1024 512 0 CODE Figure 29 AD9735 INL 25 C 30 mA FS Rev A Page 21 of 72 AD9734 AD9735 AD9736 AD9734 STATIC LINEARITY 10 mA 20 mA 30 mA FULL SCALE 0 04 0 03 o N ERROR LSB ERROR LSB 0 01 0 02 128 256 384 512 640 768 896 1024 CODE Figure 36 AD9734 DNL 25 C 10 mA FS 04862 031 04862 034 0 03 0 02 2 o ERROR LSB ERROR LSB 0 01 0 02 0 03 0 128 256 384 512 640 768 896 1024 CODE Figure 37 AD9734 DNL 25 C 20 mA FS 04862 032 04862 035 CODE Figure 34 AD9734 INL 25 C 20 mA FS 1 e S gt ERROR LSB ERROR LSB ONE 3 0 06 0 08 0 10 0 12 0 128 256 384 512 640 768 896 1024 CODE Figure 38 AD9734 DNL 25 C 30 mA FS 0 128 256 384 512 640 768 896 1024 CODE Figure 35 AD9734 INL 25 C 30
39. 2 163 164 165 0 50 100 150 200 250 300 350 400 450 500 550 four MHz 04862 055 Figure 57 AD9736 1 Tone NSD vs four over 50 Parts 1 2 GSPS 25 C 0 50 100 150 200 250 300 350 400 450 500 550 four MHz 04862 056 Figure 58 AD9736 8 Tone NSD vs four over 50 Parts 1 2 GSPS 25 C AD9734 AD9735 AD9736 AD9735 AD9734 DYNAMIC PERFORMANCE 20 mA FULL SCALE 80 90 85 75 80 70 75 5 5 65 70 5 65 60 60 55 55 50 50 8 0 50 100 150 200 250 300 350 400 450 500 550 600 5 0 50 100 150 200 250 300 350 400 450 500 550 600 four MHz four MHz Figure 59 AD9735 SFDR vs four over foac 1 2 GSPS Figure 62 AD9734 IMD vs four over fpac 1 2 GSPS 80 150 152 75 154 156 70 1 TONE 158 8 5 65 m 160 x 162 2 8 TONES 164 166 55 168 50 5 170 i 0 50 100 150 200 250 300 350 400 450 500 550 600 5 0 50 100 150 200 250 300 350 400 450 500 550 600 four MHz four MHz Figure 60 AD9734 SFDR vs four over foac 1 2 GSPS Figure 63 AD9735 NSD vs fo
40. 20 04862 023 ERROR LSB ERROR LSB 0 5 4 0 T 1 0 1 5 1 5 2 0 0 2048 4096 6144 8192 10240 12288 14336 16384 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 23 AD9736 INL 85 C 30 mA FS Figure 26 AD9736 DNL 85 C 30 mA FS 04862 021 04862 024 Rev A Page 20 of 72 AD9734 AD9735 AD9736 AD9735 STATIC LINEARITY 10 mA 20 mA 30 mA FULL SCALE 820 298 0 0 100 dl TIT 5 0 100 861 40323 0 150 0 200 0 250 3584 4096 3072 1024 1536 2048 2560 512 0 CODE Figure 30 AD9735 DNL 25 C 10 mA FS 520 298 0 0 4 0 3 N 861 4033 o 0 1 0 2 1024 1536 2048 2560 3072 3584 4096 512 0 CODE Figure 27 AD9735 INL 25 C 10 mA FS 0 050 620 298 0 861 0 100 0 125 3584 4096 3072 1024 1536 2048 2560 512 0 CODE Figure 31 AD9735 DNL 25 C 20 mA FS 90 29870 T o 10 e 0 05 1 861 0 10 0 15 0 20 3584 4096 1024 1536 2048 2560 3072 5
41. 5 kQ ANALOG SUPPLY VOLTAGES AVDD33 3 13 3 3 3 47 3 13 3 3 3 47 3 13 3 3 3 47 V CVDD18 1 70 1 8 1 90 1 70 1 8 1 90 1 70 1 8 1 90 V DIGITAL SUPPLY VOLTAGES DVDD33 3 13 3 3 3 47 3 13 3 3 3 47 3 13 3 3 3 47 V DVDD18 1 70 1 8 1 90 1 70 1 8 1 90 1 70 1 8 1 90 V SUPPLY CURRENTS 1x Mode 1 2 GSPS AVDD33 25 25 25 mA cvpp18 47 47 47 mA 10 10 10 mA Ipvppis 122 122 122 mA FIR Bypass 1x Mode 380 380 380 mW 2x Mode 1 2 GSPS AVDD33 25 25 25 mA cvpp18 47 47 47 mA 10 10 10 mA 18 234 234 234 FIR 2x Interpolation Filter 550 550 550 mW Enabled Rev A Page 4 of 72 AD9734 AD9735 AD9736 AD9736 AD9735 AD9734 Parameter Min Typ Max Min Typ Max Min Typ Max Unit Static No Clock AVDD33 25 25 25 mA 8 8 8 mA 10 10 10 mA Ipvppis 2 2 2 mA FIR Bypass 1x Mode 133 133 133 mW Sleep Mode No Clock AVDD33 2 5 3 15 2 5 3 15 2 5 3 15 mA FIR Bypass 1x Mode 59 65 59 65 59 65 mW Power Down Mode AVDD33 0 01 0 13 0 01 0 13 0 01 0 13 mA cvpp18 0 02 0 12 0 02 0 12 0 02 0 12 mA 0 01 0 12 0 01 0 12 0 01 0 12 mA Ipvppis 0 01 0 11 0 01 0 11 0 01 0 11 mA FIR Bypass 1x Mode 0 12 1 24 0 12 1 24 0 12 1 24 mW 1 Default band gap adjustment Reg OxOE 2 0 0x0 Use an external amplifier to drive any external load 3 Typical wake up time is 8 us with recommended 1 nF capacitor on VREF pin Rev A Page 5 of 72 AD9734 AD9735
42. 9 Theory of Operation oett tee 35 Thermal Resistance eie e nrbe 9 Serial Peripheral Interface sse 36 ESD Ca tion eite etie etie 9 General Operation of the Serial Interface 36 Pin Configurations and Function Descriptions 10 Short Instruction Mode 8 Bit Instruction 36 Location of Supply and Control 16 Long Instruction Mode 16 Bit Instruction 36 Terminology io eite eben 17 Serial Interface Port Pin 36 Typical Performance Characteristics sss 18 SGLK Serial Clock 36 AD9736 Static Linearity 10 mA Full Scale 18 E 37 AD9736 Static Linearity 20 mA Full Scale 19 SDIO Serial Data T O issii 37 AD9736 Static Linearity 30 mA Full Scale 20 SDO Serial Data Qut tne nes 37 AD9735 Static Linearity 10 mA 20 mA 30 mA tones e e Rte RR Ae Deve 21 MSB LSB Transfers sentent 37 AD9734 Static Linearity 10 mA 20 mA 30 mA Notes on Serial Port Operation sse 37 anten 22 Pin Mode Operation aaa 38 AD9736 Power Consumption 20 mA Full Scale
43. 9735 AD9736 THEORY OF OPERATION The AD9736 AD9735 and AD9734 are 14 bit 12 bit and 10 bit DACs that run at an update rate up to 1 2 GSPS Input data can be accepted up to the full 1 2 GSPS rate or a 2x interpolation filter can be enabled 2x mode allowing full speed operation with a 600 MSPS input data rate The DATA and DATACLK_IN inputs are parallel LVDS meeting the IEEE reduced swing LVDS specifications with the exception of input hysteresis The DATACLK_IN input runs at one half the input DATA rate in a double data rate DDR format Each edge of DATACLK IN transfers DATA into the AD9736 as shown in Figure 79 DACCLK DACCLK inputs Pin and Pin F1 directly drive the DAC core to minimize clock jitter The DACCLK signal is also divided by 2 1x and 2x mode then output as the DATACLK OUT The DATACLK OUT signal clocks the data source The DAC expects DDR LVDS data DB lt 13 0 gt aligned with the DDR input clock DATACLK IN from a circuit simi lar to the one shown in Figure 96 Table 19 shows the clock relationships Table 19 AD973x Clock Relationship MODE DACCLK DATACLK OUT DATACLK IN DATA 1x 1 2 GHz 600 MHz 600 MHz 1 2 GSPS 2x 1 2 GHz 600 MHz 300 MHz 600 MSPS Maintaining correct alignment of data and clock is a common challenge with high speed DACs complicated by changes in temperature and other operating conditions Using the DATACLK_OUT signal to generate the data all
44. ANALOG DEVICES 10 12 14 Bit 1200 MSPS DACS AD9734 AD9735 AD9736 FEATURES Pin compatible family Excellent dynamic performance AD9736 SFDR 82 dBc at four 30 MHz AD9736 SFDR 69 dBc at four 130 MHz AD9736 IMD 87 dBc at four 30 MHz AD9736 IMD 82 dBc at four 130 MHz LVDS data interface with on chip 100 terminations Built in self test LVDS sampling integrity LVDS to DAC data transfer integrity Low power 380 mW Irs 20 mA four 330 MHz 1 8 3 3 V dual supply operation Adjustable analog output 8 66 mA to 31 66 mA Ri 25 to 500 On chip 1 2 V reference 160 lead chip scale ball grid array package APPLICATIONS Broadband communications systems Cellular infrastructure digital predistortion Point to point wireless CMTS VOD Instrumentation automatic test equipment Radar avionics GENERAL DESCRIPTION The AD9736 AD9735 and AD9734 are high performance high frequency DACs that provide sample rates of up to 1200 MSPS permitting multicarrier generation up to their Nyquist frequency The AD9736 is the 14 bit member of the family while the AD9735 and the AD9734 are the 12 bit and 10 bit members respectively They include a serial peripheral interface SPI port that provides for programming of many internal parameters and enables readback of status registers reduced specification LVDS interface is utilized to achieve the high sample rate The output current can be programmed ove
45. CLK cycle at 1 2 GHz 833 ps Stopping the AD973x DATACLK IN while the DACCLK is still running can lead to unpredictable output signals This occurs because the internal digital signal path is interleaved The last two samples clocked into the DAC continue to be clocked out by DACCLK even after DATACLK IN has stopped The result ing output signal is at a frequency of one half fpac and the amplitude depends on the difference between the last two samples Control of the AD973x functions is via the serially programmed registers listed in Table 9 Optionally a limited number of func tions can be directly set by external pins in pin mode Rev A Page 35 of 72 AD9734 AD9735 AD9736 SERIAL PERIPHERAL INTERFACE The AD973x serial port is a flexible synchronous serial communications port allowing easy interface to many industry standard microcontrollers and microprocessors The serial I O is compatible with most synchronous transfer formats including both the Motorola SPI and Intel SSR protocols The interface allows read write access to all registers that configure the AD973x Single or multiple byte transfers are supported as well as most significant bit first MSB first or least significant bit first LSB first transfer formats The AD973x serial interface port can be configured as a single pin I O SDIO or two unidirectional pins for in out SDIO SDO SDO PIN G14 SDIO PIN F14 AD973x SPI PORT SCLK PIN G13 CSB
46. D973x family uses a proprietary switching technique that enhances dynamic performance 5 The current output s of the AD9736 family are easily con figured for single ended or differential circuit topologies One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 Analog Devices Inc All rights reserved AD9734 AD9735 AD9736 TABLE OF CONTENTS tuns 1 Full Scale Current FSC Registers Reg 2 Reg 3 31 Applications sette ee e RUDI pepe ters 1 LVDS Controller 5 Registers Reg 4 Reg 5 Reg aa w a bte aie 31 General Description o ette A E 1 SYNC Controller SYNC CNT Registers Functional Block 4 4 4 4 1 Reg 7 8 e y ERR 32 Product Highlights 1 Cross Controller CROS CNT Registers Revision History 3 Reg 10 Reg 11 1 44 4 40 0000 00 4 4 92 Specifications 4 Analog Control ANA CNT Registers R g 145 Reg 33 DC Specificatlons 4 Built In Self Test Control BIST CNT Registers Digital Specifications rete itae tear 6 Reg 17 Reg 18 Reg 19 Reg 20 Reg 21 33 Specifications edited te 8 Controller Clock Predivider CCLK DIV Reading Register 22 iiie euo eei He 34 Absolute Maximum Ratings u
47. DE Figure 89 lrs vs DAC Gain Code Rev A Page 49 of 72 AD9734 AD9735 AD9736 APPLICATIONS INFORMATION DRIVING THE DACCLK INPUT The DACCIK input requires a low jitter differential drive TTL OR CMOS d signal It is a PMOS input differential pair powered from the TOUT 1 8 V supply so it is important to maintain the specified 400 mV input common mode voltage Each input pin can safely swing 500 BAV99ZXCT from 200 mV p p to 800 mV p p about the 400 mV common L HIGH SPEED mode voltage While these input levels are not directly LVDS VO d 3 compatible DACCLK can be driven by an offset ac coupled fon s LVDS signal as shown in Figure 90 Figure 91 TTL or CMOS DACCLK Drive Circuit LVDS P IN A simple bias network for generating is shown in 500 Figure 92 It is important to use CVDD18 and CVSS for the Vom 400 clock bias circuit Any noise or other signal that is coupled onto 500 the clock is multiplied by the DAC digital input signal and may LVDS N IN 5 degrade the DAC performance 1 8 3 Vom 400mV Figure 90 LVDS DACCLK Drive Circuit zu If a clean sine clock is available it can be transformer coupled To to DACCLK as shown in Figure 107 Use ofa CMOS or TTL 2870 clock can also be acceptable for lower sample rates It is routed Cvss 5 through a CMOS to LVDS translator then ac coupled as Figure 92 Generator Circuit described previously
48. DE DATAFRMT PD Table 10 Mode Register Bit Descriptions Bit Name Read Write Description SDIO_DIR WRITE 0 input only per SPI standard 1 bidirectional per SPI standard LSB MSB WRITE 0 MSB first per SPI standard 1 LSB first per SPI standard NOTE Only change LSB MSB order in single byte instructions to avoid erratic behavior due to bit order errors RESET WRITE 0 execute software reset of SPI and controllers reload default register values except Registers 0x00 and 0x04 1 set software reset write 0 on the next or any following cycle to release the reset LONG_INS WRITE 0 short single byte instruction word 1 long two byte instruction word not necessary since the maximum internal address is REG31 Ox1F 2x_MODE WRITE 0 disable 2x interpolation filter 1 enable 2x interpolation filter FIFO MODE WRITE 0 disable FIFO synchronization 1 enable FIFO synchronization DATAFRMT WRITE 0 signed input DATA with midscale 0x0000 1 unsigned input DATA with midscale 0x2000 PD WRITE 0 enable LVDS Receiver DAC and clock circuitry 1 power down LVDS Receiver DAC and clock circuitry INTERRUPT REQUEST REGISTER IRQ REG 1 ADDR Name Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x01 IRQ LVDS SYNC CROSS RESERVED IE_LVDS IE_SYNC IE_CROSS RESERVED Table 11 Interrupt Register Bit Descriptions
49. MALIZED TO Figure 75 Interpolation Filter Response 04862 073 0 10 0 08 0 06 0 04 0 02 0 02 MAGNITUDE dB 0 04 0 06 0 08 0 10 0 0 05 0 10 0 15 0 20 0 25 FREQUENCY NORMALIZED TO fpac 04862 074 Figure 76 Interpolation Filter Pass Band Flatness DATA INTERFACE CONTROLLERS Two internal controllers are utilized in the operation of the AD973x The first controller helps maintain optimum LVDS data sampling the second controller helps maintain optimum synchronization between the DACCLK and the incoming data The LVDS controller is responsible for optimizing the sampling of the data from the LVDS bus DB13 0 while the sync controller resolves timing problems between the DAC CLK CLK and the DATACLK A block diagram of these controllers is shown in Figure 77 DATACLK DATACLK OUT CLK DATACLK CONTROL LVDS SYNC CONTROLLER CONTROLLER DB lt 13 0 gt Figure 77 Data Controllers 04862 075 The controllers clocked with divided down version of the DAC CLK The divide ratio is set utilizing the controller clock predivider bits CCD lt 3 0 gt located at Reg 22 Bits 3 0 to generate the controller clock as follows Controller Clock CLK 2 CCD 3 0 4 Note that the controller clock cannot exceed 10 MHz for correct operation Until CCD lt 3 0 gt is properly programmed to meet this requiremen
50. ODE 0 IRQ Active low open drain interrupt request output pull up to DVDD33 with 10 resistor If PIN MODE 1 UNSIGNED Digital input pin where 0 twos complement input data format 1 unsigned If PIN MODE 0 RESET 1 resets the AD9735 If PIN MODE 1 PD 1 puts the AD9735 in the power down state See the Serial Peripheral Interface section and the Pin Mode Operation section for pin description See the Pin Mode Operation section for pin description See the Pin Mode Operation section for pin description See the Pin Mode Operation section for pin description 1 8 V Digital Supply Digital Supply Ground Rev A Page 12 of 72 AD9734 AD9735 AD9736 Pin No Mnemonic Description K13 14 0 lt 11 gt 0 lt 11 gt Negative Positive Data Input Bit 11 MSB Conforms to 1596 reduced range link L1 PIN MODE 0 SPI Mode SPI is enabled 1 PIN Mode SPI disabled direct pin control L7 L8 M7 M8 N7 N8 P7 P8 DVDD33 3 3 V Digital Supply 113 114 M1 2 13 14 1 1 N2 P2 N3 P3 N4 P4 N5 P5 N6 P6 N9 P9 N10 P10 N11 P11 N12 P12 N13 P13 N14 P14 DB 10 DB 10 4 NC DB 9 DB 9 4 NC DB lt 0 gt DB lt 0 gt DB lt 1 gt DB lt 1 gt DB 2 DB 2 4 DB 3 DB 3 4 DATACLK OUT DATACLK_OUT DATACLK IN DATACLK 0 lt 4 gt 0 lt 4 gt 0 lt 5 gt 0 lt 5 gt 0 lt 6 gt 0 lt 6 gt
51. OUTB IOUTA 9 10 11 12 13 14 1120 Figure 8 Analog and SPI Control Pins Top View VREF IPTAT PIN MODE 0 SPI ENABLED IRQO ORESET CSBO Osbio SCLKO Ospo PIN_MODE 1 SPI DISABLED UNSIGNEDO OPD 2xO OFIFO 5 OFsc1 04862 006 AD9734 AD9735 AD9736 TERMINOLOGY Linearity Error Integral Nonlinearity or INL The maximum deviation of the actual analog output from the ideal output determined by a straight line drawn from zero to full scale Differential Nonlinearity DNL The measure of the variation in analog value normalized to full scale associated with a 1 LSB change in digital input code Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases Offset Error The deviation of the output current from the ideal of zero For IOUTA 0 mA output is expected when the inputs are all 0s For IOUTB 0 mA output is expected when all inputs are set to 1s Gain Error The difference between the actual and ideal output span The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to Os Output Compliance Range The range of allowable voltage at the output of a current output DAC Operation beyond the maxim
52. Pin Function Descriptions Pin No Mnemonic Description A1 A2 A3 B1 B2 B3 C1 C2 C3 D2 D3 CVDD18 1 8V Clock Supply A4 A5 A9 A10 A11 B4 B5 B6 B9 AVSS Analog Supply Ground B10 B11 CA C5 C6 C9 C10 C11 DA D5 D6 D9 D10 D11 A7 B7 C7 D7 IOUTB DAC Negative Output 10 mA to 30 mA full scale output current A8 B8 C8 D8 IOUTA DAC Positive Output 10 mA to 30 mA full scale output current A12 A13 B12 B13 C12 C13 D12 D13 AVDD33 3 3 V Analog Supply A14 DNC Do Not Connect B14 1120 Nominal 1 2 V Reference Tie to analog ground via 10 resistor to generate a 120 pA reference current 614 VREF Band Gap Voltage Reference I O Tie to analog ground via 1 nF capacitor output impedance approximately 5 kO 01 E2 E4 F2 F4 G1 G2 G3 G4 CVSS Clock Supply Ground D14 IPTAT Factory Test Pin Output current proportional to absolute ET F1 E11 E12 F11 F12 G11 G12 E13 E14 F13 F14 G13 G14 H1 H2 H3 H4 H11 H12 H13 H14 J1 J2 J3 J4 J11 J12 J13 J14 K1 K2 K3 K4 K11 K12 L2 L3 L4 L5 L6 L9 L10 L11 L12 M3 M4 M5 M6 M9 M10 M11 M12 DACCLK DACCLK AVSS IRQ UNSIGNED RESET PD CSB 2x SDIO FIFO SCLK FSCO SDO FSC1 DVDD18 DVSS temperature is approximately 10 A at 25 C with a slope of approximately 20 nA C Negative Positive DAC Clock Input DACCLK Analog Supply Ground Shield Tie to AVSS at the DAC If PIN_M
53. RITE 00 write result of the LVDS Phase 1 BIST to BIST lt 31 0 gt 01 write result of the LVDS Phase 2 BIST to BIST lt 31 0 gt 10 write result of the SYNC Phase 1 BIST to BIST lt 31 0 gt 11 write result of the SYNC Phase 2 BIST to BIST lt 31 0 gt SIG_READ WRITE 0 no action 1 enable BIST signature readback LVDS_EN WRITE 0 no action 1 enable LVDS BIST SYNC_EN WRITE 0 no action 1 enable SYNC BIST CLEAR WRITE 0 no action 1 clear all BIST registers BIST lt 31 0 gt READ Results of the built in self test Rev A Page 33 of 72 AD9734 AD9735 AD9736 CONTROLLER CLOCK PREDIVIDER CCLK DIV READING REGISTER REG 22 ADR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x16 CCLK_DIV RESERVED RESERVED RESERVED RESERVED CCD lt 3 gt CCD lt 2 gt CCD lt 1 gt CCD lt 0 gt Table 18 Controller Clock Predivider Register Bit Descriptions Bit Name Read Write Description CCD lt 3 0 gt WRITE 0x0 controller clock DACCLK 16 0x1 controller clock DACCLK 32 0x2 controller clock DACCLK 64 OxF controller clock DACCLK 524288 NOTE The 100 MHz to 1 2 GHz DACCLK must be divided to less than 10 MHz for correct operation CCD lt 3 0 gt must be programmed to divide the DACCLK so that this relationship is not violated Controller clock DACCLK 2 CCD lt 3 0 gt 4 Rev A Page 34 of 72 AD9734 AD
54. S which is a delayed version of DACCLK IN The data is read out of the memory based on a second cyclic read counter clocked by DACCLK The 8 word FIFO shown in Figure 82 provides sufficient margin to maintain proper timing under most conditions The sync logic is designed to prevent the read and write pointers from crossing If the timing drifts far enough to require an update of the phase offset lt 1 0 gt two samples are duplicated or dropped Figure 83 shows the timing diagram for the sync logic DAC lt 13 0 gt DAC lt 13 0 gt FIFOSTAT lt 2 0 gt DSS 04862 080 Figure 82 Sync Logic Block Diagram SYNC LOGIC AND CONTROLLER OPERATION The relationship between the readout pointer and the write pointer initially is unknown because the startup relationship between DACCLK DATACLK IN is unknown The sync logic measures the relative phase between the two counters with the zero detect block and the flip flop in Figure 82 The relative phase is returned FIFOSTAT lt 2 0 gt Reg 7 Bits 6 4 and sync logic errors are indicated by FIFOSTAT lt 3 gt Reg 7 Bit 7 If FIFOSTAT lt 2 0 gt returns a value of 0 or 7 the memory is sampling in a critical state read and write pointers are close to crossing If the FIFOSTAT lt 2 0 gt returns a value of 3 or 4 the memory is sampling at the optimal state read and write pointers are farthest apart If FIFOSTAT lt 2 0 gt returns a critical value the pointer can
55. TION The long instruction bytes are shown in the following table MSB LSB 115 114 113 112 111 110 19 8 R W N1 NO A12 A11 A10 A9 A8 17 l6 15 14 12 n 10 A7 6 5 4 2 1 0 If LONG INS 1 Reg 0 Bit 4 the instruction byte is extended to 2 bytes where the second byte provides an additional 8 bits of address information Address 0x00 to Address 0x1F are equivalent in short and long instruction modes The AD973x does not use any addresses greater than 31 Ox1F so always set LONG INS 0 SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK Serial Clock The serial clock pin is used to synchronize data to and from the AD973x and to run the internal state machines The maximum frequency of SCLK is 20 MHz All data input to the AD973x is registered on the rising edge of SCLK All data is driven out of the AD973x on the rising edge of SCLK Rev A Page 36 of 72 AD9734 AD9735 AD9736 CSB Chip Select For multibyte transfers writing to this register can occur during Active low input starts and gates a communication cycle It the middle of the communication cycle Care must be taken to allows more than one device to be used on the same serial compensate for this new configuration for the remaining bytes communications lines The SDO and SDIO pins go to a high of the current communication cycle The same considerations impedance state when this input is high Chip select should sta
56. VDD33 3 3V Analog Supply A14 DNC Do Not Connect 14 1120 Nominal 1 2 V Reference Tie to analog ground via 10 resistor to generate a 120 pA reference current 614 VREF Band Gap Voltage Reference I O Tie to analog ground via 1 nF capacitor output impedance is approximately 5 kO D1 E2 E4 F2 F3 F4 G1 G2 G3 G4 CVSS Clock Supply Ground D14 IPTAT Factory Test Pin Output current proportional to absolute ET F1 E11 E12 F11 F12 G11 G12 E13 E14 F13 F14 G13 G14 H1 H2 H3 H4 H11 H12 H13 H14 J1 J2 J3 J4 J11 J12 J13 J14 DACCLK DACCLK AVSS IRQ UNSIGNED RESET PD CSB 2x SDIO FIFO SCLK FSC0 SDO FSC1 DVDD18 temperature is approximately 10 A at 25 C with a slope of approximately 20 nA C Negative Positive DAC Clock Input DACCLK Analog Supply Ground Shield Tie to AVSS at the DAC If PIN MODE 0 IRQ Active low open drain interrupt request output pull up to DVDD33 with 10 resistor If PIN MODE 1 UNSIGNED Digital input pin where 0 twos complement input data format 1 2 unsigned If PIN MODE 0 RESET 1 resets the AD9736 If PIN MODE 1 PD 1 puts the AD9736 in the power down state See the Serial Peripheral Interface section and the Pin Mode Operation section for pin description See the Pin Mode Operation section for pin description See the Pin Mode Operation section for pin description See the Pin Mode Operation section for pin descr
57. a POSSA N9SGA1 80 os oaa cossa 22 4 dead asoas gso zossa 34 Ej Neaa e 23 dsad aesan V 13934 13934 Qd d oul N19 OldLO ma atga 22 1HM Nvaa N6SGA1 1 dead doLSaA1 alsan T wg Nega NOLSQA1 NISQA1 d0SQA1 aciaa M 2M VagA NOSGA1 jg Neta 69 var diaa dziSa 1 Ids VSSA T 1V1dl NZLSGAT ZZSSA oa p VSSA guuvas vERVOGA d08G yyy d SdA1 LYON Hy sar 09094 Heyy NELSQAT VZSSA 24 OLDER z OXOL ca ZLSSA 6SSA Paw H 09009 Ve vadA LV 29000 ESSA SSSA 7286 66 2 66 66 issn 99 2256 66 5 59 LIKEN EN DAI 55 0 66 66 SSA ZEEYSSA 6 evSSA eu SCA a OZEEYSSA 8ELYSSA GLEEVSSA ESSA d 90000 pu
58. aken when using PIN_MODE because only the control bits shown in Table 22 can be changed If the remaining register default values are not suitable for the desired operation PIN_MODE cannot be used If the FIFO is enabled the controller clock must be less than 10 MHz This limits the DAC clock to 160 MHz RESET OPERATION The RESET pin forces all SPI register contents to their default values see Table 9 which places the DAC in a known state The software reset bit forces all SPI register contents except Reg 0 and Reg 4 to their default values The internal reset signal is derived from a logical OR operation on the RESET pin state and from the software reset state This internal reset signal drives all SPI registers to their default values except Reg 0 and Reg 4 which are unaffected The data registers are not affected by either reset The software reset is asserted by writing 1 to Reg 0 Bit 5 It may be cleared on the next SPI write cycle or a later write cycle PROGRAMMING SEQUENCE The AD973x registers should be programmed in this order Reset hardware Make changes to SPI port configuration if necessary Input format if unsigned Interpolation if in 2x mode Calibrate and set the LVDS controller Enable the FIFO Calibrate and set the sync controller Step 1 through Step 4 required while Step 5 through Step 7 are optional The LVDS controller can help assure proper data
59. al in the region of a removed tone Rev A Page 17 of 72 AD9734 AD9735 AD9736 TYPICAL PERFORMANCE CHARACTERISTICS AD9736 STATIC LINEARITY 10 mA FULL SCALE 1 00 1 0 0 75 0 8 0 50 0 6 0 25 0 4 0 0 25 m 4 4 x 0 50 5 0 75 9 r4 r4 4 00 1 25 0 6 1 50 1 75 0 8 2 00 2 1 0 5 0 2048 4096 6144 8192 10240 12288 14336 16384 5 0 2048 4096 6144 8192 10240 12288 14336 16384 5 CODE 3 CODE 3 Figure 9 AD9736 INL 40 C 10 mA FS Figure 12 AD9736 DNL 40 C 10 mA FS 1 00 1 0 0 75 0 8 0 50 0 6 0 25 0 4 0 0 25 m 4 4 70 50 5 0 75 9 r4 r4 1 00 u 1 25 0 6 1 50 1 75 0 8 2 00 2 1 0 z 0 2048 4096 6144 8192 10240 12288 14336 16384 5 0 2048 4096 6144 8192 10240 12288 14336 16384 5 CODE CODE Figure 10 AD9736 25 C 10 mA FS Figure 13 AD9736 DNL 25 C 10 mA FS 1 00 1 0 0 75
60. ale Package Ball Grid Array CSP BC 160 1 AD9736BBCZ 40 to 85 C 160 Lead Chip Scale Package Ball Grid Array CSP_BGA BC 160 1 AD9736BBCZRL 40 C to 85 C 160 Lead Chip Scale Package Ball Grid Array CSP_BGA BC 160 1 AD9734 EB Evaluation Board AD9735 EB Evaluation Board AD9736 EB Evaluation Board 17 Pb free part Rev A Page 69 of 72 AD9734 AD9735 AD9736 NOTES Rev A Page 70 of 72 AD9734 AD9735 AD9736 NOTES Rev A Page 71 of 72 AD9734 AD9735 AD9736 NOTES 2006 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D04862 0 9 06 A DEVICES www analo g com Rev A Page 72 of 72
61. as shown in Figure 86 1 23 1 22 1 21 VREF V 1 2 101 110 1 19 111 04862 084 1 18 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE C Figure 86 Band Gap Temperature Characteristic for Various TRMBG Values The temperature changes are sensitive to process variations and Figure 86 may not be representative of all fabrication lots Optimum adjustment requires measurement of the device operation at two temperatures and development of a trim algorithm to program the correct TRMBG lt 2 0 gt values in external nonvolatile memory MIRROR ROLL OFF FREQUENCY CONTROL With MSEL 1 0 Reg 14 Bits 7 6 the user can adjust the noise contribution of the internal current mirror to optimize the 1 f noise Figure 87 shows MSEL vs the 1 f noise with 20 mA full scale current into a 50 resistor 110 125 NOISE IdBm Hz 130 135 140 04862 0 085 1 10 1 F kHz Figure 87 1 f Noise with Respect to MSEL Bits e HEADROOM BITS HDRM 7 0 Reg 15 Bits 7 0 are for internal evaluation Changing the default reset values is not recommended VOLTAGE REFERENCE The AD973x output current is set by a combination of digital control bits and the I120 reference current as shown in Figure 88 AD973x 5 lt 9 0 gt CURRENT
62. ation ERR LO READ One of the 15 LVDS inputs is below the input voltage limits of the IEEE reduced link specification CHECK READ 0 phase measurement sampling in the previous or following DATA cycle 1 phase measurement sampling in the correct DATA cycle LSURV WRITE 0 the controller stops after completion of the current measurement cycle 1 continuous measurements are taken and an interrupt is issued if the clock alignment drifts beyond the threshold value LAUTO WRITE 0 sample delay is not automatically updated 1 continuously starts measurement cycles and updates the sample delay according to the measurement NOTE LSURV Reg 6 Bit 7 must be set to 1 and the LVDS Reg 1 Bit 3 must be set to 0 for AUTO mode LFLT lt 3 0 gt WRITE 0x0 average filter length Delay Delay Delta Delay 2 LFLT lt 3 0 gt values greater than 12 0 0 are clipped to 12 LTRH lt 2 0 gt WRITE 000 set auto update threshold values Rev A Page 31 of 72 AD9734 AD9735 AD9736 SYNC CONTROLLER SYNC CNT REGISTERS REG 7 REG 8 ADDR Name Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 0x07 SYNC 1 FIFOSTAT3 FIFOSTAT2 FIFOSTAT1 FIFOSTATO VALID SCHANGE PHOF lt 1 gt lt 0 gt 0 08 SYNC CNT2 SSURV SAUTO SFLT 3 SFLT 2 SFLT lt 1 gt SFLT 0 RESERVED STRH 0 Table 14 Sync Controller Register Bit Descriptions Bit Name Read Wr
63. ative Positive Data Input Bit 2 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 3 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 4 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 5 Conforms to IEEE 1596 reduced range link Negative Positive Data Output Clock Conforms to IEEE 1596 reduced range link Negative Positive Data Input Clock Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 6 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 7 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 8 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 9 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 10 Conforms to IEEE 1596 reduced range link Rev A Page 11 of 72 AD9734 AD9735 AD9736 1234 5 6 7 8 9 10 11 12 13 14 A B D DACCLK E OOO DACCLK F Boos H OOOO J OOOO L N 8888 3588 DATACLK OUT DB11 MSB DB10 DB9 Z m p al 9 g 3 a Figure 3 AD9735 Digital LVDS Input Clock I O Top View Table 7 AD9735
64. continues to run LVDS SAMPLE LOGIC simplified diagram of the AD973x LVDS data sampling engine is shown in Figure 78 and the timing diagram is shown in Figure 79 The incoming LVDS data is latched by the data sampling signal DSS which is derived from DATACLK IN The LVDS controller delays DATACLK IN to create the data sampling signal DSS which is adjusted to sample the LVDS data in the center of the valid data window The skew between the DATACLK IN and the LVDS data bits DB lt 13 0 gt must be minimal for proper operation Therefore it is recommended that the DATACLK IN be generated in the same manner as the LVDS data bits DB lt 13 0 gt with the same driver and data lines that is it should just be another LVDS data bit running a constant 01010101 sequence as shown in Figure 96 If the DATACLK IN signal is stopped the DACCLK continues to generate an output signal based on the last two values clocked into the registers that drive D1 and D2 as shown in Figure 78 If these two registers are not equal a large output at a frequency of one half can be generated at the DAC output DB lt 13 0 gt DATA SAMPLING SIGNAL SD lt 3 0 gt SAMPLE DELAY MSD lt 3 0 gt DELAY Figure 78 Internal LVDS Data Sampling Logic CHECK CLOCK SAMPLING SIGNAL 04862 076 CLK TO DB SKEW DB13 0 DATACLK IN PROP DELAY TO LATCH DATA SAMPLING SIGNAL DSS PROP DELAY TO LATCH 01 2 3 Figure 79 Inte
65. d DNDEL the charge injection into the positive and negative outputs This we INCREMENT DNDEL TO MOVE adjustment impacts certain performance characteristics such as X THE CROSSING TOWARD THE harmonic distortion or IMD System performance can be en hanced by adjusting the cross controller 4 IDEAL DIFFERENTIAL OUTPUT CROSSING ALIGNMENT If the system is calibrated after manufacture adjust the cross controller offsets to provide optimum performance To start increment DNDEL 5 0 Reg 11 Bits 5 0 while observing INCREMENT UPDEL TO MOVE x THE CROSSING TOWARD THE HD2 second harmonic distortion and or IMD to find the IDEAL VALUE desired optimum If DNDEL does not influence the perform ance set it to 0 and increment UPDEL 5 0 Reg 10 Bits 5 0 Based on system characterization set one of these controls to the maximum value to yield the best performance 04862 083 Figure 85 Effect of UPDEL and DNDEL Rev A Page 47 of 72 AD9734 AD9735 AD9736 ANALOG CONTROL REGISTERS The AD973x includes some registers for optimizing its analog performance These registers include temperature trim for the band gap noise reduction in the output current mirror and output current mirror headroom adjustments BAND GAP TEMPERATURE CHARACTERISTIC TRIM BITS Using TRMBG lt 2 0 gt Reg 14 Bits 2 0 the temperature characteristic of the internal band gap can be trimmed to minimize the drift over temperature
66. e DATACLK_IN 04862 097 Figure 99 FPGA ASIC Timing for Driving AD973x Digital Inputs 2x Mode Rev A Page 53 of 72 AD9734 AD9735 AD9736 INPUT DATA TIMING The AD973x is intended to operate with the LVDS and sync controllers running to compensate for timing drift due to voltage and temperature variations In this mode the key to correct data capture is to present valid data for a minimum amount of time The AD973x minimum valid data time is measured by increasing the input data rate to the point of failure The nominal supply voltages are used and the temperature is set to the worst case of 85 C The input data is verified via the BIST signature registers because the DAC output does not run as fast as the input data logic The following example explains how the minimum data valid period is calculated for the typical performance case These factors must be considered in determining the minimum valid data window at the receiver input e Data rise and fall times 100 ps rise fall e Internal clock jitter 10 ps DATACLK_OUT DATACLK_IN Bit to bit skew 50 ps Bit to DATACLK IN skew 50 ps e Internal data sampling signal resolution 80 ps For nominal silicon the BIST typically indicates failure at 2 15 GSPS or a DACCLK period of 465 ps The valid data window is calculated by subtracting all the other variables from the total data period Minimum Data Valid Time DACCLK Period Data Rise Data Fall
67. ecause T1 has a differential input but a single ended output Pin 4 of T1 has a higher capacitance to ground due to parasitics to Pin 3 T1 Pin 6 has lower parasitic capacitance to ground because it drives 50 at Pin 1 This presents unbalanced load to the DAC output so T3 is added to improve the load balancing Refer to Figure 107 for the transformer part numbers Rev A Page 51 of 72 AD9734 AD9735 AD9736 DC COUPLED DAC OUTPUT In some cases it may be desirable to dc couple the AD973x output The best method for doing this is shown in Figure 94 This circuit can be used with voltage or current feedback amplifiers Because the DAC output current is driving a virtual ground this circuit may offer enhanced settling times The settling time is limited by the op amp rather than by the DAC This circuit is intended for use where the amplifiers can be powered by a bipolar supply 2Vp p DAC 1V TO 1V eU PUT OUTPUT IOUTB 04862 092 Figure 94 Op Amp I to V Conversion Output Circuit An alternate circuit is shown in Figure 95 It suffers from dc offset at the output unless the DAC load resistors are small relative to the amplifier gain and feedback resistors 0 5V p p x OV TO 0 5V IOUTA 2V pp DAC OUTPUT ov TO 2V 20 FULL SCALE OUTPUT 2 IOUTB AVSS 04862 093 Figure 95 Differential Op Amp Output Circuit Rev A Page 52 of 72 AD9734 AD9735 AD9736 DAC DATA SOURCES The circuit show
68. etup and hold values in Table 28 conform to the standard convention of setup time occurring prior to the latching edge and hold time occurring after the latching edge as shown in Figure 102 Symbol and Definition Fast 40 Typ 40 C All 25 C Typ 85 C Slow 85 C Unit DACCLK to DATACLK OUT Delay 1650 1800 1890 2050 2350 ps tocisu DATACLK_IN to DATA Setup 100 120 150 170 220 ps DATACLK IN to DATA Hold 210 220 240 280 360 ps tosu DATACLK OUT to DATA Setup 1310 1440 1611 1710 1970 ps toin DATACLK_OUT to DATA Hold 1250 1360 1548 1640 1890 ps Rev A Page 55 of 72 AD9734 AD9735 AD9736 POWER SUPPLY SEQUENCING The 1 8 V supplies should be enabled prior to enabling the 3 3 V supplies Do not enable the 3 3 V supplies when the 1 8 V supplies are off DATACLK_IN DOMAIN i DACCLK DOMAIN 1 D1 D1A DB lt 13 0 gt DAC_OUTPUT DATA SAMPLING SIGNAL DACCLK COMMON SYSTEM CLOCK DELAYS THROUGH PATH A AND B WILL TRACK THUS REDUCING TIMING UNCERTAINTY IN THE SYSTEM 04862 101 Figure 103 Simplified Internal Clock Routing Rev A Page 56 of 72 AD9734 AD9735 AD9736 AD973x EVALUATION BOARD SCHEMATICS 4 33DIG L6 FERRITE RED VDD33 LC1210 ct ACASE 10uF 6 3V 2 vss TP5 BLK L7 FERRITE VDD18B LC1210 n 022 ACASE 10uF eU
69. foac 491 52 MSPS REF 22 754 AVG LOG 10dB ATTEN 6dB 04862 059 VBW 300kHz SPAN 33 88MHz 10 S2 SWEEP 109 9ms 601pts CENTER 134 83MHz RES BW 30kHz LOWER UPPER RMS RESULTS OFFSET FREQ REF BW dBc dBm dBc dBm CARRIER POWER 5 00MHz 3 840MHz 71 07 81 83 71 23 81 99 10 76dBm 10 0MHz 3 840MHz 70 55 81 31 71 42 82 19 3 84000MHz 15 0MHz 3 884MHz 70 79 81 56 71 25 82 01 Figure 67 AD9734 WCDMA Carrier at 134 83 MHz foac 491 52 MSPS Rev A Page 28 of 72 AD9734 AD9735 AD9736 SPI REGISTER MAP Write 0 to unspecified or reserved bit locations Reading these bits returns unknown values Table 9 SPI Register Map Reg Addr Default Pin Mode Dec Hex Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex Hex 0 00 MODE SDIO DIR LSBFIRST RESET LONG INS 2X MODE FIFO MODE DATAFRMT PD 00 00 1 01 IRQ LVDS SYNC CROSS RESERVED IE_LVDS IE_SYNC IE_CROSS RESERVED 00 00 2 02 FSC_1 SLEEP FSC lt 9 gt FSC lt 8 gt 02 02 3 03 FSC_2 FSC lt 7 gt FSC lt 6 gt FSC lt 5 gt FSC lt 4 gt FSC lt 3 gt FSC lt 2 gt FSC lt 1 gt 5 lt 0 gt 00 00 4 04 LVDS 1 MSD lt 3 gt MSD lt 2 gt MSD lt 1 gt MSD lt 0 gt MHD lt 3 gt MHD lt 2 gt MHD 1 MHD 0 00 00 5 05 LVDS CNT2 SD 3 SD 2 SD lt 1 gt SD lt 0 gt LCHANGE ERR_HI ERR_LO CHECK 00 00 6 06 LVDS_CNT3 LSURV LAUTO LFLT lt 3 gt LFLT lt 2 gt LFLT lt 1 gt LFLT 0 LTRH
70. heck bit goes low To find the trailing edge increment the measured hold delay MHD until check goes low Always set MHD 0 when incrementing MSD and vice versa The incremental units of SD MSD and MHD are in units of real time not fractions of a clock cycle The nominal step size is 80 ps OPERATING THE LVDS CONTROLLER IN MANUAL MODE VIA THE SPI PORT The manual operation of the LVDS controller allows the user to step through both the setup and hold delays to calculate the optimal sampling delay that is the center of the data eye With SD lt 3 0 gt and MHD lt 3 0 gt set to 0 increment the setup time delay MSD lt 3 0 gt Reg 4 Bits 7 4 until the check bit Reg 5 Bit 0 goes low and record this value This locates the leading DATACLK IN and data transition as shown in Figure 80 With SD lt 3 0 gt and MSD lt 3 0 gt set to 0 increment the hold time delay MHD lt 3 0 gt Reg 4 Bits 3 0 until the check bit Reg 5 Bit 0 goes low and record this value This locates the trailing DATACLK IN and DB lt 13 0 gt transition as shown in Figure 81 Once both DATACLK IN edges are located the sample delay SD lt 3 0 gt Reg 5 Bits 7 4 must be updated by Sample Delay MHD MSD 2 After updating SD lt 3 0 gt verify that the sampling signal is in the middle of the valid data window by adjusting both MHD and MSD with the new sample delay until the check bit goes low The new MHD and MSD values should be equal to
71. idest bandwidth NOTE See the plot in the Analog Control Registers section lt 2 0 gt 000 band gap temperature characteristic trim NOTE See the plot in the Analog Control Registers section HDRM lt 7 0 gt WRITE OxCA output stack headroom control HDRM lt 7 4 gt set reference offset from AVDD33 VCAS centering HDRM lt 3 0 gt set overdrive current density trim temperature tracking Note Set to for optimum performance BUILT IN SELF TEST CONTROL BIST_CNT REGISTERS REG 17 REG 18 REG 19 REG 20 REG 21 ADDR Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 0x11 BIST_CNT SEL lt 1 gt SEL lt 0 gt SIG READ 5 EN SYNC EN CLEAR 0x12 5 lt 7 0 gt 5 lt 7 gt 5 lt 6 gt 5 lt 5 gt BIST lt 4 gt BIST lt 3 gt BIST lt 2 gt BIST lt 1 gt 5 lt 0 gt 0x13 BIST lt 15 8 gt BIST lt 15 gt BIST lt 14 gt BIST lt 13 gt BIST lt 12 gt BIST lt 11 gt BIST lt 10 gt BIST lt 9 gt BIST lt 8 gt 0x14 BIST lt 23 16 gt BIST lt 23 gt BIST lt 22 gt BIST lt 21 gt BIST lt 20 gt BIST lt 19 gt BIST lt 18 gt BIST lt 17 gt BIST lt 16 gt 0x15 BIST lt 31 24 gt BIST lt 31 gt BIST lt 30 gt BIST lt 29 gt BIST lt 28 gt BIST lt 27 gt BIST lt 26 gt BIST lt 25 gt BIST lt 24 gt Table 17 BIST Control Register Bit Descriptions Bit Name Read Write Description SEL lt 1 0 gt W
72. iption 1 8 V Digital Supply Rev A Page 10 of 72 AD9734 AD9735 AD9736 Pin No Mnemonic Description K1 K2 K3 K4 K11 K12 L2 L3 L4 L5 L6 L9 L10 L11 L12 M3 M4 5 M6 9 M10 M11 M12 K13 K14 L1 L7 L8 M7 M8 7 N8 P7 P8 113 114 2 1 M13 M14 N1 P1 N2 P2 N3 P3 N4 P4 N5 P5 N6 P6 N9 P9 N10 P10 N11 P11 N12 P12 N13 P13 N14 P14 DVSS DB 13 DB 13 4 PIN MODE DVDD33 DB 12 DB 12 4 DB lt 0 gt DB lt 0 gt DB lt 11 gt DB lt 11 gt DB lt 1 gt DB lt 1 gt DB lt 2 gt DB lt 2 gt DB lt 3 gt DB lt 3 gt DB lt 4 gt DB lt 4 gt DB lt 5 gt DB lt 5 gt DATACLK OUT DATACLK_OUT DATACLK IN DATACLK DB lt 6 gt DB lt 6 gt DB lt 7 gt DB lt 7 gt DB lt 8 gt DB lt 8 gt DB lt 9 gt DB lt 9 gt DB 10 DB 10 4 Digital Supply Ground Negative Positive Data Input Bit 13 MSB Conforms to IEEE 1596 reduced range link 0 SPI Mode SPI is enabled 1 PIN Mode SPI is disabled direct pin control 3 3V Digital Supply Negative Positive Data Input Bit 12 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 0 LSB Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 11 Conforms to IEEE 1596 reduced range link Negative Positive Data Input Bit 1 Conforms to IEEE 1596 reduced range link Neg
73. is not implied Exposure to absolute maximum ratings for extended periods may effect device reliability THERMAL RESISTANCE is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 5 Thermal Resistance Package Type Unit 160 Lead Ball CSP BGA 312 C W Table 4 With Parameter Respectto Min Max AVDD33 AVSS 0 3V 3 6 V DVDD33 DVSS 0 3 V 3 6 V DVDD18 DVSS 0 3 V 1 98 V CVDD18 CVSS 0 3 V 1 98 V AVSS DVSS 0 3V 40 3 V AVSS CVSS 0 3 V 0 3 V DVSS CVSS 0 3 V 0 3 V CLK CLK CVSS 0 3 V CVDD18 0 18 V PIN_MODE DVSS 0 3 V DVDD33 DATACLK_IN DVSS 0 3 V DVDD33 0 3 V DATACLK_OUT LVDS Data Inputs DVSS 0 3 V DVDD33 0 3 V IOUTA IOUTB AVSS 1 0V AVDD33 0 3 V 1120 VREF IPTAT AVSS 0 3 V AVDD33 0 3 V IRQ CSB SCLK SDO DVSS 0 3 V DVDD33 0 3 V SDIO RESET Junction Temperature 150 C Storage Temperature 65 150 ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality 18 meas
74. ite Description FIFOSTAT 2 0 READ Position of FIFO read counter ranges from 0 to 7 FIFOSTAT 3 READ 0 SYNC logic OK 1 error in SYNC logic VALID READ 0 FIFOSTAT 3 0 is not valid yet 1 FIFOSTAT lt 3 0 gt is valid after a reset SCHANGE READ 0 no change in 5 lt 3 0 gt 1 FIFOSTAT 3 0 has changed since the previous measurement cycle when SSURV 1 surveillance mode active PHOF lt 1 0 gt WRITE 00 change the readout counter READ Current setting of the readout counter PHOF lt 1 0 gt in surveillance mode SSURV 1 after an interrupt Current calculated optimal readout counter value in AUTO mode SAUTO 1 SSURV WRITE 0 the controller stops after completion of the current measurement cycle 1 continuous measurements are taken and an interrupt is issued if the readout counter drifts beyond the threshold value SAUTO WRITE 0 readout counter PHOF 3 0 is not automatically updated 1 continuously starts measurement cycles and updates the readout counter according to the measurement NOTE SSURV Reg 8 Bit 7 must be set to 1 and the SYNC IRQ Reg 1 Bit 2 must be set to 0 for AUTO mode SFLT lt 3 0 gt WRITE 0x0 average filter length FIFOSTAT FIFOSTAT Delta FIFOSTAT 2 SFLT lt 3 0 gt values greater than 12 0xOC are clipped to 12 5 lt 0 gt WRITE 0 if FIFOSTAT lt 2 0 gt 0 or 7 a sync interrupt is generated 1 if FIFOSTAT 2 0 0 1 6 or 7 a sync interrupt is genera
75. lue on the data input also allows the BIST to be set up while the DAC clock is running The idle value should be all 0 in unsigned mode 0x0000 and all 0 except for the MSB in twos complement mode 0x2000 The BIST consists of two stages the first stage is after the LVDS receiver and the second stage is after the FIFO The first BIST stage verifies correct sampling of the data from the LVDS bus while the second BIST stage verifies correct synchronization between the DAC CLK domain and the DATACLK IN domain The BIST vector is generated using 32 bit LFSR signature logic Because the internal architecture is a 2 bus parallel system there are two 32 bit LFSR signature logic blocks on both the LVDS and SYNC blocks Figure 84 shows where the LVDS and SYNC phases are located Table 24 BIST Selection Bits Bit SEL 1 SEL lt 0 gt LVDS Phase 1 0 0 LVDS Phase 2 0 1 SYNC Phase 1 1 0 SYNC Phase 2 1 1 SPI PORT SYNC LOGIC 04862 082 Figure 84 Block Diagram Showing LVDS and SYNC Phase 1 and SYNC Phase 2 Rev A Page 44 of 72 AD9734 AD9735 AD9736 AD973x BIST PROCEDURE 1 Set RESET pin 1 2 Set input DATA 0x0000 for signed 0x2000 for unsigned Enable DATACLK_IN if it is not already running Run for at least 16 DATACLK_IN cycles Set RESET pin 0 Run for at least 16 DATACLK_IN cycles Set RESET pin 1 Run for at least 16 DATACLK_IN cycles Set RESET pin 0 60 M ON GR 10
76. mA FS 04862 033 04862 036 Rev Page 22 of 72 AD9734 AD9735 AD9736 AD9736 POWER CONSUMPTION 20 mA FULL SCALE 0 50 0 45 0 40 0 35 0 30 023 DVDD18 0 20 DVDD18 0 15 0 10 AVDD33 0 05 CVDD18 DVDD33 0 250 500 750 1000 1250 1500 0 250 500 750 1000 1250 1500 5 foac MHz fpac MHz Figure 39 AD9736 1x Mode Power vs foac at 25 C Figure 40 AD9736 2x Interpolation Mode Power vs foacat 25 C Rev A Page 23 of 72 AD9734 AD9735 AD9736 AD9736 DYNAMIC PERFORMANCE 20 mA FULL SCALE 80 SS 75 _ SENS m 5 800MSPS 65 IMD dBc SFDR dBc 60 1 2GSPS 1GSPS 55 50 0 50 100 150 200 250 300 350 400 450 500 550 four MHz 0 50 100 150 200 250 300 350 400 450 500 550 600 four MHz 04862 039 04862 042 Figure 41 AD9736 SFDR vs four over foac at 25 C Figure 44 AD9736 IMD vs four over 50 Parts 25 C 1 2 GSPS 80 75 70 65 800MSPS IMD dBc SFDR dBc 60 55 50 0 50 100 150 200 250 300 350 400 450 500 550 600 four MHz 04862 040 04862 043 four MHz Figure 42 AD9736 SFDR vs four over Temperature Figure 45 AD9736 IMD vs four over foac at 25 C
77. n in Figure 96 allows optimum data alignment when running the AD973x at full speed This circuit can be easily implemented in the FPGA or ASIC used to drive the digital input It is important to use the DATACLK OUT signal because it helps to cancel some of the timing errors In this configuration DATACLK OUT generates the DDR LVDS DATACLK IN to drive the AD973x The circuit aligns the DATACLK IN and the digital input data DB lt 13 0 gt as required by the AD973x The LVDS controller in the AD973x uses DATACLK IN to generate the internal 055 to capture the incoming data in the center of the valid data window DATACLK OUT FROM AD9736 DDR DB 13 0 TO AD9736 DATACLK IN LOGIC 1 TO AD9736 DDR 094 5 04862 Figure 96 Recommended FPGA ASIC Configuration for Driving AD9736 Digital Inputs 1x Mode 04862 095 Figure 97 FPGA ASIC Timing for Driving AD973x Digital Inputs 1x Mode To operate in 2x mode the circuit in Figure 96 must be modified to include a divide by 2 block in the path of DATACLK OUT Without this additional divider the data and DATACLK IN runs 2x too fast DATACLK OUT is always DACCLK 2 Contact FPGA vendors directly regarding the maximum output data rates supported by their products DATACLK OUT FROM AD9736 DDR DB 13 0 TO AD9736 DATACLK LOGIC 1 TO AD9736 DDR LOGIC 0 096 04862 Figure 98 Recommended FPGA ASIC Configuration for Driving AD9736 Digital Inputs 2x Mod
78. o BLK vss L1 L3 L4 L5 L6 AND L7 ES 4FERRITE BEAD CORE RED PANASONIC EXC CL3225U1 VDD18A LC1210 DIGIKEY PN P9811CT ND vss BLK JP1 vss a vssa TP1 33ANA L1 FERRITE RED UNDER DUT CTB2 1 VDDA33 LC1210 ACASE VSSA 6 3v 2 2 VSSA TP3 POWER INPUT FILTERS BLK TP9 18ANA 13 FERRITE RED TB 3 VDDC LC1210 C10 ACASE 10uF 6 3V VSSA L4 FERRITE CTB2 4 VSSA 3 LC1210 TP11 BLK 8 Figure 104 Power Supply Input for AD973x Evaluation Board Rev F Rev A Page 57 of 72 cv 9 cv lt cv cr 82 SSA 01 298 0 HO193NNOO eni SSA lt SI 861 ASN 9 16 3LON GBA ad WOLLOS VSSA i p de ween Jury 15 9013 LLOSSA 554 09059 d 242 509059 919 509059 SLO 3SVOV SQq 13lHS OLOSSA co A 9 759 1 a zt sog S SSS ZO 209009 ju sood V0 Sov rip 57 ttal Zaans rossa LOA 12 NIdy19q dNDIT2SQA1 1 53 8 1n0dw 120 213 58 8 sq wise 09S
79. or within one unit delay if SD lt 3 0 gt was set correctly MHD and MSD may not be equal to or within one unit delay if the external clock jitter and noise exceeds the internal delay resolution Differences of 2 3 or more are possible and can require more filtering to provide stable operation The sample delay calibration should be performed prior to enabling surveillance mode or auto mode SETUP TIME ts DB lt 13 0 gt DATACLK_IN SAMPLE DELAY SD lt 3 0 gt CSS SAMPLE DCS CSS WITH MHD lt 3 0 gt 0 MSD lt 3 0 gt 2012345 DSC DELAYED BY MSD lt 3 0 gt 04862 078 Figure 80 Setup Delay Measurement SETUP TIME ts HOLD TIME tr DB lt 13 0 gt DATACLK_IN DELAY 0 lt 3 0 gt MSD lt 3 0 gt 2012345 CSS SAMPLE DCS 5 CSS WITH gt MHD lt 3 0 gt 0 DSC DELAYED BY MSD lt 3 0 gt 0 CHECK 111110 CHECK 1 04862 079 Figure 81 Hold Delay Measurement OPERATING THE LVDS CONTROLLER IN SURVEILLANCE AND AUTO MODE In surveillance mode the controller searches for the edges of the data eye in the same manner as in the manual mode of operation and triggers an interrupt if the clock sampling signal CSS has moved more than the threshold value set by LTRH lt 1 0 gt Reg 6 Bits 1 0 There is an internal filter that averages the setup and hold time measurements to filter out noise and glitches on the clock lines Average Value MHD MSD 2 New Average A
80. os 25 mV Output Current Driver Shorted to Ground Isa Iss 20 mA Output Current Drivers Shorted Together Isas 4 mA Power Off Output Leakage Ixa 10 mA Maximum Clock Rate 600 MHz DAC CLOCK INPUT CLK Input Voltage Range CLK or CLK 0 800 Differential Peak to Peak Voltage 400 800 1600 mV Common Mode Voltage 300 400 500 mV Maximum Clock Rate 1200 MHz SERIAL PERIPHERAL INTERFACE Maximum Clock Rate 1 tsax 20 MHz Minimum Pulse Width High tewH 20 ns Minimum Pulse Width Low 20 ns Minimum SDIO and CSB to SCLK Setup tps 10 ns Minimum SCLK to SDIO Hold tox 5 ns Maximum SCLK to Valid SDIO and SDO tov 20 ns Minimum SCLK to Invalid SDIO and SDO 5 ns Rev A Page 6 of 72 AD9734 AD9735 AD9736 Parameter Min Typ Max Unit INPUT SDI SDIO SCLK CSB Voltage in High Viu 2 0 3 3 V Voltage in Low Vi 0 0 8 V Current in High 10 10 Current in Low lit 10 10 SDIO OUTPUT Voltage out High Vou 24 3 6 V Voltage out Low Vo 0 0 4 V Current out High lou 4 mA Current out Low lo 4 mA Refer to the Input Data Timing section for recommended LVDS differential drive levels Rev A Page 7 of 72 AD9734 AD9735 AD9736 ACSPECIFICATIONS AVDD33 DVDD33 3 3 V CVDD18 DVDD18 1 8 V maximum sample rate Irs 20 mA 1x mode 25 O 1 balanced load unless otherwise noted Table 3 AD9736 AD9735 AD9734 Parameter Min
81. ows most of the internal process temperature and voltage delay variation to be cancelled The AD973x further simplifies this high speed data capture problem with two adaptive closed loop timing controllers One timing controller manages the LVDS data and data clock alignment LVDS controller and the other manages the LVDS data and DACCLK alignment sync controller The LVDS controller locates the data transitions and delays the DATACLK IN so that its transition is in the center of the valid data window The sync controller manages the FIFO that moves data from the LVDS DATACLK IN domain to the DACCLK domain Both controllers can operate in manual mode under external processor control in surveillance mode where error conditions generate external interrupts or in automatic mode where errors are automatically corrected The LVDS and sync controllers include moving average filtering for noise immunity and variable thresholds to control activity Normally the controllers are set to run in automatic mode making any necessary adjustments without dropping or dupli cating samples sent to the DAC Both controllers require initial calibration prior to entering automatic update mode The AD973x analog output changes 35 DACCLK cycles after the input data changes in 1x mode with the FIFO disabled The FIFO adds up to eight additional cycles of delay This delay is read from the SPI port Internal clock delay variation is less than a single DAC
82. perating speed The ability of the receiver to recover the data depends on the input signal overdrive With a 250 mV input there is a 150 mV overdrive and with a 400 mV signal there is 300 mV overdrive The relationship between overdrive level and timing is very nonlinear Higher levels of overdrive result in smaller minimum valid data windows For typical silicon decreasing the LVDS swing from 400 mV p p to 250 mV p p requires the minimum data valid period to increase by 1596 This is illustrated in Figure 100 225ps 260ps 1 1 Figure 100 Typical Minimum Valid Data Time twp vs LVDS Swing a 3 lt 04862 098 minimum valid data window changes with temperature voltage and process The maximum value presented in the specification table was determined from a 66 distribution in the worst case conditions Rev A Page 54 of 72 AD9734 AD9735 AD9736 SYNCHRONIZATION TIMING When more than one AD973x must be synchronized or when a constant group delay must be maintained the internal controllers cannot be used If the FIFO is enabled the delay between multiple AD973x devices is unknown If the DATACLK OUT from multiple devices is used there is an uncertainty of two DACCLK periods because the initial phase of DATACLK OUT with respect to DACCLK cannot be controlled This means one DAC must be used to provide DATACLK OUT for all synchronized DACs and all timing must be externally managed
83. r a range of 8 66 mA to 31 66 mA The AD973x family is manufactured on a 0 18 um CMOS process and operates from 1 8 V and 3 3 V supplies for a total power consumption of 380 mW in bypass mode It is supplied in a 160 lead chip scale ball grid array for reduced package parasitics Rev Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result fromits use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM RESET IRQ DACCLK DACCLK SDIO SDO CSB SCLK DATACLK_OUT DATACLK OUT m DATACLK IN Q gt M IOUTA DATACLK_IN gt 5 q H gt IOUTB DB 13 0 9 5 DB 13 0 x 2 pcc i O s VREF 1120 Figure 1 PRODUCT HIGHLIGHTS 1 Low noise and intermodulation distortion IMD features enable high quality synthesis of wideband signals at inter mediate frequencies up to 600 MHz 2 Double data rate DDR LVDS data receivers support the maximum conversion rate of 1200 MSPS 3 Direct pin programmahbility of basic functions or SPI port access offers complete control of all AD973x family functions 4 Manufactured on a CMOS process the A
84. rnal LVDS Data Sampling Logic Timing LVDS SAMPLE LOGIC CALIBRATION The internal DSS delay must be calibrated to optimize the data sample timing Once calibrated the AD973x generates an IRQ or automatically corrects its timing if temperature or voltage variations change the timing too much This calibration is done using the delayed clock sampling signal CSS to sample the delayed clock signal DCS The LVDS sampling logic finds the edges of the DATACLK IN signal and from this measurement the center of the valid data window is located The internal delay line that derives the delayed DSS from DATACLK IN is controlled by SD3 0 Reg 5 Bits 7 4 while the DCS is controlled by MSD3 0 Reg 4 Bits 7 4 and the CSS is controlled by MHD3 0 Reg 4 Bits 3 0 DATACLK IN transitions must be time aligned with the LVDS data DB 13 0 transitions This allows the CSS derived from the DATACLK to find the valid data window of DB lt 13 0 gt by locating the DATACLK IN edges The latching rising edge of CSS is initially placed using Bits SD lt 3 0 gt and can then be shifted to the left using MSD lt 3 0 gt and to the right using MHD lt 3 0 gt When CSS samples the DCS and the result is 1 which can be read back via the check bit at Reg 5 Bit 0 the sampling occurs in the correct data cycle Rev A Page 40 of 72 AD9734 AD9735 AD9736 To find the leading edge of the data cycle increment the measured setup delay until the c
85. s sss 46 Cross Controller Registers 47 Analog Control Registers seen 48 Band Gap Temperature Characteristic Trim Bits 48 REVISION HISTORY 9 06 Rev 0 to Rev A Updated Format street Changes to Table 1 Changes to Table 2 Changes to Table 3 Inserted Table 5 eite ap Replaced Pin Configuration and Function Descriptions za Changes to Figure 27 to Figure 38 Changes to Figure 40 euet ee Rire ee des 9 ed rt Changes to Figure 103 22 222111 Changes to Figure 105 seen Changes to Figure 107 cere ee n IRE d Changes to Figure 108 2 2 2 2 2 0 2 0 Changes to Fig re 115 Updated Outline Dimensions see Changes to Ordering Guide sse 4 05 Revision 0 Initial Version Mirror Roll Off Frequency 48 Headroom Biis ceo etie 48 Voltage Reference ise pete epe etd 48 Applications Information 50 Driving the DACCLK 50 DAC Output Distortion Sources sse 51 DC Coupled DAC Output sees 52 DAC Dat SOUIC S tt rtt fetten tnter 53 Input Data Timing eniti siisii 54 Synchronization Timing
86. scale output current LVDS CONTROLLER LVDS CNT REGISTERS REG 4 REG 5 REG 6 ADDR Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 0x04 LVDS MSD 3 MSD lt 2 gt MSD lt 1 gt MSD 0 MHD lt 3 gt MHD lt 2 gt MHD lt 1 gt MHD 0 0x05 LVDS_CNT2 SD lt 3 gt SD lt 2 gt SD lt 1 gt SD lt 0 gt LCHANGE ERR_HI ERR_LO CHECK 0x06 LVDS CNT3 LSURV LAUTO LFLT lt 3 gt LFLT lt 2 gt LFLT lt 1 gt LFLT lt 0 gt LTRH lt 1 gt LTRH 0 Table 13 LVDS Controller Register Bit Descriptions Bit Name Read Write Description MSD lt 3 0 gt WRITE 0x0 set setup delay for the measurement system READ If LAUTO 1 the latest measured value for the setup delay If LAUTO 0 readback of the last SPI write to this bit MHD lt 3 0 gt WRITE 0 0 set hold delay for the measurement system READ If LAUTO 1 the latest measured value for the hold delay If LAUTO 0 readback of the last SPI write to this bit SD lt 3 0 gt WRITE 0x0 set sample delay READ If LAUTO 1 the result of a measurement cycle is stored in this register If LAUTO 0 readback of the last SPI write to this bit LCHANGE READ 0 no change from previous measurement 1 change in value from the previous measurement NOTE The average filter and the threshold detection are not applied to this bit ERR HI READ One of the 15 LVDS inputs is above the input voltage limits of the IEEE reduced link specific
87. t the DAC output may not be stable This means the FIFO cannot be enabled in PIN MODE unless the DACCLK is less than 160 MHz Rev A Page 39 of 72 AD9734 AD9735 AD9736 The LVDS and sync controllers are independently operated in three modes via SPI port Reg 6 and Reg 8 e Manual mode e Surveillance mode e Auto mode In manual mode all of the timing measurements and updates are externally controlled via the SPI In surveillance mode each controller takes measurements and calculates a new optimal value continuously The result of the measurement is passed through an averaging filter before evaluating the results for increased noise immunity The filtered result is compared to a threshold value set via Reg 6 and Reg 8 of the SPI port If the error is greater than the threshold an interrupt is triggered and the controller stops Reg 1 of the SPI port controls the interrupts with Bit 3 and Bit 2 enabling the respective interrupts and Bit 7 and Bit 6 indicating the respective controller interrupt If an interrupt is enabled it also activates the AD973x IRQ pin To clear an interrupt the interrupt enable bit of the respective controller must be set to 0 for at least 1 controller clock cycle controller clock 10 MHz Auto mode is almost identical to surveillance mode Instead of triggering an interrupt and stopping the controller the controller automatically updates its settings to the newly calculated optimal value and
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89. ted CROSS CONTROLLER CROS CNT REGISTERS REG 10 REG 11 ADDR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CROS UPDEL lt 5 gt UPDEL lt 4 gt UPDEL lt 3 gt UPDEL lt 2 gt UPDEL lt 1 gt UPDEL lt 0 gt 0x0B CROS_CNT2 DNDEL lt 5 gt DNDEL lt 4 gt DNDEL lt 3 gt DNDEL lt 2 gt DNDEL lt 1 gt DNDEL 0 Table 15 Cross Controller Register Description Bit Name Read Write Description UPDEL lt 5 0 gt WRITE 0x00 move the differential output stage switching point up set to 0 if DNDEL is non zero DNDEL lt 5 0 gt WRITE 0x00 move the differential output stage switching point down set to 0 if UPDEL is non zero Rev A Page 32 of 72 AD9734 AD9735 AD9736 ANALOG CONTROL ANA CNT REGISTERS REG 14 REG 15 ADDR Name Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 OxOE ANA 1 MSEL 1 MSEL lt 0 gt TRMBG 2 TRMBG 1 TRMBG 0 OxOF ANA CNT2 HDRM 7 HDRM 6 HDRM 5 HDRM 4 HDRM 3 HDRM 2 HDRM 1 HDRM 0 Table 16 Analog Control Register Bit Descriptions Bit Name Read Write Description MSEL lt 1 0 gt WRITE 00 mirror roll off frequency control bypass 01 mirror roll off frequency control narrowest bandwidth 10 mirror roll off frequency control medium bandwidth 11 mirror roll off frequency control w
90. the expected signatures shown in Table 25 18 Flush the BIST circuitry This must be done once before valid data can be read Loop back to Step 11 and rerun the test to obtain the correct result Each time BIST mode is entered this flush needs to be performed once Multiple BIST runs can be performed without reflushing as long as the device remains in BIST mode AD973x EXPECTED BIST SIGNATURES The BIST vectors provided on the AD973x EB CD are in signed mode so no programming is necessary for the part to pass the BIST The BIST vector is for 1x no FIFO and signed data For testing all 14 input bits use the vector all bits unsnew txt and verify against the signatures in Table 25 Table 25 Expected BIST Data Readback for All Bits LVDSPhase1 LVDSPhase2 SYNCPhase1 SYNC Phase 2 CF71487C 66DF5250 CF71487C 66DF5250 For individual bit tests use the vectors named bitn txt where n is the desired bit number being tested and compare them against the values in Table 26 Table 26 Expected BIST Data Readback for Individual Bits Bit LVDS Rise LVDS Fall Vector Number Expected Expected bitO txt 0 2 400500 bit1 txt 1 2 00 6 400500 bit2 txt 2 29 0 00 9400500 bit3 txt 3 2DBCOA00 ED410500 bit4 txt 4 25B80A00 E5430500 bit5 txt 5 35B00A00 F5470500 bit6 txt 6 15A00A00 D54F0500 bit7 txt 7 55800A00 955 0500 bit8 txt 8 D5C00A00 157F0500 bit9 txt 9 D5410A00 153E0500 bit
91. um compliance limits can cause either output stage saturation or breakdown resulting in nonlinear performance Temperature Drift Specified as the maximum change from the ambient 25 C value to the value at either Tum or Tmax For offset and gain drift the drift is reported in ppm of full scale range FSR per C For reference drift the drift is reported in ppm per C Power Supply Rejection The maximum change in the full scale output as the supplies are varied from nominal to minimum and maximum specified voltages Settling Time The time required for the output to reach and remain within a specified error band about its final value measured from the start of the output transition Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse It is specified as the net area of the glitch in pV s Spurious Free Dynamic Range The difference in dB between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth Total Harmonic Distortion THD The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal It is expressed as a percentage or in decibels dB Multitone Power Ratio The spurious free dynamic range containing multiple carrier tones of equal amplitude It is measured as the difference between the rms amplitude ofa carrier tone to the peak spurious sign
92. ur 1 2 GSPS 145 147 149 151 153 v 5 8 155 a S Q 157 z 159 161 163 165 0 50 100 150 200 250 300 350 400 450 500 550 600 2 0 50 100 150 200 250 300 350 400 450 500 550 600 5 four MHz 3 four MHz E Figure 61 AD9735 IMD vs four over 1 2 GSPS Figure 64 AD9734 NSD vs four 1 2 GSPS Rev A Page 27 of 72 AD9734 AD9735 AD9736 AD973x WCDMA ACLR 20 mA FULL SCALE REF 22 754 AVG LOG 10dB ATTEN 6dB 04862 057 PAVG VBW 300kHz SPAN 33 88MHz 10 SWEEP 109 9ms 601pts wi 52 CENTER 134 83MHz RES BW 30kHz LOWER UPPER RMS RESULTS OFFSET FREQ REF BW dBc dBm dBc dBm CARRIER POWER 5 00MHz 3 840MHz 81 65 92 37 81 39 92 11 10 72dBm 10 0MHz 3 840MHz 82 06 92 78 82 43 93 16 3 84000 2 15 0MHz 3 884MHz 82 11 92 83 82 39 93 11 Figure 65 AD9736 WCDMA Carrier at 134 83 MHz foac 491 52 MSPS REF 22 75dBm AVG LOG 10dB ATTEN 6dB PAVG VBW 300kHz SPAN 33 88MHz 10 52 SWEEP 109 9ms 601pts CENTER 134 83MHz RES BW 30kHz LOWER UPPER RMS RESULTS OFFSET FREQ REF BW dBc dBm dBc dBm CARRIER POWER 5 00 2 3 840MHz 80 32 91 0 80 60 91 38 10 72dBm 10 0MHz 3 840MHz 81 13 91 91 80 75 91 53 3 84000MHz 15 0MHz 3 884MHz 80 43 9121 81 36 92 13 Figure 66 AD9735 WCDMA Carrier at 134 83 MHz
93. urement in still air LP ESD SENSITIVE DEVICE Note that this device in its current form does not meet Analog Devices standard requirements for ESD as measured against the charged device model CDM As such special care should be used when handling this product especially in a manufacturing environment Analog Devices will provide a more ESD hardy product in the near future at which time this warning will be removed from this data sheet Rev A Page 9 of 72 AD9734 AD9735 AD9736 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 123 4 5 6 7 8 9 10 11 12 13 14 A B DACCLK E OOO DACCLK F OOO c H OOOO J OOOO K L OOOO pBo LsB M 8888 P DATACLK_OUT OOOOOOOOOOOOOO OOOOOOOOOOOOOO DB13 MSB DB12 DB11 DATACLK IN DB6 DB7 DB8 DB9 DB10 04862 005 Figure 2 AD9736 Digital LVDS Input Clock I O Top View Table 6 AD9736 Pin Function Descriptions Pin No Mnemonic Description A1 A2 A3 B1 B2 B3 C1 C2 C3 D2 D3 CVDD18 1 8V Clock Supply A4 A5 A6 A9 A10 A11 B4 B5 B6 B9 AVSS Analog Supply Ground B10 B11 C4 C5 C6 C9 C10 C11 D4 D5 D6 D9 D10 D11 A7 B7 C7 D7 IOUTB DAC Negative Output 10 mA to 30 mA full scale output current A8 B8 C8 D8 IOUTA DAC Positive Output 10 mA to 30 mA full scale output current A12 A13 B12 B13 C12 C13 D12 D13 A
94. verage Value A Average 2 LFLT lt 3 0 gt If an accumulating error in the average value causes it to exceed the threshold value LTHR lt 1 0 gt an interrupt is issued The maximum allowable value for LFLT lt 3 0 gt is 12 If LFLT lt 3 0 gt is too small clock jitter and noise can cause erratic behavior In most cases LFLT can be set to the maximum value In surveillance mode the ideal sampling point should first be found using manual mode and then applied to the sample delay registers Set the threshold and filter values depending on how far the CSS signal is allowed to drift before an interrupt occurs Then set the surveillance bit high Reg 6 Bit 7 and monitor the interrupt signal either via the SPI port Reg 1 Bit 7 or the IRQ pin In auto mode follow the same steps to set up the sample delay threshold and filter length To run the controller in auto mode both the LAUTO Reg 6 Bit 6 and LSURV Reg 6 Bit 7 bits need to be set to 1 In auto mode the LVDS interrupt should be set low Reg 1 Bit 3 to allow the sample delay to be automati cally updated if the threshold value is exceeded Rev A Page 41 of 72 AD9734 AD9735 AD9736 SYNC LOGIC AND CONTROLLER A FIFO structure is utilized to synchronize the data transfer between the DACCLK and the DATACLK clock domains The sync controller writes data from DB lt 13 0 gt into an 8 word memory register based on a cyclic write counter clocked by the DS
95. y apply to setting the software reset RESET Reg 0 Bit 5 All low during the entire communication cycle registers are set to their default values except Reg 0 and Reg 4 which remain unchanged SDIO Serial Data I O Data is always written into the AD973x on this pin However Use of only single byte transfers when changing serial port configurations or initiating a software reset is highly recommended In the event of unexpected programming sequences the AD973x SPI can become inaccessible For example if user code inadvertently changes the LONG INS bit this pin can be used as a bidirectional data line The configu ration of this pin is controlled by SDIO DIR at Reg 0 Bit 7 The default is Logic 0 which configures the SDIO pin as unidirectional or the LSBFIRST bit the following bits experience unexpected SDO Serial Data Out results The SPI can be returned to a known state by writing an Data is read from this pin for protocols that use separate lines incomplete byte 1 to 7 bits of all 0s followed by 3 bytes of for transmitting and receiving data In the case where the 0x00 This returns to MSB first short instructions AD973x operates in a single bidirectional I O mode this pin Reg 0 0x00 so the device can be reinitialized does not output data and is set to a high impedance state INSTRUCTION CYCLE DATA TRANSFER CYCLE MSB LSB TRANSFERS s The AD973x serial port can support both MSB first or LSB first
96. yte communication cycle SOEK E AD973x serial port controller data address decrements SDIO so fas aa wt from the data address written toward 0x00 for multibyte Figure 71 Serial Register Interface Timing LSB First Write operations if the MSB first mode is active The serial port controller address increments from the data address written INSTRUCTION CYCLE DATA TRANSFER CYCLE i toward Ox1F for multibyte I O operations if the LSB first mode is active NOTES ON SERIAL PORT OPERATION The AD973x serial port configuration is controlled by Reg 0 SDIO so Jat nz as hne re n TERRE 00 Bit 4 5 Bit 6 and Bit 7 Note that th figuration ch p Pi i 5 Bit 6 an Bi ote that the configuration changes a paps pan immediately upon writing to the last bit of the register 04862 069 04862 070 Figure 72 Serial Register Interface Timing LSB First Read Rev A Page 37 of 72 AD9734 AD9735 AD9736 tps lt 1 1 i gt 1 1 1 1 1 CSB I 1 e tpw e I 1 em SCLK t I Ia P 4 toH 04862 071 SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 73 Timing Diagram for SPI Register Write CSB SCLK ec X X Figure 74 Timing Diagram for SPI Register Read 04862 072 After the last instruction bit is written to the SDIO pin the

ANALOG DEVICES AD9734 English products handbook

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