Home

ANALOG DEVICES AD5378 English products handbook Rev A

1. Figure 1 Protected by U S Patent No 5 969 657 and 6 823 416 other patents pending Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Vgias Vngri Vggri REFGND A1 05292 001 REFGND A2 Vrer2 Vrer2 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A www analog com Fax 781 461 3113 2005 2009 Analog Devices Inc All rights reserved Tel 781 329 4700 AD5378 TABLE OF CONTENTS Features cc er uec None OSS 1 Applications viret e SHIP REDIERE 1 Functional Block Diagram sse 1 REVISION HistoEy eee eR BUR RUUERBURUBRIIRUIENO 2 General DescriptloIE oett te bt e e 3 Specifications usce e Der OR MPH Rec iier Rede 4 AG Characteristics te t RR RE 5 Timing Characteristics eset ieaiai 6 Serial Interface secet ER dia 6 Parallel Interfaces 5a pede PEE 9 Absolute Maximum Ratings seen 11 ESD Ca tion eee ene Heel ert 11 Pin Configuration and Function Descriptions 12 Typical Performance Character
2. inputs The maximum output voltage span is 17 5 V corresponding to a bipolar output range of 8 75 V to 8 75 V and is achieved with reference volt ages of Vrer 3 5 V and Vrer 5 V The AD5378 guarantees operation over a wide Vss Vpp supply range from 11 4 V to 16 5 V The output amplifier headroom requirement is 2 5 V operating with a load current of 1 5 mA and 2 V operating with a load current of 0 5 mA The AD5378 contains a double buffered parallel interface in which 14 data bits are loaded into one of the input registers under the control of the WR CS and DAC channel address pins A0 to A7 It also has a 3 wire serial interface which is compatible with SPI OSPI MICROWIRE and DSP inter face standards and can handle clock speeds of up to 50 MHz Table 1 40 Channel Bipolar Voltage Output DAC AD5378 The DAC outputs are updated when the DAC registers receive new data All the outputs can be updated simultaneously by taking the LDAC input low Each channel has a programmable gain and an offset adjust register Each DAC output is gained and buffered on chip with respect to an external REFGND input The DAC outputs can also be switched to REFGND via the CLR pin Table 1 and Table 2 show the product portfolio for high channel count bipolar and unipolar voltage output DACs Output Package Model Resolution Analog Supplies Channels Linearity Error LSB Description Package Option AD5379ABC
3. Vss X Isink Junction Temperature 130 C max Ty Ta Proma x 0 Temperature range for the A version 40 C to 85 C Typical specifications are at 25 C Guaranteed by design and characterization not production tested 3 Where 0 represents the package thermal impedance AC CHARACTERISTICS Voc 2 7 V to 5 5 V Voo 11 4 V to 16 5 V Vss 11 4 V to 16 5 V Vre 5 V Vre 3 5 V AGND DGND REFGND 0 V Vsus 5 V Ci 220 pF Ri 11 kQ to 3 V gain 1 offset 0 V Table 4 Parameter A Version Unit Test Conditions Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 20 us typ Full scale change to 1 2 LSB 30 us max DAC latch contents alternately loaded with all 0s and all 1s Slew Rate 1 V us typ Digital to Analog Glitch Energy 20 nV s typ Glitch Impulse Peak Amplitude 15 mV max Channel to Channel Isolation 100 dB typ Vner 4 2V p p 1 Vaus 1 kHz Vaer 1 V DAC to DAC Crosstalk 40 nV s typ See the Terminology section between DACs inside a group 10 nV s typ Between DACs from different groups Digital Crosstalk 0 1 nV s typ Digital Feedthrough 1 nV s typ Effect of input bus activity on DAC output under test Output Noise Spectral Density 1 kHz 350 nV Hz typ Vrer Vrer OV Guaranteed by design and characterization not production tested Rev A Page 5 of 28 AD5378 TIMING CHARACTERISTICS SERIAL INTERFACE Vcc 2 7 V to 5 5 V Voo
4. 0 3 V AGND to DGND 0 3 V to 0 3 V Operating Temperature Range Ta Industrial A Version 40 C to 85 C Storage Temperature Range 65 C to 150 C Junction Temperature T max 150 C 108 Lead CSPBGA Package Osa Thermal Impedance 37 5 C W Osc Thermal Impedance 8 5 C W Reflow Soldering Peak Temperature 230 C Time at Peak Temperature 10 sec to 40 sec ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features WARNING S proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Sprit Ate electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance ERU SENSEVE DEVICE degradation or loss of functionality Rev A Page 11 of 28 AD5378 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 12 3 4 5 8 9 10 11 12 QOQ0000Q000 QOOOOOOOOOOO s 000000000000 c pe OOO QQQ n F gg AD5378 QOQ r G OOO TOP VIEW QOQ G QOO O 008009009000 QOQQO 00000000000 1 234 5 9 10 11 12 05292 007 Figure 7 Pin tee Table 8 108 Lead CSPBGA Ball Configuration CSPBGA No Ball Name CSPBGA No Ball Name CSPBGA No Ball Name CSPBGA No Ball Name Al REGO C4 SER PAR G1 DB1 K10 VOUT14 A2 Vcc3 C5 LDAC G2 DBO K11 VOUT18 A3 DB10 C6 VOUT6 G3 BUSY K12 VOUT19 A4 AGND4 C7 V
5. 11 4 V to 16 5 V Vss 11 4 V to 16 5 V Vre 5 V Vrer 3 5 V AGND DGND REFGND 0 V Vans 5 V FIFOEN 0 V all specifications Tw to Tmax unless otherwise noted Table 5 Parameter gt Limit at Tin Tmax Unit Description t 20 ns min SCLK Cycle Time t 8 ns min SCLK High Time ts 8 ns min SCLK Low Time ta 10 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time t 15 ns min 24th SCLK Falling Edge to SYNC Falling Edge te 25 ns min Minimum SYNC Low Time t 10 ns min Minimum SYNC High Time ts 5 ns min Data Setup Time to 4 5 ns min Data Hold Time tio 30 ns max 24th SCLK Falling Edge to BUSY Falling Edge tu 330 ns max BUSY Pulse Width Low Single Channel Update See Table 11 ti 20 ns min 24th SCLK Falling Edge to LDAC Falling Edge tis 20 ns min LDAC Pulse Width Low tia 150 ns typ BUSY Rising Edge to DAC Output Response Time tis 0 ns min BUSY Rising Edge to LDAC Falling Edge tis 100 ns min LDAC Falling Edge to DAC Output Response Time t 20 30 us typ max DAC Output Settling Time tis 10 ns min CLR Pulse Width Low tis 350 ns max CLR RESET Pulse Activation Time t207 25 ns max SCLK Rising Edge to SDO Valid tai 5 ns min SCLK Falling Edge to SYNC Rising Edge toa 5 ns min SYNC Rising Edge to SCLK Rising Edge tos 20 ns min SYNC Rising Edge to LDAC Falling Edge toa 30 ns min SYNC Rising Edge to BUSY Falling Edge tos 10 ns min RESET Pulse Width Low toe 120 us ma
6. When the FIFO is full additional writes to the AD5378 are ignored BUSY INPUT FUNCTION Because the BUSY pin is bidirectional and open drain for correct operation use a pull up resistor to digital supply a second AD5378 or any other device such as a system control ler can pull BUSY low and therefore delay DAC update s if required This is a means of delaying any LDAC action This feature allows synchronous updates of multiple AD5378 devices in a system at maximum speed As soon as the last device connected to the BUSY pin is ready all DACs update automati cally Tying the BUSY pin of multiple devices together enables synchronous updating of all DACs without extra hardware POWER ON RESET FUNCTION The AD5378 contains a power on reset generator and state machine During power on CLR becomes active internally the power on state machine resets all internal registers to their default values and BUSY goes low This sequence takes 8 ms typical The outputs VOUTO to VOUT31 are switched to the AD5378 externally set potential on the REFGND pin During power on the parallel interface is disabled so it is not possible to write to the part Any transitions on LDAC during the power on period are ignored in order to reject initial LDAC pin glitching A rising edge on BUSY indicates that power on is complete and that the parallel interface is enabled All DACs remain in their power on state until
7. 1 or decre mented DB8 0 The maximum amount by which the user is allowed to increment or decrement the data is 127 LSBs that is DB6 DBO 1111111 The 0 LSB step is included to facilitate software loops in the user s application See Table 16 The AD5378 has digital overflow and underflow detection circuitry to clamp at full scale or zero scale when the values chosen for increment or decrement mode are out of range Rev A Page 21 of 28 AD5378 INTERFACES The AD5378 contains parallel and serial interfaces The active interface is selected via the SER PAR pin The AD5378 uses an internal FIFO memory to allow high speed successive writes in both serial and parallel modes The user can continue writing new data to the AD5378 while write instructions are being executed The BUSY signal goes low while instructions in the FIFO are being executed Up to 120 successive instructions can be written to the FIFO at maximum speed When the FIFO is full additional writes to the AD5378 are ignored To minimize both the power consumption of the device and on chip digital noise the active interface powers up fully only when the device is being written to that is on the falling edge of WR or on the falling edge of SYNC All digital interfaces are 2 5 V LVTTL compatible when operating from a 2 7 V to 3 6 V Vcc supply PARALLEL INTERFACE A pull down on the SER PAR pin makes the parallel interface the default If using
8. 1 MO ensures that the RESET input is held high The function of this pin is equivalent to that of the power on reset generator When this pin is taken low the AD5378 state machine initiates a reset sequence to digitally reset the x1 m c and X2 registers to their default power on values This sequence takes 100 us typ Furthermore the input to each of the DAC output buffer stages VOUTO to VOUT31 is switched to the externally set potential on the relevant REFGND pin During RESET BUSY goes low and the parallel interface is disabled All LDAC pulses are ignored until BUSY goes high When RESET goes high again the DAC ouputs remain at REFGND until LDAC is taken low REFGNDA1 Reference Ground for DACs 0 to 5 VOUTO to VOUTS are referenced to this voltage REFGNDA2 Reference Ground for DACs 6 and 7 VOUT6 and VOUT7 are referenced to this voltage REFGNDB1 Reference Ground for DACs 8 to 13 VOUT8 to VOUT13 are referenced to this voltage REFGNDB2 Reference Ground for DACs 14 and 15 VOUT14 and VOUT15 are referenced to this voltage REFGNDC1 Reference Ground for DACs 16 to 21 VOUT16 to VOUT21 are referenced to this voltage REFGNDC2 Reference Ground for DACs 22 and 23 VOUT22 and VOUT23 are referenced to this voltage REFGNDD1 Reference Ground for DACs 24 to 29 VOUT24 to VOUT29 are referenced to this voltage REFGNDD2 Reference Ground for DACs 30 and 31 VOUT30 and VOUT31 are referenced to this voltage These serial interface signals
9. 14 Bits 11 4V to 16 5 V 40 3 108 Lead CSPBGA BC 108 Table 2 High Channel Count Low Voltage Single Supply DACs Output Package Model Resolution AVop Range Channels Linearity Error LSB Description Package Option AD5380BST 5 14 Bits 45Vto5 5V 40 4 100 Lead LOFP ST 100 AD5380BST 3 14 Bits 2 Vto3 6V 40 4 100 Lead LOFP ST 100 AD5381BST 5 12 Bits 45Vto5 5V 40 1 100 Lead LQFP ST 100 AD5381BST 3 12 Bits 2 7 V to 3 6 V 40 1 100 Lead LOFP ST 100 AD5384BBC 5 14 Bits 45Vto5 5V 40 4 100 Lead CSPBGA BC 100 AD5384BBC 3 14 Bits 2 7 V to 3 6 V 40 4 100 Lead CSPBGA BC 100 AD5382BST 5 14 Bits 45Vto5 5V 32 4 100 Lead LOFP ST 100 AD5382BST 3 14 Bits 2 7 V to 3 6 V 32 4 100 Lead LQFP ST 100 AD5383BST 5 12 Bits 45Vto5 5V 32 1 100 Lead LQFP ST 100 AD5383BST 3 12 Bits 2 7 V to 3 6 V 32 1 100 Lead LOFP ST 100 AD5390BST 5 14 Bits 45Vto5 5V 16 3 52 Lead LOFP ST 52 AD5390BCP 5 14 Bits 45Vto5 5V 16 3 64 Lead LFCSP CP 64 AD5390BST 3 14 Bits 2 Vto3 6V 16 4 52 Lead LOFP ST 52 AD5390BCP 3 14 Bits 2 7 V to 3 6 V 16 4 64 Lead LFCSP CP 64 AD5391BST 5 12 Bits 4 5 V to 5 5 V 16 1 52 Lead LQFP ST 52 AD5391BCP 5 12 Bits 4 5 V to 5 5 V 16 1 64 Lead LFCSP CP 64 AD5391BST 3 12 Bits 2 7 V to 3 6 V 16 1 52 Lead LOFP ST 52 AD5391BCP 3 12 Bits 2 7 V to 3 6 V 16 1 64 Lead LFCSP CP 64 AD5392BST 5 14 Bits 45Vto5 5V 8 3 52 Lead LQFP ST 52 AD5392BCP 5 14 Bits 45Vto5 5V 8 3 64 Lead LFCSP CP 64 AD5392BST 3 14 Bits 2 7 V to 3 6 V 8 4 52 Lead LQ
10. 2 where x2is the data word loaded to the resistor string DAC The default is 10 0000 0000 0000 x1 is the 14 bit data word written to the DAC input register The default is 10 0000 0000 0000 m is the 13 bit gain coefficient The default is 1 1111 1111 1111 c is the 14 bit offset coefficient The default is 10 0000 0000 0000 n is the DAC resolution n 14 Figure 19 shows a single DAC channel and its associated registers The power on values for the m and c registers are full scale and 0x2000 respectively The user can individually adjust the voltage range on each DAC channel by overwriting the power on values of m and c The AD5378 has digital overflow and underflow detection circuitry to clamp the DAC output at full scale or at zero scale when the values chosen for x1 m and c result in x2 being out of range LDAC Vrer 05292 019 Figure 19 Single DAC Channel The complete transfer function for the AD5378 can be represented as VOUT 3 5 x Vrer AGND x x2 2 2 5 x Vrer AGND REFGND where x2 is the data word loaded to the resistor string DAC Vrer is the voltage at the positive reference pin Vrer is the voltage at the negative reference pin Figure 20 shows the output amplifier stage of a single channel VDAC is the voltage output from the resistor string DAC The nominal range of VDAC is 1 LSB to full scale 05292 020 Figure 20 Output Amplifier Stage Rev A Page 18 of
11. determines at which node on the string the voltage is tapped off before being fed into the output amplifier The output amplifier translates the output of the DAC to a wider range The DAC output is gained up by a factor of 3 5 and offset by the voltage on the Vrer pin See the Transfer Function section CHANNEL GROUPS The 32 DAC channels on the AD5378 are arranged into four groups A B C D of eight channels In each group six channels are connected to Vrerl and Vrerl the remaining two channels are connected to Vrer2 and Vrer2 Each group has two individual REFGND pins For example in Group A six channels are connected to REFGNDAL and the remaining two channels are connected to REFGNDA2 In addition to an input register x1 and a DAC register x2 each channel has a gain register m and an offset register c See Table 18 Including these registers allows the user to calibrate out errors in the complete signal chain including the DAC errors Table 10 shows the reference and REFGND inputs and the m and c registers for Group A Groups B C and D are similar Table 10 Inputs and Registers for Group A Channel Reference REFGND m c Registers 0 5 Veer 1 Veer 1 REFGNDA1 m REGO 5 c REGO 5 6 7 Varr 2 4 Vrer2 REFGNDA2 m REG6 7 c REG6 7 TRANSFER FUNCTION The digital input transfer function for each DAC can be represented as x2 m 1 28 x x1 c
12. 28 AD5378 Vers FUNCTION The AD5378 on chip voltage generator provides a bias voltage of 4 25 V min The Vsus pin is provided for bypassing and overdriving purposes only It is not intended to be used as a supply or a reference If Vrer gt 4 25 V Vsus must be pulled high externally to an equal or higher potential such as 5 V The external voltage source should be capable of driving a 50 uA typical current sink load REFERENCE SELECTION The voltages applied to Vrer and Vrer determine the output voltage range and span on VOUTO to VOUT31 If the offset and gain features are not used m and c are left at their power on values the reference levels required can be calculated as follows Vrer min VOUT max VOUT min 3 5 Vrer max AGND VOUT nin 2 5 If the offset and gain features of the AD5378 are used the output range required is slightly different The output range chosen should take into account the offset and gain errors that need to be trimmed out Therefore the output range should be larger than the actual required range The reference levels required can be calculated as follows 1 Identify the nominal output range on VOUT 2 Identify the maximum offset span and the maximum gain required on the full output signal range 3 Calculate the new maximum output range on VOUT including the maximum offset and gain errors expected 4 Choose the new VOUT max and VOUT min required keeping the n
13. 3 where DB13 is the MSB and DBO is the LSB Parallel Address Inputs A7 to A4 are decoded to select one group or multiple groups of registers input registers gain registers m or offset registers c for a data transfer This pin is used in conjunction with the REG1 and REGO pins to determine the destination register for the input data See the Parallel Interface section for details of the address decoding Parallel Interface Register Select Input This pin is used together with REG1 to select data registers gain registers Offset registers increment decrement mode or the soft reset function See Table 12 Parallel Interface Register Select Input This pin is used together with REGO to select data registers gain registers Offset registers increment decrement mode or the soft reset function See Table 12 Asynchronous Clear Input Level sensitive active low When CLR is low the input to each of the DAC output buffer stages VOUTO to VOUT31 is switched to the externally set potential on the relevant REFGND pin While CLR is low all LDAC pulses are ignored When CLR is taken high again the DAC outputs remain cleared until LDAC is taken low The contents of input registers and DAC Registers 0 to 31 are not affected by taking CLR low Digital Input Open Drain Output This pin must be pulled high with a pull up resistor for correct operation BUSY goes low during internal calculations of x2 During this time the user can continue writing new
14. ANALOG DEVICES FEATURES 32 channel DAC in 13 mm x 13 mm 108 lead CSPBGA Guaranteed monotonic to 14 bits Buffered voltage outputs Output voltage span of 3 5 V x Vrer Maximum output voltage span of 17 5 V System calibration function allowing user programmable offset and gain Pseudo differential outputs relative to REFGND Clear function to user defined REFGND CLR pin Simultaneous update of DAC outputs LDAC pin DAC increment decrement mode Channel grouping and addressing features 32 Channel 14 Bit Parallel and Serial Input Bipolar Voltage Output DAC AD5378 Interface options Parallel interface DSP microcontroller compatible 3 wire serial interface 2 5 V to 5 5 V JEDEC compliant digital levels SDO daisy chaining option Power on reset Digital reset RESET pin and soft reset function APPLICATIONS Level setting in automatic test equipment ATE Variable optical attenuators VOAs Optical switches Industrial control systems FUNCTIONAL BLOCK DIAGRAM AGND DGND Voo Vss POWER ON RESET LDAC RESET jp DCEN WR Q j vicies O Mres HOO REGO o 0 1 REG1 m REGO 1 ee aN c REG0 1 SINDEN wi j 44 INPUTIi4 14 a THR eC is AQ Lm REG b E E ha BI AO a 1 E ipid iu e 14 prd 14 O O 14 serk O Ken ME FIFOEN e i REFGND B1 REFGND B2 REFGND C1 REFGND C2 REFGND D1 REFGND D2 Q BUSY
15. CHARACTERISTICS Output Voltage Range Vss 2 Vss 2 5 V min lioap 0 5 mA t1 5 mA Voo 2 Vpp 2 5 V max loan 30 5 MA 1 5 mA Short Circuit Current 15 mA max Load Current 15 mA max Capacitive Load 2200 pF max DC Output Impedance 1 Q max DIGITAL INPUTS JEDEC compliant Input High Voltage 1 7 V min Vcc 2 7 V to 3 6 V 2 0 V min Vcc 3 6 V to 5 5 V Input Low Voltage 0 8 V max Vcc 2 7 V to 5 5 V Input Current with pull up pull down 8 uA max SER PAR FIFOEN and RESET pins only Input Current no pull up pull down 1 uA max All other digital input pins Input Capacitance 10 pF max DIGITAL OUTPUTS BUSY SDO Output Low Voltage 0 5 V max Sinking 200 uA Output High Voltage SDO Vcc 0 5 V min Sourcing 200 pA High Impedance Leakage Current 70 uA max SDO only High Impedance Output Capacitance 10 pF typ Rev A Page 4 of 28 AD5378 Parameter A Version Unit Test Conditions Comments POWER REQUIREMENTS Vcc 2 7 5 5 V min max Voo 8 5 16 5 V min max Vss 3 16 5 V min max Power Supply Sensitivity A Full Scale A Vop 75 dB typ A Full Scale A Vss 75 dB typ A Full Scale A Vcc 90 dB typ lec 5 mA max Vcc 5 5 V Vin Vcc Vii GND Ipp 28 mA max Outputs unloaded typically 20 mA Iss 23 mA max Outputs unloaded typically 15 mA Power Dissipation Power Dissipation Unloaded P 850 mW max Vpp 16 5 V Vss 16 5 V Power Dissipation Loaded Prorat 2000 mW max Prorat P X Vpp Vo X Isource Vo
16. DING The AD5378 contains an 8 bit address bus A7 to AO This address bus allows each DAC input register x1 each offset c register and each gain m register to be individually updated Table 18 DAC Group Addressing AD5378 The REGI and REGO bits in the special function register SFR see Table 10 show the decoding for data offset and gain registers When all 32 DAC channels are selected Address Bits A 3 0 are ignored A7 A6 A5 A4 Group A3 A2 A1 AO Data Offset Gain INC DEC Register 0 0 0 0 All 32 DACs 0 0 0 0 Register 0 0 0 0 1 Group A 0 0 0 1 Register 1 0 0 1 0 Group B 0 0 1 0 Register 2 0 0 1 1 Groups A B 0 0 1 1 Register 3 0 1 0 0 Group C 0 1 0 0 Register 4 0 1 0 1 Groups A C 0 1 0 1 Register 5 0 1 1 0 Groups B C 1 0 0 0 Register 6 0 1 1 1 Groups A B C 1 0 0 1 Register 7 1 0 0 0 Group D 1 0 0 1 Groups A D 1 0 1 0 Groups B D 1 0 1 1 Groups A B D 1 1 0 0 Groups C D 1 1 0 1 Groups A C D 1 1 1 0 Groups B C D 1 1 1 1 Groups A B C D Rev A Page 25 of 28 AD5378 POWER SUPPLY DECOUPLING In any circuit where accuracy is important careful considera tion of the power supply and ground return layout helps to ensure the rated performance The printed circuit board on which the AD5378 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board If the AD5378 is in a system where multi
17. FP ST 52 AD5392BCP 3 14 Bits 2 7 V to 3 6 V 8 4 64 Lead LFCSP CP 64 Rev A Page 3 of 28 AD5378 SPECIFICATIONS Vcc 2 7 V to 5 5 V Voo 11 4 V to 16 5 V Vss 11 4 V to 16 5 V Vrer 5 V Vrer 3 5 Vj AGND DGND REFGND 0 V Vsus 5 V Ci 200 pF to GND Ri 11 kQ to 3 V gain 1 offset 0 V all specifications Tw to Tmax unless otherwise noted Table 3 Parameter A Version Unit Test Conditions Comments ACCURACY Resolution 14 Bits Relative Accuracy 3 LSB max 40 C to 85 C 2 5 LSB max 0 C to 70 C Differential Nonlinearity 1 4 1 5 LSB max Guaranteed monotonic by design over temperature Zero Scale Error 12 mV max 40 C to 85 C 5 mV max 0 C to 70 C Full Scale Error 12 mV max 40 C to 85 C 8 mV max 0 C to 70 C Gain Error 8 mV max 40 C to 85 C 1 45 mV typ max 0 C to 70 C VOUT Temperature Coefficient 5 ppm FSR C typ Includes linearity offset and gain drift see Figure 11 DC Crosstalk 0 5 mV max Typically 100 pV REFERENCE INPUTS Veer DC Input Impedance 1 MQ min Typically 100 MO Veer DC Input Impedance 8 kQ min Typically 12 kQ Vrer Input Current 10 uA max Per input typically 30 nA Vrer Range 1 5 5 V min max 2 for specified operation Vrer Range 3 5 0 V min max 2 for specified operation REFGND INPUTS DC Input Impedance 80 kO min Typically 120 kO Input Range 0 5 V min max OUTPUT
18. LDAC is used to update the DAC outputs RESET INPUT FUNCTION The AD5378 can be placed into the power on reset state at any time by activating the RESET pin The AD5378 state machine initiates a reset sequence to digitally reset the x1 m c and x2 registers to their default power on values This sequence takes 95 us typical 120 us max and 70 us min During this sequence BUSY goes low While RESET is low any transitions on LDAC are ignored As with the CLR input while RESET is low the DAC outputs are switched to REFGND The outputs remain at REFGND until an LDAC pulse is applied This reset function can also be implemented via the parallel interface by setting the REGO and REGI pins low and writing all 1s to DB13 to DBO See Table 17 for soft reset INCREMENT DECREMENT FUNCTION The AD5378 has a special function register that enables the user to increment or decrement the internal 14 bit input register data x1 in steps of 0 to 127 LSBs The increment decrement function is selected by setting both REG1 and REGO pins or bits low Address Pins or bits A7 to AO are used to select a DAC channel or group of channels The amount by which the x1 register is incremented or decremented is determined by the DB6 to DBO bits pins For example for a 1 LSB increment or decrement DB6 DB0 0000001 while for a 7 LSB increment or decrement DB6 DB0 0000111 DB8 determines whether the input register data is incremented DB8
19. OEN 0 V all specifications Tum to Tmax unless otherwise noted AD5378 Table 6 Parameter gt Limit at Tmn to Tmax Unit Description to 4 5 ns min REGO REG1 Address to WR Rising Edge Setup Time t 4 5 ns min REGO REG1 Address to WR Rising Edge Hold Time t 10 ns min CS Pulse Width Low ts 10 ns min WR Pulse Width Low ta 0 ns min CS to WR Falling Edge Setup Time ts 0 ns min WR to CS Rising Edge Hold Time te 4 5 ns min Data to WR Rising Edge Setup Time t7 4 5 ns min Data to WR Rising Edge Hold Time ts 20 ns min WR Pulse Width High to 240 ns min Minimum WR Cycle Time Single Channel Write tio 0 30 ns min max WR Rising Edge to BUSY Falling Edge ti 330 ns max BUSY Pulse Width Low Single Channel Update See Table 11 tia 0 ns min BUSY Rising Edge to WR Rising Edge tis 30 ns min WR Rising Edge to LDAC Falling Edge tia 20 ns min LDAC Pulse Width Low ti 150 ns typ BUSY Rising Edge to DAC Output Response Time tie 20 ns min LDAC Rising Edge to WR Rising Edge t 0 ns min BUSY Rising Edge to LDAC Falling Edge tis 100 ns typ LDAC Falling Edge to DAC Output Response Time tio 20 30 us typ max DAC Output Settling Time to 10 ns min CLR Pulse Width Low tai 350 ns max CLR RESET Pulse Activation Time t 10 ns min RESET Pulse Width Low tas 120 us max RESET Time Indicated by BUSY Low 1 Guaranteed by design and characterization not production tested All input signals are specified
20. OUT3 G10 Vss3 L1 A7 A5 Veins C8 VOUTA G11 VOUT23 L2 A6 A6 VOUT5 C9 VOUT7 G12 REFGNDC2 L3 N C A7 AGND3 c10 VOUT28 H1 WR DCEN L4 RESET A8 REFGNDA1 c11 VOUT26 H2 SDO L5 AGND AD Voo5 C12 VOUT27 H3 CS SYNC L6 AGND2 A10 Vss5 D1 DB7 H10 VOUT22 L7 VOUT12 AM Vss4 D2 DB8 H11 AGND L8 VOUT8 AT Voo4 D3 DGND1 H12 AGND L9 Voo1 B1 REG D10 Veer n AO L10 Veer2 B2 DGND4 D11 VOUT29 J2 Al L11 VOUT16 B3 DB9 D12 AGND J3 A2 L12 VOUTI7 B4 CLR E1 DB5 J10 VOUT15 M1 DGND3 B5 AGND E2 DB6 J11 VOUT20 M2 Vcc2 B6 AGND E3 Vcl J12 VOUT21 M3 FIFOEN B7 VOUTO E10 REFGNDB2 K1 A4 M4 AGND1 B8 VOUT1 E11 AGND K2 A5 M5 VOUT13 B9 VOUT2 E12 VOUT30 K3 A3 M6 VOUT9 B10 VOUT25 F1 DB4 KA DGND2 M7 REFGNDB1 B11 REFGNDD1 F2 DB3 K5 REFGNDA2 M8 Vrer 1 B12 VOUT24 F3 DB2 K6 Vner2 M9 Vss1 Ci DB13 F10 Vpo3 K7 VOUT10 M10 Vss2 e DB12 SCLK F11 REFGNDD2 K8 VOUT 1 M11 Voo2 C3 DB11 DIN F12 VOUT31 K9 AGND M12 REFGNDC1 Internal 1 MQ pull down device on this logic input Therefore it can be left floating and it defaults to a logic low condition N C Do not connect to this pin Internal active pull up device on these logic inputs They default to a logic high condition 3 Internal 1 MQ pull up device on this logic input Therefore it can be left floating and it defaults to a logic high condition Rev A Page 12 of 28 AD5378 Table 9 Pin Function Descriptions Pin Description Vec 1 3 Logic Power Supply 2 7 V to 5 5 V These pins should
21. be decoupled with 0 1 uF ceramic capacitors and 10 uF tantalum capacitors Vss 1 5 Negative Analog Power Supply 11 4 V to 16 5 V for specified performance These pins should be decoupled with 0 1 uF ceramic capacitors and 10 uF tantalum capacitors Vop 1 5 Positive Analog Power Supply 11 4 V to 16 5 V for specified performance These pins should be decoupled with 0 1 pF ceramic capacitors and 10 uF tantalum capacitors AGND 1 4 Ground for All Analog Circuitry All AGND pins should be connected to the AGND plane DGND 1 4 Ground for All Digital Circuitry All DGND pins should be connected to the DGND plane Vaer 1 4 Vaer 1 Vaer2 4 Vrer2 Vals VOUTO to VOUT31 SER PAR SYNC SCLK DIN SDO DCEN CS WR DB13 to DBO AO to A7 REGO REG1 CLR BUSY LDAC Reference Inputs for DACs 0 to 5 8 to 13 16 to 21 and 24 to 30 These voltages are referred to AGND Reference Inputs for DACs 6 7 14 15 22 23 30 and 31 These reference voltages are referred to AGND DAC Bias Voltage Input Output This pin provides an access to the on chip voltage generator voltage It is provided for bypassing and overdriving purposes only If Veer gt 4 25 V Veins must be pulled high externally to an equal or higher potential for example 5 V If Veer lt 4 25 V the on chip bias generator can be used In this case the Vaas pin should be decoupled with a 10 nF capacitor to AGND DAC Outpu
22. calcula tion of x2 the BUSY output goes low While BUSY is low the user can continue writing new data to the x1 m or c registers but no DAC output updates can take place The DAC outputs are updated by taking the LDAC input low If LDAC goes low while BUSY is active the LDAC event is stored and the DAC outputs update immediately after BUSY goes high A user can also hold the LDAC input permanently low In this case the DAC outputs update immediately after BUSY goes high Table 11 BUSY Pulse Width BUSY Pulse Width ns max FIFO FIFO Action Enabled Disabled Loading x1 c or m to 1 channel 530 330 Loading x1 c or m to 2 channels 700 500 Loading x1 c or m to 3 channels 900 700 Loading x1 c or m to 4 channels 1050 850 Loading x1 c or m to all 32 5500 5300 channels The value of x2 for a single channel or group of channels is recalculated each time there is a write to any x1 register s c register s or m register s During the calculation of x2 BUSY goes low The duration of this BUSY pulse depends on the number of channels being updated For example if x1 c or m data is written to one DAC channel BUSY goes low for 550 ns max However if data is written to two DAC channels BUSY goes low for 700 ns max There are approximately 200 ns of overhead due to FIFO access See Table 11 The AD5378 contains an additional feature whereby a DAC register is not updated u
23. ce levels the user can adopt one of these approaches e Use a resistor divider to divide down a convenient higher reference level to the required level e Select convenient reference levels above Vrer min or below Vrer max Modify the gain and offset registers to downsize the references digitally In this way the user can use almost any convenient reference level but can reduce performance by overcompaction of the transfer function e Use a combination of these two approaches Rev A Page 19 of 28 AD5378 CALIBRATION The user can perform a system calibration by overwriting the default values in the m and c registers for any individual DAC channel as follows 1 Calculate the nominal offset and gain coefficients for the new output range see the revious example 2 Calculate the new m and c values for each channel based on the specified offset and gain errors Calibration Example Nominal Offset Coefficient 0 Nominal Gain Coefficient 10 10 5 x 8191 0 95238 x 8191 7801 Example 1 Channel 0 Gain Error 3 Offset Error 100 mV l Gain Error 3 Calibration 7801 x 1 03 8035 gt Load Code 1 1111 0110 0011 to m Register 0 2 Offset Error 100 mV Calibration LSB Size 10 5 16384 641 uV Offset Coefficient for 100 mV Offset 100 0 64 156 LSBs gt Load 10 0000 1001 1100 to c Register 0 Example 2 Channel 1 Gain Error 396 Offset Error 100 mV l Gain Error 396 Calib
24. d ing on the value of REGI and REGO this data is loaded into the addressed DAC input register s offset c register s gain m register s or the special function register Table 13 DAC Data Format REGI 1 REGO 1 Table 15 Gain Data Format REGI 0 REGO 1 DB13 to DBO DAC Output 1111111111 1111 16383 16384 Vrer V 11111111111110 16382 16384 Vrer V 10 0000 0000 0001 8193 16384 Vrer V 10 0000 0000 0000 8192 16384 Vrer V 0111111111 1111 8191 16384 Vrer V 00 0000 0000 0001 1 16384 Vrer V 00 0000 0000 0000 0v DB13 to DB1 Gain 111111111 1111 8192 8192 111111111 1110 8191 8192 1 0000 0000 0001 4098 8192 1 0000 0000 0000 4097 8192 0111111111111 4096 8192 0 0000 0000 0001 2 8192 0 0000 0000 0000 1 8192 Table 16 Special Function Data Format REGI 0 REGO 0 DB13 to DBO Increment Decrement Step LSB Table 14 Offset Data Format REGI 1 REGO 0 DB13 to DBO Offset LSB 1111111111 1111 8191 1111111111 1110 8190 10 0000 0000 0001 1 10 0000 0000 0000 0 011111 11111111 1 00 0000 0000 0001 8191 00 0000 0000 0000 8192 00000 10 1111111 00000 10 0000111 00000 10 0000001 00000 X0 0000000 00000 00 0000001 00000 00 0000111 00000 00 1111111 127 7 1 Table 17 Soft Reset REG1 0 REGO 0 DB13 to DBO DAC Output 1111111111 1111 REFGND Rev A Page 24 of 28 ADDRESS DECO
25. data to additional x1 c and m registers these are stored in a FIFO but no further updates to the DAC registers and DAC outputs can take place If LDAC is taken low while BUSY is low this event is stored Because BUSY is bidirectional it can be pulled low externally to delay LDAC action BUSY also goes low during power on reset or when the RESET pin is low During a RESET operation the parallel interface is disabled and any events on LDAC are ignored Load DAC Logic Input Active low If LDAC is taken low while BUSY is inactive high the contents of the input registers are transferred to the DAC registers and the DAC outputs are updated If LDAC is taken low while BUSY is active and internal calculations are taking place the LDAC event is stored and the DAC registers are updated when BUSY goes inactive However any events on LDAC during power on reset or RESET are ignored Rev A Page 13 of 28 AD5378 Pin Description FIFOEN FIFO Enable Level sensitive active high When connected to DVDD the internal FIFO is enabled allowing the user to write to the device at full speed FIFO is available in both serial and parallel modes The FIFOEN pin has an internal 1 MO pull down resistor connected to ground meaning that the FIFO is disabled by default RESET Asynchronous Digital Reset Input Falling edge sensitive If unused RESET can be left unconnected an internal pull up resistor
26. do not require separate pins but share parallel interface pins Rev A Page 14 of 28 TYPICAL PERFORMANCE E INL LSBs FREQUENCY INL ERROR LSB 1 5 0 5 ji ji MW i 1 bL i M v UB Il l id 0 5 Vpp 12V Vss 12V 1 0 Vngr 5V Vner 3 5V Ta 25 C 1 5 0 2 4 6 8 10 12 14 46 AD5378 CODE 103 05292 008 Figure 8 Typical INL Plot 1400 Vpp 12V Vss 12V Vrer 5V Vrer 3 5V 1200 1000 800 600 400 3 2 1 0 1 2 3 INL ERROR LSB 05292 009 Figure 9 INL Error Distribution 40 C 25 C 85 C Superimposed Vpp 12V Vss 12V Vrer 5V Vue 3 5V Tmax 85 C 20 0 20 40 60 80 05292 010 TEMPERATURE C Figure 10 Typical INL Error vs Temperature Rev AD5378 05292 011 05292 012 Vpp 12V Vss 12V Vrer 5V Vner 3 5V Tmax 85 C s E m o d 3 TT TEMPERATURE C Figure 11 Typical Full Scale and Zero Scale Errors vs Temperature 19 0 Vpp 412V Vpee 45V 18 9 Vss 2 12V Vper 3 5V 18 8 85 C 18 7 186 E 25 C S8 185 184 40 C 18 3 18 2 18 1 10 0 10 5 11 0 11 5 12 0 12 5 13 0 135 14 0 14 5 15 0 Vpp V Figure 12 lbo vs Von over Temperatu
27. e property of their respective owners www ana l 0 g com 15 5 lal DEVICES Rev A Page 28 of 28
28. ent of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function It is measured after adjusting for zero scale error and full scale error and is expressed in least significant bits LSB Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB maximum ensures monotonicity Zero Scale Error Zero scale error is the error in the DAC output voltage when all Os are loaded into the DAC register Ideally with all 0s loaded to the DAC and m is all 1s cis 10 0000 0000 0000 VOUT eero scale 2 5 X Vrer AGND REFGND Zero scale error is a measurement of the difference between VOUT actual and VOUT ideal expressed in mV Zero scale error is mainly due to offsets in the output amplifier Full Scale Error Full scale error is the error in DAC output voltage when all 1s are loaded into the DAC register Ideally with all 1s loaded to the DAC and m is all 1s c is 10 0000 0000 0000 VOUT ursa 3 5 x Vrer AGND 2 5 x Vrer AGND REFGND Full scale error is a measurement of the difference between VOUT actual and VOUT ideal expressed in mV It does not include zero scale error Gain Error Gain error is the difference between full scale error and zero scale error It is expressed in mV Gain Error Full Scale Er
29. es daisy chain mode The first falling edge of SYNC starts the write cycle The SCLK is continuously applied to the input shift register when SYNC is low If more than 24 clock pulses are applied the data ripples out of the shift register and appears on the SDO line This data is clocked out on the rising edge of SCLK and is valid on the falling edge By connecting this line to the DIN input on the next device in the chain a multidevice interface is constructed For each AD5378 in the system 24 clock pulses are required Therefore the total number of clock cycles must equal 24N where N is the total number of AD5378 devices in the chain If fewer than 24 clocks are applied the write sequence is ignored When the serial transfer to all devices is complete SYNC should be taken high This latches the input data in each device in the daisy chain and prevents any additional data from being clocked into the input shift register A continuous SCLK source can be used if SYNC is held low for the correct number of clock cycles Alternatively a burst clock containing the exact number of clock cycles can be used and SYNC taken high after the final clock to latch the data When the transfer to all input registers is complete a common LDAC signal updates all DAC registers and all analog outputs are updated simultaneously Rev A Page 23 of 28 AD5378 DATA DECODING The AD5378 contains a 14 bit data bus DB13 to DBO Depen
30. ew VOUT limits centered on the nominal values and assuming REFGND is 0 V or equal to AGND Vpp and Vss must provide sufficient headroom 5 Calculate the values of Vrer and Vres as follows Vagr min VOUT max VOUT min 3 5 Vrer max AGND VOUT min 2 5 In addition when using reference values other than those suggested Vrer 5 V and Vrer 3 5 V the expected offset error component changes as follows Vorrser 0 125 x Vrer a 0 7 x Vrer a where Vrer a is the new negative reference value Vrer a is the new positive reference value If this offset error too large to calibrated out it is possible to adjust the negative reference value to account for this by using the following equation Vrer new Vrer a Vorrser 2 625 Reference Selection Example Nominal Output Range 10 V 2 V to 8 V Offset Error 100 mV Gain Error 3 REFGND AGND 0 V l Gain Error 3 gt Maximum Positive Gain Error 3 gt Output Range including Gain Error 10 0 03 10 10 3 V 2 Offset Error 100 mV gt Maximum Offset Error Span 2 100 mV 0 2 V gt Output Range including Gain Error and Offset Error 10 3 0 2 10 5 V 3 Vrer and Vrrr Calculation Actual Output Range 10 5 V that is 2 25 V to 8 25 V centered gt Vrer 8 25 2 25 3 5 3 V and Vrer 2 25 2 5 0 9 V If the solution yields inconvenient referen
31. glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog output change at another converter It is specified in nV s Digital Crosstalk The glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter is defined as the digital crosstalk and is specified in nV s Digital Feedthrough When the device is not selected high frequency logic activity on the devices digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins It can also be coupled along the supply and ground lines This noise is digital feedthrough Output Noise Spectral Density This is a measurement of internally generated random noise Random noise is characterized as a spectral density voltage per Hz It is measured by loading all DACs to midscale and measuring noise at the output It is measurement in nV Hz Rev A Page 17 of 28 AD5378 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE GENERAL The AD5378 contains 32 DAC channels and 32 output amplifiers in a single package The architecture of a single DAC channel consists of a 14 bit resistor string DAC followed by an output buffer amplifier The resistor string section is simply a string of resistors each of value R from Vrer to AGND This type of architecture guarantees DAC monotonicity The 14 bit binary digital code loaded to the DAC register
32. istics sssss 15 Terminology i it e E RR ntes 17 Functional Description sseeeeeeeenttetentnnns 18 DAC Architecture General sse 18 Channel Groups repeteret etit p e PARE 18 Transfer FUDCtioD dette tettte eia edente ee eed 18 Vers FUNCTION M 19 REVISION HISTORY 7 09 Rev 0 to Rev A Chianges to Table lrini PR Ear 24 4 05 Revision 0 Initial Version R f rence Selection eee e 19 Calibrationgz emn RES ce 20 CIear Eunction ve RR E I 20 BUSY and LDAC Functions s 20 FIFO vs Non FIFO Operation sse 21 BUSY Input Function eee peterent tret 21 Power On Reset Function eene 21 RESET Input Function seeeeeeeetenttnnttenten tenens 21 Increment Decrement Function esee 21 Interfaces ettet eet EI CAES 22 Parallel interface et DR 22 Serial Interfacezocostsec e DLL E IU 22 Data Decoding i node tet en sie iq Pd to eR eig tse 24 Address Decodihig sannari onia 25 Power Supply Decoupling seen 26 BAONE OM TETERE ETT EE TTET 26 Typical Application Circuit seen 27 O tline Dimensions citri ERE RR ERE ER eR ERO Een 28 Ordering Gilde soe ete abes 28 Rev A Page 2 of 28 GENERAL DESCRIPTION The AD5378 contains 32 14 bit DACs in one CSPBGA package The AD5378 provides a bipolar output range determined by the voltages applied to the Vrex and Vrer
33. m Shown here is one provides solutions for all these functions pin of a typical logic tester It is apparent that a number of discrete levels are required for the pin driver active load circuit parametric measurement unit comparators and clamps DRIVEN SHIELD 500 COAX TIMING GENERATOR DLL LOGIC GND SE DEVICE POWER SUPPLY 05292 022 Figure 22 Typical Application Circuit for Logic Tester Rev A Page 27 of 28 AD5378 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 2111098 7654321 o 00000000000 OOoooooooooo o0000000000 oo INDICATOR BOTTOM VIEW TOP VIEW ooo0oo000000 Oooooooooo OoOoooooooo SrReIO MmMOODWD o o o o o o o o o o o oo oo oo oo oo oo oo oo 1 85 DETAIL A 1 70 1 55 DETAIL A 1 05 1 00 0 90 0 75 0 70 0 65 al i 0 12 MAX 0 64TYP SEATING COPLANARITY BALL DIAMETER COMPLIANT WITH JEDEC STANDARDS MO 192 AAD 1 WITH i THE EXCEPTION OF PACKAGE HEIGHT AND BALL DIAMETER 5 Figure 23 108 Ball Chip Scale Package Ball Grid Array CSP_BGA BC 108 2 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Linearity Error LSBs Package Description Package Option AD5378ABC 40 C to 85 C 3 108 Ball CSP_BGA BC 108 2 AD5378ABCZ 40 C to 85 C 3 108 Ball CSP_BGA BC 108 2 Z RoHS Compliant part 2005 2009 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are th
34. nless its x2 register is written to since the last time LDAC was brought low Normally when LDAC is brought low the DAC registers are filled with the contents of the x2 registers However the AD5378 updates the DAC register only if the x2 data changes thereby removing unnecessary digital crosstalk Rev A Page 20 of 28 FIFO VS NON FIFO OPERATION Data can be loaded to the AD5378 registers with FIFO disabled or enabled Operation with FIFO disabled is optimum for single writes to the device If the system requires significant data transfers to the AD5378 however operation with FIFO enabled is more efficient When FIFO is enabled the AD5378 uses an internal FIFO memory to allow high speed successive writes in both serial and parallel modes This optimizes the interface speed and efficiency minimizes the total conversion time due to internal digital efficiencies and minimizes the overhead on the master controller when managing the data transfers The BUSY signal goes low while instructions in the state machine are being executed Table 11 compares operation with FIFO enabled and FIFO disabled for different data transfers to the AD5378 Operation with FIFO enabled is more efficient for all operations except single write operations When using the FIFO the user can continue writing new data to the AD5378 while write instruc tions are being executed Up to 128 successive instructions can be written to the FIFO at maximum speed
35. or to AGND Avoid crossover of digital and analog signals Traces on opposite sides of the board should run at right angles to each other This reduces the effects of feedthrough through the board A microstrip technique is by far the best but not always possible with a double sided board In this technique the component side of the board is dedicated to ground plane while signal traces are placed on the solder side As for all thin packages care must be taken to avoid flexing the CSPBGA package and to avoid a point load on the surface of this package during the assembly process POWER ON An on chip power supply monitor makes the AD5378 robust to power sequencing The supply monitor powers up the analog section after Vpp Vss is greater than 7 V typical The output buffers power up in CLR mode forced to the DUTGND potential even if Vcc remains at 0 V After Vss is applied the analog circuitry powers up and the buffered DAC output level settles linearly within the supply range Rev A Page 26 of 28 AD5378 TYPICAL APPLICATION CIRCUIT The high channel count of the AD5378 makes it wellsuited to In addition to the DAC levels required in the ATE system applications requiring high levels of integration such as optical shown drivers loads comparators and parametric and automatic test equipment ATE systems Figure 22 shows measurement unit functions are also required Analog Devices the AD5378 as it is used in an ATE syste
36. ple devices require an AGND to DGND connection the connection should be made at one point only The star ground point should be established as close as possible to the device For supplies with multiple pins Vss Vor Vcc it is recom mended to tie these pins together and to decouple each supply once The AD5378 should have ample supply decoupling of 10 uF in parallel with 0 1 uF on each supply located as close to the package as possible ideally right up against the device The 10 pF capacitors are the tantalum bead type The 0 1 uF capaci tor should have low effective series resistance ESR and effective series inductance ESI such as the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching Digital lines running under the device should be avoided because these couple noise onto the device The analog ground plane should be allowed to run under the AD5378 to avoid noise coupling The power supply lines of the AD5378 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line Fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs It is essential to mini mize noise on all Vrer and Vrer lines The Vsus pin should be decoupled with a 10 nF capacit
37. ration 7801 x 0 97 7567 gt Load Code 1 1110 1000 1111 to m Register 1 2 Offset Error C100 mV Calibration LSB Size 10 5 16384 641 uV Offset Coefficient for 100 mV Offset 100 0 64 156 LSBs gt Load 01 1111 0110 0100 to c Register 1 CLEAR FUNCTION The clear function on the AD5378 can be implemented in hardware or software Hardware Clear Bringing the CLR pin low switches the outputs VOUTO to VOUT31 to the externally set potential on the REFGND pin This is achieved by switching in REFGND and reconfiguring the output amplifier stages into unity gain buffer mode thus ensuring that VOUT is equal to REFGND The contents of the input registers and DAC registers are not affected by taking CLR low When CLR is brought high the DAC outputs remain cleared until LDAC is taken low While CLR is low the value of LDAC is ignored Software Clear Loading a clear code to the x1 registers also enables the user to set VOUTO to VOUT31 to the REFGND level The default clear code corresponds to m at full scale and c at midscale x2 x1 Default Clear Code 2 x Output Offset Output Range 2 x 2 5 x AGND Vrer 3 5 x Vazr 4 AGND The more general expression for the clear code is as follows Clear Code 2 m 1 x Default Clear Code c BUSY AND LDAC FUNCTIONS The value of x2 is calculated each time the user writes new data to the corresponding x1 c or m registers During the
38. re 14 6 Vpp 12V Vrer 45V Vss 2 12V Vper 3 5V 14 8 40 C 15 0 lt E 15 2 o 2 25 C 15 4 15 6 85 C 15 8 10 0 10 5 11 0 11 5 12 0 12 5 13 0 13 5 14 0 14 5 15 0 Vpp V 05292 013 Figure 13 Iss vs Vpp over Temperature A Page 15 of 28 AD5378 Icc mA AMPLITUDE V AMPLITUDE V 3 5 3 0 2 5 2 0 1 5 1 0 0 208 0 211 0 214 0 217 0 220 0 208 0 211 0 Vpp 12V Vss 12V Vrer 5V Vrer 3 5V 3 0 3 5 4 0 4 5 SUPPLY VOLTAGE V Figure 14 Icc vs Supply 5 0 TA 25 C Vpp 12V Vss 12V Vrer 5V Vrer 3 5V 5 5 8 TIME us 12 Figure 15 Major Code Transition Glitch Energy TA 25 C Vgs 12V Vper 3 5V Vpp 12V Vggr 4 45V 20 2 8 TIME us 4 2 Figure 16 Digital Feedthrough 05292 014 05292 015 05292 016 Rev Icc mA A Page 16 of 28 Ta 25 C Vpp 12V Vss 12V Vrer 5V Vrer 3 5V Figure 17 DAC to DAC Crosstalk Ta 25 C Vpp 12V Vss 12V Vrer 5V Vrer 3 5V Voc 3 3V 1 2 1 6 2 0 INPUT VOLTAGE V Figure 18 Supply Current vs Digital Input Voltage 05292 017 05292 018 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint linearity is a measurem
39. ror Zero Scale Error VOUT Temperature Coefficient This includes output error contributions from linearity offset and gain drift DC Output Impedance DC output impedance is the effective output source resistance It is dominated by package lead resistance AD5378 DC Crosstalk The 32 DAC outputs are buffered by op amps that share common Vpp and Vss power supplies If the dc load current changes in one channel due to an update this can result in a further dc change in one or more channel outputs This effect is more significant at high load currents and reduces as the load currents are reduced With high impedance loads the effect is virtually unmeasurable Multiple Vpn and Vss terminals are provided to minimize dc crosstalk Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a full scale input change Digital to Analog Glitch Energy This is the amount of energy injected into the analog output at the major code transition It is specified as the area of the glitch in nV s It is measured by toggling the DAC register data between Ox1FFF and 0x2000 Channel to Channel Isolation Channel to channel isolation refers to the proportion of input signal from one DAC s reference input that appears at the output of another DAC operating from another reference It is expressed in dB and measured at midscale DAC to DAC Crosstalk DAC to DAC crosstalk is the
40. the following pins SYNC DIN SCLK Standard 3 wire interface pins DCEN Selects standalone mode or daisy chain mode SDO Data out pin for daisy chain mode Figure 4 and Figure 5 show the timing diagrams for a serial write to the AD5378 in standalone and daisy chain modes respectively The 24 bit data word format for the serial interface is shown in Figure 21 MSB LSB A7 A0 REG1 Eg DB13 DBO E Dp ge GROUP CHANNEL REGISTER SELECT REGISTER DATA BITS SELECT BITS BITS 05292 021 Figure 21 Serial Data Format Standalone Mode By connecting the DCEN daisy chain enable pin low standalone mode is enabled The serial interface works with both a continuous and a burst serial clock The first falling edge of SYNC starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits is shifted into the serial shift register Additional edges on SYNC are ignored until 24 bits are shifted in Once 24 bits are shifted in the SCLK is ignored For another serial transfer to take place the counter must be reset by the falling edge of SYNC Rev A Page 22 of 28 AD5378 Daisy Chain Mode For systems that contain several DACs the SDO pin can be used to daisy chain several devices together This daisy chain mode can be useful in system diagnostics and in reducing the number of serial interface lines Connecting the DCEN daisy chain enable pin high enabl
41. the parallel interface the SER PAR pin can be left unconnected Figure 6 shows the timing diagram for a parallel write to the AD5378 The parallel interface is controlled by the following pins CS Pin Active low device select pin WR Pin On the rising edge of WR with CS low the address values at Pins A7 to AO are latched and data values at Pins DB13 to DBO are loaded into the selected AD5378 input registers REG1 REGO Pins The REGI and REGO pins determine the destination register of the data being written to the AD5378 See Table 12 Table 12 Register Selection REG1 REGO Register Selected 1 1 Input Data Register x1 1 0 Offset Register c 0 1 Gain Register m 0 0 Special Function Register DB13 to DBO Pins The AD5378 accepts a straight 14 bit parallel word on DBO to DB13 where DB13 is the MSB and DBO is the LSB See Table 13 to Table 17 A7 to AO Pins Each of the 32 DAC channels can be addressed individually In addition several channel groupings enable the user to simulta neously write the same data to multiple DAC channels Address Bits A7 to A4 are decoded to select one group or multiple groups of registers Address Bits A3 to A0 select one of ten input data registers x1 offset registers c or gain registers m See Table 18 SERIAL INTERFACE The SER PAR pin must be tied high to enable the serial inter face and disable the parallel interface The serial interface is controlled by
42. ts Buffered analog outputs for each of the 32 DAC channels Each analog output can drive an output load of 5 kO to ground Typical output impedance of these amplifiers is 1 O Interface Select Input This pin allows the user to select whether the serial or parallel interface is used This pin has an internal 1 MO pull down resistor meaning that the default state at power on is parallel mode If this pin is tied high the serial interface is used Active Low Input This is the frame synchronization signal for the serial interface Serial Clock Input Data is clocked into the shift register on the falling edge of SCLK This pin operates at clock speeds up to 50 MHz Serial Data Input Data must be valid on the falling edge of SCLK Serial Data Output CMOS output SDO can be used for daisy chaining several devices together Data is clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK Daisy Chain Select Input Level sensitive active high When high this signal is used in conjunction with SER PAR high to enable serial interface daisy chain mode Parallel Interface Chip Select Input Level sensitive active low When this pin is low the device is selected Parallel Interface Write Input Edge sensitive The rising edge of WR is used in conjunction with CS low and the address bus inputs to write to the selected AD5378 registers Parallel Data Inputs The AD5378 can accept a straight 14 bit parallel word on DBO to DB1
43. with t tr 2 ns 10 to 90 of Vcc and timed from a voltage level of 1 2 V 3 See Figure 6 Measured with load circuit in Figure 2 Rev A Page 9 of 28 AD5378 to t fag er EE EET REGO REG1 A7 A02 DB12 DBO BUSY LDAC VOUT too VOUT 1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE AFTER BUSY t22 RESET VOUT tos m tos S BUSY lt 8 Figure 6 Parallel Interface Timing Diagram Rev A Page 10 of 28 AD5378 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Transient currents of up to 100 mA do not cause SCR latch up Table 7 Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device This is a stress Vos to AGND 03Vto 17V rating only functional operation of the device at these or any Vss to AGND 17V to 40 3 V other conditions above those listed in the operational sections Ve to DGND 03Vto47V of this specification is not implied Exposure to absolute Digital Inputs to DGND 03VtoVcc 03V maximum rating conditions for extended periods may affect Digital Outputs to DGND 0 3 V to Vee 03V device reliability Only one absolute maximum rating may be Veer Vrer2 to AGND 03Vto 47V applied at eny onetime Vner 1 Veer2 to AGND Vss 0 3 V to Voo 0 3 V Veias to AGND 0 3 V to 7 V VOUTO VOUT31 to AGND Vss 0 3 V to Voo 0 3 V REFGND to AGND Vss 0 3 V to Voo
44. x RESET Time Indicated by BUSY Low 1 Guaranteed by design and characterization not production tested All input signals are specified with t tr 2 ns 10 to 90 of Vcc and timed from a voltage level of 1 2 V 3 See Figure 4 and Figure 5 Standalone mode only 5 This is measured with the load circuit of Figure 2 6 This is measured with the load circuit of Figure 3 Daisy chain mode only Vcc RL 2 2ko TO V in V L OUTPUT on min Vo max PIN c 2 TO E OUTPUT VoL 8 PIN 8 8 C_ 50pF s 8 M i Figure 3 Load Circuit for SDO Timing Diagram Figure 2 Load Circuit for BUSY Timing Diagram Serial Interface Daisy Chain Mode Rev A Page 6 of 28 AD5378 SCLK SYNC DIN LDAC u VOUT LDAC tie VOUT tis tio VOUT 1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE AFTER BUSY tos RESET VOUT lio pusy Ne cs BUSY Figure 4 Serial Interface Timing Diagram Standalone Mode 05292 004 Rev A Page 7 of 28 AD5378 SCLK t __ t4 SYNC ts ty INPUT WORD FOR DAC N INPUT WORD FOR DAC N 1 so X X XXX KOO UNDEFINED INPUT WORD FOR DAC N to3 tis LDAC tog BUSY in Figure 5 Serial Interface Timing Diagram Daisy Chain Mode Rev A Page 8 of 28 05292 005 PARALLEL INTERFACE Vcc 2 7 V to 5 5 V Voo 11 4 V to 16 5 V Vss 11 4 V to 16 5 V AGND DGND DUTGND 0 V Vrer 5 V Vrer 3 5 V FIF

ANALOG DEVICES AD5378 English products handbook Rev A

Contents

Download Pdf Manuals

Related Search

Related Contents