ATMEL AT94S Secure Series Programmable SLI handbook
Contents
1. Usable Gates Speed Grade Ordering Code Package Operation Range Commercial AL 25D 256ZA AT94S05AL 25DGC 56 0 C 70 C ii ndustrial AL 25DGI 256ZA AT94S05AL 25DG 56 40 85 C AT94S10AL 25DGC 256ZA Commercial AT94S10AL 25BQC 144L 1 0 C 70 C 10 000 25 MHz AT94S10AL 25DGI 256ZA Industrial AT94S10AL 25BQI 144L 1 40 C 85 C AT94S40AL 25DGC 256ZA Commercial AT94S40AL 25BQC 144L 1 0 C 70 C 40 000 16 MHz AT94S40AL 25DGI 256ZA Industrial AT94S40AL 25BQI 144L 1 40 C 85 C Package Type 256ZA 256 ball Chip Array Ball Grid Array Package CABGA 144L1 144 lead Low Profile Plastic Gull Wing Quad Flat Package LQFP 28 AT94S Secure Family s 2314D FPSLI 2 04 AT94S Secure Family Packaging Information 256ZA CABGA D A1 Ball Pad Corner D B rb ir b m D D E D D D D D D D Y k A1 Top View A Side View A1 Ball Pad Corner 2555502 oooooooooooooooolA e ooooooooooooooool lB oooooooooooooooolc loo osos ooo oa D oooooooooooooooolF Unit of Measure mm ooooooooooooooooldG ooooooooooooooool lH SYMBOL MIN NOM MAX NOTE oooooooooooooooolu O000000000000000 K D 17 BSC oooooooooooooooo L E 17 BSC _ oooooooooooooooolM mi oooooooooooooooo N A 1 30 1 40 1 50 S oooooooooooooooolP 12. Data Byte LSB MSB DO D1 D2 D3 D4 D5 D6 D7 1st 2nd 3rd 4th 5th 6th 7th 8th The organization of the Data Byte is shown above Note that in this case the Data Byte is clocked into the device LSB first and MSB last Writing Writing to the normal address space takes place in pages A page is 128 bytes long in 2314D FPSLI 2 04 the 1 Mbit part The page boundaries are respectively addresses where Ag down to Agos are all zero and Ag down to Ag are all zero Writing can start at any address within a page and the number of bytes written must be 128 for the 1 Mbit part The first byte is written at the transmitted address The address is incremented in the Configura tor following the receipt of each Data Byte Only the lower 7 bits of the address are incremented Thus after writing to the last byte address within the given page the address will roll over to the first byte address of the same page A Write Instruction con sists of a Start Condition a Device Address Byte with R W 0 An Acknowledge Bit from the Configurator MS Byte of the EEPROM Address An Acknowledge Bit from the Configurator Next Byte of the EEPROM Address An Acknowledge Bit from the Configurator LS Byte of EEPROM Address An Acknowledge Bit from the Configurator One or more Data Bytes sent to the Configurator Each followed by an Acknowledge Bit from the Configurator a Stop Condition WRITE POLLING On receipt of the Stop Condition the Config
3. When Security Bit Cleared Entire Chip Erase Performed In System Programming Enabled Data Verification Enabled External Data pins allow for In System Programming of the device and setting of the EEPROM based security bit When the security bit is set active this programming con nection will only respond to a device erase command Data cannot be read out of the external programming data pins when the security bit is set The part can be re pro grammed but only after first being erased Atmel s Configurator Programming Software CPS available from the Atmel web site http www atmel com dyn products tools_card asp tool_id 3191 creates the pro gramming algorithm for the embedded configurator however if you are planning to write your own software or use other means to program the embedded configurator the section below includes the algorithm and other details The FPSLIC Configurator is a serial EEPROM memory which is used to load program mable devices This document describes the features needed to program the Configurator from within its programming mode i e when SER EN is driven Low Reference schematics are supplied for ISP applications The serial bus is a two wire bus one wire CSCK functions as a clock and is provided by the programmer the second wire CSDA is a bi directional signal and is used to pro vide data and control information Information is transmitted on the serial bus in messages Each
4. 1149 1 Compliant Interface Extensive On chip Debugging Support Limited Boundary scan Capabilities According to the JTAG Standards AVR Ports AVR Fixed Peripherals Industry standard 2 wire Serial Interface Two Programmable Serial UARTs Two 8 bit Timer Counters with Separate Prescaler and PWM One 16 bit Timer Counter with Separate Prescaler Compare Capture Modes and Dual 8 9 or 10 bit PWM Support for FPGA Custom Peripherals AVR Peripheral Control Up to 16 Decoded AVR Address Lines Directly Accessible to FPGA FPGA Macro Library of Custom Peripherals Up to 16 FPGA Supplied Internal Interrupts to AVR Up to Four External Interrupts to AVR 8 Global FPGA Clocks Two FPGA Clocks Driven from AVR Logic FPGA Global Clock Access Available from FPGA Core Multiple Oscillator Circuits Programmable Watchdog Timer with On chip Oscillator Oscillator to AVR Internal Clock Circuit Software selectable Clock Frequency Oscillator to Timer Counter for Real time Clock Voc 3 0V 3 6V 5V Tolerant I O 3 3V 33 MHz PCI Compliant FPGA I O 20 mA Sink Source High performance I O Structures All FPGA VO Individually Programmable High performance Low power 0 354 CMOS Five layer Metal Process State of the art Integrated PC based Software Suite including Co verification ATMEL T 6 VIA Secure 5K 40K Gates of AT40K FPGA with 8 bit AVR Microcontroller up to 36 Kbytes of SRAM and On chip
5. Program Storage EEPROM AT94S Secure Series Programmable SLI Rev 2314D FPSLI 2 04 AMEL Description The AT94S Series Secure FPSLIC family shown in Table 1 is a combination of the popular Atmel AT40K Series SRAM FPGAs the AT17 Series Configuration Memories and the high performance Atmel AVR 8 bit RISC microcontroller with standard peripher als Extensive data and instruction SRAM as well as device control and management logic are included in this multi chip module MCM The embedded AT40K FPGA core is a fully 3 3V PCl compliant SRAM based FPGA with distributed 10 ns programmable synchronous asynchronous dual port single port SRAM 8 global clocks Cache Logic ability partially or fully reconfigurable without loss of data and 5 000 to 40 000 usable gates Table 1 The AT94S Series Family Device AT94S05AL AT94S10AL AT94S40AL Configuration Memory Size 1 Mbit 1 Mbit 1 Mbit FPGA Gates 5K 10K 40K FPGA Core Cells 256 576 2304 FPGA SRAM Bits 2048 4096 18432 FPGA Registers Total 436 846 2862 Maximum FPGA User I O 95 143 287 AVR Programmable I O Lines 8 16 16 Program SRAM Bytes 4K 16K 20K 32K 20K 32K Data SRAM Bytes 4K 16K 4K 16K 4K 16K Hardware Multiplier 8 bit Yes Yes Yes 2 wire Serial Interface Yes Yes Yes UARTs 2 2 2 Watchdog Timer Yes Yes Yes Timer Counters 3 3 3 Real time Clock Yes Yes Yes JTAG ICE Yes Yes Yes Typical A
6. 0107 A4 1 0161 A4 1 0325 A4 A10 121 1 0108 A5 1 0162 A5 1 0326 A5 G10 122 NC 1 0163 1 0327 G9 NC 1 0164 1 0328 F9 1 0109 1 0165 1 0329 E9 123 1 0110 1 0166 1 0330 C9 124 1 0331 1 0332 1 0333 1 0334 1 0111 A6 1 0167 A6 1 0335 A6 B9 125 1 0112 A7 1 0168 A7 1 0336 A7 A9 126 1 0113 A8 1 0169 A8 1 0337 A8 A8 129 1 0114 A9 1 0170 A9 1 0338 A9 B8 130 1 0339 AMEL gt 2314D FPSLI 2 04 Table 5 AT94S Pin List Continued AMEL Package AT94S05 AT94S10 AT94S40 Chip Array 256 96 FPGA I O 144 FPGA I O 288 FPGA I O CABGA LQ1440 1 0340 1 0341 1 0342 1 0115 1 0171 1 0343 C8 131 1 0116 1 0172 1 0344 D8 132 NC 1 0173 1 0345 E8 NC 1 0174 1 0346 F8 1 0117 A10 1 0175 A10 1 0347 A10 H8 133 1 0118 A11 1 0176 A11 1 0348 A11 A7 134 NC NC 1 0349 C7 NC NC 1 0350 D7 1 0351 1 0352 1 0353 1 0354 1 0355 1 0356 NC 1 0177 1 0357 F7 NC 1 0178 1 0358 A6 1 0119 1 0179 1 0359 F6 135 1 0120 1 0180 1 0360 B6 136 1 0361 1 0362 NC 1 0181 1 0363 D6 NC 1 0182 1 0364 E6 1 0365 1 0366 1 0367 1 0368 1 0121 1 0183 1 0369 A5 1 0122 1 0184 1 0370 B5 1 0123 A12 1 0185 A12 1 0371 A12 E5 138 1 0124 A13 1 0186 A13 1 0372 A13 C5 139 1 0373 26 AT94S Secure Family s 2314D FPSLI 2 04 www x AT94S Secure Family Table 5 AT94S Pin List Conti
7. 9 1 010 1 014 1 026 G7 10 1 011 A20 1 015 A20 1 027 A20 G6 11 1 012 A21 1 016 A21 1 028 A21 G4 12 NC 1 017 1 029 G5 NC 1 018 1 030 G2 1 031 1 032 1 033 1 034 NC NC 1 035 G1 NC NC 1 036 H7 1 037 1 038 NC NC 1 039 H6 NC NC 1 040 H5 NC 1 019 1 041 H3 NC 1 020 1 042 H4 1 013 021 1 043 H2 13 1 014 1 022 1 044 H1 14 1 045 1 046 1 015 A22 1 023 A22 1 047 A22 J7 15 1 016 A23 1 024 A23 1 048 A23 J1 16 1 017 A24 1 025 A24 1 049 A24 J4 19 1 018 A25 1 026 A25 1 050 A25 J5 20 1 051 18 AT94S Secure Family s 2314D FPSLI 2 04 www x AT94S Secure Family Table 5 AT94S Pin List Continued Package AT94S05 AT94S10 AT94S40 Chip Array 256 96 FPGA I O 144 FPGA I O 288 FPGA I O CABGA LQ1440 O52 1 019 1 027 1 053 J6 21 1 020 1 028 1 054 J8 22 NC 1 029 1 055 K1 NC 1 030 1 056 K2 1 057 1 058 1 059 1 060 NC NC 1 061 K4 NC NC 1 062 K5 1 063 1 064 NC NC 1 065 K6 NC NC 1 066 L1 NC 1 031 1 067 L2 NC 1 032 1 068 L5 1 021 A26 1 033 A26 1 069 A26 L4 23 1 022 A27 1 034 A27 1 070 A27 M1 24 1 023 1 035 1 071 M2 25 1 024 FCK2 1 036 FCK2 1 072 FCK2 N1 26 1 073 1 074 1 037 1 075 1 038 1 076 1 077 1 078 1 079 1 080 1 025 1 039 1 081 M3 1 026 1 040 1 082 N2 1 041 1 083 1 042 1 084 1 085 AMEL 2314D FPSLI 2 04 Table 5 AT94S Pin
8. AT94S Secure Family s 2314D FPSLI 2 04 www x AT94S Secure Family Figure 5 Serial Data Timing Diagram cSCK cSDA cSDA 2314D FPSLI 2 04 low t HIGH AMEL tsu sto 13 ATMEL DC Characteristics Voc 3 3V 10 T 40 C 85 C 20 Symbol Parameter Test Condition Min Typ Max Units Vcc Supply Voltage 3 0 3 3 3 6 V loc Supply Current Voc 3 6 2 3 mA lu Input Leakage Current Vin Vcc Or Vss 0 10 10 yA lio Output Leakage Current Vout Vcc Or Vss 0 05 10 HA ViH High level Input Voltage Vec x 0 7 Vec 0 5 Vi Low level Input Voltage 0 5 0 2 VoL Output Low level Voltage lo 2 1 mA 0 4 Notes 1 Specific to programming mode i e when SER EN is driven Low 2 Commercial temperature range 0 C 70 C 3 Industrial temperature range 40 C 85 C 4 This parameter is characterized and is not 10096 tested AC Characteristics Voc 3 3V 10 Ta 40 C 85 C 9 Symbol Parameter Min Max Units feLock Clock Frequency Clock 100 KHz tiow Clock Pulse Width Low 4 us tHiGH Clock Pulse Width High 4 us taa Clock Low to Data Out Valid 0 1 1 us teur Time the Bus Must Be Free Before a New Transmission Can Start 4 5 us D STA Start Hold Time 2 us tsu sTA Start Setup Time 2 us HD DAT Data In Hold Time 0 us tsu par Data In Setup Time 0 2 us ta Inputs Rise Time 0 3 us tr Inputs
9. Fall Time 0 3 us tsu sto Stop Setup Time 2 us ton Data Out Hold Time 0 1 us twn Write Cycle Time 20 ms Notes 1 Specific to programming mode i e when SER_EN is driven Low 2 Commercial temperature range 0 C 70 C 3 Industrial temperature range 40 C 85 C 4 This parameter is characterized and is not 100 tested 14 AT94S Secure Family s 2314D FPSLI 2 04 ew www A 94S Secure Family Security Bit AT17LV512 010 Security Bit Programming Disabling the Security Bit Enabling the Security Bit Verifying the Security Bit 2314D FPSLI 2 04 Secure FPSLIC Configurator Pin Configurations 144 pin LOFP 105 256 pin CABGA D16 Name cSDA Description Three state DATA output for configuration Open collector bi directional pin for programming 107 C16 cSCK CLOCK output Used to increment the internal address and bit counter for reading and programming 53 K9 RESET O E RESET OE input when SER EN is High A Low level on both the CE and RESET OE inputs enables the data output driver A High level on RESET OE resets both the address and bit counters The logic polarity of this input is programmable as either RESET OE or RESET OE This document describes the pin as RESET OE 72 N16 Chip Enable input Used for device selection only when SER EN is High A Low level on both CE and OE enables the data output driver A High level on CE disables both the address an
10. knowledge Bit from t Next Byte of the EEPROM Add An Ac LS Byte An Ac a Start of knowledge Bit from t EEPROM Address knowledge bit from t Condition a Device Address with R W An Ac ge knowledge Bit from t he Configurator ss he Configurator ress he Configurator he Configurator 1 he Configurator Data Byte from the Configurator a Stop Condition from the programmer AT94S Secure Family s 2314D FPSLI 2 04 ew 94S Secure Family Programmer Functions Reading Manufacturer s and Device Codes Programming the Device Important Note on AT94S Series Configurators Programming Verifying the Device In System Programming Applications 2314D FPSLI 2 04 SEQUENTIAL READ Sequential Reads follow either a Current Address Read or a Random Address Read After the programmer receives a Data Byte it may respond with an Acknowledge Bit As long as the Configurator receives an Acknowledge Bit it will continue to increment the Data Byte address and serially clock out sequential Data Bytes until the memory address limit is reached The Sequential Read instruction is terminated when the programmer does not respond with an Acknowledge Bit but instead generates a Stop Condition following the receipt of a Data Byte Note 1 Ifan ACK is sent by the programmer after the data in the last memory address is sent by the configurator the internal address counter will rollove
11. 1 F15 INTP2 INTP2 INTP2 F14 TOSC1 TOSC1 TOSC1 E16 101 TOSC2 TOSC2 TOSC2 E15 102 RX1 RX1 RX1 E14 103 TX1 TX1 TX1 E13 104 DATAO cSDA DATA0 cSDA DATA0 cSDA D16 105 INTP3 CSOUT INTP3 CSOUT INTP3 CSOUT D15 106 CCLK eSCK CCLK cSCK CCLK cSCK C16 107 1 065 96 Are Unbonded 1 097 144 Are Unbonded 1 0193 288 Are Unbonded FPSLIC Array Testclock Testclock Testclock C15 109 1 097 A0 1 0145 A0 1 0289 A0 C14 111 1 098 GCK7 A1 1 0146 GCK7 A1 1 0290 GCK7 At B15 112 1 099 1 0147 1 0291 A16 113 1 0100 1 0148 1 0292 D13 114 1 0293 1 0294 NC NC 1 0295 C13 NC NC 1 0296 B14 1 0101 CS1 A2 1 0149 CST A2 1 0297 CST A2 A15 115 1 0102 A3 1 0150 A3 1 0298 A3 A14 116 1 0299 1 0300 1 0104 1 0151 1 0301 Shared with Test clock NC 1 0152 1 0302 D12 1 0103 1 0153 1 0303 C12 117 NC 1 0154 1 0304 A13 NC NC 1 0305 B12 24 AT94S Secure Family s 2314D FPSLI 2 04 www x AT94S Secure Family Table 5 AT94S Pin List Continued Package AT94S05 AT94S10 AT94S40 Chip Array 256 96 FPGA I O 144 FPGA I O 288 FPGA I O CABGA LQ1440 1 0306 1 0307 1 0308 NC 1 0155 1 0309 A12 NC 1 0156 1 0310 E11 NC NC 1 0311 C11 NC NC 1 0312 D11 1 0105 1 0157 1 0313 A11 119 1 0106 1 0158 1 0314 F10 120 NC 1 0159 1 0315 E10 NC 1 0160 1 0316 D10 NC NC 1 0317 C10 NC NC 1 0318 B10 1 0319 1 0320 1 0321 1 0322 1 0323 1 0324 1
12. 3 TMS P7 48 1 044 TCK 1 064 TCK 1 0124 TCK R7 49 NC 1 065 1 0125 K7 NC 1 066 1 0126 K8 1 0127 1 0128 1 0129 1 0130 1 0131 1 0132 1 0133 1 0134 NC 1 067 1 0135 M8 NC 1 068 1 0136 R8 1 045 1 069 1 0137 P8 50 1 046 1 070 1 0138 N8 51 1 0139 1 0140 1 0141 1 0142 1 047 TD7 1 071 TD7 1 0143 TD7 L8 52 1 048 InitErr RESET OE 1 072 InitErr RESET OE 1 0144 InitErr RESET OE K9 53 1 049 TD6 1 073 TD6 1 0145 TD6 P9 56 1 050 TD5 1 074 TD5 1 0146 TD5 N9 57 1 0147 1 0148 2314D FPSLI 2 04 ATMEL 21 Table 5 AT94S Pin List Continued AMEL Package AT94S05 AT94S10 AT94S40 Chip Array 256 96 FPGA I O 144 FPGA I O 288 FPGA I O CABGA LQ1440 O149 1 0150 1 051 1 075 1 0151 M9 58 1 052 1 076 1 0152 L9 59 NC 1 077 1 0153 J9 NC 1 078 1 0154 T10 1 0155 1 0156 1 0157 1 0158 1 0159 1 0160 1 0161 1 0162 NC 1 079 1 0163 P10 NC 1 080 1 0164 N10 1 053 TD4 1 081 TD4 1 0165 TD4 L10 60 1 054 TD3 1 082 TD3 1 0166 TD3 T11 61 1 055 1 083 1 0167 R11 62 1 056 1 084 1 0168 M11 63 NC NC 1 0169 N11 NC NC 1 0170 T12 NC 1 085 1 0171 R12 NC 1 086 1 0172 T13 1 0173 1 0174 1 0175 1 0176 NC 1 087 1 0177 N12 NC 1 088 1 0178 P12 1 057 1 089 1 0179 R13 1 058 1 090 1 0180 T14 NC NC 1 0181 N13 NC NC 1 0182 P13 22 AT94S Secure Family s 2314D FPSLI 2 04 ww
13. ADDRESS ADDRESS BYTE ADDRESS BYTE ADDRESS BYTE BYTE 1 ACK BIT CONFIGURATOR DATA STOP BYTE n CONDITION Current Address Read Extended to Sequential Read Instruction Message Format START DEVICE STOP CONDITION ADDRESS CONDITION ACK BIT ACK BIT eee CONFIGURATOR PROGRAMMER The Start Condition is indicated by a high to low transition of the cSDA line when the cSCK line is High Similarly the Stop Condition is generated by a low to high transition of the cSDA line when the cSCK line is High as shown in Figure 2 The Start Condition will return the device to the state where it is waiting for a Device Address its normal quiescent mode The Stop Condition initiates an internally timed write signal whose maximum duration is twp refer to AC Characteristics table for actual value During this time the Configurator must remain in programming mode i e SER EN is driven Low cSDA and cSCK lines are ignored until the cycle is completed Since the write cycle typically completes in less than twp seconds we recommend the use of polling as described in later sections Input levels to all other pins should be held constant until the write cycle has been completed The Acknowledge ACK Bit shown in Figure 2 is provided by the Configurator receiving the byte The receiving Configurator can accept the byte by asserting a Low value on the cSDA line or it can refuse the byte by asserting allowing the sig
14. List Continued AMEL Package AT94S05 AT94S10 AT94S40 Chip Array 256 96 FPGA I O 144 FPGA I O 288 FPGA I O CABGA LQ1440 1 086 1 087 1 088 1 027 A28 1 043 A28 1 089 A28 P1 28 1 028 1 044 1 090 P2 29 1 091 1 092 1 029 1 045 1 093 R1 30 1 030 1 046 1 094 N3 31 1 031 OTS 1 047 OTS 1 095 OTS T1 32 1 032 GCK2 A29 1 048 GCK2 A29 1 096 GCK2 A29 P3 33 AVRRESET AVRRESET AVRRESET R2 34 MO MO MO R3 36 FPSLIC Array M2 M2 M2 T3 38 1 033 GCK3 1 049 GCK3 1 097 GCK3 R4 39 1 034 HDC TDI 1 050 HDC TDI 1 098 HDC TDI T4 40 1 035 1 051 1 099 N5 41 1 036 1 052 1 0100 P5 42 1 053 1 0101 43 SER_EN SER_EN SER_EN M5 81 1 038 LDC TDO 1 054 LDC TDO 1 0102 LDC TDO R5 44 1 0103 1 0104 1 0105 1 0106 NC NC 1 0107 T5 NC NC 1 0108 M6 1 039 1 055 1 0109 P6 1 040 1 056 1 0110 R6 NC 1 057 1 0111 L6 NC 1 058 1 0112 T6 1 0113 1 0114 20 AT94S Secure Family s 2314D FPSLI 2 04 www x AT94S Secure Family Table 5 AT94S Pin List Continued Package AT94S05 AT94S10 AT94S40 Chip Array 256 96 FPGA I O 144 FPGA I O 288 FPGA I O CABGA LQ1440 0115 1 0116 1 059 1 0117 1 060 1 0118 1 0119 1 0120 1 041 1 061 1 0121 M7 46 1 042 1 062 1 0122 N7 47 1 043 TMS 1 063 TMS 1 012
15. MESSAGE is preceded by a Start Condition and ends with a Stop Condition The message consists of an inte ger number of bytes each byte consisting of 8 bits of data followed by a ninth Acknowledge Bit This Acknowledge Bit is provided by the recipient of the transmitted byte This is possible because devices may only drive the cSDA line Low The system must provide a small pull up current 1 kO equivalent for the cSDA line The MESSAGE FORMAT for read and write instructions consists of the bytes shown in Bit Format on page 5 While writing the programmer is responsible for issuing the instruction and data While reading the programmer issues the instruction and acknowledges the data from the Configurator as necessary 4 AT94S Secure Family s 2314D FPSLI 2 04 www AT94S Secure Family Bit Format Start and Stop Conditions Acknowledge Bit 2314D FPSLI 2 04 Again the Acknowledge Bit is asserted on the cSDA line by the receiving device on a byte by byte basis The factory blanks devices to all zeros before shipping The array cannot otherwise be initialized except by explicitly writing a known value to each location using the serial protocol described herein Data on the cSDA pin may change only during the cSCK Low time whereas Start and Stop Conditions are identified as transitions during the cSCK High time Write Instruction Message Format START DEVICE MS EEPROM NEXT EEPROM LS EEPROM DATA CONDITION
16. TART Condition Condition 16 AT94S Secure Family s 2314D FPSLI 2 04 www x AT94S Secure Family Packaging and Pin List information Table 3 Part and Package Combinations Available Part Package AT94S05 AT94S10 AT94S40 BG256 DG 93 137 162 LQ144 BQ 84 84 Table 4 AT94K JTAG ICE Pin List AT94S05 AT94S10 AT94S40 Pin 96 FPGA I O 192 FPGA I O 384 FPGA I O TDI 1034 1050 1098 TDO 1038 1054 10102 TMS 1043 1063 10123 TCK 1044 1064 10124 Table 5 AT94S Pin List Package AT94S05 AT94S10 AT94S40 Chip Array 256 96 FPGA I O 144 FPGA I O 288 FPGA I O CABGA LQ1440 FPSLIC Array 1 01 GCK1 A16 1 01 GCK1 A16 1 01 GCK1 A16 A1 2 1 02 A17 1 02 A17 1 02 A17 D4 3 1 03 1 03 1 03 D3 4 1 04 1 04 1 04 B1 5 1 05 A18 1 05 A18 1 05 A18 C2 6 1 06 A19 1 06 A19 1 06 A19 C1 7 1 07 1 08 NC NC 1 09 D2 NC NC 1 010 D1 1 011 1 012 1 013 1 014 1 07 1 07 1 015 E3 1 08 1 08 1 016 E4 NC 1 09 1 017 E2 17 2314D FPSLI 2 04 AMEL Table 5 AT94S Pin List Continued AMEL Package AT94S05 AT94S10 AT94S40 Chip Array 256 96 FPGA I O 144 FPGA I O 288 FPGA I O CABGA LQ1440 NC 1 010 1 018 Et 1 019 1 020 NC 1 011 1 021 F4 NC 1 012 1 022 F3 1 023 1 024 1 09 FCK1 1 013 FCK1 1 025 FCK1 F1
17. VR 25 MHz 19 MIPS 19 MIPS 19 MIPS Throughput 40 MHz 30 MIPS 30 MIPS 30 MIPS Operating Voltage 3 0 3 6V 3 0 3 6V 3 0 3 6V 2 AT94S Secure Family s 2314D FPSLI 2 04 Figure 1 AT94S Architecture Configuration Logic Configuration EEPROM VO For ISP and Chip Erase 2314D FPSLI 2 04 5 40K Gates FPGA Up to 16K x 16 Program Program Counter SRAM Memory AT94S Secure Family PROGRAMMABLE I O Up to 16 Decoded Address Lines Data Bus 8 bit Status and Test Up to 16 Interrupt Lines Control Registrers Interrupt 32x8 Unit 4 Interrupt Lines Instruction General Register Purpose Registrers 2 wire Serial gt 1 0 Unit Decoder o Two Serial 2 5 UARTS eno o 9 M 2 5 i o o Control Lines 2 lt Two 8 bit 3 9 Timer Counters 5 a 16 bit Timer Counter with PWM Watchdog Timer 16 Prog VO Lines 5 The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by exe cuting povverful instructions in a single clock eycle and allovvs system designers to optimize povver consumption versus processing speed The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general pur pose working registers All 32 registers are directly connected to the Arithmetic Logic Unit ALU allowing two independent registers to be accessed in one single instruction executed in one clock cycle The resulting architecture is more
18. W 1st 2nd 3rd 4th 5th 6th 7th 8th Where R W 1 Read 0 Write EEPROM Address Byte Order 512 Kbit 1 Mbit Page Length A LSB MSB LSB d Lsey 0 0 0 0 0 0 0 Acie ACK Azis Aksa Azis Aziz Azn Aexo Ago Agg ACK Ag Aes Ags Ag Az Az Az Ago ACK ist 2nd 3rd 4th 5th 6th 7th 8th ist 2nd 3rd 4th 5th 6th 7th 8th ist 2nd 3rd 4th 5th 6th 7th 8th 512 Kbit Address Space 1 Mbit Address Space The EEPROM Address consists of three bytes on the 1 Mbit part Each Address Byte is followed by an Acknowledge Bit provided by the Configurator These bytes define the normal address space of the Configurator The order in which each byte is clocked into the Configurator is also indicated Unused bits in an Address Byte must be set to 0 Exceptions to this are when reading Device and Manufacturer Codes AT94S Secure Family s 2314D FPSLI 2 04 Programming Summary Write to Whole Device START SER_EN lt Low PAGE_COUNT lt 0 Send Start Condition BYTE_COUNT lt 0 Send Device Address A6 Send MSB of EEPROM Address Middle Byte EEPROM Address Yes Send LSB of EEPROM Address Send Data Byte BYTE COUNT lt BYTE COUNT 1 Send Stop Condition PAGE COUNT lt PAGE COUNT PAGE COUNT 1 T PAGE Yes Send Start Condition f lt Verify Final Write Cycle Completion Yes SER EN lt High 1st Data Byte Value Changed Due Low power Standby to Write Power Cy
19. cle EEPROM Latches 1st Byte for FPGA Download Operations 2314D FPSLI 2 04 AT94S Secure Family Notes 1 The 1 Mbit part requires three EEPROM address bytes all three bytes must be individually ACK d by the EEPROM 2 Data byte received sent LSB to MSB EEPROM Address is Defined as AT17LVO10 0000 000xg XgX XgXg X4X4XoX X000 0000 Note where X Xo is PAGE COUNT b T BYTE AT17LV010 128 T_PAGE AT17LV010 1024 START CONDITION mds n cSDA STOP CONDITION ae cSDA DATA BIT cSDA ACK BIT cSCK LT TL cSDA XA k AMEL 7 Programming Summary Notes 1 The 1 Mbit part requires three EEPROM address Read from Whole Device Random Access Setup Sequential Read from Current Address bytes all three bytes must be individually ACK d by the EEPROM 2 Data byte received sent LSB to MSB EEPROM Address is Defined as AT17LV010 00 00 00 ih TT BYTE AT17LV010 131072 d Send Start Condition START CONDITION Send Device Address A6 Middle Byte EEPROM Address cSCK cSDA C No STOP CONDITION y cSCK Yes C No SAMPLE DATA BIT cSCK Y i i i eSDA ACK BIT eS6K F eSDA XA AGK Y Yes Read Data Byte BYTE COUNT lt BYTE COUNT 1 Send ACK No BYTE COUNT TT BYTE Sent Stop Condition SER EN High Low power Standby AT94S Secure Family s www x AT94S Secure Family
20. code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers at the same clock frequency The AVR executes out of on chip SRAM Both the FPGA configuration SRAM and AVR instruction code SRAM are automatically loaded at sys tem power up using Atmel s in system programmable AT17 Series EEPROM configuration memories which are part of the AT94S Multi chip Module MCM State of the art FPSLIC design tools System Designer were developed in conjunc tion with the FPSLIC architecture to help reduce overall time to market by integrating microcontroller development and debugging FPGA development place and route and complete system co verification in one easy to use software tool AMEL Internal Architecture FPSLIC and Configurator Interface Programming and Configuration Timing Characteristics The FPSLIC Configurator Serial Bus Overview AMEL For details of the AT94S Secure FPSLIC architecture please refer to the AT94K FPSLIC datasheet and the AT17 Series Configuration Memory datasheet available on the Atmel web site at http www atmel com This document only describes the differ ences between the AT94S Secure FPSLIC and the AT94K FPSLIC Fully In System Programmable and Re programmable When Security Bit Set Data Verification Disabled Data Transfer to FPSLIC not Externally Visible Secured EEPROM Will Only Boot the FPSLIC Device or Respond to a Chip Erase
21. ctions 1 Read the Manufacturers Code and the Device Code 2 Program the device 3 Verify the device data While Atmel s Secure FPSLIC Configurators can be programmed from various sources e g on board microcontrollers or PLDs the applications shown here are designed to facilitate users of our ATDH2225 Configurator Programming Cable The typical system setup is shown in Figure 3 The pages within the configuration EEPROM can be selectively rewritten This document is limited to example implementations for Atmel s AT94S application ATMEL n 12 AMEL Figure 3 Typical System Setup Target System Secure Secure FPSLIC FPSLIC ATDH2225 In System Programming Programming Dongle Connector Header The diode connection between the AT94S RESET pin and the SER EN signal allows the external programmer to force the FPGA into a reset state during ISP This eliminates the potential for contention on the cSCK line The pull up resistors required on the lines to RESET CON and INIT are present on the inputs internally to the AT94S FPSLIC see Figure 4 Figure 4 ISP of the AT17LV512 010 in an AT94S FPSLIC Application cSDA 1 cSCK 3 5 7 9 GND AT94S RESET SER_EN SER EN DATAO cSDA 1 a CLK cSCK M2 INIT RESET OE CON CE 1 1 MO Note 1 Configurator signal names are shown in parenthesis
22. d bit counters and forces the device into a low power mode Note this pin will not enable disable the device in the 2 wire Serial mode i e when SER EN is driven Low 81 M5 SER EN Serial enable is normally High during FPGA loading operations Bringing SER EN Low enables the programming mode Once the security bit is programmed data will no longer output from the normal data pad Once the fuse is set any attempt to erase the fuse will cause the configurator to erase all of it contents Write 4 bytes 00 00 00 00 to addresses 800000 800003 twice without a power cycle in between using the previously defined 2 wire write algorithm Write 4 bytes FF FF FF FF to addresses 800000 800003 using the previously defined 2 wire write algorithm Read 4 bytes of data from addresses 800000 800003 using the previously defined 2 wire Random Read algorithm If the data is FF FF FF FF the security bit has been enabled If the data is 00 00 00 00 the security bit has been disabled AMEL 15 AMEL Chip Erase Timing The entire device can be erased at once by writing to a specific address This operation will erase the entire array See Table 2 for specifics on the write algorithm Table 2 Chip Erase Cycle Characteristics Tec Chip Erase Cycle Time 25 ms Figure 6 Chip Erase Timing Diagram tsu dat thigh tlovv o je tnd dat SDA Z Ack 5 lt Tec gt STOP S
23. nal to be externally pulled up to a High value on the cSDA line All bytes from accepted messages must be terminated by either an Acknowledge Bit or a Stop Condition Following an ACK Bit when the cSDA line is released during an exchange of control between the Configurator and the programmer the cSDA line may be pulled High temporarily due to the open col lector output nature of the line Control of the line must resume before the next rising edge of the clock AMEL s Bit Ordering Protocol Device Address Byte AMEL The most significant bit is the first bit of a byte transmitted on the cSDA line for the Device Address Byte and the EEPROM Address Bytes It is followed by the lesser sig nificant bits until the eighth bit the least significant bit is transmitted However for Data Bytes both writing and reading the first bit transmitted is the least significant bit This protocol is shown in the diagrams below The contents of the Device Address Byte are shown below along with the order in which the bits are clocked into the device The CE pin cannot be used for device selection in programming mode i e when SER_EN is drive Low Figure 2 Start and Stop Conditions cSDA 8th Bit ACK BIT ZEE Byten m WR i STOP START Condition Condition Device Address Byte MSB LSB 1 0 1 0 0 1 1 R
24. nued Package AT94S05 AT94S10 AT94S40 Chip Array 256 96 FPGA I O 144 FPGA I O 288 FPGA I O CABGA LQ1440 1 0374 1 0375 1 0376 1 0377 1 0378 NC 1 0187 1 0379 A4 NC 1 0188 1 0380 B4 1 0125 1 0189 1 0381 A3 140 1 0126 1 0190 1 0382 C4 141 1 0127 A14 1 0191 A14 1 0383 A14 B3 142 1 0128 GCK8 A15 1 0192 GCK8 A15 1 0384 GCK8 A15 A2 143 Note 1 LQ144 is only offered in the AT94S10 and AT94S40 Table 6 256 CABGA and LQ144 Vpp Vec and GND Pins Package Vo Vee GND 256 B2 G13 R14 G8 H10 J3 D14 F12 P4 G3 H9 E7 B11 B13 B16 B7 C3 C6 D5 D9 F11 F13 T15 F16 CABGA K13 L3 M10 T7 K10 L13 M13 T9 F2 F5 G16 H11 H16 J15 J2 K16 K3 T2 L14 L16 L7 M4 N15 N4 N6 P11 R9 R10 R15 T8 LQ144 90 18 37 54 73 108 128 144 o eM 55 64 71 91 100 110 118 127 Note 1 For power rail support for product migration to lower power devices refer to the Designing in Split Power Supply Support for AT94KAL AX and AT94SAL AX Devices application note doc2308 pdf available on the Atmel web site at http www atmel com dyn products app_notes asp family_id 627 Thermal Coefficient Table Theta J A C W Theta J A C W Theta J A C W Package Style Lead Count 0 LFPM 225 LFPM 500 LPFM CABGA 256 27 23 20 LQFP 144 35 2314D FPSLI 2 04 AMEL 27 AMEL Ordering Information
25. o licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products expressly or by implication Atmel s products are not authorized for use as critical components in life support devices or systems Atmel Corporation 2004 All rights reserved Atmel and combinations thereof AVR and Cache Logic are the registered trademarks and FPSLIC Secure FPSLIC FreeRAM System Designer and megaAVR are the trademarks of Atmel Corporation or its subsidiaries Other terms and product names may be the trademarks of others Printed on recycled paper 2314D FPSLI 2 04 xM
26. oooooooooooooooolR A1 0 31 0 36 0 41 kom lc dl T A2 0 29 0 34 0 39 n A3 0 65 0 70 0 75 1 00 REF He en e 1 00 B Bottom View 256 SOLDER BALLS b 0 46 REF 2314D FPSLI 2 04 ATMEL Notes 1 This drawing is for general information only Refer to JEDEC Drawing MO 205 for proper dimensions tolerances datums etc 2 Array as seen from the bottom of the package 11 07 01 TITLE DRAWING NO REV MEL 2325 Orchard Parkway 256ZA 256 ball 16 x 16 Array 17 x 17 mm Body AIMEL san Jose CA 95131 Chip Array Ball Grid Array CABGA Package 2 A 29 AMEL 144L1 LQFP EE Bottom View Top View COMMON DIMENSIONS Unit of Measure mm SYMBOL 22 00 BSC SUE 20 00 BSC 22 00 BSC Side View 20 00 BSC 0 50 BSC 0 22 L1 1 00 REF This drawing is for general information only refer to JEDEC Drawing MS 026 for additional information The top package body size may be smaller than the bottom package size by as much as 0 15 mm Dimensions D1 and E1 do not include mold protrusions Allowable protrusion is 0 25 mm per side D1 and E1 are maximum plastic body size dimensions including mold mismatch Dimension b does not include Dambar protr
27. r to the first byte address of the memory array and continue to send data as long as an ACK is sent by the programmer The following programmer functions are supported while the Configurator is in program ming mode i e when SER EN is driven Low 1 Read the Manufacturers Code and the Device Code optional for ISP 2 Program the device 3 Verify the device In the order given above they are performed in the following manner On AT17LV010 Configurator the sequential reading of these bytes are accomplished by performing a Random Read at EEPROM Address 040000H The correct codes are Manufacturers Code Byte 0 1E Device Code Byte 1 F7 AT17LV010 Note The Manufacturer s Code and Device Code are read using the byte ordering specified for Data Bytes i e LSB first MSB last All the bytes in a given page must be written The page access order is not important but it is suggested that the Configurator be written sequentially from address 0 Writing is accomplished by using the cSDA and cSCK pins The first byte of data will not be cached for read back during FPGA Configuration i e when SER EN is driven High until the Configurator is power cycled All bytes in the Configurator should be read and compared to their intended values Reading is done using the cSDA and cSCK pins The AT94S Series Configurators are in system re programmable ISP The example shown on the following page supports the following programmer fun
28. t operation was a read at address n then the current address would be n 1 If the final operation was a write at address n then the current address would again be n 1 with one exception If address n was the last byte address in the page the incremented address n 1 would roll over to the first byte address on the next page CURRENT ADDRESS READ Once the Device Address with the R W select bit set to High is clocked in and acknowledged by the Configurator the Data Byte at the current address is serially clocked out by the Configurator in response to the clock from the pro grammer The programmer generates a Stop Condition to accept the single byte of data and terminate the read instruction A Current Address Read instruction consists of a Start Condition a Device Address with R W 1 An Acknowledge Bit from the Configurator a Data Byte from the Configurator a Stop Condition from the programmer RANDOM READ A Random Read is a Current Address Read preceded by an aborted write instruction The write instruction is only initiated for the purpose of loading the EEPROM Address Bytes Once the Device Address Byte and the EEPROM Address Bytes are clocked in and acknowledged by the Configurator the programmer immedi ately initiates a Current Address Read A Random Address Read instruction consists of a Start Condition a Device Address with R W 0 An Ac MS Byte An Ac of knowledge Bit from t the EEPROM Addre
29. urator enters an inter nally timed write cycle While the Configurator is busy with this write cycle it will not acknowledge any transfers The programmer can start the next page write by sending the Start Condition followed by the Device Address in effect polling the Configurator If this is not acknowledged then the programmer should abandon the transfer without asserting a Stop Condition The programmer can then repeatedly initiate a write instruc tion as above until an acknowledge is received When the Acknowledge Bit is received the write instruction should continue by sending the first EEPROM Address Byte to the Configurator An alternative to write polling would be to wait a period of twp before sending the next page of data or exiting the programming mode All signals must be maintained during the entire write cycle AMEL o Reading 10 AMEL Read instructions are initiated similarly to write instructions However with the R W bit in the Device Address set to one There are three variants of the read instruction current address read random read and sequential read For all reads it is important to understand that the internal Data Byte address counter maintains the last address accessed during the previous read or write operation incre mented by one This address remains valid between operations as long as the chip power is maintained and the device remains in 2 wire access mode i e SER_EN is driven Low If the las
30. usion Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0 08 mm Dambar cannot be located on the lower radius or the foot Minimum space between protrusion and an adjacent lead is 0 07 mm for 0 4 and 0 5 mm pitch packages These dimensions apply to the flat section of the lead between 0 10 mm and 0 25 mm from the lead tip A1 is defined as the distance from the seating place to the lowest point on the package body 11 30 01 TITLE DRAWING NO REV 2325 Orchard Parkvvay 144L1 144 lead 20 x 20 x 1 4 mm Body Low Profile San Jose CA 95131 Plastic Quad Flat Pack LQFP 30 AT94S Secure Family 2314D FPSLI 2 04 AlINEL uu Atmel Corporation 2325 Orchard Parkvvay San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH 1705 Fribourg Switzerland Tel 41 26 426 5555 Fax 41 26 426 5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fax 852 2722 1369 Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Atmel Operations Memory 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 Microcontrollers 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fa
31. w x AT94S Secure Family Table 5 AT94S Pin List Continued Package AT94S05 AT94S10 AT94S40 Chip Array 256 96 FPGA I O 144 FPGA I O 288 FPGA I O CABGA LQ1440 1 059 TD2 1 091 TD2 1 0183 TD2 T16 65 1 060 TD1 1 092 TD1 1 0184 TD1 P14 66 1 0185 1 0186 1 0187 1 0188 1 061 1 093 1 0189 R16 67 1 062 1 094 1 0190 P15 68 1 063 TDO 1 095 TDO 1 0191 TDO N14 69 1 064 GCK4 1 096 GCK4 1 0192 GCK4 P16 70 CON CE CON CE CON CE N16 72 FPSLIC Array RESET RESET RESET M14 74 PEO PEO PEO M12 75 PE1 PE1 PE1 M15 76 PDO PDO PDO M16 77 PD1 PD1 PD1 L12 78 PE2 PE2 PE2 L15 79 PD2 PD2 PD2 L11 80 NC NC NC E12 SER_EN SER_EN SER_EN M5 81 PD3 PD3 PD3 K11 82 PD4 PD4 PD4 K12 83 PE3 PE3 PE3 K14 84 CS0 cso CS0 K15 85 SDA SDA SDA J10 SCL SCL SCL J12 PD5 PD5 PD5 J14 86 PD6 PD6 PD6 J13 87 PE4 PE4 PE4 J16 88 PE5 PE5 PE5 J11 89 PE6 PE6 PE6 H15 92 PE7 CHECK PE7 CHECK PE7 CHECK H14 93 PD7 PD7 PD7 H13 94 2314D FPSLI 2 04 Table 5 AT94S Pin List Continued AMEL Package AT94S05 AT94S10 AT94S40 Chip Array 256 96 FPGA I O 144 FPGA I O 288 FPGA I O CABGA LQ1440 INTPO INTPO INTPO H12 95 XTAL1 XTAL1 XTAL1 G15 96 XTAL2 XTAL2 XTAL2 G14 97 RXO RXO RXO G12 98 TXO TXO TXO G11 99 INTP1 INTP1 INTP
32. x 1 408 436 4314 La Chantrerie BP 70602 44306 Nantes Cedex 3 France Tel 33 2 40 18 18 18 Fax 33 2 40 18 19 60 ASIC ASSP Smart Cards Zone Industrielle 13106 Rousset Cedex France Tel 33 4 42 53 60 00 Fax 33 4 42 53 60 01 1150 East Cheyenne Mtn Blvd Colorado Springs CO 80906 USA Tel 1 719 576 3300 Fax 1 719 540 1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 OQR Scotland Tel 44 1355 803 000 Fax 44 1355 242 743 RF Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn Germany Tel 49 71 31 67 0 Fax 49 71 31 67 2340 1150 East Cheyenne Min Blvd Colorado Springs CO 80906 USA Tel 1 719 576 3300 Fax 1 719 540 1759 Biometrics Imaging Hi Rel MPU High Speed Converters RF Datacom Avenue de Rochepleine BP 123 38521 Saint Egreve Cedex France Tel 33 4 76 58 30 00 Fax 33 4 76 58 34 80 Literature Requests www atmel com literature Disclaimer Atmel Corporation makes no warranty for the use of its products other than those expressly contained in the Company s standard warranty which is detailed in Atmel s Terms and Conditions located on the Company s web site The Company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein N
33. zi8gAT94S10A LE2SBQC ELVIS Features Multichip Module Containing Field Programmable System Level Integrated Circuit FPSLIC and Secure Configuration EEPROM Memory 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In System Programming ISP Field Programmable System Level Integrated Circuit FPSLIC AT40K SRAM based FPGA with Embedded High performance RISC AVR Core and Extensive Data and Instruction SRAM 5 000 to 40 000 Gates of Patented SRAM based AT40K FPGA with FreeRAM 2 18 4 Kbits of Distributed Single Dual Port FPGA User SRAM High performance DSP Optimized FPGA Core Cell Dynamically Reconfigurable In System FPGA Configuration Access Available On chip from AVR Microcontroller Core to Support Cache Logic Designs Very Low Static and Dynamic Power Consumption Ideal for Portable and Handheld Applications Patented AVR Enhanced RISC Architecture 120 Powerful Instructions Most Single Clock Cycle Execution High performance Hardware Multiplier for DSP based Systems Approaching 1 MIPS per MHz Performance C Code Optimized Architecture with 32 x 8 General purpose Internal Registers Low power Idle Power save and Power down Modes 100 pA Standby and Typical 2 3 mA per MHz Active Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM Up to 16 Kbytes x 8 Internal 15 ns Data SRAM JTAG IEEE Std
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ATMEL AT94S Secure Series Programmable SLI handbook