ANALOG DEVICES AD5623R/AD5643R/AD5663R English products handbook Rev E
Contents
1. ao o tc tc tc u FULL SCALE E 20 40 60 80 100 120 8 TEMPERATURE C 40 20 0 20 40 60 80 100 3 TEMPERATURE C 8 Figure 22 INL Error and DNL Error vs Temperature Figure 25 Gain Error and Full Scale Error vs Temperature ZERO SCALE ERROR s gt g 5 05 Ei 1 0 1 5 FFSET ERRO 8 2 0 0 75 1 25 175 225 2 75 3 25 3 75 425 4 75 pd V 100 TEMPERATURE am 8 Figure 23 INL Error and DNL Error vs V gt g Figure 26 Zero Scale Error and Offset Error vs Temperature MAX INL DNL gt LL SCALE ERROR E MIN DNL tc tc MIN INL 2 7 3 2 3 7 4 2 4 7 5 2 s 2 1s T a Vpp V a 2 3 Vpp V 8 Figure 24 INL Error and DNL Error vs Supply 1 Figure 27 Gain Error and Full Scale Error vs Supply Rev E Page 13 of 32 AD5623R AD5643R AD5663R DAC LOADED WITH DAC LOADED WITH i FULL SCALE ZERO SCALE ZERO SCALE ERROR SOURCING CURRENT SINKING CURRENT 3V 1 25V tc gt u tc tr FSET ERROR 27 3 2 3 7 4 2 4 7 5 2 3 740 8 6 4 2 Q0 2 14 6 8 10 Vpp V 8 CURRENT mA 8 Figure 28 Zero Sca2. 10 1 0 Vpp 3V 3V 8 Vegrour 1 25V 0 8 1 25V 25 C i 25 C 6 0 6 4 2 0 4 a m a 2 I 02 gt x 9 ol Q o tr tr u ul a 02 z z 4 0 4 Wi 6 I 0 6 8 hat 0 8 10 1 0 0 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 5 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE 8 CODE 8 Figure 16 INL AD5663R 3 Figure 19 DNL AD5663R 3 0 5 Vpp 3V 3V Vrerout 1 25V 0 4 VREFOUT 1 25V 25 C Ta 25 C 0 3 _ 0 2 a m 4 tc 9 0 tc a a 04 1 u TA 2 2 a 0 2 0 3 0 4 05 85 CODE 8 CODE 5 Figure 17 INL AD5643R 3 Figure 20 DNL AD5643R 3 1 0 0 20 Vpp 3V 0 8 VREFour 1 25 0 15 VREFour 1 25V 25 C 0 6 0 10 0 4 8 8 o2 2 0 05 tc 9 Q o g 0 2 2 0 05 0 4 a 0 10 0 6 0 8 015 1 0 0 20 2 0k CODE Figure 18 INL AD5623R 3 2 5k 3 0k 3 5k 4 0k 05858 019 Rev E Page 12 of 32 2 0k CODE Figure 21 DNL AD5623R 3 05858 022 AD5623R AD5643R AD5663R
3. 0 4 11 17 T 0 6 0 8 2 1 0 x 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 5 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 5 CODE 8 CODE 8 Figure 10 INL AD5663R 5 Figure 13 DNL AD5663R 5 0 5 5V 5V Vaerour 2 5V 0 4 Vrerour 2 5V Ta 25 C Ta 25 C 0 3 _ 0 2 T 7 a d 041 c tc 0 tr ui zi 0 1 1 z 0 2 0 3 0 4 0 5 o e e o e e e e e e e i wo wo d N N e N wo N N e N M e N N N T 92 FEB T Cen mo Um oom gt CODE 8 8 Figure 11 INL AD5643R 5 0 20 Vpp 5V Vpp 5V VreFout 2 5V 0 15 2 5V Ta 25 C 25 C 0 10 m m o a 0 05 0 Li EI z 2 0 05 0 10 0 15 2 0 20 0 0 5k 1 0k 1 5k 20k 2 5k 3 0k 3 5k 4 0k 0 0 5k 1 0k 1 5k 20k 25k 30k 35k 4 0k CODE 8 CODE 8 Figure 12 INL AD5623R 5 Figure 15 DNL AD5623R 5 Rev E Page 11 of 32 AD5623R AD5643R AD5663R
4. The outputs of all DACs can be simultaneously updated using the hardware LDAC pin Synchronous LDAC The DAC registers are updated after new data is read in on the falling edge of the 24th SCLK pulse LDAC can be permanently low or pulsed as shown in Figure 2 The outputs are not updated at the same time that the input registers are written to When LDAC goes low the DAC registers are updated with the contents of the input register The LDAC register gives the user full flexibility and control over the hardware LDAC pin This register allows the user to select which combination of channels to simultaneously update when the hardware LDAC pin is executed Setting the LDAC bit register to 0 for a DAC channel means that the update of this channel is controlled by the LDAC pin If this bit is set to 1 this channel synchronously updates that is the DAC register is updated after new data is read in regardless of the state of the LDAC pin It effectively sees the LDAC pin as being pulled low See Table 15 for the LDAC register mode of operation This flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating Writing to the DAC using Command 110 loads the 2 bit LDAC register DB1 DBO The default for each channel is 0 that is the LDAC pin works normally Setting the bits to 1 means the DAC register is updated
5. to 105 C 2 LSB INL 2 5V 10 Lead LFCSP WD CP 10 9 DKB AD5623RARMZ 5REEL7 40 to 105 C 2 LSB INL 2 5V 10 Lead MSOP RM 10 DKP AD5623RARMZ 5 40 to 105 C 2 LSB INL 2 5V 10 Lead MSOP RM 10 DKP AD5643RBRMZ 3 40 105 C 4 LSB INL 1 25V 10 Lead MSOP RM 10 D81 AD5643RBRMZ 3REEL7 40 to 105 C 4 LSB INL 1 25V 10 Lead MSOP RM 10 D81 AD5643RBRMZ 5 40 to 105 C 4 LSB INL 2 5V 10 Lead MSOP RM 10 D7Q AD5643RBRMZ 5REEL7 40 to 105 C 4 LSB INL 2 5V 10 Lead MSOP RM 10 D7Q AD5663RBCPZ 3R2 40 to 105 C 16 LSB INL 1 25V 10 Lead LFCSP_WD CP 10 9 D7S AD5663RBCPZ 3REEL7 40 C to 105 C 16 LSB INL 1 25V 10 Lead LFCSP_WD CP 10 9 D7S AD5663RBCPZ 5REEL7 40 105 C 16 LSB INL 2 5V 10 Lead LFCSP WD CP 10 9 D7H AD5663RBRMZ 3 40 to 105 C 16 LSB INL 1 25V 10 Lead MSOP RM 10 D7S AD5663RBRMZ 3REEL7 40 to 105 C 16 LSB INL 1 25V 10 Lead MSOP RM 10 D7S AD5663RBRMZ 5 40 to 105 C 16 LSB INL 2 5V 10 Lead MSOP RM 10 D7H AD5663RBRMZ 5REEL7 40 to 105 C 16 LSB INL 2 5V 10 Lead MSOP RM 10 D7H EVAL AD5663REBZ Evaluation Board 17 RoHS Compliant Part Rev E Page 29 of 32 AD5623R AD5643R AD5663R NOTES Rev E Page 30 of 32 AD5623R AD5643R AD5663R NOTES Rev E Page 31 of 32 AD5623R AD5643R AD5663R NOTES 2006 2012 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their
6. temperature is shown in Figure 25 Gain Error Gain error is a measure of the span error of the DAC It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full scale range Zero Scale Error Drift Zero scale error drift is the measurement of the change in zero scale error with a change in temperature It is expressed in microvolts C uV C Gain Temperature Coefficient Gain temperature coefficient is a measurement of the change in gain error with changes in temperature It is expressed in ppm of full scale range C Offset Error Offset error is a measure of the difference between Vour actual and Vovr ideal expressed in mV in the linear region of the transfer function Offset error is measured on the AD56x3R with code 512 loaded in the DAC register It can be negative or positive DC Power Supply Rejection Ratio PSRR PSRR indicates how the output of the DAC is affected by changes in the supply voltage PSRR is the ratio of the change in VOUT to a change in VDD for full scale output of the DAC It is measured in dB VREF is held at 2 V and VDD is varied by 10 Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a 1 4 to 3 4 full scale input change and is measured from the 24th falling edge of SCLK Digital to Analog Glitch Impulse The impulse injected into the ana
7. The total current required with a 5 kO load on the DAC output is 500 pA 5 V 5 1 25 mA The load regulation of the REF195 is typically 2 ppm mA which results in a 3 ppm 15 uV error for the 1 5 mA current drawn from it This corresponds to a 0 196 LSB error 15V REF195 SYNC O VoD THREE WIRE AD5623R Vout OV TO 5V QO AD5643R O SERIAL SCLK O INTERFACE DINO 05858 041 Figure 60 REF195 as Power Supply to the AD5623R AD5643R AD5663R BIPOLAR OPERATION USING THE AD5663R The AD5663R has been designed for single supply operation but a bipolar output range is also possible using the circuit in Figure 61 The circuit gives an output voltage range of 5 V Rail to rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier The output voltage for any input code can be calculated as follows D R1 R2 R2 V Von X E gt RI 2 where D represents the input code in decimal 0 to 65 535 With Vpp 5 V RI R22 10 10x D Vo 5 65 536 This is an output voltage range of 5 V with 0x0000 corre sponding to a 5 V output and OxFFFF corresponding to a 5 V output R2 10kQ 45V AD820 OP295 5V THREE WIRE SERIAL INTERFACE 05858 042 Figure 61 Bipolar Operation with the AD5663R USING THE AD5663R WITH A GALVANICALLY ISOLATED INTERFACE In process control application
8. Vin Voo and GND Temperature range B grade 40 C to 105 C Linearity calculated using a reduced code range AD5663R Code 512 to Code 65 024 AD5643R Code 128 to Code 16 256 and AD5623R Code 32 to Code 4064 Output unloaded 3 Guaranteed by design and characterization not production tested 4 Interface inactive All DACs active DAC outputs unloaded 5 Both DACs powered down AC CHARACTERISTICS 2 7 V to 5 5 V Ri 2 to GND C 200 pF to GND Vrer Vos all specifications Tum to Tmax unless otherwise noted Table 4 Parameter Output Voltage Settling Time AD5623R AD5643R AD5663R Slew Rate Digital to Analog Glitch Impulse Digital Feedthrough Reference Feedthrough Digital Crosstalk Analog Crosstalk DAC to DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise Min Typ 100 15 Max Unit dB nV 4Hz nV 4Hz MV Conditions Comments 1 4 to 34 scale settling to 0 5 LSB 1 4 to 34 scale settling to 0 5 LSB 1 4 to 3 4 scale settling to 2 LSB 1 LSB change around major carry Vre 2V 0 1 V frequency 10 Hz to 20 MHz External reference Internal reference External reference Internal reference Veer 2V 0 1 V Vre 2 V 0 1 V frequency 10 kHz DAC code midscale 1 kHz DAC code midscale 10 kHz 0 1 Hz to 10 Hz 1 Guaranteed
9. regardless of the state of the LDAC pin See Table 14 for contents of the input shift register during the LDAC register setup command Table 15 LDAC Register Mode of Operation LDAC Bits DB1 to DBO 0 1 Rev E Page 23 of 32 LDAC Pin 1 0 x don t care LDAC Operation Determined by LDAC pin The DAC registers are updated after new data is read in on the falling edge of the 24th SCLK pulse AD5623R AD5643R AD5663R INTERNAL REFERENCE SETUP Table 16 Reference Setup Register Internal Reference The on chip reference is off at power up by default This i Setup Register DB0 reference can be turned on or off by setting a software Action programmahble bit DB0 in the control register Table 16 shows 0 how the state of the bit corresponds to the mode of operation 1 Reference off default Reference on Command 111 is reserved for setting up the internal reference see Table 8 See Table 16 for the contents of the input shift register during the internal reference setup command Table 17 32 Bit Input Shift Register Contents for Reference Setup Function MSB LSB DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15toDB1 DBO x 1 1 1 x x x x 1 0 Don t care Command bits C2 to CO Address bits A2 to AO Don t care Reference setup register Rev E Page 24 of 32 AD5623R AD5643R AD5663R MICROPROCESSOR INTERFACING AD5623R AD5
10. Figure 47 Multiplying Bandwidth Rev E Page 17 of 32 AD5623R AD5643R AD5663R TERMINOLOGY Relative Accuracy or Integral Nonlinearity INL For the DAC relative accuracy or integral nonlinearity is a measurement of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function A typical INL vs code plot is shown in Figure 5 Differential Nonlinearity DNL Differential nonlinearity DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB maximum ensures monotonicity This DAC is guaranteed monotonic by design A typical DNL vs code plot is shown in Figure 9 Zero Scale Error Zero scale error is the measurement of the output error when zero code 0x0000 is loaded to the DAC register Ideally the output should be 0 V The zero scale error is always positive in the AD56x3R because the output of the DAC cannot go below 0 V It is due to a combination of the offset errors in the DAC and the output amplifier Zero scale error is expressed in mV A plot of zero scale error vs temperature is shown in Figure 26 Full Scale Error Full scale error is the measurement of the output error when full scale code OxFFFF is loaded into the DAC register Ideally the output should be Vr 1 LSB Full scale error is expressed in percent of full scale range A plot of full scale error vs
11. by design and characterization not production tested 2 See the Terminology section 3 Temperature range A B grade 40 to 105 typical at 25 C Rev E Page 6 of 32 AD5623R AD5643R AD5663R TIMING CHARACTERISTICS All input signals are specified with tr tr 1 ns V 10 to 90 of Vp and timed from a voltage level of Viu 2 2 7 V to 5 5 V all specifications Tmn to Tmax unless otherwise noted Table 5 Limit at Twin Tmax Parameter Von 2 7 V to 5 5 V Unit Conditions Comments ti 20 ns min SCLK cycle time t 9 ns min SCLK high time ts 9 ns min SCLK low time ta 13 ns min SYNC to SCLK falling edge setup time ts 5 ns min Data setup time t 5 ns min Data hold time t 0 ns min SCLK falling edge to SYNC rising edge ts 15 ns min Minimum SYNC high time to 13 ns min SYNC rising edge to SCLK fall ignore tio 0 ns min SCLK falling edge to SYNC fall ignore tu 10 ns min LDAC pulse width low t 15 ns min SCLK falling edge to LDAC rising edge tis 5 ns min CLR pulse width low tua 0 ns min SCLK falling edge to LDAC falling edge ts 300 ns max CLR pulse activation time 1 Guaranteed by design and characterization not production tested 2 Maximum SCLK frequency is 50 MHz at Voo 2 7 V to 5 5 V TIMING DIAGRAM SCLK SYNC DIN LDAC LDAC GL lt gt Vour 5 1ASYNCHRONOUS UPDATE MODE NS 2SYNCHRONOUS LDAC UPDATE MODE 05858 002 Figur
12. clocks The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC 7 SCLK Serial Clock Input Data is clocked into the input shift register on the falling edge of the serial clock input Data can be transferred at rates up to 50 MHz 8 DIN Serial Data Input This device has a 24 bit shift register Data is clocked into the register on the falling edge of the serial clock input 9 Power Supply Input These parts can be operated from 2 7 V to 5 5 V and the supply should decoupled with 10 pF capacitor in parallel with a 0 1 uF capacitor to GND 10 Vrerin Vrerour Common Reference Input Reference Output When the internal reference is selected this is the reference output pin When using an external reference this is the reference input pin The default for this pin is a reference input Rev E Page 9 of 32 AD5623R AD5643R AD5663R TYPICAL PERFORMANCE CHARACTERISTICS INL ERROR LSB INL ERROR LSB INL ERROR LSB Vpp 5V 25 C t o tc tc tc ul al z a 10 8 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 2 CODE Figure 4 INL AD5663R External Reference 4 Vpp 5V 25 C 3 2 a 1 c 0 2 t
13. the MSB first The 80C51 80L51 transmit routine should take this into account AD5643R AD5663R 80C51 80L511 05858 039 ADDITIONAL PINS OMITTED FOR CLARITY Figure 58 AD5623R AD5643R AD5663R to 80C512 80L51 Interface AD5623R AD5643R AD5663R to MICROWIRE Interface Figure 59 shows an interface between the AD5623R AD5643R AD5663R and any MICROWIRE compatible device Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5623R AD5643R AD5663R on the rising edge of the SK AD5643R AD5663R MICROWIRE1 TADDITIONAL PINS OMITTED FOR CLARITY Figure 59 AD5623R AD5643R AD5663R to MICROWIRE Interface 05858 040 Rev E Page 25 of 32 AD5623R AD5643R AD5663R APPLICATIONS INFORMATION USING A REFERENCE AS A POWER SUPPLY Because the supply current required by the AD5623R AD5643R AD5663R is extremely low an alternative option is to use a voltage reference to supply the required voltage to the parts see Figure 60 This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V or 3 V for example 15 V The voltage reference outputs a steady supply voltage for the AD5623R AD5643R AD5663R If the low dropout REF195 is used it must supply 500 of current to the AD5623R AD5643R AD5663R with no load on the output of the DAC When the DAC output is loaded the REF195 also needs to supply the current to the load
14. 0 150 200 250 300 350 400 450 51 SAMPLE NUMBER 05858 060 TIME BASE 4ys DIV Figure 35 Full Scale Settling Time 5 V Figure 38 Digital to Analog Glitch Impulse Negative 2 498 Vpp Vrer 5V 25 C 2 497 5ns SAMPLE NUMBER ANALOG CROSSTALK 0 424nV 2 496 2495 o gt 2 494 2 493 2 492 2 5 2 491 B CH1 2 0V CH2 500mV MiO0us 125MS s 8 0ns pt 0 50 100 150 200 250 300 350 400 450 512 A CH1 1 28V 8 SAMPLE NUMBER Figure 36 Power On Reset to 0 V Figure 39 Analog Crosstalk External Reference Rev E Page 15 of 32 AD5623R AD5643R AD5663R 2 496 2 494 j j i 2 492 Vpp 3V 2 490 Vaerour 1 25V 2 488 25 C 2486 DAC LOADED WITH MIDSCALE 2 484 2 482 _ 2 480 2 478 5 2 476 a 2 474 5 gt 2 472 5 2 470 HH HH 2 468 f I Vrerour 25V 2 462 Ta 25 C 2 460 5ns SAMPLE N
15. 5 for AD5663R 16 bit Nis the DAC resolution RESISTOR STRING The resistor string section is shown in Figure 50 It is simply a string of resistors each of Value R The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier The voltage is tapped off by closing one of the switches connecting the string to the amplifier Because it is a string of resistors it is guaranteed monotonic OUTPUT AMPLIFIER The output buffer amplifier can generate rail to rail voltages on its output which gives an output range of 0 V to Vor It can drive a load of 2 in parallel with 1000 pF to GND The source and sink capabilities of the output amplifier can be seen in Figure 31 The slew rate is 1 8 V us with a 1 4 to 3 4 full scale settling time of 10 us where R R R TO OUTPUT AMPLIFIER I I I I I 1 1 1 1 1 R R 05858 033 Figure 50 Resistor String INTERNAL REFERENCE The AD5623R AD5643R AD5663R on chip reference is off at power up and is enabled via a write to a control register See the Internal Reference Setup section for details The AD56x3R 3 has a 1 25 V 5 ppm C reference giving a full scale output of 2 5 V The AD56x3R 5 has a 2 5 V 5 ppm C reference giving a full scale output of 5 V The internal refer ence associated with each part is available at the Vrerour pin A buffer is required if the reference output is used to drive externa
16. 643R AD5663R to Blackfin ADSP BF53X Interface Figure 56 shows a serial interface between the AD5623R AD5643R AD5663R and the Blackfin ADSP BF53X micro processor The ADSP BF53X processor family incorporates two dual channel synchronous serial ports SPORT1 and SPORTO for serial and multiprocessor communications Using SPORTO to connect to the AD5623R AD5643R AD5663R the setup for the interface is as follows DTOPRI drives the DIN pin of the AD5623R AD5643R AD5663R while TSCLKO drives the SCLK of the parts The SYNC is driven from TFSO AD5643R AD5663R ADSP BF53x1 ADDITIONAL PINS OMITTED FOR CLARITY Figure 56 AD5623R AD5643R AD5663R to Blackfin ADSP BF53X Interface 05858 037 AD5623R AD5643R AD5663R to 68HC1 1 68L11 Interface Figure 57 shows a serial interface between the AD5623R AD5643R AD5663R and the 68HC11 68L11 microcontroller SCK of the 68HC11 68L11 drives the SCLK of the AD5623R AD5643R AD5663R and the MOSI output drives the serial data line of the DAC AD5643R AD5663R 68 11 681111 05858 038 TADDITIONAL PINS OMITTED FOR CLARITY Figure 57 AD5623R AD5643R AD5663R to 68HC11 68L11 Interface The SYNC signal is derived from a port line PC7 The setup conditions for correct operation of this interface are as follows the 68HC11 68L11 is configured with its CPOL bit as 0 and its CPHA bit as 1 When data is being transmitted to the DAC the SYNC line is taken low PC7 When the 68HC11 68L11
17. ANALOG DEVICES FEATURES Low power smallest pin compatible dual nanoDAC AD5663R 16 bits AD5643R 14 bits AD5623R 12 bits User selectable external or internal reference External reference default On chip 1 25 V 2 5 V 5 ppm C reference 10 lead MSOP and 3 mm x 3 mm LFCSP 2 7V to 5 5 V power supply Guaranteed monotonic by design Power on reset to zero scale Per channel power down Serial interface up to 50 MHz Hardware LDAC and CLR functions APPLICATIONS Process control Data acquisition systems Portable battery powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5623R AD5643R AD5663R members of the nanoDAC family are low power dual 12 14 and 16 bit buffered voltage out digital to analog converters DAC that operate from a single 2 7 V to 5 5 V supply and are guaranteed monotonic by design The AD5623R AD5643R AD5663R have an on chip reference The AD5623R 3 AD5643R 3 AD5663R 3 have a 1 25 V 5 ppm C reference giving a full scale output of 2 5 V and the AD5623R 5 AD5643R 5 AD5663R 5 have 2 5 V 5 ppm C reference giving a full scale output of 5 V The on chip reference is off at power up allowing the use of an external reference and all devices can be operated from a single 2 7 V to 5 5 V supply The internal reference is turned on by writing to the DAC The parts incorporate a power on reset circuit tha
18. External Reference 10 uV Due to full scale output change RL 2 to GND or Voo 10 HV mA Due to load current change 5 uV Due to powering down per channel DC Crosstalk Internal Reference 25 uV Due to full scale output change 2 to GND or Voo 20 HV mA Due to load current change 10 uV Due to powering down per channel OUTPUT CHARACTERISTICS Output Voltage Range 0 Vop V Capacitive Load Stability 2 nF 10 nF RL 2kO DC Output Impedance 0 5 Short Circuit Current 30 mA Vpp 3V Power Up Time 4 us Coming out of power down mode Voo 3 V REFERENCE INPUTS Reference Current 170 200 HA Veer 3 6 V Reference Input Range 0 75 Vop V Reference Input Impedance 26 Output Voltage 1 247 1 253 V At ambient Reference Temperature Coefficient 5 15 ppm C MSOP package models 10 ppm C LFCSP package models Output Impedance 7 5 kQ Rev E Page 5 of 32 AD5623R AD5643R AD5663R B Grade Parameter Min Typ Max Unit Conditions Comments LOGIC INPUTS Input Current 2 HA All digital inputs Vint Input Low Voltage 0 8 V Vop 3V Input High Voltage 2 V Vpp 3V Pin Capacitance 3 pF DIN SCLK and SYNC 19 pF LDAC and CLR POWER REQUIREMENTS Von 2 7 3 6 V loo Normal Mode Vin Voo and Vi GND Voo 2 7 V to 3 6V 200 425 HA Internal reference off Vpp 2 7V to 3 6V 800 900 HA Internal reference on All Power Down Modes Vpp 2 7V to 3 6V 0 2 1
19. ON OF 0 75 0 05 MAX THE EXPOSED PAD REFER TO 0 02 NOM THE PIN CONFIGURATION AND 0 70 LY FUNCTION DESCRIPTIONS H H H 1 COPLANARITY SECTION OF THIS DATA SHEET SEATING _ 0 30 0 08 PLANE 0 25 0 20 REF 0 20 Figure 63 10 Lead Lead Frame Chip Scale Package LFCSP WD 3mm x 3 mm Body Very Very Thin Dual Lead CP 10 9 Dimensions shown in millimeters 3 10 3 00 2 90 PIN 1 IDENTIFIER 0 95 15 MAX 0 85 T 075 L 0 70 0 15 _ 0 30 6 4 0 23 0 55 0 05 wl 945 P 0 1 0 40 COPLANARITY 0 15 0 10 091709 A COMPLIANT TO JEDEC STANDARDS MO 187 BA Figure 64 10 Lead Mini Small Outline Package MSOP RM 10 Dimensions shown in millimeters Rev E Page 28 of 32 02 27 2012 B AD5623R AD5643R AD5663R ORDERING GUIDE Internal Package Model Temperature Range Accuracy Reference Package Description Option Branding AD5623RBCPZ 3R2 40 C to 105 C 1 LSB INL 1 25V 10 Lead LFCSP WD CP 10 9 D85 AD5623RBCPZ 3REEL7 40 to 105 C 1 LSB INL 1 25V 10 Lead LFCSP_WD CP 10 9 D85 AD5623RBCPZ 5REEL7 40 to 105 C 1 LSB INL 2 5V 10 Lead LFCSP WD CP 10 9 D86 AD5623RBRMZ 3 40 to 105 C 1 LSB INL 1 25V 10 Lead MSOP RM 10 D85 AD5623RBRMZ 3REEL7 40 to 105 C 1 LSB INL 1 25V 10 Lead MSOP RM 10 D85 AD5623RBRMZ 5 40 to 105 C 1 LSB INL 2 5V 10 Lead MSOP RM 10 D86 AD5623RBRMZ 5REEL7 40 to 105 C 1 LSB INL 2 5V 10 Lead MSOP RM 10 D86 AD5623RACPZ 5REEL7 40
20. UMBER ANALOG CROSSTALK 4 462nV 0 50 100 150 200 250 300 350 400 450 512 5 SAMPLE NUMBER 4s DIV 8 Figure 40 Analog Crosstalk Internal Reference Figure 43 0 1 Hz to 10 Hz Output Noise Plot Internal Reference 800 Ta 25 C MIDSCALE LOADED Vpp Vrer 5V Ta 25 C DAC LOADED WITH MIDSCALE 500 1 50 ul 9 400 2 EP 2 2 o I g 0 s 100 1k 10k 1M 10 2 P 8 FREQUENCY Hz 8 Figure 41 0 1 Hz to 10 Hz Output Noise Plot External Reference Figure 44 Noise Spectral Density Internal Reference 20 Vpp 5V 5 v 30 TA 25 C REFOUT 2 DAC LOADED WITH FULL SCALE Ta 25 C Vi 2V 0 3V DAC LOADED WITH MIDSCALE 40 REF n 50 2 a 8 60 e 70 80 1 90 z 100 5 3 2k 4k 6k 8k 10k 5 5s DIV 8 FREQUENCY Hz 8 Figure 42 0 1 Hz to 10 Hz Output Noise Plot Internal Reference Figure 45 Total Harmonic Distortion Rev E Page 16 of 32 AD5623R AD5643R AD5663R TIME us 05858 050 1 0V M200ns 1 10V CH3 5 0V CH4 1 0V 05858 068 nF Figure 46 Settling Time vs Capacitive Load Figure 48 CLR Pulse Activation Time Vpp 5V Ta 25 C dB 10k 100k 1M 10M FREQUENCY Hz 05858 069
21. at operates at clock rates up to 50 MHz and they are compatible with standard SPI QSPI MICROWIRE and DSP interface standards The on chip precision output amplifier enables rail to rail output swing to be achieved PRODUCT HIGHLIGHTS 1 Dual 12 14 and 16 bit DAC 2 On chip 1 25 V 2 5 V 5 ppm C reference 3 Available in 10 lead MSOP and 10 lead 3 mm x 3 mm LFCSP 4 Low power typically consumes 0 6 mW at 3 V and 1 25 mW at 5 V 5 4 5 us maximum settling time for the AD5623R One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 2012 Analog Devices Inc All rights reserved AD5623R AD5643R AD5663R TABLE OF CONTENTS Features ss 1 Applications sossa 1 Functional Block Diagram 1 General Description 1 Product Hiehlights tette te emi etis 1 R vision History Sayaq nie 2 E 3 5623 5 5643 5 5663 5 3 5623 3 5643 3 5663 3 5 AC Characteristics ay yuq ep ee ot e e p eater 6 Timing Characteristics 7 Timing a terrier 7 Absolute Maximum Ratings seen 8 eet sasssa 8 Pin Configuration and Function 9 Typical Performance Characteristics 10 Terminology TR ite i
22. by setting Bit DB5 and Bit DB4 to normal operation mode Again to select which combination of DAC channels to power up set the corresponding bits Bit DB1 and Bit DBO to 1 See Table 13 for contents of the input shift register during power down power up operation The DAC output powers up to the value in the input register while LDAC is low If LDAC is high the DAC ouput powers up to the value held in the DAC register before power down Table 11 Modes of Operation DB5 DB4 Operating Mode 0 0 Normal operation Power down modes 0 1 1 kO to GND 1 0 100 kO to GND 1 1 Three state When both Bit DB1 and Bit DB2 are set to 0 the part works normally with its normal power consumption of 250 at 5 V However for the three power down modes the supply current falls to 480 nA at 5 V 200 nA at 3 V Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values This has the advantage that the output impedance of the part is known while the part is in power down mode The outputs can either be connected internally to GND through a 1 or 100 resistor or left open circuited three state see Figure 55 RESISTOR STRING DAC O Vour POWER DOWN CIRCUITRY RESISTOR NETWORK Figure 55 Output Stage During Power Down 05858 036 The bias generator the output amplifier the resistor string and o
23. c ul E a 2 0 2 5k 5 0k 7 5 10 0k 12 5k 15 0k 05858 006 CODE Figure 5 INL AD5643R External Reference Vpp 5V Ta 25 C DNL ERROR LSB 0 0 5k 1 0k 1 5k 20k 25k 30k 3 5k 4 0k CODE Figure 6 INL AD5623R External Reference 05858 007 Rev E Page 10 of 32 parum lu ult MULT 0 10k 20k 30k 40k 50k 60k CODE Figure 7 DNL AD5663R External Reference Von 5V 0 2 5 5 0k 7 5 10 0k 12 5k 15 0k CODE Figure 8 DNL AD5643R External Reference Vpp 5V 25 C 0 0 5k 1 0k 1 5k 20k 25k 3 0k 35k 4 0k CODE Figure 9 DNL AD5623R External Reference 05858 008 05858 009 05858 010 AD5623R AD5643R AD5663R 1 0 Vpp 5V Von 5V VnEFOUT 2 5V 0 8 2 5V Ta 25 C Ta 25 C 0 6 _ 04 m a 2 a 0 2 gt 5 tt oc 0 tc tc ui 5 0 2 77 2
24. double buffered interfaces consisting of two banks of registers input registers and DAC registers The input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence The DAC registers contain the digital code used by the resistor strings Access to the DAC registers is controlled by the LDAC pin When the LDAC pin is high the DAC registers are latched and the input registers can change state without affecting the contents of the DAC registers When LDAC is brought low however the DAC registers become transparent and the contents of the input registers are transferred to them The double buffered interface is useful if the user requires simultaneous updating of all DAC outputs The user can write to one of the input registers individually and then by bringing LDAC low when writing to the other DAC input register all outputs will update simultaneously These parts each contain an extra feature whereby a DAC register is not updated unless its input register has been updated since the last time LDAC was brought low Normally when LDAC is brought low the DAC registers are filled with the contents of the input registers In the case of the AD5623R AD5643R AD5663R the DAC register updates only if the input register has changed since the last time the DAC register was updated thereby removing unnecessary digital crosstalk
25. e Because the SYNC buffer draws more current when Vis 2 V than it does when Vis 0 8 V SYNC should be idled low between write sequences for even lower power operation As mentioned previously it must however be brought high again just before the next write sequence INPUT SHIFT REGISTER The input shift register is 24 bits wide see Figure 52 The first two bits are dont cares The next three are Command Bit C2 to Command Bit CO see Table 8 followed by the 3 bit DAC Address A2 to DAC Address 0 see Table 9 and finally the 16 14 and 12 bit data word The data word comprises the 16 14 and 12 bit input codes followed by zero two or four don t care bits for the AD5663R AD5643R and AD5623R respectively see Figure 51 Figure 52 and Figure 53 The data bits are transferred to the DAC register on the 24th falling edge of SCLK DB23 MSB AAA AA ae COMMAND BITS ADDRESS BITS Table 8 Command Definition c2 C1 CO Command 0 0 0 Write to Input Register n 0 0 1 Update DAC Register n 0 1 0 Write to Input Register n update all software LDAC 0 1 1 Write to and update DAC Channel n 1 0 0 Power down DAC power up 1 0 1 Reset 1 1 0 LDAC register setup 1 1 1 Internal reference setup on off Table 9 Address Command A2 A1 AO ADDRESS n 0 0 0 DACA 0 0 1 DACB 0 1 0 Reserved 0 1 1 Reserved 1 1 1 All DACs SYNC INTERRUPT In a
26. e 2 Serial Write Operation Rev E Page 7 of 32 AD5623R AD5643R AD5663R ABSOLUTE MAXIMUM RATINGS 25 C unless otherwise noted Table 6 Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device This is a stress Voo to GND 0 3V to 7 V rating only functional operation of the device at these or any Vour to GND 0 3 V to Voo 0 3 V other conditions above those indicated in the operational Vrerin Vrerour to GND 0 3 V to Voo 0 3 V section of this specification is not implied Exposure to absolute Digital Input Voltage to GND 0 3 V to Vop 0 3 V maximum rating conditions for extended periods may affect Operating Temperature Range device reliability Industrial 40 C to 105 C Storage Temperature Range 65 C to 150 C Junction Temperature T max 150 ESD CAUTION Power Dissipation Ts max Ta ja ESD electrostatic discharge sensitive device LFCSP Package 4 Layer Board Charged devices and circuit boards can discharge Thermal Impedance 61 C W 4 without detection Although this product features patented or proprietary protection circuitry damage MSOP Package 4 Layer Board A may occur on devices subjected to high energy ESD Thermal Impedance 142 C W Therefore proper ESD precautions should be taken to Oc Thermal Impedance 43 7C W avoid performance degradation or loss of functionality JC Reflow Soldering Pea
27. eed 3 Changes to Table 3 en eR Ren RID 5 Changes Sis aha tet teet 9 Changes to Ordering 28 4 06 Revision 0 Initial Version Rev E Page 2 of 32 AD5623R AD5643R AD5663R SPECIFICATIONS AD5623R 5 AD5643R 5 AD5663R 5 4 5 V to 5 5 V Ri 2 to GND C 200 pF to GND Vrer Vos all specifications Tum to Tmax unless otherwise noted Table 2 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions Comments STATIC PERFORMANCE AD5663R Resolution 16 Bits Relative Accuracy 8 16 LSB Differential Nonlinearity 1 LSB Guaranteed monotonic by design AD5643R Resolution 14 Bits Relative Accuracy 2 4 LSB Differential Nonlinearity 0 5 LSB Guaranteed monotonic by design AD5623R Resolution 12 Bits Relative Accuracy 1 2 0 5 1 LSB Differential Nonlinearity 1 0 25 LSB Guaranteed monotonic by design Zero Scale Error 2 10 2 10 mV All Os loaded to DAC register Offset Error 1 10 1 10 mV Full Scale Error 0 1 1 0 1 1 of All 1 loaded to DAC register FSR Gain Error 1 5 1 5 of FSR Zero Scale Error Drift 2 2 uV C Gain Temperature Coefficient 2 5 2 5 Of FSR C DC Power Supply Rejection Ratio 100 100 dB DAC code midscale 5 V 10 DC Crosstalk External Reference 10 10 uV Due to full scale output change 2 to GND or Voo 10 10 uV mA Due to load current change 5 5 uV Due to powering down per chan
28. et 18 Theory of Operation erase r tete te iE 20 Digital to Analog Section 20 Resistor String tpe erento reete 20 REVISION HISTORY 4 12 Rev D to Rev C Changes to Table 2 3 Updated Outline Dimensions 28 Changes to Ordering Guide 29 4 11 Rev C to Rev D Changes to Ordering Guide 29 6 10 Rev B to Rev C Changes to Ordering Guide sees 28 Output Amplifier one ARD REIS 20 Internal Reference rire pee re 20 External Reference siss 20 Serial Interface ee E RUE ROO Ea 20 Input Shift Register coe 21 SYNC Titerr pt aus s p ten temer etnia 21 Power On R eset c eie HR 22 Software Reset u u usa He eR Ree REP 22 Power Down Modes 22 LDAC Function 23 Internal Reference Setup 24 Microprocessor Interfacing sse 25 Applications Information 26 Using a Reference as a Power 26 Bipolar Operation Using the 5663 26 Using the AD5663R with a Galvanically Isolated Interface 26 Power Supply Bypassing and Grounding 27 Outline Dimensions 28 Ordering Guide iecit nt rete eiie rans 29 4 10 Rev A to Rev B Updated Outline Dimensions eerte 28 12 06 Rev 0 to Rev A Changes to Table 2 dict nennt thi tae ind
29. hange is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale It is expressed in microvolts milliamps uV mA Rev E Page 18 of 32 AD5623R AD5643R AD5663R Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full scale code change all 05 to all 1s and vice versa in the input register of another DAC It is measured in standalone mode and is expressed in nanovolts second nV s Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC It is measured by loading one of the input registers with a full scale code change all 0s to all 1s and vice versa while keeping LDAC high Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed The area of the glitch is expressed in nanovolts second nV s DAC to DAC Crosstalk DAC to DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC This includes both digital and analog crosstalk It is measured by loading one of the DACs with a full scale code change all 0s to all 1s and vice versa with LDAC low and monitoring the output of another DAC The energy of the glitch is expressed in nanovolts second nV s Multiplying Bandwidth The amplifiers within the DAC
30. have a finite bandwidth The multiplying bandwidth is a measure of this A sine wave on the reference with full scale code loaded to the DAC appears on the output The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input Total Harmonic Distortion THD Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC The sine wave is used as the reference for the DAC and the THD is a measurement of the harmonics present on the DAC output It is measured in decibels dB Rev E Page 19 of 32 AD5623R AD5643R AD5663R THEORY OF OPERATION DIGITAL TO ANALOG SECTION The AD5623R AD5643R AD5663R DAC is fabricated on a CMOS process The architecture consists of a string DAC followed by an output buffer amplifier Figure 49 shows a block diagram of the DAC architecture OUTPUT AMPLIFIER REF GAIN 2 DAC RESISTOR STRING 05858 032 GND Figure 49 DAC Architecture Because the input coding to the DAC is straight binary the ideal output voltage when using an external reference is given by D Vour X The ideal output voltage when using the internal reference is given by V OUT 2xV D REFOUT X 2N D is the decimal equivalent of the binary code that is loaded to the DAC register 0 to 4095 for AD5623R 12 bit 0 to 16 383 for AD5643R 14 bit 0 to 65 53
31. is configured as described previously data appearing on the MOSI output is valid on the falling edge of SCK Serial data from the 68HC11 68L11 is transmitted in 8 bit bytes with only eight falling clock edges occurring in the transmit cycle Data is transmitted MSB first To load data to the AD5623R AD5643R AD5663R PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC PC7 is taken high at the end of this procedure AD5623R AD5643R AD5663R to 80C51 80L51 Interface Figure 58 shows a serial interface between the AD5623R AD5643R AD5663R and the 80C51 80L51 microcontroller The setup for the interface is as follows TxD of the 80C51 80L51 drives SCLK of the AD5623R AD5643R AD5663R and RxD drives the serial data line of the part The SYNC signal is again derived from a bit programmable pin on the port In this case Port Line P3 3 is used When data is to be transmitted to the AD5623R AD5643R AD5663R P3 3 is taken low The 80C51 80L51 transmit data in 8 bit bytes only thus only eight falling clock edges occur in the transmit cycle To load data to the DAC P3 3 is left low after the first eight bits are transmitted and a second write cycle is initiated to transmit the second byte of data P3 3 is taken high following the completion of this cycle The 80C51 80L51 output the serial data in a format that has the LSB first The AD5623R AD5643R AD5663R must receive data with
32. k Temperature Pb Free 260 0 5 C Rev E Page 8 of 32 AD5623R AD5643R AD5663R PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Varg 7 AD5623R v ours AD5643R GND AD5663R 5 DIN NOTE EXPOSED PAD TIED TO GND ON LFCSP PACKAGE 05858 003 Figure 3 Pin Configuration Table 7 Pin Function Descriptions Pin No Mnemonic Description 1 VourA Analog Output Voltage from DAC A The output amplifier has rail to rail operation 2 VourB Analog Output Voltage from DAC B The output amplifier has rail to rail operation 3 GND Ground Reference point for all circuitry on the part 4 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data This allows simultaneous update of all DAC outputs Alternatively this pin can be tied permanently low 5 CLR Asynchronous Clear Input The CLR input is falling edge sensitive While CLR is low all LDAC pulses are ignored When CLR is activated zero scale is loaded to all input and DAC registers This clears the output to 0 V The part exits clear code mode on the 24th falling edge of the next write to the part If CLR is activated during a write sequence the write is aborted 6 SYNC Level Triggered Control Input Active Low This is the frame synchronization signal for the input data When SYNC goes low it enables the input shift register and data is transferred in on the falling edges of the following
33. l loads When using the internal reference it is recommended that a 100 nF capacitor be placed between reference output and GND for reference stability EXTERNAL REFERENCE The Vrenn pins on the AD56x3R 3 and the AD56x3R 5 allows the use of an external reference if the application requires it The on chip reference is off at power up and this is the default condition The AD56x3R 3 and the AD56x3R 5 can be operated from a single 2 7 V to 5 5 V supply SERIAL INTERFACE The AD5623R AD5643R AD5663R have a 3 wire serial interface SYNC SCLK and DIN that is compatible with SPI QSPI and MICROWIRE interface standards as well as with most DSPs See Figure 2 for a timing diagram ofa typical write sequence The write sequence begins by bringing the SYNC line low Data from the DIN line is clocked into the 24 bit shift register on the falling edge of SCLK The serial clock frequency can be as high as 50 MHz making the AD5623R AD5643R AD5663R compatible with high speed DSPs On the 24th falling clock edge the last data bit is clocked in and the programmed function is executed for example a change in DAC register contents and or a change in the mode of operation Rev E Page 20 of 32 AD5623R AD5643R AD5663R At this stage the SYNC line can be kept low or be brought high In either case it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequenc
34. le Error and Offset Error vs Supply Figure 31 Headroom at Rails vs Source and Sink Vpp 5V VREFOUT 2 5V Ta 25 C o E z 2 5 5 t gt 0 230 0 235 0 240 0 245 0 250 0 255 3 30 20 10 0 10 20 30 8 mA 8 CURRENT mA 8 Figure 29 Histogram with External Reference Figure 32 AD56x3R 5 Source and Sink Capability 5 Vpp 3V VrEFour 1 25V Ta 25 C 4 o E z gt gt m 3 gt 2 2 5 1 0 78 0 80 0 82 0 84 30 20 10 0 10 20 30 F Ipp mA 8 CURRENT mA 8 Figure 30 loo Histogram with Internal Reference Figure 33 AD56x3R 3 Source and Sink Capability Rev E Page 14 of 32 AD5623R AD5643R AD5663R VREFIN 7 Ipp mA CH1 5 0V 500mV M400ns 14V 40 20 0 20 40 60 80 100 3 TEMPERATURE C 8 CH3 5 0V 8 Figure 34 Supply Current vs Temperature Figure 37 Exiting Power Down to Midscale Vpp 5V Ta 25 C 5ns SAMPLE NUMBER t sis cement GLITCH IMPULSE 9 494nV 1LSB CHANGE AROUND MIDSCALE 0x8000 TO Ox7FFF Vpp 5V 25 C FULL SCALE CODE CHANGE 0 0000 OxFFFF 2 OUTPUT LOADED WITH 2kQ 4 AND 200pF TO GND 1 Vour 909mV DIV 05858 058 50 10
35. log output when the input code in the DAC register changes state It is normally specified as the area of the glitch in nV s and is measured when the digital input code is changed by 1 LSB at the major carry transition 0x7FFF to 0x8000 See Figure 38 Digital Feedthrough A measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC digital feedthrough is measured when the DAC output is not updated It is specified in nV s and it is measured with a full scale code change on the data bus that is from all 0s to all 1s and vice versa Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated that is LDAC is high It is expressed in decibels dB Noise Spectral Density Noise spectral density is a measurement of the internally generated random noise Random noise is characterized as a spectral density nV VHz It is measured by loading the DAC to midscale and measuring noise at the output A plot of noise spectral density is shown in Figure 44 DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC It is measured with a full scale output change on one DAC or soft power down and power up while monitoring another DAC kept at midscale It is expressed in microvolts HV DC crosstalk due to load current c
36. n Voo and GND Temperature range A B grade 40 C to 105 C Linearity calculated using a reduced code range AD5663R Code 512 to Code 65 024 AD5643R Code 128 to Code 16 256 and AD5623R Code 32 to Code 4064 Output unloaded 3 Guaranteed by design and characterization not production tested 4 Interface inactive All DACs active DAC outputs unloaded 5 Both DACs powered down Rev E Page 4 of 32 AD5623R AD5643R AD5663R AD5623R 3 AD5643R 3 AD5663R 3 2 7 V to 3 6 V Ri 2 to GND C 200 pF to GND Vrer Vos all specifications Tuis to Tmax unless otherwise noted Table 3 B Grade Parameter Min Typ Max Unit Conditions Comments STATIC PERFORMANCE AD5663R Resolution 16 Bits Relative Accuracy 8 16 LSB Differential Nonlinearity 1 LSB Guaranteed monotonic by design AD5643R Resolution 14 Bits Relative Accuracy 2 4 LSB Differential Nonlinearity 0 5 LSB Guaranteed monotonic by design AD5623R Resolution 12 Bits Relative Accuracy 0 5 1 LSB Differential Nonlinearity 0 25 LSB Guaranteed monotonic by design Zero Scale Error 2 10 mV All Os loaded to DAC register Offset Error 1 10 mV Full Scale Error 0 1 1 96 of FSR All 1s loaded to DAC register Gain Error 1 5 96 of FSR Zero Scale Error Drift 2 uV C Gain Temperature Coefficient 2 5 ppm Of FSR C DC Power Supply Rejection Ratio 100 dB DAC code midscale Voo 3 V 1096 DC Crosstalk
37. nel DC Crosstalk Internal Reference 25 25 uV Due to full scale output change 2 to GND or Voo 20 20 uV mA Due to load current change 10 10 uV Due to powering down per channel OUTPUT CHARACTERISTICS Output Voltage Range 0 Vop 0 V Capacitive Load Stability 2 2 nF 10 10 nF RL 2kO DC Output Impedance 0 5 0 5 Q Short Circuit Current 30 30 mA Vpp 5 V Power Up Time 4 4 us Coming out of power down mode Vpp 5V REFERENCE INPUTS Reference Current 170 200 170 200 HA Veer 5 5 V Reference Input Range 0 75 Voo 0 75 Voo V Reference Input Impedance 26 26 Rev E Page 3 of 32 AD5623R AD5643R AD5663R A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions Comments REFERENCE OUTPUT Output Voltage 2 495 2 505 2 495 2 505 V At ambient Reference Temperature Coefficient 10 5 10 ppm C MSOP package models 10 10 ppm C LFCSP package models Output Impedance 75 75 LOGIC INPUTS Input Current 2 2 All digital inputs Input Low Voltage Vin 0 8 0 8 V Vop 5V Input High Voltage 2 2 V Vpp 5V Pin Capacitance 3 3 pF DIN SCLK and SYNC 19 19 pF LDAC and CLR POWER REQUIREMENTS Von 4 5 5 5 4 5 5 5 V lbp Normal Mode Vin Voo and Vi GND Vpp 4 5 V to 5 5 V 0 25 0 45 0 25 0 45 mA Internal reference off Vpp 4 5 V to 5 5 0 8 1 0 8 1 mA Internal reference on Ibo All Power Down Modes Vpp 4 5 V to 5 5 V 0 48 1 0 48 1 Vi
38. normal write sequence the SYNC line is kept low for at least 24 falling edges of SCLK and the DAC is updated on the 24th falling edge However if SYNC is brought high before the 24th falling edge this acts as an interrupt to the write sequence The shift register is reset and the write sequence is seen as invalid Neither an update of the DAC register contents nor a change in the operating mode occurs see Figure 54 LSB DATA BITS 05858 034 Figure 51 AD5663R Input Shift Register Contents DB23 MSB a ot IS A V COMMAND BITS ADDRESS BITS LSB DATA BITS 05858 071 Figure 52 AD5643R Input Shift Register Contents DB23 MSB ESEZESEREXERESESESEOEZEJES COMMAND BITS ADDRESS BITS LSB DATA BITS 05858 072 Figure 53 AD5623R Input Shift Register Contents om 0 es Mn Xx X Ces INVALID WRITE SEQUENCE SYNC HIGH BEFORE 24TH FALLING EDGE VALID WRITE SEQUENCE OUTPUT UPDATES ON THE 24TH FALLING EDGE 05858 035 Figure 54 SYNC Interrupt Facility Rev E Page 21 of 32 AD5623R AD5643R AD5663R POWER ON RESET The AD5623R AD5643R AD5663R contain a power on reset circuit that controls the output voltage during power up The AD5623R AD5643R AD5663R DACs output power up to 0 V and the output remains there until a valid write sequence is made to the DACs This is
39. respective owners ANALOG D05858 0 4 12 E DEVICES www analog com Rev E Page 32 of 32
40. s in industrial environments it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common mode voltages that can occur in the area where the DAC is functioning iCoupler provides isolation in excess of 2 5 kV The AD5663R uses a 3 wire serial logic interface so the ADuM1300 3 channel digital isolator provides the required isolation see Figure 62 The power supply to the part also needs to be isolated which is done by using a transformer On the DAC side of the transformer a 5 V regulator provides the 5 V supply required for the AD5663R 05858 043 Figure 62 AD5663R with a Galvanically Isolated Interface Rev E Page 26 of 32 AD5623R AD5643R AD5663R POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit it is helpful to carefully consider the power supply and ground return layout on the board The printed circuit board containing the AD5663R should have separate analog and digital sections each having its own area of the board If the AD5663R is in a system where other devices require an AGND to DGND connection the connection should be made at one point only This ground point should be as close as possible to the AD5663R The power supply to the AD5663R should be bypassed with 10 uF and 0 1 capacitors The capacitors should be located as close as possible to the device with the 0 1 uF capacitor ideally righ
41. t ensures the DAC output powers up to 0 V and remains there until a valid write takes place The part contains a power down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software selectable output loads while in power down mode Rev E Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result from its use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Dual 12 14 16 Bit nanoDAC with 9 ppm C On Chip Reference AD5623R AD5643R AD5663R FUNCTIONAL BLOCK DIAGRAM Vrerin VREFOUT 1 25V 2 5V REFERENCE INPUT DAC PN REGISTER REGISTER DAC A INPUT DAC REGISTER REGISTER AD5623R AD5643R AD5663R POWER ON BONER DOWN RESET LOGIC 3 DAC CLR GND Figure 1 Table 1 Related Devices Part No Description AD5663 2 7 V to 5 5 V dual 16 bit nanoDAC with external reference The low power consumption of this part in normal operation makes it ideally suited to portable battery operated equipment The AD5623R AD5643R AD5663R use a versatile 3 wire serial interface th
42. t up against the device The 10 uF capacitors are the tantalum bead type It is important that the 0 1 capacitor have low effective series resistance ESR and effective series inductance ESI which is found for example in common ceramic types of capacitors This 0 1 capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground Avoid crossover of digital and analog signals if possible When traces cross on opposite sides of the board ensure that they run at right angles to each other to reduce feedthrough effects through the board The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side However this is not always possible with a 2 layer board Rev E Page 27 of 32 AD5623R AD5643R AD5663R OUTLINE DIMENSIONS 2 48 3 10 CE 7 H 3 00 SQ 2 90 0 50 BSC 1 6 10 PIN 1 INDEX EXPOSED 1 74 AREA PAD 164 0 50 149 0 40 0 30 TOP VIEW BOTTOM VIEW INDICATOR R 0 15 0 80 FOR PROPER CONNECTI
43. ther associated linear circuitry are shut down when power down mode is activated However the contents of the DAC register are unaffected when in power down The time to exit power down is typically 4 us for both VDD 5 V and VDD 3 V see Figure 37 Table 12 24 Bit Input Shift Register Contents for Software Reset Command MSB LSB DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DBO x 1 0 1 x x x x 1 0 Don t care Command bits C2 to CO Address bits A2 to AO Don t care Determines software reset mode Rev E Page 22 of 32 AD5623R AD5643R AD5663R Table 13 24 Bit Input Shift Register Contents of Power Up Down Function MSB LSB DB23 to DB15 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB6 DB5 DB4 083 DB2 DB1 DBO x 1 0 0 x x x x PD1 PD0 x x DAC DACA Don t Command bits C2 to CO Address bits A2 to AO Don t Power down Don t care Power down Power up care Don t care care mode channel selection set bit to 1 to select channel Table 14 24 Bit Input Shift Register Contents for LDAC Setup Command MSB LSB DB23 to DB21 DB20 DB19 DB110 DB17 DB16 DB15toDB2 DB1 DBO DB22 x 1 1 0 x x x x DACB DAC A Don t care Command bits C2 to CO Address bits A3 to AO Don t care Set DAC to 0 or 1 for required Don t care mode of operation LDAC FUNCTION Asynchronous LDAC The AD5623R AD5643R AD5663R DACs have
44. useful in applications where it is important to know the state of the output of the DACs while they are in the process of powering up Any events on LDAC or CLR during power on reset are ignored SOFTWARE RESET The AD5623R AD5643R AD5663R contain a software reset function Command 101 is reserved for the software reset function see Table 8 The software reset command contains two reset modes that are software programmable by setting bit DBO in the control register Table 10 shows how the state of the bit corresponds to the mode of operation of the device Table 12 shows the contents of the input shift register during the software reset mode of operation Table 10 Software Reset Modes DBO Registers Reset to Zero 0 DAC register Input register DAC register Input register LDAC register Power down register Internal reference setup register 1 Power on Reset POWER DOWN MODES The AD5623R AD5643R AD5663R contain four separate modes of operation Command 100 is reserved for the power down function see Table 8 These modes are software programmable by setting Bit DB5 and Bit DB4 in the control register Table 11 shows how the state of the bits corresponds to the mode of operation of the device Any or all DACs DAC B and DAC A can be powered down to the selected mode by setting the corresponding two bits Bit DB1 and Bit DBO to 1 By executing the same Command 100 any combination of DACs can be powered up
Download Pdf Manuals
Related Search
ANALOG DEVICES AD5623R/AD5643R/AD5663R English products handbook Rev E