ANALOG DEVICES AD5410 English products handbook
Contents
1. EE E m d 3 AG Performance Characteristics voor nm eR PRORSUS TUR 5 Timing Characteristics ecco ap HIR 5 Absolute Maximum Ratings eese 7 DESDE qutiol cnet No ME E 7 Pin Configuration and Function Descriptions 8 Typical Performance Characteristics nomin ae mom ete 10 JTerminolo9y 15 Theory Operation qe dad dues 16 16 SOMA Marise a 16 18 Transter FUNGON 18 Datt REPISTO 52 Ud t 18 Control 18 Reset Pasii babuit ques 19 eU IS LO IM CEDE 19 REVISION HISTORY 5 12 Rev C to Rev D Reorganized LAVOUL oie e a i ER OR Universal Chances to Product MUR 1 Added Companion Products Section Changes to Features Section and Applications Section 1 Chances to Table 9 Chance to EIS Ure 11 Added HART Communication Section and Figure 41 Renumbered Sequentially ess 21 Changes to Industrial HART Compatible Analog Output Application Section and Fi2. Des pss 90 10 REXT OUTEN SRdok SRstep SEN DCN RO Rev D Page 18 of 28 AD5410 AD5420 RESET REGISTER Table 15 Status Register Bit Functions The reset register is addressed by setting the address byte of the Bit Description input shift register to 0x56 reset register contains a single lour Fault This bit is set if a fault is detected on the lour pin reset bit at Position DBO as shown in Table 16 Writing a logic Slew Active This bit is set while the output value is slewing high to this bit performs a reset operation restoring the part to ley ae control Overtemp This bit is set if the AD5410 AD5420 core its power on state STATUS REGISTER The status register is a read only register The status register bit functionality is shown in Table 15 and Table 17 temperature exceeds approximately 150 C Table 16 Programming the Reset Register MSB LSB sis 2 DBio Das Das DBS Dea pss 082 DBI 080 Table 17 Decoding the Status Register LSB MSB pets bia DB10 Des pez Des Dea pes 02 080 Rev D Page 19 of 28 AD5410 AD5420 AD5410 AD5420 FEATURES FAULT ALERT The AD5410 AD5420 are equipped with a FAULT pin which is an open drain output allowing several AD541
3. 85 Ambient Temperature of 85 C 34 5I V and Driving 24 mA Directly to App Oy 0 028 x42 Al pp 0 028x28 Ground Rev D Page 26 of 28 AD5410 AD5420 INDUSTRIAL HART COMPATIBLE ANALOG OUTPUT APPLICATION Many industrial control applications have requirements for accurately controlled current output signals and the AD5410 AD5420 are ideal for such applications Figure 54 shows the AD5410 AD5420 in a circuit design for an output module spe cifically for use in an industrial control application The design provides for a HART enabled current output with the HART capability provided by the AD5700 AD5700 1 HART modem the industry s lowest power and smallest footprint HART compliant IC modem For additional space savings the AD5700 1 offers a 0 596 precision internal oscillator OUT signal from the AD5700 is attenuated and ac coupled into the CAP2 pin of the AD5420 Further information on this configuration can be found in Application Note AN 1065 An alternative method of coupling the HART signal into the RSET pin only applicable of the external RSET is used is available in Circuit Note CN 0270 Use of either configuration results in the AD5700 HART modem output modulating the 4 mA to 20 mA analog current without affecting the dc level of the current This circuit adheres to the HART physical layer specifications as defined by the HART Communication Foundation The module is powered
4. the output should be full scale 1 LSB Full scale error is expressed as a percentage of the full scale range FSR Full Scale Error Temperature Coefficient TC This is a measure of the change in full scale error with changes in temperature Full scale error TC is expressed in ppm FSR C Gain Error This is a measure of the span error of the DAC It is the devia tion in slope of the DAC transfer characteristic from the ideal expressed in FSR A plot of gain error vs temperature can be seen in Figure 15 Gain Error Temperature Coefficient TC This is a measure of the change in gain error with changes in temperature Gain error TC is expressed in ppm FSR C Current Loop Compliance Voltage This is the maximum voltage at the Iour pin for which the output current is equal to the programmed value Power Supply Rejection Ratio PSRR PSRR indicates how the output of the DAC is affected by changes in the power supply voltage Voltage Reference Temperature Coefficient TC Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature The voltage reference TC is calculated using the box method which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm C as follows FOS VnEFmax V REFmin x10 6 Viggo X LempRange where Vrermax 15 the maximum reference output measured over the total temperature range Vrermin is t
5. 4 mA to 20 mA Output Current Step Using External Capacitors on the and CAP2 Pins OUTPUT CURRENT mA NO EXTERNAL CAPS 10nF ON CAP1 10nF ON CAP2 07027 043 TIME ms Figure 46 Smoothing Out the Steps Caused by the Digital Slew Rate Control Feature FEEDBACK MONITORING OF OUTPUT CURRENT For feedback or monitoring of the output current value a sense resistor can be placed in series with the Iour output pin and the voltage drop across it measured As well as being an additional component the resistor increases the compliance voltage required An alternative method is to use a resistor that is already in place R3 is such a resistor and is internal to the AD5410 AD5420 as shown in Figure 47 By measuring the voltage between the R3sxs and BOOST pins the value of the output current can be calculated as follows 2 where is the voltage drop across measured between the R3sensz and BOOST pins is a constant bias current flowing through with a typical value of 444 uA R3 is the resistance value of resistor R3 with a typical value of 40 R3sENsE BOOST louT 07027 050 Figure 47 Structure of Current Output Circuit Rev D Page 23 of 28 AD5410 AD5420 and Isis both have a tolerance of 10 and a temperature To eliminate errors due to the tolerances of and Isis a two coefficient of 30 ppm C Connecting to R3sensz rather than measurement calibration
6. AD5410 AD5420 APPLICATIONS INFORMATION DRIVING INDUCTIVE LOADS When driving inductive or poorly defined loads connect a 0 01 uF capacitor between Iovr and GND This ensures stability with loads beyond 50 mH There is no maximum capacitance limit The capacitive component of the load may cause slower settling Alternatively the capacitor can be connected from CAPI and or CAP2 to AVpp to reduce the slew rate of the current The digital slew rate control feature may also prove useful in this situation TRANSIENT VOLTAGE PROTECTION The AD5410 AD5420 contain ESD protection diodes that prevent damage from normal handling The industrial control environ ment can however subject I O circuits to much higher transients To protect the AD5410 AD5420 from excessively high voltage transients external power diodes and a surge current limiting resistor may be required as shown in Figure 50 The constraint on the resistor value is that during normal operation the output level at Iour must remain within its voltage compliance limit of 2 5 V and the two protection diodes and resistor must have appropriate power ratings Further protection can be pro vided with transient voltage suppressors TVS or transorbs These are available as both unidirectional suppressors protect against positive high voltage transients and bidirectional suppressors protect against both positive and negative high voltage transients and are available in
7. avoid performance degradation or loss of functionality Atos Rev D Page 7 of 28 AD5410 AD5420 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 DVcc 2 FAULT 3 GND NC 1 PIN 1 30 NC ADS410 FAULT 2 INDICATOR 29 CAP2 GND 5 AD5420 GND 3 H 28 GND 4 BH 7 CLEAR 6 Not to Scale CLEAR 5 H AD5410 AD5420 H 26 lour LATCH 6 TOP VIEW 25 R3SENSE E Not to Scale 4 NC LATCH SDIN 8 23 DVcc SELECT DO 9 NC SCLK 8 NC 10 21 NC SDIN 9 SDO 10 GND 11 GND 12 NOTES NOTES 1 NC NO CONNECT 1 NC NO CONNECT 2 GROUND REFERENCE CONNECTION IT IS RECOMMENDED THAT THE 8 2 GROUND REFERENCE CONNECTION IT IS RECOMMENDED THAT THE 8 EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR 5 EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR 5 ENHANCED THERMAL PERFORMANCE 5 ENHANCED THERMAL PERFORMANCE S Figure 5 TSSOP Pin Configuration Figure 6 LFCSP Pin Configuration Table 5 Pin Function Descriptions TSSOP Pin No LFCSP Pin No NOE Description 1 4 5 12 3 4 14 15 37 These pins must be connected to ground 2 Digital Supply Pin Voltage ranges from 2 7 V to 5 5 V 3 Fault Alert This pin is asserted low when an open circuit is detected between lour and GND or an overtemperature is detected The FAULT pin is an open drain output and must be connected to DVc through a pull up resistor typically 10 6 Active High Input Asserting this
8. can be performed as the following AV pp avoids incorporating into R3 internal metal connections example illustrates that have large temperature coefficients and result in large 1 Progam code 0x1000 and measure Iour and Vr In this errors See Figure 48 for a plot of R3 vs ambient temperature example the measured values are and Figure 49 for a plot of R3 vs output current lcsc14796540 40 98 m 79 55446 mV our 12mA 40 96 R3 12 444pA 2 Program Code OxF000 and measure and Vr again 40 94 The measured values this time are has lour 22 46754 mA Vrs 946 39628 mV Using this information and Equation 2 two simultaneous A OL equations can be generated from which the values of R3 and 40 84 ds uw Iss can be calculated as follows R3 RESISTANCE e I OUT Vrs BIAS R3 B _ R3 40 78 gt T ouis Lour 40 R3 07027 051 AMBIENT TEMPERATURE C Figure 48 R3 Resistor Value vs Temperature Simultaneous Equation 1 DOO 0 00147965 R3 Simultaneous Equation 2 094639025 0 02246754 From these two equations 41 302 and 446 5 And Equation 2 becomes ae OUT 11302 EN NEM ee NN 5 SEE NEN 446 5uA 07027 052 lour mA Figure 49 R3 Resistor Value vs lour Rev D Page 24 of 28
9. from a field supply of 24 V This supplies AV pp directly For transient overvoltage protection transient voltage suppressors TVS are placed on both the Iour and field BACKPLANE SUPPLY ADuM1400 MICROCONTROLLER DIGITAL OUTPUTS _ BACKPLANE INTERFACE UART DIGITAL Voa Via INTERFACE INTPUTS 1 Voeg GND GND ADuM1200 lt ADuM1402 V AGND DGND V ADC IP supply connections 24 V TVS is placed on the Iour connection and 36 V TVS is placed on the field supply input For added protection clamping diodes are connected from the Iour pin to the and GND power supply pins The recommended external band pass filter for the AD5700 HART modem includes 150 resistor which limits current to a sufficiently low level to adhere to intrinsic safety requirements In this case the input has higher transient voltage protection and should therefore not require additional protection circuitry even in the most demanding of industrial environments Isolation between the AD5410 AD5420 and the backplane circuitry is provided with the ADuM1400 and ADuM1200 iCoupler digital isolators further information on iCoupler products is available at www analog com icouplers The internally generated digital power supply of the AD5410 AD5420 powers the field side of the digital isolators removing the need to generate a digital power supply on the field side of the isolation barrier The AD5410 AD542
10. low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time Serial output delay time Ci spo 50 pF Guaranteed by characterization but not production tested All input signals are specified with tr tr 5 ns 10 to 90 of DVcc and timed from a voltage level of 1 2 V See Figure 2 Figure 3 and Figure 4 Cispo Capacitive load on SDO output Rev D Page 5 of 28 AD5410 AD5420 SCLK 1 B 1 LATCH lt SDIN CLEAR o c 07027 002 SCLK 1 2 tio a i3 som en X X OC OC es INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ UNDEFINED DATA FIRST 8 BITS ARE SELECTED REGISTER DON T CARE BITS DATA CLOCKED OUT 07027 003 Figure 3 Readback Mode Timing Diagram LATCH INPUT WORD t g a INPUT WORD FOR 1 UNDEFINED INPUT WORD FOR DAC N 07027 004 Figure 4 Daisy Chain Mode Timing Diagram Rev D Page 6 of 28 AD5410 AD5420 ABSOLUTE MAXIMUM RATINGS 25 C unless otherwise noted Transient currents of up to 80 mA do not cause SCR latch up Table 4 Parameter AVop to GND DVcc to GND Digital Inputs to GND Digital Outputs to GND REFIN REFOUT to GND lour to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature T max 24 Lead TSSOP Package Ther
11. use as a digital power supply for other devices in the system or as a termination for pull up resistors This facility offers the advantage of not having to bring a digital supply across an isolation barrier The internal power supply is enabled by leaving the DVcc SELECT pin unconnected To disable the internal supply DVcc SELECT should be tied to 0 V DVcc is capable of supplying up to 5 mA of current See Figure 27 for a load regulation graph EXTERNAL BOOST FUNCTION The addition of an external boost transistor as shown in Figure 40 reduces the power dissipated in the AD5410 AD5420 by reducing the current flowing in the on chip output transistor dividing it by the current gain of the external circuit A discrete NPN transistor with a breakdown voltage greater than 40 V can be used The external boost capability allows the AD5410 AD5420 to be used at the extremes of the supply voltage load current and temperature range The boost transistor can also be used to reduce the amount of temperature induced drift in the part This minimizes the temperature induced drift of the on chip voltage reference which improves drift and linearity MJD31C 2N3053 BOOST AD5410 AD5420 0 022 07027 036 Figure 40 External Boost Configuration Rev D Page 20 of 28 AD5410 AD5420 HART COMMUNICATION The AD5410 AD54120 contain a CAP2 pin into which a HART signal can be coupled The HART signal appears
12. values steps digitally at a rate defined by two parameters accessible via the control register as shown in Table 14 The parameters are SR clock and SR step SR clock defines the rate at which the digital slew is updated SR step defines by how much the output value changes at each update Both parameters together define the rate of change of the output current Table 18 and Table 19 outline the range of values for both the SR clock and SR step parameters Figure 42 shows the output current changing for ramp times of 10 ms 50 ms and 100 ms Table 18 Slew Rate Update Clock Values SR Clock 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Update Clock Frequency Hz 257 30 198 410 152 440 131 580 115 740 69 440 37 590 25 770 20 160 16 030 10 290 8280 6900 5530 4240 3300 Table 19 Slew Rate Step Size Options AD5410 Step Size LSB AD5420 Step Size LSB SR Step 000 001 010 011 100 101 110 111 OUTPUT CURRENT mA TA 25 C AVpp 24V 3000 10ms RAMP SR CLOCK 0x1 SR STEP 0x5 50 RAMP SR CLOCK SR STEP 0x7 100ms RAMP SR CLOCK 0x8 SR STEP 0x5 0 10 07027 139 20 30 40 50 60 70 80 90 100 110 TIME ms Figure 42 Output Current Slewing Under Control of the Digital Slew Rate Rev D Page 21 of 28 Control Feature AD5410 AD5420 The time it takes for the output current to slew over a given v
13. 0 AD5420 devices to be connected together to one pull up resistor for global fault detection The FAULT pin is forced active by any one of the following fault scenarios e The voltage at Iovr attempts to rise above the compliance range due to an open loop circuit or insufficient power supply voltage The current is controlled by PMOS transistor and internal amplifier as shown in Figure 38 The internal circuitry that develops the fault output avoids using a comparator with window limits because this requires an actual output error before the FAULT output becomes active Instead the signal is generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability when the gate of the output PMOS transistor nearly reaches ground Thus the FAULT output activates slightly before the compliance limit is reached Because the comparison is made within the feed back loop of the output amplifier the output accuracy is maintained by its open loop gain and an output error does not occur before the FAULT output becomes active e Ifthe core temperature of the AD5410 AD5420 exceeds approximately 150 C The fault and overtemp bits of the status register are used in conjunction with the FAULT pin to inform the user which fault condition caused the FAULT pin to be asserted See Table 17 and Table 15 ASYNCHRONOUS CLEAR CLEAR CLEAR is an active high clear th
14. 0 digital supply out put supplies up to 5 mA which is more than enough to supply the 2 8 mA requirement of the ADuM1400 and ADuM1200 operating at a logic signal frequency of up to 1 MHz To reduce the number of isolators required nonessential signals such as CLEAR can be connected to GND and FAULT and SDO can be left unconnected reducing the isolation requirements to just three signals Doing so however disables the fault alert features of the part 24V lO FIELD SUPPLY SMAJ36CA 36V FIELD 0 1 pF GROUND V C3 AVpp SELECT AD5410 AD5420 lout 180 lout 24 SMAJ24CA V V OV C2 22nF T T 22nF Y F 1 1 2MQ 150kQ 150pF i y 07027 048 Figure 54 AD5410 AD5420 in an Industrial Analog Output Application Rev D Page 27 of 28 OUTLINE DIMENSIONS EXPOSED PAD Pins Up 6 40 BSC TOP VIEW FOR PROPER CONNECTION OF 1 05 THE EXPOSED PAD REFER TO 1 20 MAX tag THE PIN CONFIGURATION AND 8 FUNCTION DESCRIPTIONS Y NEEEBEBHEHHBHELHLELNI 0 80 ov SECTION OF THIS DATA SHEET 015 X He 4 0 20 gt 0 05 SEATING 0 65 0 30 0 09 0 75 PLANE BSC 6 19 0 60 0 10 COPLANARITY 0 45 061708 A COMPLIANT TO JEDEC STANDARDS MO 153 ADT Figure 55 24 Lead Thin Shrink Small Outline Package Exposed Pad TSSOP_EP RE 24 Dimensions shown in millimeters 0 60 0 60 INDICAT
15. 10 11 19 20 NC Do not connect to these pins 21 22 24 30 31 32 33 34 35 38 40 Rev D Page 8 of 28 AD5410 AD5420 TSSOP Pin No LFCSP Pin No Mnemonic Description 18 19 20 21 22 24 25 EPAD 26 27 28 29 36 41 EPAD lout BOOST CAP1 CAP2 AVpp Exposed pad The voltage measured between this pin and the BOOST pin is directly proportional to the output current and can be used as a monitor feedback feature This should be used as a voltage sense output only current should not be sourced from this pin See the AD5410 AD5420 Features section Current Output Pin Optional External Transistor Connection Connecting an external transistor reduces the power dissipated in the AD5410 AD5420 See the AD5410 AD5420 Features section Connection for Optional Output Filtering Capacitor See the AD5410 AD5420 Features section Connection for Optional Output Filtering Capacitor See the AD5410 AD5420 Features section Also HART Input Connection see Device Features Section Positive Analog Supply Pin Voltage ranges from 10 8 V to 40 V Ground Reference Connection It is recommended that the exposed pad be thermally connected to a copper plane for enhanced thermal performance Rev D Page 9 of 28 AD5410 AD5420 TYPICAL PERFORMANCE CHARACTERISTICS DNL ERROR LSB INL ERROR FSR TOTAL UNADJUSTED ERROR 96 FSR EXTERNAL Reet INTERNAL EX
16. 27 049 TIME ps Figure 35 Digital to Analog Glitch OUTPUT CURRENT mA 07027 134 TIME ps Figure 36 4 mA to 20 mA Output Current Step AD5410 AD5420 TERMINOLOGY Relative Accuracy or Integral Nonlinearity INL For the DAC relative accuracy or integral nonlinearity INL is a measure of the maximum deviation in 96 FSR from a straight line passing through the endpoints of the DAC transfer function A typical INL vs code plot is shown in Figure 7 Differential Nonlinearity DNL Differential nonlinearity DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB maximum ensures monotonicity This DAC is guaranteed monotonic by design A typical DNL vs code plot can be seen in Figure 8 Total Unadjusted Error TUE Total unadjusted error TUE is a measure of the output error taking all the various errors into account namely INL error offset error gain error and output drift over supplies and temperature TUE is expressed in FSR A typical TUE vs code plot can be seen in Figure 9 Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code The AD5410 AD5420 are monotonic over their full operating temperature range Full Scale Error Full scale error is a measure of the output error when full scale code is loaded to the data register Ideally
17. 5 C Gain Error Temperature Coefficient TC ppm FSR C Full Scale Error FSR FSR Ta 25 C Full Scale Error Temperature Coefficient TC ppm FSR C ACCURACY EXTERNAL Assumes an ideal 15 kO resistor Resolution Bits AD5420 Bits AD5410 Total Unadjusted Error TUE FSR AD5420 FSR AD5420 Ta 25 C FSR AD5410 FSR AD5410 Ta 25 C Relative Accuracy INL FSR AD5420 96 FSR AD5410 Differential Nonlinearity DNL LSB Guaranteed monotonic Offset Error 96 FSR FSR 25 C Offset Error Temperature Coefficient TC ppm FSR C Gain Error FSR FSR Ta 25 C Gain Error Temperature Coefficient TC ppm FSR C Full Scale Error FSR FSR Ta 25 C Full Scale Error Temperature Coefficient TC ppm FSR C OUTPUT CHARACTERISTICS Current Loop Compliance Voltage Output Current Drift vs Time Internal Rser drift after 1000 hours at 125 C External Rser drift after 1000 hours at 125 C Resistive Load Inductive Load DC Power Supply Rejection Ratio PSRR 25 C Rev D Page 3 of 28 AD5410 AD5420 Parameter Output Impedance Output Current Leakage R3 Resistor Value R3 Resistor Temperature Coefficient TC lass Current lass Current Temperature Coefficient TC REFERENCE INPUT OUTPUT Reference Input Reference Input Voltage DC Input Impedance Reference Output Min Typ Max Unt Test Conditions Comments 50 MO 25 5 30 Output disabled Ta 25 For spe
18. 8 Reference Turn on Transient TA 25 C lout Alpp mA IW 07027 023 07027 026 0 2uV M2 00s LINE 1 8V AVpp V Figure 26 Alpp vs AVpp Figure 29 Reference Noise 0 1 Hz to 10 Hz Bandwidth tld EEEE SHEL ETE EE DVcc OUTPUT VOLTAGE 0 21 19 17 15 13 11 9 7 5 3 1 1 098 EINE 2 7 LOAD CURRENT mA Figure 27 DVcc Output Voltage vs Load Current Figure 30 Reference Noise 100 kHz Bandwidth 07027 024 07027 027 Rev D Page 13 of 28 AD5410 AD5420 Ta 25 C AVpp 40V OUTPUT DISABLED LEAKAGE CURRENT pA COMPLIANCE VOLTAGE V Figure 31 Output Leakage Current vs Compliance Voltage 5 003 50 DEVICES SHOWN 5 002 5 001 5 000 4 999 REFERENCE OUTPUT VOLTAGE V 4 998 TEMPERATURE C Figure 32 Reference Output Voltage vs Temperature 45 ot ve ELL 10 POPULATION 5 0 TEMPERATURE COEFFICIENT ppm C Figure 33 Reference Temperature Coefficient Histogram 07027 030 07027 028 07027 029 OUTPUT CURRENT pA Rev D Page 14 of 28 REFERENCE OUTPUT VOLTAGE V 0 1 2 3 4 5 6 7 8 9 LOAD CURRENT mA 07027 031 Figure 34 Reference Output Voltage vs Load Current AVpp 24V 0x8000 TO 0x7FFF TA 25 C Ox7FFF TO 0x8000 RLOAD z 2500 070
19. ANALOG DEVICES Single Channel 12 16 Bit Serial Input 4 mA to 20 mA Current Source DAC HART Connectivity AD5410 AD5420 FEATURES 12 16 bit resolution and monotonicity Current output ranges 4 mA to 20 mA 0 mA to 20 mA or 0 mA to 24 mA 0 01 FSR typical total unadjusted error TUE 3 ppm C typical output drift Flexible serial digital interface On chip output fault detection On chip reference 10 ppm C maximum Feedback monitoring of output current Asynchronous clear function Power supply AVpp range 10 8 V to 40 V AD5410AREZ AD5420AREZ 10 8 V to 60 V ADBA10ACPZ AD5420ACPZ Output loop compliance to AVpp 2 5 V Temperature range 40 C to 85 C 24 lead TSSOP and 40 lead LFCSP packages APPLICATIONS Process control Actuator control PLC HART network connectivity GENERAL DESCRIPTION The AD5410 AD5420 are low cost precision fully integrated 12 16 bit converters offering a programmable current source output designed to meet the requirements of industrial process control applications The output current range is programmable at 4 mA to 20 mA 0 mA to 20 mA or an overrange function of 0 mA to 24 mA The output is open circuit protected The device operates with a power supply AVpp range from 10 8 V to 60 V Output loop compliance is 0 V to AVpp 2 5 V The flexible serial interface is SPI MICROWIRE and DSP compatible and can be operated in 3 wire mode to minimize the digital isol
20. Figure 51 shows a 4 channel isolated interface to the AD5410 AD5420 using an ADuMI1AOO For further information visit www analog com icouplers CONTROLLER ADuM1400 SERIAL TO d ENCODE DECODE gt SERIAL y DATA sh ENCODE DECODE qp hz ENCODE DECODE gt OUT LATCH CONTROL 5 ENCODE DECODE d TO ie e ADDITIONAL PINS OMITTED FOR CLARITY 07027 040 Figure 51 Isolated Interface Rev D Page 25 of 28 AD5410 AD5420 MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5410 AD5420 is via a serial bus that uses a protocol compatible with microcontrollers and DSP processors The communication channel is a 3 wire mini mum interface consisting of a clock signal a data signal and a latch signal The AD5410 AD5420 require a 24 bit data word with data valid on the rising edge of SCLK DMA For all interfaces the DAC output update is initiated on the rising edge of LATCH The contents of the registers can be read using the readback function THERMAL AND SUPPLY CONSIDERATIONS 0 45 50 55 60 6 70 75 8 The AD5410 AD5420 designed to operate at a maximum junction temperature of 125 C It is important that the device POWER DISSIPATION W gt 0 07027 055 AMBIENT TEMPERATURE Figure 52 Maximum Power Dissipation vs Ambient Temperature not be operated under conditions that cause the j
21. Hz a 6 s Ja a 257 730 0 0020 198 410 0 0026 152 440 0 0034 131 580 0 0039 115 740 0 0044 69 440 0 007 37 590 0 014 25 770 0 020 20 160 0 025 16 030 0 03 10 290 0 05 8280 0 06 6900 0 07 5530 0 09 4240 0 12 3300 0 16 Rev D Page 22 of 28 AD5410 AD5420 lour FILTERING CAPACITORS Capacitors can be placed between and AVpp and CAP2 and AVpp as shown in Figure 43 AVpp AVpp 1 AD5420 GND 07027 037 Figure 43 lour Filtering Capacitors The capacitors form a filter on the current output circuitry as shown in Figure 44 reducing the bandwidth and the slew rate of the output current Figure 45 shows the effect the capacitors have on the slew rate of the output current To achieve significant reductions in the rate of change very large capacitor values are required which may not be suitable in some applications In this case the digital slew rate control feature should be used The capacitors can be used in conjunction with the digital slew rate control feature as a means of smoothing out the steps caused by the digital code increments as shown in Figure 46 07027 038 Figure 44 lour Filter Circuitry 25 20 lt 5 15 tc tc 2 10 CAPACITOR o 10nF ON CAP1 5 10nF ON 2 47nF ON CAP1 47nF ON CAP2 07027 142 05 0 05 10 15 20 25 30 35 40 TIME ms Figure 45 Slew Controlled
22. OR zm BSC ey 4 1050 0 50 3 95 0 4 039 30 0 25 MIN 12 MAX 0 80 MAX IE 0 65 TYP 0 05 MAX FOR PROPER CONNECTION OF E 005 THE EXPOSED PAD REFER TO 1 00 0 02 NOM THE PIN CONFIGURATION AND 0 85 0 30 1 FUNCTION DESCRIPTIONS 0 80 0 23 0 20REF SECTION OF THIS DATA SHEET SEATING 0 08 0 18 072108 COMPLIANT JEDEC STANDARDS MO 220 VJJD 2 Figure 56 40 Lead Lead Frame Chip Scale Package LFCSP_VQ 6 mm x 6 mm Body Very Thin Quad CP 40 1 Dimensions shown in millimeters ORDERING GUIDE Model Package Option AD5410AREZ 40 C to 85 C 12 Bits 0 3 Max 24 Lead TSSOP_EP RE 24 AD5410AREZ REEL7 40 C to 85 C 12 Bits 0 3 Max 24 Lead TSSOP_EP RE 24 AD5410ACPZ REEL 40 C to 85 C 12 Bits 0 3 Max 40 Lead LFCSP_VQ CP 40 1 AD5410ACPZ REEL7 40 C to 85 C 12 Bits 0 3 Max 40 Lead LFCSP_VQ CP 40 1 AD5420AREZ 40 C to 85 C 16 Bits 0 15 Max 24 Lead TSSOP_EP RE 24 AD5420AREZ REEL7 40 C to 85 C 16 Bits 0 15 Max 24 Lead TSSOP_EP RE 24 AD5420ACPZ REEL 40 C to 85 C 16 Bits 0 15 Max 40 Lead LFCSP_VQ CP 40 1 AD5420ACPZ REEL7 40 C to 85 C 16 Bits 0 15 Max 40 Lead LFCSP_VQ CP 40 1 tution Board Z RoHS Compliant Part 2009 2012 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners Rev D Page 28 of 28
23. TERNAL BOOST TRANSISTOR INTERNAL Rger BOOST TRANSISTOR wee wv Ws AVpp z 2 4V TA 25 C RLoap 2500 0 10 000 20 000 30 000 40 000 50 000 60 000 CODE Figure 7 Integral Nonlinearity Error vs Code asm EXTERNAL INTERNAL Reet EXTERNAL BOOST TRANSISTOR INTERNAL BOOST TRANSISTOR 0 10 000 20 000 30 000 40 000 50 000 60 000 0 05 0 03 0 01 0 01 0 03 0 05 0 07 0 09 0 11 0 13 0 15 Figure 8 Differential Nonlinearity Error vs Code AVpp 24V Ta 25 C Ri oAD z 2500 EXTERNAL Rept INTERNAL Reet EXTERNAL BOOST TRANSISTOR INTERNAL Rger BOOST TRANSISTOR LEVEL AIVI 07027 008 0 10 000 20 000 30 000 40 000 50 000 60 000 Figure 9 Total Unadjusted Error vs Code 07027 007 AVpp 24V OmA TO 24mA RANGE INL ERROR FSR 0 006 0 008 07027 006 07027 009 40 20 0 20 40 60 80 TEMPERATURE C Figure 10 Integral Nonlinearity Error vs Temperature Internal Rser 0 003 tc 0 001 LL 5 tc c 0 tc tc 0 001 07027 109 40 20 0 20 40 60 80 TEMPERATURE C Figure 11 Integral Nonlinearity Error vs Temperature External Rser DNL ERROR LSB 07027 010 40 20 0 20 40 60 80 TEMPERATURE C Figure 12 Differential Nonlinearity Error vs Temperat
24. The voltage output from the DAC core is converted to a current see Figure 38 that is then mirrored to the supply rail so that the application simply sees a current source output with respect to ground AVpp 12 16 BIT DAC 07027 034 Figure 38 Voltage to Current Conversion Circuitry SERIAL INTERFACE The AD5410 AD5420 are controlled over a versatile 3 wire serial interface that operates at clock rates of up to 30 MHz They are compatible with SPI QSPI MICROWIRE and DSP standards Input Shift Register The input shift register is 24 bits wide Data is loaded into the device MSB first as a 24 bit word under the control of a serial clock input SCLK Data is clocked in on the rising edge of SCLK The input shift register consists of eight address bits and 16 data bits as shown in Table 6 The 24 bit word is uncondition ally latched on the rising edge of LATCH Data continues to be clocked in irrespective of the state of LATCH On the rising edge of LATCH the data that is present in the input shift register is latched that is the last 24 bits to be clocked in before the rising edge of LATCH is the data that is latched The timing diagram for this operation is shown in Figure 2 Standalone Operation The serial interface works with both a continuous and noncon tinuous SCLK A continuous SCLK source can be used only if LATCH is taken high after the correct number of data bits has been clocked in In gated clock mode a b
25. V Figure 15 Gain Error vs Temperature Figure 18 Differential Nonlinearity Error vs AVpp External Rser Rev D Page 11 of 28 AD5410 AD5420 louT 24mA OAD z 5000 2 8 2 tc 5 9 2 z x lt lt AVpp V TEMPERATURE C Figure 19 Differential Nonlinearity Error vs AVpo Internal Rser Figure 22 Compliance Voltage Headroom vs Temperature 0 025 AVpp 24V 0 020 Ta 25 C RLoap 2500 5 0 015 lt 0 010 a 0 005 tc e 2 2 a 0 lt 2 B 0 015 5 5 10 15 20 25 30 35 40 0 AVpp V TIME us Figure 20 Total Unadjusted Error vs AVpp External Rser Figure 23 Output Current vs Time on Power Up o Us 2 AVpp 24 a 25 C tc oc Ri 2500 m 25 C 24 2 2 gt lt z 2 ol lt 0 05 10 15 20 25 30 35 40 45 50 AVpp V TIME us Figure 21 Total Unadjusted Error vs Internal Rser Figure 24 Output Current vs Time on Output Enable Rev D Page 12 of 28 AD5410 AD5420 SRP SERRE ni ILLI _ YIN LLLI HAH o e e e e Dlcc HA 07027 022 07027 025 2 00V M200us CH3 2 1V CH3 5 00V 05 10 15 20 25 30 35 40 45 50 LOGIC VOLTAGE V Figure 25 Dlcc vs Logic Input Voltage Figure 2
26. a wide range of standoff and breakdown voltage ratings It is recommended that all field connected nodes be protected AVpp AVpp AD5410 AD5420 97 GND 07027 039 Figure 50 Output Transient Voltage Protection LAYOUT GUIDELINES In any circuit where accuracy is important careful consideration of the power supply and ground return layout helps to ensure the rated performance The printed circuit board PCB on which the AD5410 AD5420 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board If the AD5410 AD5420 are in a system where multiple devices require an AGND to DGND connection the connection should be made at one point only The star ground point should be established as close as possible to the device The AD5410 AD5420 should have ample supply bypassing of 10 uF in parallel with 0 1 uF on each supply located as close to the package as possible ideally right up against the device The 10 capacitors are the tantalum bead type The 0 1 uF capacitor should have low effective series resistance ESR and low effective series inductance ESI such as the common ceramic types which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching The power supply lines of the AD5410 AD5420 should use as large a trace as possible to provide low impedance paths and to reduce the e
27. alue with a write to the control register To avoid halting the output range can be expressed as follows output slew the slew active bit can be read to check that the slew has completed before writing to any of the AD5410 AD5420 registers see Table 17 The update clock frequency for any given value is the same for all output ranges The step size Step Size x Update Clock Frequency x LSB Size however varies across output ranges for a given value of step size because the LSB size is different for each output range Slew Time Output Change 1 where Slew Time is expressed in seconds Table 20 shows the range of programmable slew times for a full Output Change is expressed in amps scale change on any of the output ranges The values in Table 20 were obtained using Equation 1 The digital slew rate control When the slew rate control feature is enabled all output feature results in a staircase formation on the current output as changes change at the programmed slew rate If the CLEAR shown in Figure 46 Figure 46 also shows how the staircase can pin is asserted the output slews to the zero scale value at the be removed by connecting capacitors to the and CAP2 programmed slew rate The output can be halted at its current pins as described in the Iour Filtering Capacitors section Table 20 Programmable Slew Time Values in Seconds for a Full Scale Change on Any Output Range Step Size LSBs Update Clock Frequency
28. at clears the current output to the bottom of its programmed range It is necessary to maintain CLEAR high for a minimum amount of time see Figure 2 to complete the operation When the CLEAR signal is returned low the output remains at the cleared value The preclear value can be restored by pulsing the LATCH signal low without clocking any data A new value cannot be programmed until the CLEAR pin is returned low INTERNAL REFERENCE The AD5410 AD5420 contain an integrated 5 V voltage reference with initial accuracy of 5 mV maximum and a temperature drift coefficient of 10 ppm C maximum The reference voltage is buffered and externally available for use elsewhere within the system See Figure 34 for a load regulation graph of the integrated reference EXTERNAL CURRENT SETTING RESISTOR In Figure 38 Rser is an internal sense resistor as part of the voltage to current conversion circuitry The stability of the output current over temperature is dependent on the stability of the value of Rer An external precision 15 low drift resistor can be connected from the Rsr pin of the AD5410 AD5420 to ground this improves the overall performance of the AD5410 AD5420 The external resistor is selected via the control register See Table 14 DIGITAL POWER SUPPLY By default the DVcc pin accepts a power supply of 2 7 V to 5 5 V Alternatively via the DVcc SELECT pin an internal 4 5 V power supply can be output on the DVcc pin for
29. ation required in isolated applications The device also includes a power on reset function ensuring that the device powers up in a known state and an asynchronous CLEAR pin that sets the output to the low end of the selected current range The total unadjusted error is typically 0 01 FSR COMPANION PRODUCTS HART Modem AD5700 AD5700 1 FUNCTIONAL BLOCK DIAGRAM DVcc SELECT DVcc INPUT SHIFT REGISTER AND CONTROL REFOUT REFIN Rev D Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners CAP1 Figure 1 CAP2 GND 07027 001 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2009 2012 Analog Devices Inc All rights reserved AD5410 AD5420 TABLE OF CONTENTS eu pcc MIEL NELLE 1 APPC ONS ceo et eat et Eres 1 General DESPOT eie sc cree intra IERI 1 Companion Produc m 1 Functional Block Diagram i p E RE ER eade 1 MR 2
30. cified performance Output Voltage 4 995 5 000 Ta 25 C Reference TC 4 1 8 Output Noise 0 1 Hz to 10 Hz 18 Noise Spectral Density 100 10 kHz Output Voltage Drift vs Time Capacitive Load Load Current Short Circuit Current Load Regulation DIGITAL INPUTS Input High Voltage Vin Input Low Voltage Vi Drift after 1000 hours Ta 125 C JEDEC compliant Input Current Per pin Pin Capacitance Per pin DIGITAL OUTPUTS SDO Output Low Voltage VoL Sinking 200 Output High Voltage Vou High Impedance Leakage Current High Impedance Output Capacitance FAULT Output Low Voltage Vor Output Low Voltage Vo Output High Voltage Vou POWER REQUIREMENTS Sourcing 200 pA 10 pull up resistor to DVcc 2 5 mA load current 10 kO pull up resistor to DVcc AVbp TSSOP package LFCSP package DVcc Input Voltage Internal supply disabled Output Voltage DVcc can be overdriven up to 5 5 V Output Load Current Short Circuit Current Alp Output disabled Output enabled DVcc GND Power Dissipation AVbpp 40 V lour mA AVopp 15 V lour mA Temperature range 40 C to 85 C typical at 25 C For 0 mA to 20 mA and 0 mA to 24 mA ranges INL is measured from Code 256 for the AD5420 and Code 16 for the AD5410 Guaranteed by design and characterization but not production tested on chip reference is production trimmed and tested at 25 C and 85 C It is character
31. ffects of glitches on the power supply line Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them not required on a multilayer board that has a separate ground plane but separating the lines helps It is essential to minimize noise on the REFIN line because noise can couple through to the DAC output Avoid crossover of digital and analog signals Traces on opposite sides of the board should run at right angles to each other This reduces the effects of feedthrough on the board A microstrip technique is by far the best method but is not always possible with a double sided board In this technique the component side of the board is dedicated to the ground plane and signal traces are placed on the solder side GALVANICALLY ISOLATED INTERFACE In many process control applications it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common mode voltages that may occur The iCoupler family of products from Analog Devices Inc provides voltage isolation in excess of 2 5 kV The serial loading structure of the AD5410 AD5420 is ideal for isolated interfaces because the number of interface lines is kept to a minimum
32. gure 54 sss 27 11 11 Rev B to Rev C Changes fO 18 2 10 Rev A to Rev Chances to 23 AI5410 AD5420 20 PACAT ssim soi E EE PNE 20 Asynchronous Clear CLEAR oodd en ME 20 Internal Refetence ove ne mv iet 20 External Current Setting Resistor 20 Digital 20 External Boost oo eI 20 HAR Communicati 21 Digital Slew Rate Control 21 loon Filtering Capacitors 23 Feedback Monitoring of Output Current 23 Applications Informatio cech ets b utbs 25 Druvyinp Inductiye Lord Serseri an ma DENIS 25 Transient Voltage Protection 25 Layou Gude iet inte 25 Galvanically Isolated Interface cessus 25 Microprocessor Interfacing eese 26 Thermal and Supply Considerations 26 Industrial HART Compatible Analog Output ce 27 Outline DIMENSIONS quais ter ue ONU eM DN ME 28 CECE Tt Glo eese 28 8 09 0 to Rev A Changes to Features and General Description 1 Chanee
33. he minimum reference output measured over the total temperature range VRErnom 15 the nominal reference output voltage 5 V TempRange is the specified temperature range 40 to 85 C Reference Load Regulation Load regulation is the change in reference output voltage due to a specified change in load current It is expressed in ppm mA Rev D Page 15 of 28 AD5410 AD5420 THEORY OF OPERATION The AD5410 AD5420 are precision digital to current loop output converters designed to meet the requirements of industrial process control applications They provide a high precision fully integrated low cost single chip solution for generating current loop outputs The current ranges available are 0 mA to 20 mA 0 mA to 24 mA and 4 mA to 20 mA The desired output configuration is user selectable via the control register ARCHITECTURE The DAC core architecture of the AD5410 AD5420 consists of two matched DAC sections A simplified circuit diagram is shown in Figure 37 The four MSBs of the 12 bit or 16 bit data word decoded to drive 15 switches E1 to E15 Each of these switches connects one of 15 matched resistors to either ground or the reference buffer output The remaining 8 12 bits of the data word drive Switch 50 to Switch S7 or Switch 50 to Switch 511 of an 8 12 bit voltage mode R 2R ladder network 8 12 BIT R 2R LADDER FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS Figure 37 DAC Ladder Structure 07027 033
34. ite to the AD5410 AD5420 should be a NOP command which clocks out the data from the previously addressed register as shown in Figure 3 By default the SDO pin is disabled After having addressed the AD5410 AD5420 for a read operation a rising edge on LATCH enables the SDO pin in anticipation of data being clocked out After the data has been clocked out on SDO a rising edge on LATCH disables tristate the SDO pin once again To read back the data register for example the following sequence should be implemented 1 Write 0x020001 to the AD5410 AD5420 input shift register This configures the part for read mode with the data register selected 2 Follow this with a second write a NOP condition 0x000000 During this write the data from the data register is clocked out on the SDO line Table 8 Read Address Decoding Read Address Function 00 Read status register 01 Read data register 10 Read control register LSB _ 2 DB22 DB21 DB20 DB19 0818 DB17 0616 DBi5toDB2 081 DBO o jo 0 jo jo 1 j Reeadaddrss X 2 don t care Rev D Page 17 of 28 AD5410 AD5420 POWER ON STATE Upon power on of the AD5410 AD5420 the power on reset circuit ensures that all registers are loaded with zero code As such the output is disabled tristate Also upon power on internal calibration registers are read and the data is applied to internal calibration circuitry For a reliable read
35. ized from 40 C to 85 C Rev D Page 4 of 28 AD5410 AD5420 AC PERFORMANCE CHARACTERISTICS 10 8 V to 26 4 V GND 0 V REFIN 5 V external DVcc 2 7 V to 5 5 V Rroap 300 all specifications to Tmax unless otherwise noted Table 2 Parameter Min Unit Test Conditions Comments DYNAMIC PERFORMANCE Output Current Settling Time 10 us 16 mA step to 0 1 FSR 40 us 16 mA step to 0 1 FSR L 1 mH AC PSRR 75 dB 200 50 2 60 Hz sine wave superimposed on power supply voltage 1 Guaranteed by design and characterization not production tested Digital slew rate control feature disabled and CAP1 CAP2 open circuit TIMING CHARACTERISTICS 10 8 V to 26 4 V GND 0 V REFIN 5 V external DVcc 2 7 V to 5 5 V Rroap 300 all specifications to Tmax unless otherwise noted Table 3 Parameter 3 Limit at Tmn Unit Description WRITE MODE ti SCLK cycle time t SCLK low time SCLK high time ta LATCH delay time ts LATCH high time ts LATCH high time after a write to the control register Data setup time Data hold time LATCH low time CLEAR pulse width CLEAR activation time SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time Serial output delay time Ci spo 50 pF LATCH rising edge to SDO tristate SCLK cycle time SCLK
36. mal Impedance Thermal Impedance 40 Lead LFCSP Package Thermal Impedance Thermal Impedance 9 Power Dissipation Lead Temperature Soldering ESD Human Body Model Rating 0 3 V to 60 V 0 3V to 7 V 0 3 V to DVcc 0 3 Vor 7V whichever is less 0 3 V to DVcc 0 3 V or 7 V whichever is less 0 3 V to 7 V 0 3 V to 40 C to 85 65 to 150 C 125 C 42 C W 9 C W 28 C W 4 C W Ty max T4 0 4 JEDEC industry standard J STD 020 2 kV Power dissipated on chip must be derated to keep junction temperature below 125 C The assumption is that the maximum power dissipation condition is sourcing 24 mA into ground from AVpp with a 4 mA on chip current Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to
37. n the SDO line This data having been clocked out on the previous falling SCLK edge is valid on the rising edge of SCLK By connecting the SDO of the first device to the SDIN input of the next device in the chain a multidevice interface is constructed Each device in the system requires 24 clock pulses Therefore the total number of clock cycles must equal 24 x N Rev D Page 16 of 28 AD5410 AD5420 where N is the total number of AD5410 AD5420 devices in the chain When the serial transfer to all devices is complete LATCH is taken high This latches the input data in each device in the daisy chain The serial clock can be a continuous or a gated clock continuous SCLK source can be used only if LATCH is taken high after the correct number of clock cycles In gated clock mode a burst clock containing the exact number of clock cycles must be used and LATCH must be taken high after the final clock to latch the data See Figure 4 for a timing diagram CONTROLLER AD5410 AD5420 DATA OUT SDIN SERIAL CLOCK SCLK CONTROL OUT LATCH DATA IN SDIN AD5410 AD5420 AD5410 AD5420 07027 035 ADDITIONAL PINS OMITTED FOR CLARITY Figure 39 Daisy Chaining the AD5410 AD5420 Table 9 Input Shift Register Contents for a Read Operation MSB Readback Operation Readback mode is invoked by setting the address byte and read address as shown in Table 9 and Table 8 when writing to the input shift register The next wr
38. on the current output if the output is enabled To achieve a 1 mA peak to peak current the signal amplitude at the CAP2 pin must be 48 mV peak to peak Assuming that the modem output amplitude is 500 mV peak to peak its output must be attenuated by 500 48 10 42 If this voltage is used the current output should meet the HART amplitude specifications Figure 41 shows the recommended circuit for attenuating and coupling in the HART signal AVDD l C2 2 HART OUTPUT 07027 200 Figure 41 Coupling HART Signal In determining the absolute values of the capacitors ensure that the FSK output from the modem is passed undistorted Thus the bandwidth presented to the modem output signal must pass 1200 Hz and 2200 Hz frequencies The recommended values are 2 2 nF and C2 22 Digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for HART DIGITAL SLEW RATE CONTROL The slew rate control feature of the AD5410 AD5420 allows the user to control the rate at which the output current changes With the slew rate control feature disabled the output current changes at a rate of approximately 16 mA in 10 see Figure 36 This varies with load conditions To reduce the slew rate enable the slew rate control feature With the feature enabled via the SREN bit of the control register see Table 14 the output instead of slewing directly between two
39. operation there must be sufficient voltage on the supply when the read event is triggered by the DVcc power supply powering up Powering up the DVcc supply after AVpp supply ensures this If DVcc and AV pp are powered up simultaneously or if the internal DVcc is enabled the supplies should be powered up at a rate greater than typically 500 V sec or 24 V per 50 ms If this cannot be achieved simply issue a reset command to the AD5410 AD5420 after power on This performs a power on reset event reading the calibration registers and ensuring specified operation of the AD5410 AD5420 TRANSFER FUNCTION For the 0 mA to 20 mA 0 mA to 24 mA and 4 mA to 20 mA current output ranges the output current is respectively expressed as 20 mA aN 24 mA OUT aN 16 mA Ios xD 4mA where D is the decimal equivalent of the code loaded to the DAC N is the bit resolution of the DAC Table 12 Programming the AD5410 Data Register DATA REGISTER The data register is addressed by setting the address byte of the input shift register to 0x01 The data to be written to the data register is entered in Position DB15 to Position DB4 for the AD5410 and in Position DB15 to Position DBO for the AD5420 as shown in Table 12 and Table 13 respectively CONTROL REGISTER The control register is addressed by setting the address byte of the input shift register to 0x55 The data to be written to the control register is ente
40. pin sets the output current to the zero scale value which is either 0 mA or 4 mA depending on the output range programmed that is 0 mA to 20 mA 0 mA to 24 mA or 4 mA to 20 mA 7 Positive Edge Sensitive Latch A rising edge parallel loads the input shift register data into the relevant register In the case of the data register the output current is also updated 8 Serial Clock Input Data is clocked into the input shift register on the rising edge of SCLK This operates at clock speeds of up to 30 MHz 9 Serial Data Input Data must be valid on the rising edge of SCLK 10 Serial Data Output This pin is used to clock data from the device in daisy chain or readback mode Data is clocked out on the falling edge of SCLK See Figure 3 and Figure 4 11 GND Ground Reference Pin 13 Rset An external precision low drift 15 current setting resistor be connected to this pin to improve the overall performance of the device See the Specifications and AD5410 AD5420 Features sections 14 REFOUT Internal Reference Voltage Output Vrerout 5 V 5 mV at Ta 25 C Typical temperature drift is 1 8 ppm C 15 REFIN External Reference Voltage Input Vrerin 5 V 50 mV for specified performance 16 DVcc This pin when connected to GND disables the internal supply and an external supply SELECT must be connected to the DVc pin Leave this pin unconnected to enable the internal supply See the AD5410 AD5420 Features section 17 23 1
41. red in Position DB15 to Position DBO as shown in Table 14 The control register bit functions are described in Table 10 Table 10 Control Register Bit Functions Bit Description REXT Setting this bit selects the external current setting resistor See the AD5410 AD5420 Features section for further details When using an external current setting resistor it is recommended to only set REXT when also setting the OUTEN bit Alternately REXT can be set before the OUTEN bit is set but the range see Table 11 must be changed on the write in which the output is enabled OUTEN Output enable This bit must be set to enable the output SR Clock Digital slew rate control See the AD5410 AD5420 Features section SR Step Digital slew rate control See the AD5410 AD5420 Features section SREN Digital slew rate control enable DCEN Daisy chain enable R2 R1 RO Output range select See Table 11 Table 11 Output Range Options 4 mA to 20 mA current range mA to 20 mA current range mA to 24 mA current range LSB sis Deis DBiz DBio DBS DBs DB7 DBS DBT _ 12 bit data word X 2 don t care Table 13 Programming the AD5420 Data Register MSB LSB sis DBis DB12 DBs DBS DB3 662 DBI DBO jeu 14 Programming the Control Register LSB 7 15 oer psis psi
42. sto DET 3 Chansesto lable 5 Changes to Introduction to Table 4 and to Table 4 7 Added Figure 6 Changes to Figure 5 and Table 5 8 Added Feedback Monitoring of Output Current Section Including Figure 45 to Figure 47 Renumbered Subsequent b tics eene 23 Changes to Thermal and Supply Considerations Section and Eh 26 Updated Outline Dimensions tuerit trei etie 28 Changes to Ordering Guide ier Haee apis 28 3 09 Revision 0 Initial Version Rev D Page 2 of 28 AD5410 AD5420 SPECIFICATIONS 10 8 V to 26 4 V GND 0 V REFIN 5 V external DVcc 2 7 V to 5 5 V Rroap 300 all specifications Tmn to Tmax unless otherwise noted Table 1 Parameter Min Test Conditions Comments OUTPUT CURRENT RANGES 0 24 mA 0 20 4 20 ACCURACY INTERNAL Rser Resolution Bits AD5420 Bits AD5410 Total Unadjusted Error TUE FSR AD5420 FSR AD5420 Ta 25 C FSR AD5410 FSR AD5410 Ta 25 C Relative Accuracy INL FSR AD5420 FSR AD5410 Differential Nonlinearity DNL LSB Guaranteed monotonic Offset Error FSR FSR Ta 25 C Offset Error Temperature Coefficient TC ppm FSR C Gain Error 96 FSR AD5420 FSR AD5420 25 C AD5410 AD5410 Ta 2
43. unction tempera ture to exceed this value Excessive junction temperature can i occur if the AD5410 AD5420 are operated from the maximum 60 AV p while driving the maximum current 24 mA directly to ground In this case the ambient temperature should be controlled AVpp should be reduced At the maximum ambient temperature of 85 C the 24 lead TSSOP can dissipate 950 mW and the 40 Lead LFCSP can SUPPLY VOLTAGE V e dissipate 1 42 W To ensure that the junction temperature does not exceed 125 C while driving the maximum current of 24 mA directly into 30 ground also adding an on chip current of 4 mA AVpp should be reduced from the maximum rating to ensure that the oe 5 package is not required to dissipate more power than previously AMBIENT TEMPERATURE C 5 stated see Table 21 Figure 52 and Figure 53 Figure 53 Maximum Supply Voltage vs Ambient Temperature Table 21 Thermal and Supply Considerations Consideration TSSOP LFCSP Maximum Allowed Power 125 85 max T4 125 85 Dissipation When Operating at 214 EMEN 142W an Ambient Temperature of 85 C OJA 42 OJA 28 Maximum Allowed Ambient Temperature When Operating from a Supply of 40 V 60 V and Driving 24 mA Directly to Ground T max P x 4 125 40 x 0 028 x 42 78 C T max 125 60 x 0 028 x 28 78 C Maximum Allowed Supply Voltage When Operating at an T max T4 125 85 T max T 125
44. ure Rev D Page 10 of 28 AD5410 AD5420 0 10 TT 0 015 E 005 0 010 T c e 0 tc 0 05 ae a 0 10 SM gt lt 4mA TO 20mA INTERNAL Reet PQ i 0005 5 015 TO 20mA INTERNAL Reet i 24mA INTERNAL Reet 4 20mA EXTERNAL E 0 010 0 20 7 TO 20mA EXTERNAL Reet o 24mA EXTERNAL Reet x 5 0 25 5 0 015 40 20 0 20 40 60 80 TEMPERATURE C AV pp V Figure 13 Total Unadjusted Error vs Temperature Figure 16 Integral Nonlinearity Error vs AVpp External Rser 0 020 _ 0 015 OmA TO 24mA RANGE fc 0 005 a s Se 4mA 20mA INTERNAL Lee 20mA INTERNAL int E OMA 24mA INTERNAL SIS 0 010 4mA TO 20mA EXTERNAL Reet E TO 20mA EXTERNAL Reet 0 015 z TO 24mA EXTERNAL Reet S S 0 020 5 40 20 0 20 40 60 80 TEMPERATURE C AVpp V Figure 14 Offset Error vs Temperature Figure 17 Integral Nonlinearity Error vs AVop Internal Rser DNL ERROR LSB 4mA TO 20mA INTERNAL Reet 20mA INTERNAL Reet 24mA INTERNAL Reet 20mA EXTERNAL Reet 20mA EXTERNAL Rsrer 24mA EXTERNAL Rsrer GAIN ERROR FSR 07027 018 07027 012 0 20 40 TEMPERATURE C AVpp
45. urst clock containing the exact number of clock cycles must be used and LATCH must be taken high after the final clock to latch the data The first rising edge of SCLK that clocks in the MSB of the data word marks the beginning of the write cycle Exactly 24 rising clock edges must be applied to SCLK before LATCH is brought high If LATCH is brought high before the 24 rising SCLK edge the data written is invalid If more than 24 rising SCLK edges are applied before LATCH is brought high the input data is also invalid Table 6 Input Shift Register Format MSB LSB DB23 to DB16 DB15 to DBO Address byte Table 7 Address Byte Functions Address Byte Function 00000000 No operation NOP 00000001 Data register 00000010 Readback register value as per read address see Table 8 01010101 Control register 01010110 Reset register Daisy Chain Operation For systems that contain several devices the SDO pin can be used to daisy chain several devices together as shown in Figure 39 This daisy chain mode can be useful in system diagnostics and in reducing the number of serial interface lines Daisy chain mode is enabled by setting the DCEN bit of the control register The first rising edge of SCLK that clocks in the MSB of the data word marks the beginning of the write cycle SCLK is continuously applied to the input shift register If more than 24 clock pulses are applied the data ripples out of the input shift register and appears o
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